)]}'
{
  "commit": "ec669ef2e2cf277f3e73d842bb3bda1c3ea2ea73",
  "tree": "471a59939447f571fe7f0597924426ad3db4a63a",
  "parents": [
    "dd37fba90e72a48998d9f0eb5497088ea2b02ad1"
  ],
  "author": {
    "name": "Nicholas Kazlauskas",
    "email": "nicholas.kazlauskas@amd.com",
    "time": "Thu Sep 08 14:17:01 2022 -0400"
  },
  "committer": {
    "name": "Alex Deucher",
    "email": "alexander.deucher@amd.com",
    "time": "Tue Sep 27 17:56:29 2022 -0400"
  },
  "message": "drm/amd/display: Wrap OTG disable workaround with FIFO control\n\n[Why]\nThe DIO FIFO will underflow if we turn off the OTG before we turn\noff the FIFO.\n\nSince this happens as part of the OTG workaround and we don\u0027t reset\nthe FIFO afterwards we see the error persist.\n\n[How]\nAdd disable FIFO before the disable CRTC and enable FIFO after enabling\nthe CRTC.\n\nReviewed-by: Syed Hassan \u003cSyed.Hassan@amd.com\u003e\nAcked-by: Jasdeep Dhillon \u003cjdhillon@amd.com\u003e\nSigned-off-by: Nicholas Kazlauskas \u003cnicholas.kazlauskas@amd.com\u003e\nTested-by: Daniel Wheeler \u003cdaniel.wheeler@amd.com\u003e\nSigned-off-by: Alex Deucher \u003calexander.deucher@amd.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8559dcd80af041266274c5f479a016d78d829daa",
      "old_mode": 33188,
      "old_path": "drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c",
      "new_id": "4a15aa7a375fe053b1cc91eb14cc2ca0c4c6c004",
      "new_mode": 33188,
      "new_path": "drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c"
    }
  ]
}