)]}'
{
  "commit": "761b4f694cb90b63ca2739ac8a8a176342636e5e",
  "tree": "3af10af362b1feb39f151015ca4a96c537485745",
  "parents": [
    "a736fa1ed772e3640e1bfaab36032c5a285d6a7b"
  ],
  "author": {
    "name": "Guo Ren",
    "email": "guoren@linux.alibaba.com",
    "time": "Wed Jan 22 11:15:14 2020 +0800"
  },
  "committer": {
    "name": "Guo Ren",
    "email": "guoren@linux.alibaba.com",
    "time": "Fri Feb 21 15:43:24 2020 +0800"
  },
  "message": "csky: Support icache flush without specific instructions\n\nSome CPUs don\u0027t support icache specific instructions to flush icache\nlines in broadcast way. We use cpu control registers to flush local\nicache and use IPI to notify other cores.\n\nSigned-off-by: Guo Ren \u003cguoren@linux.alibaba.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1c723cb11cc465d60e7b648f4fe1eecb9d52cd1a",
      "old_mode": 33188,
      "old_path": "arch/csky/Kconfig",
      "new_id": "111474b50f69004ee7b6edd07ccb0dfff50c8d97",
      "new_mode": 33188,
      "new_path": "arch/csky/Kconfig"
    },
    {
      "type": "modify",
      "old_id": "1d5fc2f78fd7e8c634b87e61eb9219fbc4f67ba3",
      "old_mode": 33188,
      "old_path": "arch/csky/include/asm/cache.h",
      "new_id": "4b5c09bf1d25e3a9b9720bd58f99effcdab09610",
      "new_mode": 33188,
      "new_path": "arch/csky/include/asm/cache.h"
    },
    {
      "type": "modify",
      "old_id": "494ec912abff072ed0a85ba6d6c2b313a27001f2",
      "old_mode": 33188,
      "old_path": "arch/csky/mm/cachev1.c",
      "new_id": "5a5a9804a0e3d468baa2ff7444d91265d35f9783",
      "new_mode": 33188,
      "new_path": "arch/csky/mm/cachev1.c"
    },
    {
      "type": "modify",
      "old_id": "b61be6518e214bbed8d8704a6d36b76d1520f479",
      "old_mode": 33188,
      "old_path": "arch/csky/mm/cachev2.c",
      "new_id": "909fdd0f59950697b036eed066960b3e41dea355",
      "new_mode": 33188,
      "new_path": "arch/csky/mm/cachev2.c"
    }
  ]
}