)]}'
{
  "commit": "d408f389060ea02ad52fb3f68673e5166d521f0f",
  "tree": "67514d75a7bc54ed9b30a7e612d71a10f09ae859",
  "parents": [
    "87e30bfd1ea14ca80bec64bf0f201e6480f856ea"
  ],
  "author": {
    "name": "Vishal Verma",
    "email": "vishal.l.verma@intel.com",
    "time": "Wed Mar 16 17:16:48 2022 -0600"
  },
  "committer": {
    "name": "Vishal Verma",
    "email": "vishal.l.verma@intel.com",
    "time": "Wed Apr 13 01:32:32 2022 -0600"
  },
  "message": "PCI/ACPI: negotiate CXL _OSC\n\nAdd full support for negotiating _OSC as defined in the CXL 2.0 spec, as\napplicable to CXL-enabled platforms. Advertise support for the CXL\nfeatures we support - \u0027CXL 2.0 port/device register access\u0027, \u0027Protocol\nError Reporting\u0027, and \u0027CXL Native Hot Plug\u0027. Request control for \u0027CXL\nMemory Error Reporting\u0027. The requests are dependent on CONFIG_* based\nprerequisites, and prior PCI enabling, similar to how the standard PCI\n_OSC bits are determined.\n\nThe CXL specification does not define any additional constraints on\nthe hotplug flow beyond PCIe native hotplug, so a kernel that supports\nnative PCIe hotplug, supports CXL hotplug. For error handling protocol\nand link errors just use PCIe AER. There is nascent support for\namending AER events with CXL specific status [1], but there\u0027s\notherwise no additional OS responsibility for CXL errors beyond PCIe\nAER. CXL Memory Errors behave the same as typical memory errors so\nCONFIG_MEMORY_FAILURE is sufficient to indicate support to platform\nfirmware.\n\n[1]: https://lore.kernel.org/linux-cxl/164740402242.3912056.8303625392871313860.stgit@dwillia2-desk3.amr.corp.intel.com/\n\nCc: Bjorn Helgaas \u003cbhelgaas@google.com\u003e\nCc: \"Rafael J. Wysocki\" \u003crafael@kernel.org\u003e\nCc: Robert Moore \u003crobert.moore@intel.com\u003e\nCc: Dan Williams \u003cdan.j.williams@intel.com\u003e\nReviewed-by: Rafael J. Wysocki \u003crafael.j.wysocki@intel.com\u003e\nReviewed-by: Davidlohr Bueso \u003cdave@stgolabs.net\u003e\nSigned-off-by: Vishal Verma \u003cvishal.l.verma@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b50b5de231c2c45723d4ad1aa3913263a2c82fbf",
      "old_mode": 33188,
      "old_path": "drivers/acpi/pci_root.c",
      "new_id": "32ddeb8f58bd5265fd5b5e41a9aeb1bfae19755f",
      "new_mode": 33188,
      "new_path": "drivers/acpi/pci_root.c"
    },
    {
      "type": "modify",
      "old_id": "9413d2389711e6ed2c4968f8a57a28a96f3dc04f",
      "old_mode": 33188,
      "old_path": "include/acpi/acpi_bus.h",
      "new_id": "f1d053a9cfd4fe3106d7bf7b7a989c9e0961433a",
      "new_mode": 33188,
      "new_path": "include/acpi/acpi_bus.h"
    },
    {
      "type": "modify",
      "old_id": "fc40da9143150a8c88ad311c4354f13040994eef",
      "old_mode": 33188,
      "old_path": "include/linux/acpi.h",
      "new_id": "ade1bf0c2f0092ee58dcb34af8ec9066e6078724",
      "new_mode": 33188,
      "new_path": "include/linux/acpi.h"
    }
  ]
}