)]}'
{
  "commit": "100fade1ac13f242d6fce9a3a7eab3f1f92f144b",
  "tree": "bebfd08208072424d801c1cbb873b82459d79008",
  "parents": [
    "027784f4c67ecf3c9480cf92ee19d44c6a7a63c3"
  ],
  "author": {
    "name": "Andrew Jones",
    "email": "ajones@ventanamicro.com",
    "time": "Wed Aug 21 19:56:10 2024 +0530"
  },
  "committer": {
    "name": "Will Deacon",
    "email": "will@kernel.org",
    "time": "Fri Aug 30 11:04:06 2024 +0100"
  },
  "message": "riscv: Correct number of hart bits\n\nThe number of hart bits should be obtained from the highest hart ID,\nnot the number of harts. For example, if a guest has 2 harts, then\nthe number of bits should be fls(1) \u003d\u003d 1.\n\nSigned-off-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nSigned-off-by: Anup Patel \u003capatel@ventanamicro.com\u003e\nReviewed-by: Andrew Jones \u003cajones@ventanamicro.com\u003e\nLink: https://lore.kernel.org/r/20240821142610.3297483-5-apatel@ventanamicro.com\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "fe9399a8ffc142fd888b5ea52293e37a31e3d32c",
      "old_mode": 33188,
      "old_path": "riscv/aia.c",
      "new_id": "21d9704145d00c43bc8b4d6e3a3697a915c7d147",
      "new_mode": 33188,
      "new_path": "riscv/aia.c"
    }
  ]
}