Re: RISC-V nommu support v2
diff --git a/m b/m
index de547e0..6f3865d 100644
--- a/m
+++ b/m
@@ -2,77 +2,61 @@
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-Subject: Re: [PATCH] riscv: Add cpu topology DT entry.
-In-Reply-To: <20190624223819.14320-1-atish.patra@wdc.com>
-From: Palmer Dabbelt <palmer@sifive.com>
-To: Atish Patra <Atish.Patra@wdc.com>
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+Subject: Re: RISC-V nommu support v2
+To: Palmer Dabbelt <palmer@sifive.com>
+References: <mhng-6f11ed95-e3f3-41dc-93c5-1576928b373b@palmer-si-x1e>
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@@ -84,62 +68,75 @@
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+Cc: Damien Le Moal <Damien.LeMoal@wdc.com>, linux-kernel@vger.kernel.org,
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-On Mon, 24 Jun 2019 15:38:19 PDT (-0700), Atish Patra wrote:
-> Currently, there is no CPU topology defined for RISC-V.
-> The following series adds topology support in RISC-V.
->
-> http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html
->
-> Add a DT node for unleashed that describes the CPU topology
-> present in HiFive Unleashed.
->
-> Signed-off-by: Atish Patra <atish.patra@wdc.com>
-> ---
->  arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 18 ++++++++++++++++++
->  1 file changed, 18 insertions(+)
->
-> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-> index 83f40b00ab63..907564f4f07a 100644
-> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-> @@ -22,6 +22,24 @@
->  		#address-cells = <1>;
->  		#size-cells = <0>;
->  		timebase-frequency = <1000000>;
-> +
-> +		cpu-map {
-> +			cluster0 {
-> +				core0 {
-> +					cpu = <&cpu1>;
-> +				};
-> +				core1 {
-> +					cpu = <&cpu2>;
-> +				};
-> +				core2 {
-> +					cpu = <&cpu3>;
-> +				};
-> +				core3 {
-> +					cpu = <&cpu4>;
-> +				};
-> +			};
-> +		};
-> +
->  		cpu0: cpu@0 {
->  			compatible = "sifive,e51", "sifive,rocket0", "riscv";
->  			device_type = "cpu";
-
-Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
-
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