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#!/usr/bin/perl -w
#
# EEPROM data decoder for SDRAM DIMM modules
#
# Copyright 1998, 1999 Philip Edelbrock <phil@netroedge.com>
# modified by Christian Zuckschwerdt <zany@triq.net>
# modified by Burkart Lingner <burkart@bollchen.de>
# Copyright (C) 2005-2017 Jean Delvare <jdelvare@suse.de>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA.
#
#
# The eeprom driver must be loaded (unless option -x is used). For kernels
# older than 2.6.0, the eeprom driver can be found in the lm-sensors package.
#
# References:
# PC SDRAM Serial Presence
# Detect (SPD) Specification, Intel,
# 1997,1999, Rev 1.2B
#
# Jedec Standards 4.1.x & 4.5.x
# http://www.jedec.org
#
require 5.004;
use strict;
use POSIX qw(ceil);
use Fcntl qw(:DEFAULT :seek);
use File::Basename;
use vars qw($opt_html $opt_bodyonly $opt_side_by_side $opt_merge
$opt_igncheck $use_sysfs $use_hexdump $sbs_col_width
@vendors %decode_callback $revision @dimm $current %hexdump_cache);
use constant LITTLEENDIAN => "little-endian";
use constant BIGENDIAN => "big-endian";
$revision = '$Revision$ ($Date$)';
$revision =~ s/\$\w+: (.*?) \$/$1/g;
$revision =~ s/ \([^()]*\)//;
@vendors = (
["AMD", "AMI", "Fairchild", "Fujitsu",
"GTE", "Harris", "Hitachi", "Inmos",
"Intel", "I.T.T.", "Intersil", "Monolithic Memories",
"Mostek", "Freescale (former Motorola)", "National", "NEC",
"RCA", "Raytheon", "Conexant (Rockwell)", "Seeq",
"NXP (former Signetics, Philips Semi.)", "Synertek", "Texas Instruments", "Toshiba",
"Xicor", "Zilog", "Eurotechnique", "Mitsubishi",
"Lucent (AT&T)", "Exel", "Atmel", "STMicroelectronics (former SGS/Thomson)",
"Lattice Semi.", "NCR", "Wafer Scale Integration", "IBM",
"Tristar", "Visic", "Intl. CMOS Technology", "SSSI",
"MicrochipTechnology", "Ricoh Ltd.", "VLSI", "Micron Technology",
"SK Hynix (former Hyundai Electronics)", "OKI Semiconductor", "ACTEL", "Sharp",
"Catalyst", "Panasonic", "IDT", "Cypress",
"DEC", "LSI Logic", "Zarlink (former Plessey)", "UTMC",
"Thinking Machine", "Thomson CSF", "Integrated CMOS (Vertex)", "Honeywell",
"Tektronix", "Oracle Corporation (former Sun Microsystems)", "Silicon Storage Technology", "ProMos/Mosel Vitelic",
"Infineon (former Siemens)", "Macronix", "Xerox", "Plus Logic",
"SunDisk", "Elan Circuit Tech.", "European Silicon Str.", "Apple Computer",
"Xilinx", "Compaq", "Protocol Engines", "SCI",
"Seiko Instruments", "Samsung", "I3 Design System", "Klic",
"Crosspoint Solutions", "Alliance Semiconductor", "Tandem", "Hewlett-Packard",
"Integrated Silicon Solutions", "Brooktree", "New Media", "MHS Electronic",
"Performance Semi.", "Winbond Electronic", "Kawasaki Steel", "Bright Micro",
"TECMAR", "Exar", "PCMCIA", "LG Semi (former Goldstar)",
"Northern Telecom", "Sanyo", "Array Microsystems", "Crystal Semiconductor",
"Analog Devices", "PMC-Sierra", "Asparix", "Convex Computer",
"Quality Semiconductor", "Nimbus Technology", "Transwitch", "Micronas (ITT Intermetall)",
"Cannon", "Altera", "NEXCOM", "QUALCOMM",
"Sony", "Cray Research", "AMS(Austria Micro)", "Vitesse",
"Aster Electronics", "Bay Networks (Synoptic)", "Zentrum or ZMD", "TRW",
"Thesys", "Solbourne Computer", "Allied-Signal", "Dialog",
"Media Vision", "Numonyx Corporation (former Level One Communication)"],
["Cirrus Logic", "National Instruments", "ILC Data Device", "Alcatel Mietec",
"Micro Linear", "Univ. of NC", "JTAG Technologies", "BAE Systems",
"Nchip", "Galileo Tech", "Bestlink Systems", "Graychip",
"GENNUM", "VideoLogic", "Robert Bosch", "Chip Express",
"DATARAM", "United Microelec Corp.", "TCSI", "Smart Modular",
"Hughes Aircraft", "Lanstar Semiconductor", "Qlogic", "Kingston",
"Music Semi", "Ericsson Components", "SpaSE", "Eon Silicon Devices",
"Programmable Micro Corp", "DoD", "Integ. Memories Tech.", "Corollary Inc.",
"Dallas Semiconductor", "Omnivision", "EIV(Switzerland)", "Novatel Wireless",
"Zarlink (former Mitel)", "Clearpoint", "Cabletron", "STEC (former Silicon Technology)",
"Vanguard", "Hagiwara Sys-Com", "Vantis", "Celestica",
"Century", "Hal Computers", "Rohm Company Ltd.", "Juniper Networks",
"Libit Signal Processing", "Mushkin Enhanced Memory", "Tundra Semiconductor", "Adaptec Inc.",
"LightSpeed Semi.", "ZSP Corp.", "AMIC Technology", "Adobe Systems",
"Dynachip", "PNY Technologies Inc. (former PNY Electronics)", "Newport Digital", "MMC Networks",
"T Square", "Seiko Epson", "Broadcom", "Viking Components",
"V3 Semiconductor", "Flextronics (former Orbit)", "Suwa Electronics", "Transmeta",
"Micron CMS", "American Computer & Digital Components Inc", "Enhance 3000 Inc", "Tower Semiconductor",
"CPU Design", "Price Point", "Maxim Integrated Product", "Tellabs",
"Centaur Technology", "Unigen Corporation", "Transcend Information", "Memory Card Technology",
"CKD Corporation Ltd.", "Capital Instruments, Inc.", "Aica Kogyo, Ltd.", "Linvex Technology",
"MSC Vertriebs GmbH", "AKM Company, Ltd.", "Dynamem, Inc.", "NERA ASA",
"GSI Technology", "Dane-Elec (C Memory)", "Acorn Computers", "Lara Technology",
"Oak Technology, Inc.", "Itec Memory", "Tanisys Technology", "Truevision",
"Wintec Industries", "Super PC Memory", "MGV Memory", "Galvantech",
"Gadzoox Nteworks", "Multi Dimensional Cons.", "GateField", "Integrated Memory System",
"Triscend", "XaQti", "Goldenram", "Clear Logic",
"Cimaron Communications", "Nippon Steel Semi. Corp.", "Advantage Memory", "AMCC",
"LeCroy", "Yamaha Corporation", "Digital Microwave", "NetLogic Microsystems",
"MIMOS Semiconductor", "Advanced Fibre", "BF Goodrich Data.", "Epigram",
"Acbel Polytech Inc.", "Apacer Technology", "Admor Memory", "FOXCONN",
"Quadratics Superconductor", "3COM"],
["Camintonn Corporation", "ISOA Incorporated", "Agate Semiconductor", "ADMtek Incorporated",
"HYPERTEC", "Adhoc Technologies", "MOSAID Technologies", "Ardent Technologies",
"Switchcore", "Cisco Systems, Inc.", "Allayer Technologies", "WorkX AG (Wichman)",
"Oasis Semiconductor", "Novanet Semiconductor", "E-M Solutions", "Power General",
"Advanced Hardware Arch.", "Inova Semiconductors GmbH", "Telocity", "Delkin Devices",
"Symagery Microsystems", "C-Port Corporation", "SiberCore Technologies", "Southland Microsystems",
"Malleable Technologies", "Kendin Communications", "Great Technology Microcomputer", "Sanmina Corporation",
"HADCO Corporation", "Corsair", "Actrans System Inc.", "ALPHA Technologies",
"Silicon Laboratories, Inc. (Cygnal)", "Artesyn Technologies", "Align Manufacturing", "Peregrine Semiconductor",
"Chameleon Systems", "Aplus Flash Technology", "MIPS Technologies", "Chrysalis ITS",
"ADTEC Corporation", "Kentron Technologies", "Win Technologies", "Tezzaron Semiconductor (former Tachyon Semiconductor)",
"Extreme Packet Devices", "RF Micro Devices", "Siemens AG", "Sarnoff Corporation",
"Itautec SA (former Itautec Philco SA)", "Radiata Inc.", "Benchmark Elect. (AVEX)", "Legend",
"SpecTek Incorporated", "Hi/fn", "Enikia Incorporated", "SwitchOn Networks",
"AANetcom Incorporated", "Micro Memory Bank", "ESS Technology", "Virata Corporation",
"Excess Bandwidth", "West Bay Semiconductor", "DSP Group", "Newport Communications",
"Chip2Chip Incorporated", "Phobos Corporation", "Intellitech Corporation", "Nordic VLSI ASA",
"Ishoni Networks", "Silicon Spice", "Alchemy Semiconductor", "Agilent Technologies",
"Centillium Communications", "W.L. Gore", "HanBit Electronics", "GlobeSpan",
"Element 14", "Pycon", "Saifun Semiconductors", "Sibyte, Incorporated",
"MetaLink Technologies", "Feiya Technology", "I & C Technology", "Shikatronics",
"Elektrobit", "Megic", "Com-Tier", "Malaysia Micro Solutions",
"Hyperchip", "Gemstone Communications", "Anadigm (former Anadyne)", "3ParData",
"Mellanox Technologies", "Tenx Technologies", "Helix AG", "Domosys",
"Skyup Technology", "HiNT Corporation", "Chiaro", "MDT Technologies GmbH (former MCI Computer GMBH)",
"Exbit Technology A/S", "Integrated Technology Express", "AVED Memory", "Legerity",
"Jasmine Networks", "Caspian Networks", "nCUBE", "Silicon Access Networks",
"FDK Corporation", "High Bandwidth Access", "MultiLink Technology", "BRECIS",
"World Wide Packets", "APW", "Chicory Systems", "Xstream Logic",
"Fast-Chip", "Zucotto Wireless", "Realchip", "Galaxy Power",
"eSilicon", "Morphics Technology", "Accelerant Networks", "Silicon Wave",
"SandCraft", "Elpida"],
["Solectron", "Optosys Technologies", "Buffalo (former Melco)", "TriMedia Technologies",
"Cyan Technologies", "Global Locate", "Optillion", "Terago Communications",
"Ikanos Communications", "Princeton Technology", "Nanya Technology", "Elite Flash Storage",
"Mysticom", "LightSand Communications", "ATI Technologies", "Agere Systems",
"NeoMagic", "AuroraNetics", "Golden Empire", "Mushkin",
"Tioga Technologies", "Netlist", "TeraLogic", "Cicada Semiconductor",
"Centon Electronics", "Tyco Electronics", "Magis Works", "Zettacom",
"Cogency Semiconductor", "Chipcon AS", "Aspex Technology", "F5 Networks",
"Programmable Silicon Solutions", "ChipWrights", "Acorn Networks", "Quicklogic",
"Kingmax Semiconductor", "BOPS", "Flasys", "BitBlitz Communications",
"eMemory Technology", "Procket Networks", "Purple Ray", "Trebia Networks",
"Delta Electronics", "Onex Communications", "Ample Communications", "Memory Experts Intl",
"Astute Networks", "Azanda Network Devices", "Dibcom", "Tekmos",
"API NetWorks", "Bay Microsystems", "Firecron Ltd", "Resonext Communications",
"Tachys Technologies", "Equator Technology", "Concept Computer", "SILCOM",
"3Dlabs", "c't Magazine", "Sanera Systems", "Silicon Packets",
"Viasystems Group", "Simtek", "Semicon Devices Singapore", "Satron Handelsges",
"Improv Systems", "INDUSYS GmbH", "Corrent", "Infrant Technologies",
"Ritek Corp", "empowerTel Networks", "Hypertec", "Cavium Networks",
"PLX Technology", "Massana Design", "Intrinsity", "Valence Semiconductor",
"Terawave Communications", "IceFyre Semiconductor", "Primarion", "Picochip Designs Ltd",
"Silverback Systems", "Jade Star Technologies", "Pijnenburg Securealink",
"takeMS - Ultron AG (former Memorysolution GmbH)", "Cambridge Silicon Radio",
"Swissbit", "Nazomi Communications", "eWave System",
"Rockwell Collins", "Picocel Co., Ltd.", "Alphamosaic Ltd", "Sandburst",
"SiCon Video", "NanoAmp Solutions", "Ericsson Technology", "PrairieComm",
"Mitac International", "Layer N Networks", "MtekVision", "Allegro Networks",
"Marvell Semiconductors", "Netergy Microelectronic", "NVIDIA", "Internet Machines",
"Memorysolution GmbH (former Peak Electronics)", "Litchfield Communication", "Accton Technology", "Teradiant Networks",
"Scaleo Chip (former Europe Technologies)", "Cortina Systems", "RAM Components", "Raqia Networks",
"ClearSpeed", "Matsushita Battery", "Xelerated", "SimpleTech",
"Utron Technology", "Astec International", "AVM gmbH", "Redux Communications",
"Dot Hill Systems", "TeraChip"],
["T-RAM Incorporated", "Innovics Wireless", "Teknovus", "KeyEye Communications",
"Runcom Technologies", "RedSwitch", "Dotcast", "Silicon Mountain Memory",
"Signia Technologies", "Pixim", "Galazar Networks", "White Electronic Designs",
"Patriot Scientific", "Neoaxiom Corporation", "3Y Power Technology", "Scaleo Chip (former Europe Technologies)",
"Potentia Power Systems", "C-guys Incorporated", "Digital Communications Technology Incorporated", "Silicon-Based Technology",
"Fulcrum Microsystems", "Positivo Informatica Ltd", "XIOtech Corporation", "PortalPlayer",
"Zhiying Software", "Parker Vision, Inc. (former Direct2Data)", "Phonex Broadband", "Skyworks Solutions",
"Entropic Communications", "I'M Intelligent Memory Ltd (former Pacific Force Technology)", "Zensys A/S", "Legend Silicon Corp.",
"sci-worx GmbH", "SMSC (former Oasis Silicon Systems)", "Renesas Electronics (former Renesas Technology)", "Raza Microelectronics",
"Phyworks", "MediaTek", "Non-cents Productions", "US Modular",
"Wintegra Ltd", "Mathstar", "StarCore", "Oplus Technologies",
"Mindspeed", "Just Young Computer", "Radia Communications", "OCZ",
"Emuzed", "LOGIC Devices", "Inphi Corporation", "Quake Technologies",
"Vixel", "SolusTek", "Kongsberg Maritime", "Faraday Technology",
"Altium Ltd.", "Insyte", "ARM Ltd.", "DigiVision",
"Vativ Technologies", "Endicott Interconnect Technologies", "Pericom", "Bandspeed",
"LeWiz Communications", "CPU Technology", "Ramaxel Technology", "DSP Group",
"Axis Communications", "Legacy Electronics", "Chrontel", "Powerchip Semiconductor",
"MobilEye Technologies", "Excel Semiconductor", "A-DATA Technology", "VirtualDigm",
"G Skill Intl", "Quanta Computer", "Yield Microelectronics", "Afa Technologies",
"KINGBOX Technology Co. Ltd.", "Ceva", "iStor Networks", "Advance Modules",
"Microsoft", "Open-Silicon", "Goal Semiconductor", "ARC International",
"Simmtec", "Metanoia", "Key Stream", "Lowrance Electronics",
"Adimos", "SiGe Semiconductor", "Fodus Communications", "Credence Systems Corp.",
"Genesis Microchip Inc.", "Vihana, Inc.", "WIS Technologies", "GateChange Technologies",
"High Density Devices AS", "Synopsys", "Gigaram", "Enigma Semiconductor Inc.",
"Century Micro Inc.", "Icera Semiconductor", "Mediaworks Integrated Systems", "O'Neil Product Development",
"Supreme Top Technology Ltd.", "MicroDisplay Corporation", "Team Group Inc.", "Sinett Corporation",
"Toshiba Corporation", "Tensilica", "SiRF Technology", "Bacoc Inc.",
"SMaL Camera Technologies", "Thomson SC", "Airgo Networks", "Wisair Ltd.",
"SigmaTel", "Arkados", "Compete IT gmbH Co. KG", "Eudar Technology Inc.",
"Focus Enhancements", "Xyratex"],
["Specular Networks", "Patriot Memory", "U-Chip Technology Corp.", "Silicon Optix",
"Greenfield Networks", "CompuRAM GmbH", "Stargen, Inc.", "NetCell Corporation",
"Excalibrus Technologies Ltd", "SCM Microsystems", "Xsigo Systems, Inc.", "CHIPS & Systems Inc",
"Tier 1 Multichip Solutions", "CWRL Labs", "Teradici", "Gigaram, Inc.",
"g2 Microsystems", "PowerFlash Semiconductor", "P.A. Semi, Inc.", "NovaTech Solutions, S.A.",
"c2 Microsystems, Inc.", "Level5 Networks", "COS Memory AG", "Innovasic Semiconductor",
"02IC Co. Ltd", "Tabula, Inc.", "Crucial Technology", "Chelsio Communications",
"Solarflare Communications", "Xambala Inc.", "EADS Astrium", "Terra Semiconductor Inc. (former ATO Semicon Co. Ltd.)",
"Imaging Works, Inc.", "Astute Networks, Inc.", "Tzero", "Emulex",
"Power-One", "Pulse~LINK Inc.", "Hon Hai Precision Industry", "White Rock Networks Inc.",
"Telegent Systems USA, Inc.", "Atrua Technologies, Inc.", "Acbel Polytech Inc.",
"eRide Inc.","ULi Electronics Inc.", "Magnum Semiconductor Inc.", "neoOne Technology, Inc.",
"Connex Technology, Inc.", "Stream Processors, Inc.", "Focus Enhancements", "Telecis Wireless, Inc.",
"uNav Microelectronics", "Tarari, Inc.", "Ambric, Inc.", "Newport Media, Inc.", "VMTS",
"Enuclia Semiconductor, Inc.", "Virtium Technology Inc.", "Solid State System Co., Ltd.", "Kian Tech LLC",
"Artimi", "Power Quotient International", "Avago Technologies", "ADTechnology", "Sigma Designs",
"SiCortex, Inc.", "Ventura Technology Group", "eASIC", "M.H.S. SAS", "Micro Star International",
"Rapport Inc.", "Makway International", "Broad Reach Engineering Co.",
"Semiconductor Mfg Intl Corp", "SiConnect", "FCI USA Inc.", "Validity Sensors",
"Coney Technology Co. Ltd.", "Spans Logic", "Neterion Inc.", "Qimonda",
"New Japan Radio Co. Ltd.", "Velogix", "Montalvo Systems", "iVivity Inc.", "Walton Chaintech",
"AENEON", "Lorom Industrial Co. Ltd.", "Radiospire Networks", "Sensio Technologies, Inc.",
"Nethra Imaging", "Hexon Technology Pte Ltd", "CompuStocx (CSX)", "Methode Electronics, Inc.",
"Connect One Ltd.", "Opulan Technologies", "Septentrio NV", "Goldenmars Technology Inc.",
"Kreton Corporation", "Cochlear Ltd.", "Altair Semiconductor", "NetEffect, Inc.",
"Spansion, Inc.", "Taiwan Semiconductor Mfg", "Emphany Systems Inc.",
"ApaceWave Technologies", "Mobilygen Corporation", "Tego", "Cswitch Corporation",
"Haier (Beijing) IC Design Co.", "MetaRAM", "Axel Electronics Co. Ltd.", "Tilera Corporation",
"Aquantia", "Vivace Semiconductor", "Redpine Signals", "Octalica", "InterDigital Communications",
"Avant Technology", "Asrock, Inc.", "Availink", "Quartics, Inc.", "Element CXI",
"Innovaciones Microelectronicas", "VeriSilicon Microelectronics", "W5 Networks"],
["MOVEKING", "Mavrix Technology, Inc.", "CellGuide Ltd.", "Faraday Technology",
"Diablo Technologies, Inc.", "Jennic", "Octasic", "Molex Incorporated", "3Leaf Networks",
"Bright Micron Technology", "Netxen", "NextWave Broadband Inc.", "DisplayLink", "ZMOS Technology",
"Tec-Hill", "Multigig, Inc.", "Amimon", "Euphonic Technologies, Inc.", "BRN Phoenix",
"InSilica", "Ember Corporation", "Avexir Technologies Corporation", "Echelon Corporation",
"Edgewater Computer Systems", "XMOS Semiconductor Ltd.", "GENUSION, Inc.", "Memory Corp NV",
"SiliconBlue Technologies", "Rambus Inc.", "Andes Technology Corporation", "Coronis Systems",
"Achronix Semiconductor", "Siano Mobile Silicon Ltd.", "Semtech Corporation", "Pixelworks Inc.",
"Gaisler Research AB", "Teranetics", "Toppan Printing Co. Ltd.", "Kingxcon",
"Silicon Integrated Systems", "I-O Data Device, Inc.", "NDS Americas Inc.", "Solomon Systech Limited",
"On Demand Microelectronics", "Amicus Wireless Inc.", "SMARDTV SNC", "Comsys Communication Ltd.",
"Movidia Ltd.", "Javad GNSS, Inc.", "Montage Technology Group", "Trident Microsystems", "Super Talent",
"Optichron, Inc.", "Future Waves UK Ltd.", "SiBEAM, Inc.", "Inicore, Inc.", "Virident Systems",
"M2000, Inc.", "ZeroG Wireless, Inc.", "Gingle Technology Co. Ltd.", "Space Micro Inc.", "Wilocity",
"Novafora, Inc.", "iKoa Corporation", "ASint Technology", "Ramtron", "Plato Networks Inc.",
"IPtronics AS", "Infinite-Memories", "Parade Technologies Inc.", "Dune Networks",
"GigaDevice Semiconductor", "Modu Ltd.", "CEITEC", "Northrop Grumman", "XRONET Corporation",
"Sicon Semiconductor AB", "Atla Electronics Co. Ltd.", "TOPRAM Technology", "Silego Technology Inc.",
"Kinglife", "Ability Industries Ltd.", "Silicon Power Computer & Communications",
"Augusta Technology, Inc.", "Nantronics Semiconductors", "Hilscher Gesellschaft", "Quixant Ltd.",
"Percello Ltd.", "NextIO Inc.", "Scanimetrics Inc.", "FS-Semi Company Ltd.", "Infinera Corporation",
"SandForce Inc.", "Lexar Media", "Teradyne Inc.", "Memory Exchange Corp.", "Suzhou Smartek Electronics",
"Avantium Corporation", "ATP Electronics Inc.", "Valens Semiconductor Ltd", "Agate Logic, Inc.",
"Netronome", "Zenverge, Inc.", "N-trig Ltd", "SanMax Technologies Inc.", "Contour Semiconductor Inc.",
"TwinMOS", "Silicon Systems, Inc.", "V-Color Technology Inc.", "Certicom Corporation", "JSC ICC Milandr",
"PhotoFast Global Inc.", "InnoDisk Corporation", "Muscle Power", "Energy Micro", "Innofidei",
"CopperGate Communications", "Holtek Semiconductor Inc.", "Myson Century, Inc.", "FIDELIX",
"Red Digital Cinema", "Densbits Technology", "Zempro", "MoSys", "Provigent", "Triad Semiconductor, Inc."],
["Siklu Communication Ltd.", "A Force Manufacturing Ltd.", "Strontium", "Abilis Systems", "Siglead, Inc.",
"Ubicom, Inc.", "Unifosa Corporation", "Stretch, Inc.", "Lantiq Deutschland GmbH", "Visipro",
"EKMemory", "Microelectronics Institute ZTE", "Cognovo Ltd.", "Carry Technology Co. Ltd.", "Nokia",
"King Tiger Technology", "Sierra Wireless", "HT Micron", "Albatron Technology Co. Ltd.",
"Leica Geosystems AG", "BroadLight", "AEXEA", "ClariPhy Communications, Inc.", "Green Plug",
"Design Art Networks", "Mach Xtreme Technology Ltd.", "ATO Solutions Co. Ltd.", "Ramsta",
"Greenliant Systems, Ltd.", "Teikon", "Antec Hadron", "NavCom Technology, Inc.",
"Shanghai Fudan Microelectronics", "Calxeda, Inc.", "JSC EDC Electronics", "Kandit Technology Co. Ltd.",
"Ramos Technology", "Goldenmars Technology", "XeL Technology Inc.", "Newzone Corporation",
"ShenZhen MercyPower Tech", "Nanjing Yihuo Technology", "Nethra Imaging Inc.", "SiTel Semiconductor BV",
"SolidGear Corporation", "Topower Computer Ind Co Ltd.", "Wilocity", "Profichip GmbH",
"Gerad Technologies", "Ritek Corporation", "Gomos Technology Limited", "Memoright Corporation",
"D-Broad, Inc.", "HiSilicon Technologies", "Syndiant Inc.", "Enverv Inc.", "Cognex",
"Xinnova Technology Inc.", "Ultron AG", "Concord Idea Corporation", "AIM Corporation",
"Lifetime Memory Products", "Ramsway", "Recore Systems BV", "Haotian Jinshibo Science Tech",
"Being Advanced Memory", "Adesto Technologies", "Giantec Semiconductor, Inc.", "HMD Electronics AG",
"Gloway International (HK)", "Kingcore", "Anucell Technology Holding",
"Accord Software & Systems Pvt. Ltd.", "Active-Semi Inc.", "Denso Corporation", "TLSI Inc.",
"Shenzhen Daling Electronic Co. Ltd.", "Mustang", "Orca Systems", "Passif Semiconductor",
"GigaDevice Semiconductor (Beijing) Inc.", "Memphis Electronic", "Beckhoff Automation GmbH",
"Harmony Semiconductor Corp (former ProPlus Design Solutions)", "Air Computers SRL", "TMT Memory",
"Eorex Corporation", "Xingtera", "Netsol", "Bestdon Technology Co. Ltd.", "Baysand Inc.",
"Uroad Technology Co. Ltd. (former Triple Grow Industrial Ltd.)", "Wilk Elektronik S.A.",
"AAI", "Harman", "Berg Microelectronics Inc.", "ASSIA, Inc.", "Visiontek Products LLC",
"OCMEMORY", "Welink Solution Inc.", "Shark Gaming", "Avalanche Technology",
"R&D Center ELVEES OJSC", "KingboMars Technology Co. Ltd.",
"High Bridge Solutions Industria Eletronica", "Transcend Technology Co. Ltd.",
"Everspin Technologies", "Hon-Hai Precision", "Smart Storage Systems", "Toumaz Group",
"Zentel Electronics Corporation", "Panram International Corporation",
"Silicon Space Technology", "LITE-ON IT Corporation", "Inuitive", "HMicro",
"BittWare Inc.", "GLOBALFOUNDRIES", "ACPI Digital Co. Ltd", "Annapurna Labs",
"AcSiP Technology Corporation", "Idea! Electronic Systems", "Gowe Technology Co. Ltd",
"Hermes Testing Solutions Inc.", "Positivo BGH", "Intelligence Silicon Technology"],
["3D PLUS", "Diehl Aerospace", "Fairchild", "Mercury Systems",
"Sonics Inc.", "GE Intelligent Platforms GmbH & Co.", "Shenzhen Jinge Information Co. Ltd",
"SCWW", "Silicon Motion Inc.", "Anurag", "King Kong",
"FROM30 Co. Ltd", "Gowin Semiconductor Corp", "Fremont Micro Devices Ltd",
"Ericsson Modems", "Exelis", "Satixfy Ltd", "Galaxy Microsystems Ltd",
"Gloway International Co. Ltd", "Lab", "Smart Energy Instruments",
"Approved Memory Corporation", "Axell Corporation", "ISD Technology Limited",
"Phytium", "Xi'an SinoChip Semiconductor", "Ambiq Micro", "eveRAM Technology Inc.",
"Infomax", "Butterfly Network Inc.", "Shenzhen City Gcai Electronics",
"Stack Devices Corporation", "ADK Media Group", "TSP Global Co. Ltd",
"HighX", "Shenzhen Elicks Technology", "ISSI/Chingis", "Google Inc.",
"Dasima International Development", "Leahkinn Technology Limited",
"HIMA Paul Hildebrandt GmbH Co KG", "Keysight Technologies",
"Techcomp International (Fastable)", "Ancore Technology Corporation",
"Nuvoton", "Korea Uhbele International Group Ltd", "Ikegami Tsushinki Co. Ltd",
"RelChip Inc.", "Baikal Electronics", "Nemostech Inc.",
"Memorysolution GmbH", "Silicon Integrated Systems Corporation",
"Xiede", "Multilaser Components", "Flash Chi", "Jone",
"GCT Semiconductor Inc.", "Hong Kong Zetta Device Technology",
"Unimemory Technology(s) Pte Ltd", "Cuso", "Kuso",
"Uniquify Inc.", "Skymedi Corporation", "Core Chance Co. Ltd",
"Tekism Co. Ltd", "Seagate Technology PLC", "Hong Kong Gaia Group Co. Limited",
"Gigacom Semiconductor LLC", "V2 Technologies", "TLi", "Neotion",
"Lenovo", "Shenzhen Zhongteng Electronic Corp. Ltd", "Compound Photonics",
"Cognimem Technologies Inc.", "Shenzhen Pango Microsystems Co. Ltd",
"Vasekey", "Cal-Comp Industria de Semicondutores", "Eyenix Co. Ltd",
"Heoriady", "Accelerated Memory Production Inc.", "INVECAS Inc.",
"AP Memory", "Douqi Technology", "Etron Technology Inc.",
"Indie Semiconductor", "Socionext Inc.", "HGST", "EVGA",
"Audience Inc.", "EpicGear", "Vitesse Enterprise Co.",
"Foxtronn International Corporation", "Bretelon Inc.", "Graphcore", "Eoplex Inc",
"MaxLinear Inc", "ETA Devices", "LOKI", "IMS Electronics Co Ltd",
"Dosilicon Co Ltd", "Dolphin Integration", "Shenzhen Mic Electronics Technolog",
"Boya Microelectronics Inc", "Geniachip (Roche)", "Axign", "Kingred Electronic Technology Ltd",
"Chao Yue Zhuo Computer Business Dept.", "Guangzhou Si Nuo Electronic Technology.",
"Crocus Technology Inc", "Creative Chips GmbH", "GE Aviation Systems LLC.",
"Asgard", "Good Wealth Technology Ltd", "TriCor Technologies", "Nova-Systems GmbH",
"JUHOR", "Zhuhai Douke Commerce Co Ltd", "DSL Memory", "Anvo-Systems Dresden GmbH",
"Realtek", "AltoBeam", "Wave Computing", "Beijing TrustNet Technology Co Ltd",
"Innovium Inc", "Starsway Technology Limited"],
["Weltronics Co LTD", "VMware Inc", "Hewlett Packard Enterprise", "INTENSO",
"Puya Semiconductor", "MEMORFI", "MSC Technologies GmbH", "Txrui",
"SiFive Inc", "Spreadtrum Communications", "XTX Technology Limited",
"UMAX Technology", "Shenzhen Yong Sheng Technology", "SNOAMOO (Shenzhen Kai Zhuo Yue)",
"Daten Tecnologia LTDA", "Shenzhen XinRuiYan Electronics", "Eta Compute",
"Energous", "Raspberry Pi Trading Ltd", "Shenzhen Chixingzhe Tech Co Ltd",
"Silicon Mobility", "IQ-Analog Corporation", "Uhnder Inc", "Impinj",
"DEPO Computers", "Nespeed Sysems", "Yangtze Memory Technologies Co Ltd",
"MemxPro Inc", "Tammuz Co Ltd", "Allwinner Technology",
"Shenzhen City Futian District Qing Xuan Tong Computer Trading Firm", "XMC",
"Teclast", "Maxsun", "Haiguang Integrated Circuit Design", "RamCENTER Technology",
"Phison Electronics Corporation", "Guizhou Huaxintong Semi-Conductor",
"Network Intelligence", "Continental Technology (Holdings)",
"Guangzhou Huayan Suning Electronic", "Guangzhou Zhouji Electronic Co Ltd",
"Shenzhen Giant Hui Kang Tech Co Ltd", "Shenzhen Yilong Innovative Co Ltd",
"Neo Forza", "Lyontek Inc", "Shanghai Kuxin Microelectronics Ltd",
"Shenzhen Larix Technology Co Ltd", "Qbit Semiconductor Ltd",
"Insignis Technology Corporation", "Lanson Memory Co Ltd",
"Shenzhen Superway Electronics Co Ltd", "Canaan-Creative Co Ltd",
"Black Diamond Memory", "Shenzhen City Parker Baking Electronics",
"Shenzhen Baihong Technology Co Ltd", "GEO Semiconductors", "OCPC", "Artery Technology Co Ltd",
"Jinyu", "ShenzhenYing Chi Technology Development", "Shenzhen Pengcheng Xin Technology",
"Pegasus Semiconductor (Shanghai) Co", "Mythic Inc", "Elmos Semiconductor AG",
"Kllisre", "Shenzhen Winconway Technology", "Shenzhen Xingmem Technology Corp",
"Gold Key Technology Co Ltd", "Habana Labs Ltd", "Hoodisk Electronics Co Ltd",
"SemsoTai (HK) Technology Co Ltd", "OM Nanotech Pvt. Ltd",
"Shenzhen Zhifeng Weiye Technology", "Xinshirui (Shenzhen) Electronics Co",
"Guangzhou Zhong Hao Tian Electronic", "Shenzhen Longsys Electronics Co Ltd",
"Deciso B.V.", "Puya Semiconductor (Shenzhen)", "Shenzhen Veineda Technology Co Ltd",
"Antec Memory", "Cortus SAS", "Dust Leopard", "MyWo AS",
"J&A Information Inc", "Shenzhen JIEPEI Technology Co Ltd", "Heidelberg University",
"Flexxon PTE Ltd", "Wiliot", "Raysun Electronics International Ltd",
"Aquarius Production Company LLC", "MACNICA DHW LTDA", "Intelimem",
"Zbit Semiconductor Inc", "Shenzhen Technology Co Ltd", "Signalchip",
"Shenzen Recadata Storage Technology", "Hyundai Technology",
"Shanghai Fudi Investment Development", "Aixi Technology", "Tecon MT",
"Onda Electric Co Ltd", "Jinshen", "Kimtigo Semiconductor (HK) Limited",
"IIT Madras", "Shenshan (Shenzhen) Electronic", "Hefei Core Storage Electronic Limited",
"Colorful Technology Ltd", "Visenta (Xiamen) Technology Co Ltd", "Roa Logic BV",
"NSITEXE Inc", "Hong Kong Hyunion Electronics", "ASK Technology Group Limited",
"GIGA-BYTE Technology Co Ltd", "Terabyte Co Ltd", "Hyundai Inc", "EXCELERAM",
"PsiKick", "Netac Technology Co Ltd", "PCCOOLER", "Jiangsu Huacun Electronic Technology",
"Shenzhen Micro Innovation Industry", "Beijing Tongfang Microelectronics Co",
"XZN Storage Technology", "ChipCraft Sp. z.o.o.", "ALLFLASH Technology Limited"],
["Foerd Technology Co Ltd", "KingSpec", "Codasip Ltd", "SL Link Co Ltd",
"Shenzhen Kefu Technology Co Limited", "Shenzhen ZST Electronics Technology",
"Kyokuto Electronic Inc", "Warrior Technology", "TRINAMIC Motion Control GmbH & Co",
"PixelDisplay Inc", "Shenzhen Futian District Bo Yueda Elec", "Richtek Power",
"Shenzhen LianTeng Electronics Co Ltd", "AITC Memory", "UNIC Memory Technology Co Ltd",
"Shenzhen Huafeng Science Technology", "Innotron Memory Co Ltd",
"Guangzhou Xinyi Heng Computer Trading Firm", "SambaNova Systems", "V-GEN",
"Jump Trading", "Ampere Computing", "Shenzhen Zhongshi Technology Co Ltd",
"Shenzhen Zhongtian Bozhong Technology", "Tri-Tech International",
"Silicon Intergrated Systems Corporation", "Shenzhen HongDingChen Information",
"Plexton Holdings Limited", "AMS (Jiangsu Advanced Memory Semi)",
"Wuhan Jing Tian Interconnected Tech Co", "Axia Memory Technology",
"Chipset Technology Holding Limited", "Shenzhen Xinshida Technology Co Ltd",
"Shenzhen Chuangshifeida Technology", "Guangzhou MiaoYuanJi Technology", "ADVAN Inc",
"Shenzhen Qianhai Weishengda Electronic Commerce Company Ltd", "Guangzhou Guang Xie Cheng Trading",
"StarRam International Co Ltd", "Shen Zhen XinShenHua Tech Co Ltd",
"UltraMemory Inc", "New Coastline Global Tech Industry Co", "Sinker", "Diamond",
"PUSKILL", "Guangzhou Hao Jia Ye Technology Co", "Ming Xin Limited", "Barefoot Networks",
"Biwin Semiconductor (HK) Co Ltd", "UD INFO Corporation", "Trek Technology (S) PTE Ltd",
"Xiamen Kingblaze Technology Co Ltd", "Shenzhen Lomica Technology Co Ltd",
"Nuclei System Technology Co Ltd", "Wuhan Xun Zhan Electronic Technology",
"Shenzhen Ingacom Semiconductor Ltd", "Zotac Technology Ltd", "Foxline",
"Shenzhen Farasia Science Technology", "Efinix Inc", "Hua Nan San Xian Technology Co Ltd",
"Goldtech Electronics Co Ltd", "Shanghai Han Rong Microelectronics Co",
"Shenzhen Zhongguang Yunhe Trading", "Smart Shine(QingDao) Microelectronics",
"Thermaltake Technology Co Ltd", "Shenzhen O'Yang Maile Technology Ltd", "UPMEM"]
);
$use_sysfs = -d '/sys/bus';
# We consider that no data was written to this area of the SPD EEPROM if
# all bytes read 0x00 or all bytes read 0xff
sub spd_written(@)
{
my $all_00 = 1;
my $all_ff = 1;
foreach my $b (@_) {
$all_00 = 0 unless $b == 0x00;
$all_ff = 0 unless $b == 0xff;
return 1 unless $all_00 or $all_ff;
}
return 0;
}
sub parity($)
{
my $n = shift;
my $parity = 0;
while ($n) {
$parity++ if ($n & 1);
$n >>= 1;
}
return ($parity & 1);
}
# The code byte includes parity, the count byte does not.
sub manufacturer_common($$)
{
my ($count, $code) = @_;
my $manufacturer;
return "Invalid" if parity($code) != 1
or ($code &= 0x7F) == 0;
return "Unknown" if $count >= @vendors
or $code - 1 >= @{$vendors[$count]};
$manufacturer = $vendors[$count][$code - 1];
$manufacturer =~ s/ \(former .*\)$// if $opt_side_by_side;
return $manufacturer;
}
# New encoding format (as of DDR3) for manufacturer just has a count of
# leading 0x7F rather than all the individual bytes. The count bytes includes
# parity!
sub manufacturer_ddr3($$)
{
my ($count, $code) = @_;
my $manufacturer;
return "Undefined" unless spd_written($count, $code);
$manufacturer = manufacturer_common($count & 0x7F, $code);
$manufacturer .= "? (Invalid parity)" if parity($count) != 1;
return $manufacturer;
}
sub manufacturer(@)
{
my @bytes = @_;
my $ai = 0;
my $first;
return ("Undefined", []) unless spd_written(@bytes);
while (defined($first = shift(@bytes)) && $first == 0x7F) {
$ai++;
}
return ("Invalid", []) unless defined $first;
return (manufacturer_common($ai, $first), \@bytes);
}
sub manufacturer_data(@)
{
my $hex = "";
my $asc = "";
return unless spd_written(@_);
foreach my $byte (@_) {
$hex .= sprintf("\%02X ", $byte);
$asc .= ($byte >= 32 && $byte < 127) ? chr($byte) : '?';
}
return "$hex(\"$asc\")";
}
sub part_number(@)
{
my $asc = "";
my $byte;
while (defined ($byte = shift) && $byte >= 32 && $byte < 127) {
$asc .= chr($byte);
}
return ($asc eq "") ? "Undefined" : $asc;
}
sub cas_latencies(@)
{
return "None" unless @_;
return join ', ', map("${_}T", sort { $b <=> $a } @_);
}
# Real printing functions
sub html_encode($)
{
my $text = shift;
$text =~ s/</\&lt;/sg;
$text =~ s/>/\&gt;/sg;
$text =~ s/ degrees C/\&deg;C/sg;
$text =~ s/\n/<br\/>\n/sg;
return $text;
}
sub same_values(@)
{
my $value = shift;
while (@_) {
return 0 unless $value eq shift;
}
return 1;
}
sub real_printl($$) # print a line w/ label and values
{
my ($label, @values) = @_;
local $_;
my $same_values = same_values(@values);
# If all values are N/A, don't bother printing
return if $values[0] eq "N/A" and $same_values;
if ($opt_html) {
$label = html_encode($label);
@values = map { html_encode($_) } @values;
print "<tr><td style=\"vertical-align: top;\">$label</td>";
if (!$opt_merge) {
print "<td>$_</td>" foreach @values;
} elsif ($same_values) {
print "<td colspan=\"".(scalar @values)."\">$values[0]</td>";
} else {
# For HTML output, merge adjacent cells even if
# the whole line cannot be merged.
my $colcnt = 0;
while (@values) {
$colcnt++;
my $value = shift @values;
next if (@values && $value eq $values[0]);
print "<td" . ($colcnt > 1 ? " colspan=\"$colcnt\"" : "") .">$value</td>";
$colcnt = 0;
}
}
print "</tr>\n";
} else {
if ($opt_merge && $same_values) {
splice(@values, 1);
}
my $format = "%-47s".((" %-".$sbs_col_width."s") x (scalar @values - 1))." %s\n";
my $maxl = 0; # Keep track of the max number of lines
# It's a bit tricky because each value may span over more than
# one line. We can easily extract the values per column, but
# we need them per line at printing time. So we have to
# prepare a 2D array with all the individual string fragments.
my ($col, @lines);
for ($col = 0; $col < @values; $col++) {
my @cells = split /\n/, $values[$col];
$maxl = @cells if @cells > $maxl;
for (my $l = 0; $l < @cells; $l++) {
$lines[$l]->[$col] = $cells[$l];
}
}
# Also make sure there are no holes in the array
for (my $l = 0; $l < $maxl; $l++) {
for ($col = 0; $col < @values; $col++) {
$lines[$l]->[$col] = ""
if not defined $lines[$l]->[$col];
}
}
printf $format, $label, @{shift @lines};
printf $format, "", @{$_} foreach (@lines);
}
}
sub printl2 # print a line w/ label and value (outside a table)
{
my ($label, $value, $style) = @_;
if ($opt_html) {
$label = html_encode($label);
$value = html_encode($value);
print "<p", (defined $style ? " style=\"$style\"" : ""), ">";
}
print "$label: $value\n";
print "</p>\n" if $opt_html;
}
sub real_prints($) # print separator w/ given text
{
my ($label, $ncol) = @_;
$ncol = 1 unless $ncol;
if ($opt_html) {
$label = html_encode($label);
print "<tr><td style=\"font-weight: bold; text-align: center;\" colspan=\"".(1+$ncol)."\">$label</td></tr>\n";
} else {
print "\n---=== $label ===---\n";
}
}
sub printh($$) # print header w/ given text
{
my ($header, $sub) = @_;
if ($opt_html) {
$header = html_encode($header);
$sub = html_encode($sub);
print "<h1>$header</h1>\n";
print "<p>$sub</p>\n";
} else {
print "\n$header\n$sub\n";
}
}
sub printc($) # print comment
{
my ($comment) = @_;
if ($opt_html) {
$comment = html_encode($comment);
print "<!-- $comment -->\n";
} else {
print "# $comment\n";
}
}
# Fake printing functions
# These don't actually print anything, instead they store the desired
# output for later processing.
sub printl($$) # print a line w/ label and value
{
my @output = (\&real_printl, @_);
push @{$dimm[$current]->{output}}, \@output;
}
sub printl_cond($$$) # same as printl but conditional
{
my ($cond, $label, $value) = @_;
return unless $cond || $opt_side_by_side;
printl($label, $cond ? $value : "N/A");
}
sub prints($) # print separator w/ given text
{
my @output = (\&real_prints, @_);
push @{$dimm[$current]->{output}}, \@output;
}
# Helper functions
sub tns1($) # print a time in ns, with 1 decimal digit
{
return sprintf("%.1f ns", $_[0]);
}
sub tns($) # print a time in ns, with 2 decimal digits
{
return sprintf("%3.2f ns", $_[0]);
}
sub tns3($) # print a time in ns, with 3 decimal digits
{
return sprintf("%.3f ns", $_[0]);
}
sub value_or_undefined
{
my ($value, $unit) = @_;
return "Undefined!" unless $value;
$value .= " $unit" if defined $unit;
return $value;
}
# Common to SDR, DDR and DDR2 SDRAM
sub sdram_voltage_interface_level($)
{
my @levels = (
"TTL (5V tolerant)", # 0
"LVTTL (not 5V tolerant)", # 1
"HSTL 1.5V", # 2
"SSTL 3.3V", # 3
"SSTL 2.5V", # 4
"SSTL 1.8V", # 5
);
return ($_[0] < @levels) ? $levels[$_[0]] : "Undefined!";
}
# Common to SDR, DDR and DDR2 SDRAM
sub sdram_module_configuration_type($)
{
my $byte = $_[0] & 0x07;
my @edc;
return "No Parity" if $byte == 0;
# Data ECC includes Data Parity so don't print both
push @edc, "Data Parity" if ($byte & 0x03) == 0x01;
push @edc, "Data ECC" if ($byte & 0x02);
# New in DDR2 specification
push @edc, "Address/Command Parity" if ($byte & 0x04);
return join ", ", @edc;
}
# Parameter: EEPROM bytes 0-127 (using 3-62 and 126-127)
sub decode_sdr_sdram($)
{
my $bytes = shift;
my $temp;
my ($ctime, $ctime1, $ctime2, $ctime_min);
# SPD revision
# Starting with SPD revision 1.2, this byte is encoded in BCD
printl("SPD Revision", $bytes->[62] < 0x12 ? $bytes->[62] :
($bytes->[62] >> 4) . "." . ($bytes->[62] & 0xf));
#size computation
prints("Memory Characteristics");
my $k = 0;
my $ii = 0;
$ii = ($bytes->[3] & 0x0f) + ($bytes->[4] & 0x0f) - 17;
if (($bytes->[5] <= 8) && ($bytes->[17] <= 8)) {
$k = $bytes->[5] * $bytes->[17];
}
if ($ii > 0 && $ii <= 12 && $k > 0) {
printl("Size", ((1 << $ii) * $k) . " MB");
} else {
printl("Size", "INVALID: " . $bytes->[3] . "," . $bytes->[4] . "," .
$bytes->[5] . "," . $bytes->[17]);
}
my @cas;
for ($ii = 0; $ii < 7; $ii++) {
push(@cas, $ii + 1) if ($bytes->[18] & (1 << $ii));
}
my $trcd;
my $trp;
my $tras;
$ctime_min = $ctime = ($bytes->[9] >> 4) + ($bytes->[9] & 0xf) * 0.1;
$trcd = $bytes->[29];
$trp = $bytes->[27];
$tras = $bytes->[30];
printl("tCL-tRCD-tRP-tRAS",
$cas[$#cas] . "-" .
ceil($trcd/$ctime) . "-" .
ceil($trp/$ctime) . "-" .
ceil($tras/$ctime));
if ($bytes->[3] == 0) { $temp = "Undefined!"; }
elsif ($bytes->[3] == 1) { $temp = "1/16"; }
elsif ($bytes->[3] == 2) { $temp = "2/17"; }
elsif ($bytes->[3] == 3) { $temp = "3/18"; }
else { $temp = $bytes->[3]; }
printl("Number of Row Address Bits", $temp);
if ($bytes->[4] == 0) { $temp = "Undefined!"; }
elsif ($bytes->[4] == 1) { $temp = "1/16"; }
elsif ($bytes->[4] == 2) { $temp = "2/17"; }
elsif ($bytes->[4] == 3) { $temp = "3/18"; }
else { $temp = $bytes->[4]; }
printl("Number of Col Address Bits", $temp);
printl("Number of Module Rows", value_or_undefined($bytes->[5]));
if ($bytes->[7] > 1) { $temp = "Undefined!"; }
else { $temp = ($bytes->[7] * 256) + $bytes->[6]; }
printl("Data Width", $temp);
printl("Voltage Interface Level",
sdram_voltage_interface_level($bytes->[8]));
printl("Module Configuration Type",
sdram_module_configuration_type($bytes->[11]));
printl("Refresh Rate", ddr2_refresh_rate($bytes->[12]));
if ($bytes->[13] & 0x80) { $temp = "Bank2 = 2 x Bank1"; }
else { $temp = "No Bank2 OR Bank2 = Bank1 width"; }
printl("Primary SDRAM Component Bank Config", $temp);
printl("Primary SDRAM Component Widths",
value_or_undefined($bytes->[13] & 0x7f));
if ($bytes->[14] & 0x80) { $temp = "Bank2 = 2 x Bank1"; }
else { $temp = "No Bank2 OR Bank2 = Bank1 width"; }
printl("Error Checking SDRAM Component Bank Config", $temp);
printl("Error Checking SDRAM Component Widths",
value_or_undefined($bytes->[14] & 0x7f));
printl("Min Clock Delay for Back to Back Random Access",
value_or_undefined($bytes->[15]));
my @array;
for ($ii = 0; $ii < 4; $ii++) {
push(@array, 1 << $ii) if ($bytes->[16] & (1 << $ii));
}
push(@array, "Page") if ($bytes->[16] & 128);
if (@array) { $temp = join ', ', @array; }
else { $temp = "None"; }
printl("Supported Burst Lengths", $temp);
printl("Number of Device Banks",
value_or_undefined($bytes->[17]));
printl("Supported CAS Latencies", cas_latencies(@cas));
@array = ();
for ($ii = 0; $ii < 7; $ii++) {
push(@array, $ii) if ($bytes->[19] & (1 << $ii));
}
if (@array) { $temp = join ', ', @array; }
else { $temp = "None"; }
printl("Supported CS Latencies", $temp);
@array = ();
for ($ii = 0; $ii < 7; $ii++) {
push(@array, $ii) if ($bytes->[20] & (1 << $ii));
}
if (@array) { $temp = join ', ', @array; }
else { $temp = "None"; }
printl("Supported WE Latencies", $temp);
my ($cycle_time, $access_time);
if (@cas >= 1) {
$cycle_time = "$ctime ns at CAS ".$cas[$#cas];
$temp = ($bytes->[10] >> 4) + ($bytes->[10] & 0xf) * 0.1;
$access_time = "$temp ns at CAS ".$cas[$#cas];
}
if (@cas >= 2 && spd_written(@$bytes[23..24])) {
$temp = $bytes->[23] >> 4;
if ($temp == 0) { $temp = "Undefined!"; }
else {
$temp += 15 if $temp < 4;
$temp += ($bytes->[23] & 0xf) * 0.1;
$ctime1 = $temp;
}
$cycle_time .= "\n$temp ns at CAS ".$cas[$#cas-1];
$temp = $bytes->[24] >> 4;
if ($temp == 0) { $temp = "Undefined!"; }
else {
$temp += 15 if $temp < 4;
$temp += ($bytes->[24] & 0xf) * 0.1;
}
$access_time .= "\n$temp ns at CAS ".$cas[$#cas-1];
}
if (@cas >= 3 && spd_written(@$bytes[25..26])) {
$temp = $bytes->[25] >> 2;
if ($temp == 0) { $temp = "Undefined!"; }
else {
$temp += ($bytes->[25] & 0x3) * 0.25;
$ctime2 = $temp;
}
$cycle_time .= "\n$temp ns at CAS ".$cas[$#cas-2];
$temp = $bytes->[26] >> 2;
if ($temp == 0) { $temp = "Undefined!"; }
else {
$temp += ($bytes->[26] & 0x3) * 0.25;
}
$access_time .= "\n$temp ns at CAS ".$cas[$#cas-2];
}
printl_cond(defined $cycle_time, "Cycle Time", $cycle_time);
printl_cond(defined $access_time, "Access Time", $access_time);
prints("Attributes");
$temp = "";
if ($bytes->[21] & 1) { $temp .= "Buffered Address/Control Inputs\n"; }
if ($bytes->[21] & 2) { $temp .= "Registered Address/Control Inputs\n"; }
if ($bytes->[21] & 4) { $temp .= "On card PLL (clock)\n"; }
if ($bytes->[21] & 8) { $temp .= "Buffered DQMB Inputs\n"; }
if ($bytes->[21] & 16) { $temp .= "Registered DQMB Inputs\n"; }
if ($bytes->[21] & 32) { $temp .= "Differential Clock Input\n"; }
if ($bytes->[21] & 64) { $temp .= "Redundant Row Address\n"; }
if ($bytes->[21] & 128) { $temp .= "Undefined (bit 7)\n"; }
printl_cond($bytes->[21], "SDRAM Module Attributes", $temp);
# standard DDR speeds
prints("Timings at Standard Speeds");
foreach $ctime (7.5, 10, 15) {
my $best_cas;
# Find min CAS latency at this speed
if (defined $ctime2 && $ctime >= $ctime2) {
$best_cas = $cas[$#cas-2];
} elsif (defined $ctime1 && $ctime >= $ctime1) {
$best_cas = $cas[$#cas-1];
} else {
$best_cas = $cas[$#cas];
}
printl_cond($ctime >= $ctime_min,
"tCL-tRCD-tRP-tRAS as PC" . int(1000 / $ctime),
ddr_core_timings($best_cas, $ctime,
$trcd, $trp, $tras));
}
$temp = "";
if ($bytes->[22] & 1) { $temp .= "Supports Early RAS# Recharge\n"; }
if ($bytes->[22] & 2) { $temp .= "Supports Auto-Precharge\n"; }
if ($bytes->[22] & 4) { $temp .= "Supports Precharge All\n"; }
if ($bytes->[22] & 8) { $temp .= "Supports Write1/Read Burst\n"; }
if ($bytes->[22] & 16) { $temp .= "Lower VCC Tolerance: 5%\n"; }
else { $temp .= "Lower VCC Tolerance: 10%\n"; }
if ($bytes->[22] & 32) { $temp .= "Upper VCC Tolerance: 5%\n"; }
else { $temp .= "Upper VCC Tolerance: 10%\n"; }
if ($bytes->[22] & 64) { $temp .= "Undefined (bit 6)\n"; }
if ($bytes->[22] & 128) { $temp .= "Undefined (bit 7)\n"; }
printl("SDRAM Device Attributes (General)", $temp);
prints("Timing Parameters");
printl("Minimum Row Precharge Time",
value_or_undefined($bytes->[27], "ns"));
printl("Row Active to Row Active Min",
value_or_undefined($bytes->[28], "ns"));
printl("RAS to CAS Delay",
value_or_undefined($bytes->[29], "ns"));
printl("Min RAS Pulse Width",
value_or_undefined($bytes->[30], "ns"));
$temp = "";
if ($bytes->[31] & 1) { $temp .= "4 MByte\n"; }
if ($bytes->[31] & 2) { $temp .= "8 MByte\n"; }
if ($bytes->[31] & 4) { $temp .= "16 MByte\n"; }
if ($bytes->[31] & 8) { $temp .= "32 MByte\n"; }
if ($bytes->[31] & 16) { $temp .= "64 MByte\n"; }
if ($bytes->[31] & 32) { $temp .= "128 MByte\n"; }
if ($bytes->[31] & 64) { $temp .= "256 MByte\n"; }
if ($bytes->[31] & 128) { $temp .= "512 MByte\n"; }
if ($bytes->[31] == 0) { $temp .= "(Undefined! -- None Reported!)\n"; }
printl("Row Densities", $temp);
$temp = (($bytes->[32] & 0x7f) >> 4) + ($bytes->[32] & 0xf) * 0.1;
printl_cond(($bytes->[32] & 0xf) <= 9,
"Command and Address Signal Setup Time",
(($bytes->[32] >> 7) ? -$temp : $temp) . " ns");
$temp = (($bytes->[33] & 0x7f) >> 4) + ($bytes->[33] & 0xf) * 0.1;
printl_cond(($bytes->[33] & 0xf) <= 9,
"Command and Address Signal Hold Time",
(($bytes->[33] >> 7) ? -$temp : $temp) . " ns");
$temp = (($bytes->[34] & 0x7f) >> 4) + ($bytes->[34] & 0xf) * 0.1;
printl_cond(($bytes->[34] & 0xf) <= 9, "Data Signal Setup Time",
(($bytes->[34] >> 7) ? -$temp : $temp) . " ns");
$temp = (($bytes->[35] & 0x7f) >> 4) + ($bytes->[35] & 0xf) * 0.1;
printl_cond(($bytes->[35] & 0xf) <= 9, "Data Signal Hold Time",
(($bytes->[35] >> 7) ? -$temp : $temp) . " ns");
# Last 2 bytes (126-127) are reserved, Intel used them as an extension
decode_intel_spec_freq($bytes);
}
sub as_ddr($$)
{
my ($gen, $ctime) = @_;
return " as DDR" . ($gen == 1 ? "" : $gen) . "-" .
int(2000 / $ctime);
}
sub ddr_core_timings($$$$$)
{
my ($cas, $ctime, $trcd, $trp, $tras) = @_;
return $cas . "-" . ceil($trcd/$ctime) . "-" . ceil($trp/$ctime) .
"-" . ceil($tras/$ctime);
}
# Parameter: EEPROM bytes 0-127 (using 3-62)
sub decode_ddr_sdram($)
{
my $bytes = shift;
my $temp;
my ($ctime, $ctime1, $ctime2, $ctime_min, $ctime_max);
# SPD revision
printl_cond($bytes->[62] != 0xff, "SPD Revision",
($bytes->[62] >> 4) . "." . ($bytes->[62] & 0xf));
# speed
prints("Memory Characteristics");
$ctime_min = $ctime = ($bytes->[9] >> 4) + ($bytes->[9] & 0xf) * 0.1;
my $ddrclk = 2 * (1000 / $ctime);
my $tbits = ($bytes->[7] * 256) + $bytes->[6];
if (($bytes->[11] == 2) || ($bytes->[11] == 1)) { $tbits = $tbits - 8; }
my $pcclk = int ($ddrclk * $tbits / 8);
$pcclk += 100 if ($pcclk % 100) >= 50; # Round properly
$pcclk = $pcclk - ($pcclk % 100);
$ddrclk = int ($ddrclk);
printl("Maximum module speed", "$ddrclk MHz (PC${pcclk})");
#size computation
my $k = 0;
my $ii = 0;
$ii = ($bytes->[3] & 0x0f) + ($bytes->[4] & 0x0f) - 17;
if (($bytes->[5] <= 8) && ($bytes->[17] <= 8)) {
$k = $bytes->[5] * $bytes->[17];
}
if ($ii > 0 && $ii <= 12 && $k > 0) {
printl("Size", ((1 << $ii) * $k) . " MB");
} else {
printl("Size", "INVALID: " . $bytes->[3] . ", " . $bytes->[4] . ", " .
$bytes->[5] . ", " . $bytes->[17]);
}
printl("Banks x Rows x Columns x Bits",
join(' x ', $bytes->[17], $bytes->[3], $bytes->[4], $bytes->[6]));
printl("Ranks", $bytes->[5]);
printl("Voltage Interface Level",
sdram_voltage_interface_level($bytes->[8]));
printl("Module Configuration Type",
sdram_module_configuration_type($bytes->[11]));
printl("Refresh Rate", ddr2_refresh_rate($bytes->[12]));
my $highestCAS = 0;
my %cas;
for ($ii = 0; $ii < 7; $ii++) {
if ($bytes->[18] & (1 << $ii)) {
$highestCAS = 1+$ii*0.5;
$cas{$highestCAS}++;
}
}
my $trcd;
my $trp;
my $tras;
$trcd = ($bytes->[29] >> 2) + (($bytes->[29] & 3) * 0.25);
$trp = ($bytes->[27] >> 2) + (($bytes->[27] & 3) * 0.25);
$tras = $bytes->[30];
# latencies
printl("Supported CAS Latencies", cas_latencies(keys %cas));
my @array;
for ($ii = 0; $ii < 7; $ii++) {
push(@array, $ii) if ($bytes->[19] & (1 << $ii));
}
if (@array) { $temp = join ', ', @array; }
else { $temp = "None"; }
printl("Supported CS Latencies", $temp);
@array = ();
for ($ii = 0; $ii < 7; $ii++) {
push(@array, $ii) if ($bytes->[20] & (1 << $ii));
}
if (@array) { $temp = join ', ', @array; }
else { $temp = "None"; }
printl("Supported WE Latencies", $temp);
# timings
my ($cycle_time, $access_time, $core_timings);
if (exists $cas{$highestCAS}) {
$core_timings = ddr_core_timings($highestCAS, $ctime,
$trcd, $trp, $tras) . as_ddr(1, $ctime);
$cycle_time = "$ctime ns at CAS $highestCAS";
$access_time = (($bytes->[10] >> 4) * 0.1 + ($bytes->[10] & 0xf) * 0.01)
. " ns at CAS $highestCAS";
}
if (exists $cas{$highestCAS-0.5} && spd_written(@$bytes[23..24])) {
$ctime1 = ($bytes->[23] >> 4) + ($bytes->[23] & 0xf) * 0.1;
$core_timings .= "\n".ddr_core_timings($highestCAS-0.5, $ctime1,
$trcd, $trp, $tras) . as_ddr(1, $ctime1);
$cycle_time .= "\n$ctime1 ns at CAS ".($highestCAS-0.5);
$access_time .= "\n".(($bytes->[24] >> 4) * 0.1 + ($bytes->[24] & 0xf) * 0.01)
. " ns at CAS ".($highestCAS-0.5);
}
if (exists $cas{$highestCAS-1} && spd_written(@$bytes[25..26])) {
$ctime2 = ($bytes->[25] >> 4) + ($bytes->[25] & 0xf) * 0.1,
$core_timings .= "\n".ddr_core_timings($highestCAS-1, $ctime2,
$trcd, $trp, $tras) . as_ddr(1, $ctime2);
$cycle_time .= "\n$ctime2 ns at CAS ".($highestCAS-1);
$access_time .= "\n".(($bytes->[26] >> 4) * 0.1 + ($bytes->[26] & 0xf) * 0.01)
. " ns at CAS ".($highestCAS-1);
}
$ctime_max = $bytes->[43] == 0xff ? 0 : $bytes->[43]/4;
printl_cond(defined $core_timings, "tCL-tRCD-tRP-tRAS", $core_timings);
printl_cond(defined $cycle_time, "Minimum Cycle Time", $cycle_time);
printl_cond(defined $access_time, "Maximum Access Time", $access_time);
printl_cond($bytes->[43] & 0xfc,
"Maximum Cycle Time (tCK max)",
$bytes->[43] == 0xff ? "No minimum frequency" :
$bytes->[43] == 0 ? "" : # Wouldn't be displayed, prevent div by 0
tns1($ctime_max)." (DDR-".int(8000 / $bytes->[43]).")");
# standard DDR speeds
prints("Timings at Standard Speeds");
foreach $ctime (5, 6, 7.5, 10) {
my $best_cas;
# Find min CAS latency at this speed
if (defined $ctime2 && $ctime >= $ctime2) {
$best_cas = $highestCAS-1;
} elsif (defined $ctime1 && $ctime >= $ctime1) {
$best_cas = $highestCAS-0.5;
} else {
$best_cas = $highestCAS;
}
printl_cond($ctime >= $ctime_min && ($ctime_max < 1 || $ctime <= $ctime_max),
"tCL-tRCD-tRP-tRAS" . as_ddr(1, $ctime),
ddr_core_timings($best_cas, $ctime,
$trcd, $trp, $tras));
}
# more timing information
prints("Timing Parameters");
printl_cond($bytes->[32] != 0xff,
"Address/Command Setup Time Before Clock",
tns(ddr2_sdram_atime($bytes->[32])));
printl_cond($bytes->[33] != 0xff,
"Address/Command Hold Time After Clock",
tns(ddr2_sdram_atime($bytes->[33])));
printl_cond($bytes->[34] != 0xff,
"Data Input Setup Time Before Clock",
tns(ddr2_sdram_atime($bytes->[34])));
printl_cond($bytes->[35] != 0xff,
"Data Input Hold Time After Clock",
tns(ddr2_sdram_atime($bytes->[35])));
printl("Minimum Row Precharge Delay (tRP)", tns($trp));
printl_cond($bytes->[28] & 0xfc,
"Minimum Row Active to Row Active Delay (tRRD)",
tns($bytes->[28]/4));
printl("Minimum RAS# to CAS# Delay (tRCD)", tns($trcd));
printl("Minimum RAS# Pulse Width (tRAS)", tns($tras));
printl_cond($bytes->[41] && $bytes->[41] != 0xff,
"Minimum Active to Active/AR Time (tRC)",
tns($bytes->[41]));
printl_cond($bytes->[42],
"Minimum AR to Active/AR Command Period (tRFC)",
tns($bytes->[42]));
printl_cond($bytes->[44],
"Maximum DQS to DQ Skew (tDQSQ)",
tns($bytes->[44]/100));
printl_cond(($bytes->[45] & 0xf0) && $bytes->[45] != 0xff,
"Maximum Read Data Hold Skew (tQHS)",
tns(ddr2_sdram_atime($bytes->[45])));
# module attributes
prints("Module Attributes");
if (($bytes->[47] & 0x03) == 0x01) { $temp = "1.125\" to 1.25\""; }
elsif (($bytes->[47] & 0x03) == 0x02) { $temp = "1.7\""; }
else { $temp = "Other"; }
printl_cond($bytes->[47] & 0x03, "Module Height", $temp);
}
sub ddr2_sdram_ctime($)
{
my $byte = shift;
my $ctime;
$ctime = $byte >> 4;
if (($byte & 0xf) <= 9) { $ctime += ($byte & 0xf) * 0.1; }
elsif (($byte & 0xf) == 10) { $ctime += 0.25; }
elsif (($byte & 0xf) == 11) { $ctime += 0.33; }
elsif (($byte & 0xf) == 12) { $ctime += 0.66; }
elsif (($byte & 0xf) == 13) { $ctime += 0.75; }
return $ctime;
}
sub ddr2_sdram_atime($)
{
my $byte = shift;
my $atime;
$atime = ($byte >> 4) * 0.1 + ($byte & 0xf) * 0.01;
return $atime;
}
# Base, high-bit, 3-bit fraction code
sub ddr2_sdram_rtime($$$)
{
my ($rtime, $msb, $ext) = @_;
my @table = (0, .25, .33, .50, .66, .75);
return $rtime + $msb * 256 + $table[$ext];
}
sub ddr2_module_types($)
{
my $byte = shift;
my @types = qw(RDIMM UDIMM SO-DIMM Micro-DIMM Mini-RDIMM Mini-UDIMM);
my @widths = (133.35, 133.25, 67.6, 45.5, 82.0, 82.0);
my @suptypes;
local $_;
foreach (0..5) {
push @suptypes, "$types[$_] ($widths[$_] mm)"
if ($byte & (1 << $_));
}
return @suptypes;
}
# Common to SDR, DDR and DDR2 SDRAM
sub ddr2_refresh_rate($)
{
my $byte = shift;
my @refresh = qw(Normal Reduced Reduced Extended Extended Extended);
my @refresht = (15.625, 3.9, 7.8, 31.3, 62.5, 125);
return "$refresh[$byte & 0x7f] ($refresht[$byte & 0x7f] us)".
($byte & 0x80 ? " - Self Refresh" : "");
}
# Parameter: EEPROM bytes 0-127 (using 3-62)
sub decode_ddr2_sdram($)
{
my $bytes = shift;
my $temp;
my ($ctime, $ctime1, $ctime2, $ctime_min, $ctime_max);
# SPD revision
printl_cond($bytes->[62] != 0xff, "SPD Revision",
($bytes->[62] >> 4) . "." . ($bytes->[62] & 0xf));
# speed
prints("Memory Characteristics");
$ctime_min = $ctime = ddr2_sdram_ctime($bytes->[9]);
my $ddrclk = 2 * (1000 / $ctime);
my $tbits = ($bytes->[7] * 256) + $bytes->[6];
if ($bytes->[11] & 0x03) { $tbits = $tbits - 8; }
my $pcclk = int ($ddrclk * $tbits / 8);
# Round down to comply with Jedec
$pcclk = $pcclk - ($pcclk % 100);
$ddrclk = int ($ddrclk);
printl("Maximum module speed", "$ddrclk MHz (PC2-${pcclk})");
#size computation
my $k = 0;
my $ii = 0;
$ii = ($bytes->[3] & 0x0f) + ($bytes->[4] & 0x0f) - 17;
$k = (($bytes->[5] & 0x7) + 1) * $bytes->[17];
if($ii > 0 && $ii <= 12 && $k > 0) {
printl("Size", ((1 << $ii) * $k) . " MB");
} else {
printl("Size", "INVALID: " . $bytes->[3] . "," . $bytes->[4] . "," .
$bytes->[5] . "," . $bytes->[17]);
}
printl("Banks x Rows x Columns x Bits",
join(' x ', $bytes->[17], $bytes->[3], $bytes->[4], $bytes->[6]));
printl("Ranks", ($bytes->[5] & 7) + 1);
printl("SDRAM Device Width", $bytes->[13]." bits");
my @heights = ('< 25.4', '25.4', '25.4 - 30.0', '30.0', '30.5', '> 30.5');
printl("Module Height", $heights[$bytes->[5] >> 5]." mm");
my @suptypes = ddr2_module_types($bytes->[20]);
printl("Module Type".(@suptypes > 1 ? 's' : ''), join(', ', @suptypes));
printl("DRAM Package", $bytes->[5] & 0x10 ? "Stack" : "Planar");
printl("Voltage Interface Level",
sdram_voltage_interface_level($bytes->[8]));
printl("Module Configuration Type",
sdram_module_configuration_type($bytes->[11]));
printl("Refresh Rate", ddr2_refresh_rate($bytes->[12]));
my @burst;
push @burst, 4 if ($bytes->[16] & 4);
push @burst, 8 if ($bytes->[16] & 8);
$burst[0] = 'None' if !@burst;
printl("Supported Burst Lengths", join(', ', @burst));
my $highestCAS = 0;
my %cas;
for ($ii = 2; $ii < 7; $ii++) {
if ($bytes->[18] & (1 << $ii)) {
$highestCAS = $ii;
$cas{$highestCAS}++;
}
}
my $trcd;
my $trp;
my $tras;
$trcd = ($bytes->[29] >> 2) + (($bytes->[29] & 3) * 0.25);
$trp = ($bytes->[27] >> 2) + (($bytes->[27] & 3) * 0.25);
$tras = $bytes->[30];
# latencies
printl("Supported CAS Latencies (tCL)", cas_latencies(keys %cas));
# timings
my ($cycle_time, $access_time, $core_timings);
if (exists $cas{$highestCAS}) {
$core_timings = ddr_core_timings($highestCAS, $ctime,
$trcd, $trp, $tras) . as_ddr(2, $ctime);
$cycle_time = tns($ctime) . " at CAS $highestCAS (tCK min)";
$access_time = tns(ddr2_sdram_atime($bytes->[10]))
. " at CAS $highestCAS (tAC)";
}
if (exists $cas{$highestCAS-1} && spd_written(@$bytes[23..24])) {
$ctime1 = ddr2_sdram_ctime($bytes->[23]);
$core_timings .= "\n".ddr_core_timings($highestCAS-1, $ctime1,
$trcd, $trp, $tras) . as_ddr(2, $ctime1);
$cycle_time .= "\n".tns($ctime1)
. " at CAS ".($highestCAS-1);
$access_time .= "\n".tns(ddr2_sdram_atime($bytes->[24]))
. " at CAS ".($highestCAS-1);
}
if (exists $cas{$highestCAS-2} && spd_written(@$bytes[25..26])) {
$ctime2 = ddr2_sdram_ctime($bytes->[25]);
$core_timings .= "\n".ddr_core_timings($highestCAS-2, $ctime2,
$trcd, $trp, $tras) . as_ddr(2, $ctime2);
$cycle_time .= "\n".tns($ctime2)
. " at CAS ".($highestCAS-2);
$access_time .= "\n".tns(ddr2_sdram_atime($bytes->[26]))
. " at CAS ".($highestCAS-2);
}
$ctime_max = ddr2_sdram_ctime($bytes->[43]);
printl_cond(defined $core_timings, "tCL-tRCD-tRP-tRAS", $core_timings);
printl_cond(defined $cycle_time, "Minimum Cycle Time", $cycle_time);
printl_cond(defined $access_time, "Maximum Access Time", $access_time);
printl_cond(($bytes->[43] & 0xf0) && $bytes->[43] != 0xff,
"Maximum Cycle Time (tCK max)",
$ctime_max == 0 ? "" : # Wouldn't be displayed, prevent div by 0
tns($ctime_max)." (DDR2-".int(2000 / $ctime_max).")");
# standard DDR2 speeds
prints("Timings at Standard Speeds");
foreach $ctime (1.875, 2.5, 3, 3.75, 5) {
my $best_cas;
# Find min CAS latency at this speed
if (defined $ctime2 && $ctime >= $ctime2) {
$best_cas = $highestCAS-2;
} elsif (defined $ctime1 && $ctime >= $ctime1) {
$best_cas = $highestCAS-1;
} else {
$best_cas = $highestCAS;
}
printl_cond($ctime >= $ctime_min && $ctime <= $ctime_max,
"tCL-tRCD-tRP-tRAS" . as_ddr(2,$ctime),
ddr_core_timings($best_cas, $ctime,
$trcd, $trp, $tras));
}
# more timing information
prints("Timing Parameters");
# According to the JEDEC standard, the four timings below can't be less
# than 0.1 ns, however we've seen memory modules code such values so
# handle them properly.
printl_cond($bytes->[32] && $bytes->[32] != 0xff,
"Address/Command Setup Time Before Clock (tIS)",
tns(ddr2_sdram_atime($bytes->[32])));
printl_cond($bytes->[33] && $bytes->[33] != 0xff,
"Address/Command Hold Time After Clock (tIH)",
tns(ddr2_sdram_atime($bytes->[33])));
printl_cond($bytes->[34] && $bytes->[34] != 0xff,
"Data Input Setup Time Before Strobe (tDS)",
tns(ddr2_sdram_atime($bytes->[34])));
printl_cond($bytes->[35] && $bytes->[35] != 0xff,
"Data Input Hold Time After Strobe (tDH)",
tns(ddr2_sdram_atime($bytes->[35])));
printl("Minimum Row Precharge Delay (tRP)", tns($trp));
printl_cond($bytes->[28] & 0xfc,
"Minimum Row Active to Row Active Delay (tRRD)",
tns($bytes->[28]/4));
printl("Minimum RAS# to CAS# Delay (tRCD)", tns($trcd));
printl("Minimum RAS# Pulse Width (tRAS)", tns($tras));
printl_cond($bytes->[36] & 0xfc,
"Write Recovery Time (tWR)",
tns($bytes->[36]/4));
printl_cond($bytes->[37] & 0xfc,
"Minimum Write to Read CMD Delay (tWTR)",
tns($bytes->[37]/4));
printl_cond($bytes->[38] & 0xfc,
"Minimum Read to Pre-charge CMD Delay (tRTP)",
tns($bytes->[38]/4));
printl_cond($bytes->[41] && $bytes->[41] != 0xff,
"Minimum Active to Auto-refresh Delay (tRC)",
tns(ddr2_sdram_rtime($bytes->[41], 0,
($bytes->[40] >> 4) & 7)));
printl_cond($bytes->[42],
"Minimum Recovery Delay (tRFC)",
tns(ddr2_sdram_rtime($bytes->[42], $bytes->[40] & 1,
($bytes->[40] >> 1) & 7)));
printl_cond($bytes->[44], "Maximum DQS to DQ Skew (tDQSQ)",
tns($bytes->[44]/100));
printl_cond($bytes->[45], "Maximum Read Data Hold Skew (tQHS)",
tns($bytes->[45]/100));
printl_cond($bytes->[46], "PLL Relock Time", $bytes->[46] . " us");
}
# Return combined time in ns
sub ddr3_mtb_ftb($$$$)
{
my ($byte1, $byte2, $mtb, $ftb) = @_;
# byte1 is unsigned in ns, but byte2 is signed in ps
$byte2 -= 0x100 if $byte2 & 0x80;
return $byte1 * $mtb + $byte2 * $ftb / 1000;
}
# Also works for DDR4
sub ddr3_reference_card($$)
{
my ($rrc, $ext) = @_;
my $alphabet = "ABCDEFGHJKLMNPRTUVWY";
my $ref = $rrc & 0x1f;
my $revision = $ext >> 5;
my $ref_card;
return "ZZ" if $ref == 0x1f;
$ref += 0x1f if $rrc & 0x80;
$revision = (($rrc >> 5) & 0x03) if $revision == 0;
if ($ref < length($alphabet)) {
# One letter reference card
$ref_card = substr($alphabet, $ref, 1);
} else {
# Two letter reference card
my $ref1 = int($ref / (length($alphabet)));
$ref -= length($alphabet) * $ref1;
$ref_card = substr($alphabet, $ref1, 1) .
substr($alphabet, $ref, 1);
}
return "$ref_card revision $revision";
}
sub ddr3_revision_number($)
{
my $h = $_[0] >> 4;
my $l = $_[0] & 0x0f;
# Decode as suggested by JEDEC Standard 21-C
return sprintf("%d", $l) if $h == 0;
return sprintf("%d.%d", $h, $l) if $h < 0xa;
return sprintf("%c%d", ord('A') + $h - 0xa, $l);
}
sub ddr3_device_type($)
{
my $byte = shift;
my $type = $byte & 0x80 ? "Non-Standard" : "Standard Monolithic";
my $die_count = ($byte >> 4) & 0x07;
my $loading = ($byte >> 2) & 0x03;
if ($die_count == 1) {
$type .= "\nSingle die";
} elsif ($die_count == 2) {
$type .= "\n2 die";
} elsif ($die_count == 3) {
$type .= "\n4 die";
} elsif ($die_count == 4) {
$type .= "\n8 die";
}
if ($loading == 1) {
$type .= "\nMulti load stack";
} elsif ($loading == 2) {
$type .= "\nSingle load stack";
}
return $type;
}
use constant DDR3_UNBUFFERED => 1;
use constant DDR3_REGISTERED => 2;
use constant DDR3_CLOCKED => 3;
use constant DDR3_LOAD_REDUCED => 4;
# Parameter: EEPROM bytes 0-127 (using 1-68)
sub decode_ddr3_sdram($)
{
my $bytes = shift;
my $temp;
my $ctime;
my ($ftb, $mtb);
my $ii;
my @module_types = (
{ type => "Undefined", width => "Unknown" },
{ type => "RDIMM", width => "133.35 mm", family => DDR3_REGISTERED },
{ type => "UDIMM", width => "133.35 mm", family => DDR3_UNBUFFERED },
{ type => "SO-DIMM", width => "67.6 mm", family => DDR3_UNBUFFERED },
{ type => "Micro-DIMM", width => "TBD", family => DDR3_UNBUFFERED },
{ type => "Mini-RDIMM", width => "82.0 mm", family => DDR3_REGISTERED },
{ type => "Mini-UDIMM", width => "82.0 mm", family => DDR3_UNBUFFERED },
{ type => "Mini-CDIMM", width => "67.6 mm", family => DDR3_CLOCKED },
{ type => "72b-SO-UDIMM", width => "67.6 mm", family => DDR3_UNBUFFERED },
{ type => "72b-SO-RDIMM", width => "67.6 mm", family => DDR3_REGISTERED },
{ type => "72b-SO-CDIMM", width => "67.6 mm", family => DDR3_CLOCKED },
{ type => "LRDIMM", width => "133.35 mm", family => DDR3_LOAD_REDUCED },
{ type => "16b-SO-DIMM", width => "67.6 mm", family => DDR3_UNBUFFERED },
{ type => "32b-SO-DIMM", width => "67.6 mm", family => DDR3_UNBUFFERED },
);
# SPD revision
printl_cond($bytes->[1] != 0xff, "SPD Revision",
($bytes->[1] >> 4) . "." . ($bytes->[1] & 0xf));
printl("Module Type", ($bytes->[3] <= $#module_types) ?
$module_types[$bytes->[3]]->{type} :
sprintf("Reserved (0x%.2X)", $bytes->[3]));
# time bases
if (($bytes->[9] & 0x0f) == 0 || $bytes->[11] == 0) {
print STDERR "Invalid time base divisor, can't decode\n";
return;
}
$ftb = ($bytes->[9] >> 4) / ($bytes->[9] & 0x0f);
$mtb = $bytes->[10] / $bytes->[11];
# speed
prints("Memory Characteristics");
$ctime = ddr3_mtb_ftb($bytes->[12], $bytes->[34], $mtb, $ftb);
# Starting with DDR3-1866, vendors may start approximating the
# minimum cycle time. Try to guess what they really meant so
# that the reported speed matches the standard.
for ($ii = 7; $ii < 15; $ii++) {
if ($ctime > 7.5/$ii - $ftb/1000 && $ctime < 7.5/$ii + $ftb/1000) {
$ctime = 7.5/$ii;
last;
}
}
my $ddrclk = 2 * (1000 / $ctime);
my $tbits = 1 << (($bytes->[8] & 7) + 3);
my $pcclk = int ($ddrclk * $tbits / 8);
# Round down to comply with Jedec
$pcclk = $pcclk - ($pcclk % 100);
$ddrclk = int ($ddrclk);
printl("Maximum module speed", "$ddrclk MHz (PC3-${pcclk})");
# Size computation
my $cap = ($bytes->[4] & 15) + 28;
$cap += ($bytes->[8] & 7) + 3;
$cap -= ($bytes->[7] & 7) + 2;
$cap -= 20 + 3;
my $k = (($bytes->[7] >> 3) & 31) + 1;
printl("Size", ((1 << $cap) * $k) . " MB");
printl("Banks x Rows x Columns x Bits",
join(' x ', 1 << ((($bytes->[4] >> 4) & 7) + 3),
((($bytes->[5] >> 3) & 31) + 12),
( ($bytes->[5] & 7) + 9),
( 1 << (($bytes->[8] & 7) + 3)) ));
printl("Ranks", $k);
printl("SDRAM Device Width", (1 << (($bytes->[7] & 7) + 2))." bits");
printl("Primary Bus Width", (8 << ($bytes->[8] & 7))." bits");
printl_cond($bytes->[8] & 24, "Bus Width Extension", ($bytes->[8] & 24)." bits");
my $taa;
my $trcd;
my $trp;
my $tras;
$taa = ddr3_mtb_ftb($bytes->[16], $bytes->[35], $mtb, $ftb);
$trcd = ddr3_mtb_ftb($bytes->[18], $bytes->[36], $mtb, $ftb);
$trp = ddr3_mtb_ftb($bytes->[20], $bytes->[37], $mtb, $ftb);
$tras = ((($bytes->[21] & 0x0f) << 8) + $bytes->[22]) * $mtb;
printl("tCL-tRCD-tRP-tRAS", ddr_core_timings(ceil($taa / $ctime), $ctime, $trcd, $trp, $tras));
# latencies
my $highestCAS = 0;
my %cas;
my $cas_sup = ($bytes->[15] << 8) + $bytes->[14];
for ($ii = 0; $ii < 15; $ii++) {
if ($cas_sup & (1 << $ii)) {
$highestCAS = $ii + 4;
$cas{$highestCAS}++;
}
}
printl("Supported CAS Latencies (tCL)", cas_latencies(keys %cas));
# standard DDR3 speeds
prints("Timings at Standard Speeds");
foreach my $ctime_at_speed (7.5/8, 7.5/7, 1.25, 1.5, 1.875, 2.5) {
my $best_cas = 0;
# Find min CAS latency at this speed
for ($ii = 14; $ii >= 0; $ii--) {
next unless ($cas_sup & (1 << $ii));
if (ceil($taa / $ctime_at_speed) <= $ii + 4) {
$best_cas = $ii + 4;
}
}
printl_cond($best_cas && $ctime_at_speed >= $ctime,
"tCL-tRCD-tRP-tRAS" . as_ddr(3, $ctime_at_speed),
ddr_core_timings($best_cas, $ctime_at_speed,
$trcd, $trp, $tras));
}
# more timing information
prints("Timing Parameters");
printl("Minimum Cycle Time (tCK)", tns3($ctime));
printl("Minimum CAS Latency Time (tAA)", tns3($taa));
printl("Minimum Write Recovery time (tWR)", tns3($bytes->[17] * $mtb));
printl("Minimum RAS# to CAS# Delay (tRCD)", tns3($trcd));
printl("Minimum Row Active to Row Active Delay (tRRD)",
tns3($bytes->[19] * $mtb));
printl("Minimum Row Precharge Delay (tRP)", tns3($trp));
printl("Minimum Active to Precharge Delay (tRAS)", tns3($tras));
printl("Minimum Active to Auto-Refresh Delay (tRC)",
tns3(ddr3_mtb_ftb((($bytes->[21] & 0xf0) << 4) + $bytes->[23], $bytes->[38], $mtb, $ftb)));
printl("Minimum Recovery Delay (tRFC)",
tns3((($bytes->[25] << 8) + $bytes->[24]) * $mtb));
printl("Minimum Write to Read CMD Delay (tWTR)",
tns3($bytes->[26] * $mtb));
printl("Minimum Read to Pre-charge CMD Delay (tRTP)",
tns3($bytes->[27] * $mtb));
printl("Minimum Four Activate Window Delay (tFAW)",
tns3(((($bytes->[28] & 15) << 8) + $bytes->[29]) * $mtb));
# miscellaneous stuff
prints("Optional Features");
my $volts = "1.5V";
if ($bytes->[6] & 1) {
$volts .= " tolerant";
}
if ($bytes->[6] & 2) {
$volts .= ", 1.35V ";
}
if ($bytes->[6] & 4) {
$volts .= ", 1.2X V";
}
printl("Operable voltages", $volts);
printl("RZQ/6 supported?", ($bytes->[30] & 1) ? "Yes" : "No");
printl("RZQ/7 supported?", ($bytes->[30] & 2) ? "Yes" : "No");
printl("DLL-Off Mode supported?", ($bytes->[30] & 128) ? "Yes" : "No");
printl("Operating temperature range", sprintf "0-%d degrees C",
($bytes->[31] & 1) ? 95 : 85);
printl_cond($bytes->[31] & 1,
"Refresh Rate in extended temp range",
($bytes->[31] & 2) ? "1X" : "2X");
printl("Auto Self-Refresh?", ($bytes->[31] & 4) ? "Yes" : "No");
printl("On-Die Thermal Sensor readout?",
($bytes->[31] & 8) ? "Yes" : "No");
printl("Partial Array Self-Refresh?",
($bytes->[31] & 128) ? "Yes" : "No");
printl("Module Thermal Sensor",
($bytes->[32] & 128) ? "Yes" : "No");
printl("SDRAM Device Type", ddr3_device_type($bytes->[33]));
# Following bytes are type-specific, so don't continue if type
# isn't known.
return if $bytes->[3] == 0 || $bytes->[3] > $#module_types;
if ($module_types[$bytes->[3]]->{family} == DDR3_UNBUFFERED ||
$module_types[$bytes->[3]]->{family} == DDR3_REGISTERED ||
$module_types[$bytes->[3]]->{family} == DDR3_CLOCKED ||
$module_types[$bytes->[3]]->{family} == DDR3_LOAD_REDUCED) {
prints("Physical Characteristics");
printl("Module Height", (($bytes->[60] & 31) + 15) . " mm");
printl("Module Thickness", sprintf("%d mm front, %d mm back",
($bytes->[61] & 15) + 1,
(($bytes->[61] >> 4) & 15) +1));
printl("Module Width", $module_types[$bytes->[3]]->{width});
printl("Module Reference Card", ddr3_reference_card($bytes->[62], $bytes->[60]));
printl_cond($module_types[$bytes->[3]]->{family} == DDR3_UNBUFFERED,
"Rank 1 Mapping", $bytes->[63] & 0x01 ? "Mirrored" : "Standard");
}
if ($module_types[$bytes->[3]]->{family} == DDR3_REGISTERED) {
prints("Registered DIMM");
my @rows = ("Undefined", 1, 2, 4);
printl("# DRAM Rows", $rows[($bytes->[63] >> 2) & 3]);
printl("# Registers", $rows[$bytes->[63] & 3]);
printl("Register manufacturer",
manufacturer_ddr3($bytes->[65], $bytes->[66]));
printl("Register device type",
(($bytes->[68] & 7) == 0) ? "SSTE32882" :
"Undefined");
printl_cond($bytes->[67] != 0xff,
"Register revision", ddr3_revision_number($bytes->[67]));
printl("Heat spreader", $bytes->[64] & 0x80 ? "Yes" : "No");
}
if ($module_types[$bytes->[3]]->{family} == DDR3_LOAD_REDUCED) {
prints("Load Reduced DIMM");
my @rows = ("Undefined", 1, 2, "Reserved");
printl("# DRAM Rows", $rows[($bytes->[63] >> 2) & 3]);
my @mirroring = ("None", "Odd ranks", "Reserved", "Reserved");
printl("Mirroring", $mirroring[$bytes->[63] & 3]);
printl("Rank Numbering", $bytes->[63] & 0x20 ? "Even only" : "Contiguous");
printl("Buffer Orientation", $bytes->[63] & 0x10 ? "Horizontal" : "Vertical");
printl("Register manufacturer",
manufacturer_ddr3($bytes->[65], $bytes->[66]));
printl_cond($bytes->[64] != 0xff,
"Buffer Revision", ddr3_revision_number($bytes->[64]));
printl("Heat spreader", $bytes->[63] & 0x80 ? "Yes" : "No");
}
}
# Return combined time in ns
sub ddr4_mtb_ftb($$$$)
{
my ($byte1, $byte2, $mtb, $ftb) = @_;
# byte1 is unsigned in ps, but byte2 is signed in ps
$byte2 -= 0x100 if $byte2 & 0x80;
return ($byte1 * $mtb + $byte2 * $ftb) / 1000;
}
# Rounded per DDR4 specifications
sub ddr4_core_timings($$$$$)
{
my ($cas, $ctime, $trcd, $trp, $tras) = @_;
return $cas . "-" . ceil($trcd/$ctime - 0.025) .
"-" . ceil($trp/$ctime - 0.025) .
"-" . ceil($tras/$ctime - 0.025);
}
use constant DDR4_UNBUFFERED => 1;
use constant DDR4_REGISTERED => 2;
use constant DDR4_LOAD_REDUCED => 4;
# Parameter: EEPROM bytes 0-383 (using 1-255)
sub decode_ddr4_sdram($)
{
my $bytes = shift;
my ($ctime, $ctime_max);
my ($ftb, $mtb);
my $ii;
my @module_types = (
{ type => "Extended type", },
{ type => "RDIMM", family => DDR4_REGISTERED },
{ type => "UDIMM", family => DDR4_UNBUFFERED },
{ type => "SO-DIMM", family => DDR4_UNBUFFERED },
{ type => "LRDIMM", family => DDR4_LOAD_REDUCED },
{ type => "Mini-RDIMM", family => DDR4_REGISTERED },
{ type => "Mini-UDIMM", family => DDR4_UNBUFFERED },
{ type => "Reserved (0x07)", },
{ type => "72b-SO-RDIMM", family => DDR4_REGISTERED },
{ type => "72b-SO-UDIMM", family => DDR4_UNBUFFERED },
{ type => "Reserved (0x0A)", },
{ type => "Reserved (0x0B)", },
{ type => "16b-SO-DIMM", family => DDR4_UNBUFFERED },
{ type => "32b-SO-DIMM", family => DDR4_UNBUFFERED },
{ type => "Reserved (0x0E)", },
{ type => "No base memory", },
);
# SPD revision
printl_cond($bytes->[1] != 0xff, "SPD Revision",
($bytes->[1] >> 4) . "." . ($bytes->[1] & 0xf));
printl("Module Type", $module_types[$bytes->[3] & 0x0f]->{type});
# CRC of block 1
my $crc_calc = calculate_crc($bytes, 128, 126);
my $crc_spd = ($bytes->[255] << 8) | $bytes->[254];
my $crc_block_1_ok = $crc_calc == $crc_spd;
printl("EEPROM CRC of bytes 128-253", $crc_block_1_ok ?
sprintf("OK (0x\%04X)", $crc_calc) :
sprintf("Bad\n(found 0x\%04X, calculated 0x\%04X)",
$crc_spd, $crc_calc));
# time bases
if (($bytes->[17] & 0x03) != 0x00 || ($bytes->[17] & 0xc0) != 0x00) {
print STDERR "Unknown time base values, can't decode\n";
return;
}
$ftb = 1; # ps
$mtb = 125; # ps
# speed
prints("Memory Characteristics");
$ctime = ddr4_mtb_ftb($bytes->[18], $bytes->[125], $mtb, $ftb);
$ctime_max = ddr4_mtb_ftb($bytes->[19], $bytes->[124], $mtb, $ftb);
my $ddrclk = 2 * (1000 / $ctime);
my $tbits = 8 << ($bytes->[13] & 7);
my $pcclk = int ($ddrclk * $tbits / 8);
# Round down to comply with Jedec
$pcclk = $pcclk - ($pcclk % 100);
$ddrclk = int ($ddrclk);
printl("Maximum module speed", "$ddrclk MHz (PC4-${pcclk})");
# Size computation
my $sdram_width = 4 << ($bytes->[12] & 0x07);
my $ranks = (($bytes->[12] >> 3) & 0x07) + 1;
my $signal_loading = $bytes->[6] & 0x03;
my $die_count = (($bytes->[6] >> 4) & 0x07) + 1;
my $cap = (256 << ($bytes->[4] & 0x0f)) / 8;
$cap *= (8 << ($bytes->[13] & 0x07)) / $sdram_width;
$cap *= $ranks;
$cap *= $die_count if $signal_loading == 0x02; # 3DS
printl("Size", $cap . " MB");
printl("Banks x Rows x Columns x Bits",
join(' x ', (1 << ($bytes->[4] >> 6)) * (4 << (($bytes->[4] >> 4) & 0x03)),
((($bytes->[5] >> 3) & 7) + 12),
( ($bytes->[5] & 7) + 9),
(8 << ($bytes->[13] & 0x07))));
printl("SDRAM Device Width", "$sdram_width bits");
printl("Ranks", $ranks);
printl_cond($ranks > 1, "Rank Mix",
$bytes->[12] & 0x40 ? "Asymmetrical" : "Symmetrical");
printl("Primary Bus Width", (8 << ($bytes->[13] & 7))." bits");
printl_cond($bytes->[13] & 0x18, "Bus Width Extension", ($bytes->[13] & 0x18)." bits");
my $taa;
my $trcd;
my $trp;
my $tras;
$taa = ddr4_mtb_ftb($bytes->[24], $bytes->[123], $mtb, $ftb);
$trcd = ddr4_mtb_ftb($bytes->[25], $bytes->[122], $mtb, $ftb);
$trp = ddr4_mtb_ftb($bytes->[26], $bytes->[121], $mtb, $ftb);
$tras = ((($bytes->[27] & 0x0f) << 8) + $bytes->[28]) * $mtb / 1000;
printl("AA-RCD-RP-RAS (cycles)",
ddr4_core_timings(ceil($taa/$ctime - 0.025), $ctime,
$trcd, $trp, $tras));
# latencies
my %cas;
my $cas_sup = ($bytes->[23] << 24) + ($bytes->[22] << 16) +
($bytes->[21] << 8) + $bytes->[20];
my $base_cas = $bytes->[23] & 0x80 ? 23 : 7;
for ($ii = 0; $ii < 30; $ii++) {
if ($cas_sup & (1 << $ii)) {
$cas{$base_cas + $ii}++;
}
}
printl("Supported CAS Latencies", cas_latencies(keys %cas));
# standard DDR4 speeds
prints("Timings at Standard Speeds");
foreach my $ctime_at_speed (15/24, 15/22, 15/20, 15/18, 15/16, 15/14, 15/12) {
my $best_cas = 0;
# Find min CAS latency at this speed
for ($ii = 29; $ii >= 0; $ii--) {
next unless ($cas_sup & (1 << $ii));
if (ceil($taa/$ctime_at_speed - 0.025) <= $base_cas + $ii) {
$best_cas = $base_cas + $ii;
}
}
printl_cond($best_cas && $ctime_at_speed >= $ctime
&& $ctime_at_speed <= $ctime_max,
"AA-RCD-RP-RAS (cycles)" . as_ddr(4, $ctime_at_speed),
ddr4_core_timings($best_cas, $ctime_at_speed,
$trcd, $trp, $tras));
}
# more timing information
prints("Timing Parameters");
printl("Minimum Cycle Time (tCKmin)", tns3($ctime));
printl("Maximum Cycle Time (tCKmax)", tns3($ctime_max));
printl("Minimum CAS Latency Time (tAA)", tns3($taa));
printl("Minimum RAS to CAS Delay (tRCD)", tns3($trcd));
printl("Minimum Row Precharge Delay (tRP)", tns3($trp));
printl("Minimum Active to Precharge Delay (tRAS)", tns3($tras));
printl("Minimum Active to Auto-Refresh Delay (tRC)",
tns3(ddr4_mtb_ftb((($bytes->[27] & 0xf0) << 4) + $bytes->[29],
$bytes->[120], $mtb, $ftb)));
printl("Minimum Recovery Delay (tRFC1)",
tns3((($bytes->[31] << 8) + $bytes->[30]) * $mtb / 1000));
printl("Minimum Recovery Delay (tRFC2)",
tns3((($bytes->[33] << 8) + $bytes->[32]) * $mtb / 1000));
printl("Minimum Recovery Delay (tRFC4)",
tns3((($bytes->[35] << 8) + $bytes->[34]) * $mtb / 1000));
printl("Minimum Four Activate Window Delay (tFAW)",
tns3(((($bytes->[36] & 0x0f) << 8) + $bytes->[37]) * $mtb / 1000));
printl("Minimum Row Active to Row Active Delay (tRRD_S)",
tns3(ddr4_mtb_ftb($bytes->[38], $bytes->[119], $mtb, $ftb)));
printl("Minimum Row Active to Row Active Delay (tRRD_L)",
tns3(ddr4_mtb_ftb($bytes->[39], $bytes->[118], $mtb, $ftb)));
printl("Minimum CAS to CAS Delay (tCCD_L)",
tns3(ddr4_mtb_ftb($bytes->[40], $bytes->[117], $mtb, $ftb)));
# Optional?
my $twr = ((($bytes->[41] & 0x0f) << 8) + $bytes->[42]) * $mtb / 1000;
printl_cond($twr, "Minimum Write Recovery Time (tWR)", tns3($twr));
my $twtr = ((($bytes->[43] & 0x0f) << 8) + $bytes->[44]) * $mtb / 1000;
printl_cond($twtr, "Minimum Write to Read Time (tWTR_S)", tns3($twtr));
$twtr = ((($bytes->[43] & 0xf0) << 4) + $bytes->[45]) * $mtb / 1000;
printl_cond($twtr, "Minimum Write to Read Time (tWTR_L)", tns3($twtr));
# miscellaneous stuff
prints("Other Information");
my $package_type = ($bytes->[6] & 0x80) == 0x00 ? "Monolithic" :
$signal_loading == 0x01 ? "Multi-load stack" :
$signal_loading == 0x02 ? "3DS" : "Unknown";
$package_type .= sprintf(" (%u dies)", $die_count) if $die_count >= 2;
printl("Package Type", $package_type);
my @mac = ("Untested",
"700 K", "600 K", "500 K", "400 K", "300 K", "200 K",
undef, "Unlimited");
my $mac = $bytes->[7] & 0x0f;
printl_cond(defined $mac[$mac], "Maximum Activate Count", $mac[$mac]);
my $ppr = $bytes->[9] >> 6;
printl("Post Package Repair",
$ppr == 0x00 ? "Not supported" :
$ppr == 0x01 ? "One row per bank group" : "Unknown");
printl_cond($ppr != 0x00, "Soft PPR", $bytes->[9] & 0x20 ?
"Supported" : "Not Supported");
printl("Module Nominal Voltage",
$bytes->[11] & 0x01 ? "1.2 V" :
$bytes->[11] & 0x02 ? "Unknown (1.2 V endurant)" : "Unknown");
printl("Thermal Sensor",
$bytes->[14] & 0x80 ? "TSE2004 compliant" : "No");
# type-specific settings
return unless $crc_block_1_ok || $opt_igncheck;
if ($module_types[$bytes->[3] & 0x0f]->{family} == DDR4_UNBUFFERED ||
$module_types[$bytes->[3] & 0x0f]->{family} == DDR4_REGISTERED ||
$module_types[$bytes->[3] & 0x0f]->{family} == DDR4_LOAD_REDUCED) {
prints("Physical Characteristics");
my $height = $bytes->[128] & 0x1f;
printl("Module Height",
$height == 0x00 ? "15 mm or less" :
$height == 0x1f ? "more than 45 mm" :
sprintf("%u mm", $height + 15));
printl("Module Thickness",
sprintf("%d mm front, %d mm back",
($bytes->[129] & 0x0f) + 1,
(($bytes->[129] >> 4) & 15) + 1));
printl("Module Reference Card",
ddr3_reference_card($bytes->[130], $bytes->[128]));
}
}
# Parameter: EEPROM bytes 0-127 (using 4-5)
sub decode_direct_rambus($)
{
my $bytes = shift;
#size computation
prints("Memory Characteristics");
my $ii;
$ii = ($bytes->[4] & 0x0f) + ($bytes->[4] >> 4) + ($bytes->[5] & 0x07) - 13;
if ($ii > 0 && $ii < 16) {
printl("Size", (1 << $ii) . " MB");
} else {
printl("Size", sprintf("INVALID: 0x%02x, 0x%02x",
$bytes->[4], $bytes->[5]));
}
}
# Parameter: EEPROM bytes 0-127 (using 3-5)
sub decode_rambus($)
{
my $bytes = shift;
#size computation
prints("Memory Characteristics");
my $ii;
$ii = ($bytes->[3] & 0x0f) + ($bytes->[3] >> 4) + ($bytes->[5] & 0x07) - 13;
if ($ii > 0 && $ii < 16) {
printl("Size", (1 << $ii) . " MB");
} else {
printl("Size", "INVALID: " . sprintf("0x%02x, 0x%02x",
$bytes->[3], $bytes->[5]));
}
}
%decode_callback = (
"SDR SDRAM" => \&decode_sdr_sdram,
"DDR SDRAM" => \&decode_ddr_sdram,
"DDR2 SDRAM" => \&decode_ddr2_sdram,
"DDR3 SDRAM" => \&decode_ddr3_sdram,
"DDR4 SDRAM" => \&decode_ddr4_sdram,
"DDR4E SDRAM" => \&decode_ddr4_sdram,
"LPDDR4 SDRAM" => \&decode_ddr4_sdram,
"LPDDR4X SDRAM" => \&decode_ddr4_sdram,
"Direct Rambus" => \&decode_direct_rambus,
"Rambus" => \&decode_rambus,
);
# Parameter: Manufacturing year/week bytes
sub manufacture_date($$)
{
my ($year, $week) = @_;
# In theory the year and week are in BCD format, but
# this is not always true in practice :(
if (($year & 0xf0) <= 0x90 && ($year & 0x0f) <= 0x09
&& ($week & 0xf0) <= 0x90 && ($week & 0x0f) <= 0x09) {
# Note that this heuristic will break in year 2080
return sprintf("%d%02X-W%02X",
$year >= 0x80 ? 19 : 20, $year, $week);
# Fallback to binary format if it seems to make sense
} elsif ($year <= 99 && $week >= 1 && $week <= 53) {
return sprintf("%d%02d-W%02d",
$year >= 80 ? 19 : 20, $year, $week);
} else {
return sprintf("0x%02X%02X", $year, $week);
}
}
sub printl_mfg_location_code($)
{
my $code = shift;
my $letter = chr($code);
# Try the location code as ASCII first, as earlier specifications
# suggested this. As newer specifications don't mention it anymore,
# we still fall back to binary.
printl_cond(spd_written($code), "Manufacturing Location Code",
$letter =~ m/^[\w\d]$/ ? $letter : sprintf("0x%.2X", $code));
}
sub printl_mfg_assembly_serial(@)
{
printl_cond(spd_written(@_), "Assembly Serial Number",
sprintf("0x%02X%02X%02X%02X", @_));
}
# Parameter: EEPROM bytes 0-175 (using 117-149)
sub decode_ddr3_mfg_data($)
{
my $bytes = shift;
prints("Manufacturer Data");
printl("Module Manufacturer",
manufacturer_ddr3($bytes->[117], $bytes->[118]));
printl_cond(spd_written(@{$bytes}[148..149]),
"DRAM Manufacturer",
manufacturer_ddr3($bytes->[148], $bytes->[149]));
printl_mfg_location_code($bytes->[119]);
printl_cond(spd_written(@{$bytes}[120..121]),
"Manufacturing Date",
manufacture_date($bytes->[120], $bytes->[121]));
printl_mfg_assembly_serial(@{$bytes}[122..125]);
printl("Part Number", part_number(@{$bytes}[128..145]));
printl_cond(spd_written(@{$bytes}[146..147]),
"Revision Code",
sprintf("0x%02X%02X", $bytes->[146], $bytes->[147]));
}
# Parameter: EEPROM bytes 0-383 (using 320-351)
sub decode_ddr4_mfg_data($)
{
my $bytes = shift;
prints("Manufacturer Data");
printl("Module Manufacturer",
manufacturer_ddr3($bytes->[320], $bytes->[321]));
printl_cond(spd_written(@{$bytes}[350..351]),
"DRAM Manufacturer",
manufacturer_ddr3($bytes->[350], $bytes->[351]));
printl_mfg_location_code($bytes->[322]);
printl_cond(spd_written(@{$bytes}[323..324]),
"Manufacturing Date",
manufacture_date($bytes->[323], $bytes->[324]));
printl_mfg_assembly_serial(@{$bytes}[325..328]);
printl("Part Number", part_number(@{$bytes}[329..348]));
printl_cond(spd_written(@{$bytes}[349]),
"Revision Code",
sprintf("0x%02X", $bytes->[349]));
}
# Parameter: EEPROM bytes 0-127 (using 64-98)
sub decode_manufacturing_information($)
{
my $bytes = shift;
my ($temp, $extra);
prints("Manufacturing Information");
# $extra is a reference to an array containing up to
# 7 extra bytes from the Manufacturer field. Sometimes
# these bytes are filled with interesting data.
($temp, $extra) = manufacturer(@{$bytes}[64..71]);
printl("Manufacturer", $temp);
$temp = manufacturer_data(@{$extra});
printl_cond(defined $temp, "Custom Manufacturer Data", $temp);
printl_mfg_location_code($bytes->[72]);
printl("Part Number", part_number(@{$bytes}[73..90]));
printl_cond(spd_written(@{$bytes}[91..92]), "Revision Code",
sprintf("0x%02X%02X", @{$bytes}[91..92]));
printl_cond(spd_written(@{$bytes}[93..94]), "Manufacturing Date",
manufacture_date($bytes->[93], $bytes->[94]));
printl_mfg_assembly_serial(@{$bytes}[95..98]);
}
# Parameter: EEPROM bytes 0-127 (using 126-127)
sub decode_intel_spec_freq($)
{
my $bytes = shift;
my $temp;
prints("Intel Specification");
if ($bytes->[126] == 0x66) { $temp = "66 MHz"; }
elsif ($bytes->[126] == 100) { $temp = "100 MHz or 133 MHz"; }
elsif ($bytes->[126] == 133) { $temp = "133 MHz"; }
else { $temp = "Undefined!"; }
printl("Frequency", $temp);
$temp = "";
if ($bytes->[127] & 1) { $temp .= "Intel Concurrent Auto-precharge\n"; }
if ($bytes->[127] & 2) { $temp .= "CAS Latency = 2\n"; }
if ($bytes->[127] & 4) { $temp .= "CAS Latency = 3\n"; }
if ($bytes->[127] & 8) { $temp .= "Junction Temp A (100 degrees C)\n"; }
else { $temp .= "Junction Temp B (90 degrees C)\n"; }
if ($bytes->[127] & 16) { $temp .= "CLK 3 Connected\n"; }
if ($bytes->[127] & 32) { $temp .= "CLK 2 Connected\n"; }
if ($bytes->[127] & 64) { $temp .= "CLK 1 Connected\n"; }
if ($bytes->[127] & 128) { $temp .= "CLK 0 Connected\n"; }
if (($bytes->[127] & 192) == 192) { $temp .= "Double-sided DIMM\n"; }
elsif (($bytes->[127] & 192) != 0) { $temp .= "Single-sided DIMM\n"; }
printl("Details for 100 MHz Support", $temp);
}
# Read various hex dump style formats: hexdump, hexdump -C, i2cdump, eeprog
# note that normal 'hexdump' format on a little-endian system byte-swaps
# words, using hexdump -C is better.
sub read_hexdump($)
{
my $addr = 0;
my $repstart = 0;
my @bytes;
my $header = 1;
my $word = 0;
# Look in the cache first
return @{$hexdump_cache{$_[0]}} if exists $hexdump_cache{$_[0]};
open F, '<', $_[0] or die "Unable to open: $_[0]";
while (<F>) {
chomp;
if (/^\*$/) {
$repstart = $addr;
next;
}
/^(?:0000 )?([a-f\d]{2,8}):?\s+((:?[a-f\d]{4}\s*){8}|(:?[a-f\d]{2}\s*){16})/i ||
/^(?:0000 )?([a-f\d]{2,8}):?\s*$/i;
next if (!defined $1 && $header); # skip leading unparsed lines
defined $1 or die "Unable to parse input";
$header = 0;
$addr = hex $1;
if ($repstart) {
@bytes[$repstart .. ($addr-1)] =
(@bytes[($repstart-16)..($repstart-1)]) x (($addr-$repstart)/16);
$repstart = 0;
}
last unless defined $2;
foreach (split(/\s+/, $2)) {
if (/^(..)(..)$/) {
$word |= 1;
if ($use_hexdump eq LITTLEENDIAN) {
$bytes[$addr++] = hex($2);
$bytes[$addr++] = hex($1);
} else {
$bytes[$addr++] = hex($1);
$bytes[$addr++] = hex($2);
}
} else {
$bytes[$addr++] = hex($_);
}
}
}
close F;
$header and die "Unable to parse any data from hexdump '$_[0]'";
$word and printc("Using $use_hexdump 16-bit hex dump");
# Cache the data for later use
$hexdump_cache{$_[0]} = \@bytes;
return @bytes;
}
# Returns the (total, used) number of bytes in the EEPROM,
# assuming it is a non-Rambus SPD EEPROM.
sub spd_sizes($)
{
my $bytes = shift;
my $type = $bytes->[2];
if ($type == 12 || $type == 14 || $type == 16 || $type == 17) {
# DDR4
my $spd_len = 256 * (($bytes->[0] >> 4) & 7);
my $used = 128 * ($bytes->[0] & 15);
return ($spd_len, $used);
} elsif ($type >= 9) {
# For FB-DIMM and newer, decode number of bytes written
my $spd_len = ($bytes->[0] >> 4) & 7;
my $size = 64 << ($bytes->[0] & 15);
if ($spd_len == 0) {
return ($size, 128);
} elsif ($spd_len == 1) {
return ($size, 176);
} elsif ($spd_len == 2) {
return ($size, 256);
} else {
return (64, 64);
}
} else {
my $size;
if ($bytes->[1] <= 14) {
$size = 1 << $bytes->[1];
} elsif ($bytes->[1] == 0) {
$size = "RFU";
} else { $size = "ERROR!" }
return ($size, ($bytes->[0] < 64) ? 64 : $bytes->[0]);
}
}
# Read bytes from SPD-EEPROM
# Note: offset must be a multiple of 16!
sub readspd($$$)
{
my ($offset, $size, $dimm_i) = @_;
my @bytes;
if ($use_hexdump) {
@bytes = read_hexdump($dimm_i);
return @bytes[$offset..($offset + $size - 1)];
} elsif ($use_sysfs) {
# Kernel 2.6 with sysfs
sysopen(HANDLE, "$dimm_i/eeprom", O_RDONLY)
or die "Cannot open $dimm_i/eeprom";
binmode HANDLE;
sysseek(HANDLE, $offset, SEEK_SET)
or die "Cannot seek $dimm_i/eeprom";
sysread(HANDLE, my $eeprom, $size)
or die "Cannot read $dimm_i/eeprom";
close HANDLE;
@bytes = unpack("C*", $eeprom);
} else {
# Kernel 2.4 with procfs
for my $i (0 .. ($size-1)/16) {
my $hexoff = sprintf('%02x', $offset + $i * 16);
push @bytes, split(" ", `cat $dimm_i/$hexoff`);
}
}
return @bytes;
}
# Calculate and verify checksum of first 63 bytes
sub checksum($)
{
my $bytes = shift;
my $dimm_checksum = 0;
local $_;
$dimm_checksum += $bytes->[$_] foreach (0 .. 62);
$dimm_checksum &= 0xff;
return ("EEPROM Checksum of bytes 0-62",
($bytes->[63] == $dimm_checksum) ? 1 : 0,
sprintf('0x%02X', $bytes->[63]),
sprintf('0x%02X', $dimm_checksum));
}
# Calculate and verify CRC
sub calculate_crc($$$)
{
my ($bytes, $start, $len) = @_;
my $crc = 0;
my $crc_ptr = $start;
my $crc_bit;
while ($crc_ptr < $start + $len) {
$crc = $crc ^ ($bytes->[$crc_ptr] << 8);
for ($crc_bit = 0; $crc_bit < 8; $crc_bit++) {
if ($crc & 0x8000) {
$crc = ($crc << 1) ^ 0x1021;
} else {
$crc = $crc << 1
}
}
$crc_ptr++;
}
return $crc & 0xffff;
}
sub check_crc($)
{
my $bytes = shift;
my $crc_cover = $bytes->[0] & 0x80 ? 116 : 125;
my $crc = calculate_crc($bytes, 0, $crc_cover + 1);
my $dimm_crc = ($bytes->[127] << 8) | $bytes->[126];
return ("EEPROM CRC of bytes 0-$crc_cover",
($dimm_crc == $crc) ? 1 : 0,
sprintf("0x%04X", $dimm_crc),
sprintf("0x%04X", $crc));
}
# Parse command-line
foreach (@ARGV) {
if ($_ eq '-h' || $_ eq '--help') {
print "Usage: $0 [-c] [-f [-b]] [-x|-X file [files..]]\n",
" $0 -h\n\n",
" -f, --format Print nice html output\n",
" -b, --bodyonly Don't print html header\n",
" (useful for postprocessing the output)\n",
" --side-by-side Display all DIMMs side-by-side if possible\n",
" --merge-cells Merge neighbour cells with identical values\n",
" (side-by-side output only, default)\n",
" --no-merge-cells Don't merge neighbour cells with identical values\n",
" (side-by-side output only)\n",
" -c, --checksum Decode completely even if checksum fails\n",
" -x, Read data from hexdump files\n",
" -X, Same as -x except treat multibyte hex\n",
" data as little endian\n",
" -h, --help Display this usage summary\n";
print <<"EOF";
Hexdumps can be the output from hexdump, hexdump -C, i2cdump, eeprog and
likely many other progams producing hex dumps of one kind or another. Note
that the default output of "hexdump" will be byte-swapped on little-endian
systems and you must use -X instead of -x, otherwise the dump will not be
parsed correctly. It is better to use "hexdump -C", which is not ambiguous.
EOF
exit;
}
if ($_ eq '-f' || $_ eq '--format') {
$opt_html = 1;
next;
}
if ($_ eq '-b' || $_ eq '--bodyonly') {
$opt_bodyonly = 1;
next;
}
if ($_ eq '--side-by-side') {
$opt_side_by_side = 1;
next;
}
if ($_ eq '--merge-cells') {
$opt_merge = 1;
next;
}
if ($_ eq '--no-merge-cells') {
$opt_merge = 0;
next;
}
if ($_ eq '-c' || $_ eq '--checksum') {
$opt_igncheck = 1;
next;
}
if ($_ eq '-x') {
$use_hexdump = BIGENDIAN;
next;
}
if ($_ eq '-X') {
$use_hexdump = LITTLEENDIAN;
next;
}
if (m/^-/) {
print STDERR "Unrecognized option $_\n";
exit;
}
push @dimm, { eeprom => basename($_), file => $_ } if $use_hexdump;
}
# Default values
$opt_merge = 1 unless defined $opt_merge;
# From a sysfs device path and an attribute name, return the attribute
# value, or undef (stolen from sensors-detect)
sub sysfs_device_attribute
{
my ($device, $attr) = @_;
my $value;
open(local *FILE, "$device/$attr") or return "";
$value = <FILE>;
close(FILE);
return unless defined $value;
chomp($value);
return $value;
}
sub get_dimm_list
{
my (@dirs, $dir, $opened, $file, @files);
if ($use_sysfs) {
@dirs = ('/sys/bus/i2c/drivers/eeprom',
'/sys/bus/i2c/drivers/at24',
'/sys/bus/i2c/drivers/ee1004'); # DDR4
} else {
@dirs = ('/proc/sys/dev/sensors');
}
foreach $dir (@dirs) {
next unless opendir(local *DIR, $dir);
$opened++;
while (defined($file = readdir(DIR))) {
if ($use_sysfs) {
# We look for I2C devices like 0-0050 or 2-0051
next unless $file =~ /^\d+-[\da-f]+$/i;
next unless -d "$dir/$file";
# Device name must be eeprom (driver eeprom)
# spd (driver at24) or ee1004 (driver ee1004)
my $attr = sysfs_device_attribute("$dir/$file", "name");
next unless defined $attr &&
($attr eq "eeprom" ||
$attr eq "spd" ||
$attr eq "ee1004"); # DDR4
} else {
next unless $file =~ /^eeprom-/;
}
push @files, { eeprom => "$file",
file => "$dir/$file" };
}
close(DIR);
}
if (!$opened) {
print STDERR "No EEPROM found, try loading the eeprom, at24 or ee1004 module\n";
exit;
}
return sort { $a->{file} cmp $b->{file} } @files;
}
# @dimm is a list of hashes. There's one hash for each EEPROM we found.
# Each hash has the following keys:
# * eeprom: Name of the eeprom data file
# * file: Full path to the eeprom data file
# * bytes: The EEPROM data (array)
# * is_rambus: Whether this is a RAMBUS DIMM or not (boolean)
# * chk_label: The label to display for the checksum or CRC
# * chk_valid: Whether the checksum or CRC is valid or not (boolean)
# * chk_spd: The checksum or CRC value found in the EEPROM
# * chk_calc: The checksum or CRC computed from the EEPROM data
# Keys are added over time.
@dimm = get_dimm_list() unless $use_hexdump;
for my $i (0 .. $#dimm) {
my @bytes = readspd(0, 128, $dimm[$i]->{file});
$dimm[$i]->{bytes} = \@bytes;
$dimm[$i]->{is_rambus} = $bytes[0] < 4; # Simple heuristic
if ($dimm[$i]->{is_rambus} || $bytes[2] < 9) {
($dimm[$i]->{chk_label}, $dimm[$i]->{chk_valid},
$dimm[$i]->{chk_spd}, $dimm[$i]->{chk_calc}) =
checksum(\@bytes);
} else {
($dimm[$i]->{chk_label}, $dimm[$i]->{chk_valid},
$dimm[$i]->{chk_spd}, $dimm[$i]->{chk_calc}) =
check_crc(\@bytes);
}
}
# Checksum or CRC validation
if (!$opt_igncheck) {
for (my $i = 0; $i < @dimm; ) {
if ($dimm[$i]->{chk_valid}) {
$i++;
} else {
splice(@dimm, $i, 1);
}
}
}
if ($opt_html && !$opt_bodyonly) {
print "<!DOCTYPE html PUBLIC '-//W3C//DTD XHTML 1.1//EN' \"http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd\">\n\n",
"<html xmlns=\"http://www.w3.org/1999/xhtml\" lang=\"en\">\n",
"<head>\n",
"\t<meta http-equiv=\"Content-Type\" content=\"text/html; charset=iso-8859-1\" />\n",
"\t<title>PC DIMM Serial Presence Detect Tester/Decoder Output</title>\n",
"</head>\n\n",
"<body>\n";
}
printc("decode-dimms version $revision");
printh('Memory Serial Presence Detect Decoder',
'By Philip Edelbrock, Christian Zuckschwerdt, Burkart Lingner,
Jean Delvare, Trent Piepho and others');
# Process the valid entries
for $current (0 .. $#dimm) {
my @bytes = @{$dimm[$current]->{bytes}};
if ($opt_side_by_side) {
printl("Decoding EEPROM", $dimm[$current]->{eeprom});
}
if (!$use_hexdump) {
if ($dimm[$current]->{file} =~ /-([\da-f]+)$/i) {
my $dimm_num = hex($1) - 0x50 + 1;
if ($dimm_num >= 1 && $dimm_num <= 8) {
printl("Guessing DIMM is in", "bank $dimm_num");
}
}
}
# Decode first 3 bytes (0-2)
prints("SPD EEPROM Information");
printl($dimm[$current]->{chk_label}, ($dimm[$current]->{chk_valid} ?
sprintf("OK (%s)", $dimm[$current]->{chk_calc}) :
sprintf("Bad\n(found %s, calculated %s)",
$dimm[$current]->{chk_spd}, $dimm[$current]->{chk_calc})));
my $temp;
if ($dimm[$current]->{is_rambus}) {
if ($bytes[0] == 1) { $temp = "0.7"; }
elsif ($bytes[0] == 2) { $temp = "1.0"; }
elsif ($bytes[0] == 0) { $temp = "Invalid"; }
else { $temp = "Reserved"; }
printl("SPD Revision", $temp);
} else {
my ($spd_size, $spd_used) = spd_sizes(\@bytes);
printl("# of bytes written to SDRAM EEPROM", $spd_used);
printl("Total number of bytes in EEPROM", $spd_size);
# If there's more data than what we've read, let's
# read it now. DDR3 will need this data.
if ($spd_used > @bytes) {
push (@bytes,
readspd(@bytes, $spd_used - @bytes,
$dimm[$current]->{file}));
}
}
my $type = sprintf("Unknown (0x%02x)", $bytes[2]);
if ($dimm[$current]->{is_rambus}) {
if ($bytes[2] == 1) { $type = "Direct Rambus"; }
elsif ($bytes[2] == 17) { $type = "Rambus"; }
} else {
my @type_list = (
"Reserved", "FPM DRAM", # 0, 1
"EDO", "Pipelined Nibble", # 2, 3
"SDR SDRAM", "Multiplexed ROM", # 4, 5
"DDR SGRAM", "DDR SDRAM", # 6, 7
"DDR2 SDRAM", "FB-DIMM", # 8, 9
"FB-DIMM Probe", "DDR3 SDRAM", # 10, 11
"DDR4 SDRAM", "Reserved", # 12, 13
"DDR4E SDRAM", "LPDDR3 SDRAM", # 14, 15
"LPDDR4 SDRAM", "LPDDR4X SDRAM", # 16, 17
);
if ($bytes[2] < @type_list) {
$type = $type_list[$bytes[2]];
}
}
printl("Fundamental Memory type", $type);
# Decode next 61 bytes (3-63, depend on memory type)
$decode_callback{$type}->(\@bytes)
if exists $decode_callback{$type};
if ($type eq "DDR3 SDRAM") {
# Decode DDR3-specific manufacturing data in bytes
# 117-149
decode_ddr3_mfg_data(\@bytes)
} elsif ($type eq "DDR4 SDRAM" ||
$type eq "DDR4E SDRAM" ||
$type eq "LPDDR4 SDRAM" ||
$type eq "LPDDR4X SDRAM") {
# Decode DDR4-specific manufacturing data in bytes
# 320-383
decode_ddr4_mfg_data(\@bytes)
} else {
# Decode next 35 bytes (64-98, common to most
# memory types)
decode_manufacturing_information(\@bytes);
}
}
# Side-by-side output format is only possible if all DIMMs have a similar
# output structure
if ($opt_side_by_side) {
for $current (1 .. $#dimm) {
my @ref_output = @{$dimm[0]->{output}};
my @test_output = @{$dimm[$current]->{output}};
my $line;
if (scalar @ref_output != scalar @test_output) {
$opt_side_by_side = 0;
last;
}
for ($line = 0; $line < @ref_output; $line++) {
my ($ref_func, $ref_label, @ref_dummy) = @{$ref_output[$line]};
my ($test_func, $test_label, @test_dummy) = @{$test_output[$line]};
if ($ref_func != $test_func || $ref_label ne $test_label) {
$opt_side_by_side = 0;
last;
}
}
}
if (!$opt_side_by_side) {
printc("Side-by-side output only possible if all DIMMS are similar\n");
# Discard "Decoding EEPROM" entry from all outputs
for $current (0 .. $#dimm) {
shift(@{$dimm[$current]->{output}});
}
}
}
# Check if all dimms have the same value for a given line
sub line_has_same_values($)
{
my $line = shift;
my $value = $dimm[0]->{output}->[$line]->[2];
# Skip lines with no values (headers)
return 1 unless defined $value;
for my $other (1 .. $#dimm) {
return 0 unless $value eq $dimm[$other]->{output}->[$line]->[2];
}
return 1;
}
# Find out the longest value string to adjust the column width
sub find_col_width($)
{
my $width = shift;
return $width unless $opt_side_by_side && !$opt_html;
my $line;
my $line_nr = @{$dimm[0]->{output}};
for ($line = 0; $line < $line_nr; $line++) {
next if $opt_merge && line_has_same_values($line);
my @strings;
for my $current (0 .. $#dimm) {
my $value = $dimm[$current]->{output}->[$line]->[2];
push @strings, split("\n", $value) if defined $value;
}
foreach my $line2 (@strings) {
my $len = length($line2);
$width = $len if $len > $width;
}
}
return $width;
}
$sbs_col_width = find_col_width(15);
# Print the decoded information for all DIMMs
for $current (0 .. $#dimm) {
if ($opt_side_by_side) {
print "\n\n";
} else {
printl2("\n\nDecoding EEPROM", $dimm[$current]->{file},
"text-decoration: underline; font-weight: bold;");
}
print "<table border=\"1\">\n" if $opt_html;
my @output = @{$dimm[$current]->{output}};
for (my $line = 0; $line < @output; $line++) {
my ($func, @param) = @{$output[$line]};
if ($opt_side_by_side) {
foreach ($current+1 .. $#dimm) {
my @xoutput = @{$dimm[$_]->{output}};
if (@{$xoutput[$line]} == 3) {
# Line with data, stack all values
push @param, @{$xoutput[$line]}[2];
} else {
# Separator, make it span
push @param, scalar @dimm;
}
}
}
$func->(@param);
}
print "</table>\n" if $opt_html;
last if $opt_side_by_side;
}
printl2("\n\nNumber of SDRAM DIMMs detected and decoded", scalar @dimm);
print "</body></html>\n" if ($opt_html && !$opt_bodyonly);