cxl: document 'cxl enable-port -m' behavior change

Add a note to warn potential breakage of 'cxl enable-port -m' option
when using an older CXL CLI with a newer kernel.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20250917235056.427188-1-dave.jiang@intel.com
Signed-off-by: Alison Schofield <alison.schofield@intel.com>

Documentation/cxl/cxl-enable-port.txt

diff --git a/Documentation/cxl/cxl-enable-port.txt b/Documentation/cxl/cxl-enable-port.txt
index 00c4050..ea9f3b0 100644
--- a/Documentation/cxl/cxl-enable-port.txt
+++ b/Documentation/cxl/cxl-enable-port.txt
@@ -33,6 +33,13 @@
 	memdev is only enabled after all CXL ports in its device topology
 	ancestry are enabled.
 
+	Note: The '-m' option requires release v83 or newer when used with
+	kernel v6.18 or later. Older releases (before v83) will not work
+	because kernel v6.18 changed how CXL ports and downstream ports are
+	enumerated. In these newer kernels, the CXL port hierarchy is only
+	established once the memdev is probed. v83 and later remain fully
+	compatible with both older and newer kernels.
+
 include::debug-option.txt[]
 
 include::../copyright.txt[]