pcilmr: Add functions for device checking and preparations before main margining processes
Follow the checklist from PCIe Base Spec Rev 5.0 section 4.2.13.3
"Receiver Margin Testing Requirements":
* Verify the Link is at 16 GT/s or higher data rate, in DO PM state;
* Verify that Margining Ready bit of the device is set;
* Disable the ASPM and Autonomous Speed/Width features for the duration
of the test.
Also verify that Upstream Port of the Link is Function 0 of a Device,
according to spec, only it must implement margining registers.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
2 files changed
