pcilmr: Add support for unique hardware quirks
Make it possible to change receiver margining parameters depending on
current hardware specificity.
In our tests Intel Ice Lake CPUs RC ports reported
MaxVoltageOffset = 50 (RxA), which led to results several times bigger
than the results of the hardware debugger.
Looks like in Intel Sapphire Rapids this was fixed, these CPU RC ports
report MaxVoltageOffset = 12 (RxA). To solve the problem it was decided
to hardcode Volt Offset to 12 (120 mV) for Ice Lake RC ports.
In the case of margining a specific link, only information about
Downstream and Upstream ports should be sufficient to decide whether to
use quirks, so the feature was implemented based on a list of devices
(vendor - device - revision triples), whose problems are known.
Back to Ice Lake ports, according to Integrators List on the pci-sig site,
the list of possible RC ports of Ice Lake Xeon's includes at least three
more options (with ids 347B/C/D) besides the one used in this commit, but
we don't have such processors to check the relevance of the MaxVoltageOffset
problem for these ports.
Reviewed-by: Sergei Miroshnichenko <s.miroshnichenko@yadro.com>
Signed-off-by: Nikita Proshkin <n.proshkin@yadro.com>
4 files changed
