| From: Ilia Mirkin <imirkin@alum.mit.edu> |
| Date: Thu, 19 Jan 2017 22:56:30 -0500 |
| Subject: drm/nouveau/nv1a,nv1f/disp: fix memory clock rate retrieval |
| |
| commit 24bf7ae359b8cca165bb30742d2b1c03a1eb23af upstream. |
| |
| Based on the xf86-video-nv code, NFORCE (NV1A) and NFORCE2 (NV1F) have a |
| different way of retrieving clocks. See the |
| nv_hw.c:nForceUpdateArbitrationSettings function in the original code |
| for how these clocks were accessed. |
| |
| Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54587 |
| Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| drivers/gpu/drm/nouveau/dispnv04/hw.c | 3 ++- |
| 1 file changed, 2 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c |
| +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c |
| @@ -225,6 +225,7 @@ nouveau_hw_get_clock(struct drm_device * |
| uint32_t mpllP; |
| |
| pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP); |
| + mpllP = (mpllP >> 8) & 0xf; |
| if (!mpllP) |
| mpllP = 4; |
| |
| @@ -235,7 +236,7 @@ nouveau_hw_get_clock(struct drm_device * |
| uint32_t clock; |
| |
| pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock); |
| - return clock; |
| + return clock / 1000; |
| } |
| |
| ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals); |