Merge branch 'rcar-3.5.1/dts-rcar-gen3.rc2' into v4.9/rcar-3.5.2.pt3
* rcar-3.5.1/dts-rcar-gen3.rc2: (80 commits)
arm64: dts: r8a7795-salvator-xs: Add Media Clock Recovery Handler device node
arm64: dts: r8a7795-salvator-xs: Add ADSP support
arm64: dts: r8a7795-salvator-xs: Add VSPM I/F driver support
arm64: dts: r8a7795-salvator-xs: Add MMNGRBUF driver support
arm64: dts: r8a7795-salvator-xs: Add MMNGR driver support
arm64: dts: r8a7795-salvator-xs: Add cpu-supply property in a57_0 node
arm64: dts: r8a7795-salvator-xs: Add regulator for DVFS
arm64: dts: r8a7795-salvator-xs: Add I2C for DVFS device support
arm64: dts: r8a7795-salvator-xs: Enable EXTALR clock
arm64: dts: r8a7795-salvator-xs: Add RCLK watchdog timer support
arm64: dts: r8a7795-salvator-xs: Add SATA device support
arm64: dts: r8a7795-salvator-xs: Add PCIe device support
arm64: dts: r8a7795-salvator-xs: Enable HS400 for SDHI2
arm64: dts: r8a7795-salvator-xs: Enable HS200 for SDHI2
arm64: dts: r8a7795-salvator-xs: Add SDHI2 device support as MMC interface
arm64: dts: r8a7795-salvator-xs: Enable UHS-I SDR-104 for SDHI0 and SDHI3
arm64: dts: r8a7795-salvator-xs: Enable UHS for SDHI0 and SDHI3
arm64: dts: r8a7795-salvator-xs: Add SDHI0 and SDHI3 device supports
arm64: dts: r8a7795-salvator-xs: Add sound MIX support
arm64: dts: r8a7795-salvator-xs: Add sound CTU support
arm64: dts: r8a7795-salvator-xs: Add AUDIO-CLKOUTn synchronous with L/R clock
arm64: dts: r8a7795-salvator-xs: Add ak4613 In/Out pin as single-end
arm64: dts: r8a7795-salvator-xs: Add CS2000 as AUDIO_CLK_B
arm64: dts: r8a7795-salvator-xs: Add Sound DVC support
arm64: dts: r8a7795-salvator-xs: Add Sound SRC support
arm64: dts: r8a7795-salvator-xs: Add Sound SSI support
arm64: dts: r8a7795-salvator-xs: Add ADV7482 video decoder devices support
arm64: dts: r8a7795-salvator-xs: Add CSI2 device support
arm64: dts: r8a7795-salvator-xs: Add VIN device support
arm64: dts: r8a7795-salvator-xs: Add PWM device support
...
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index b6c723d..8a80e59 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -1,4 +1,5 @@
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-x.dtb r8a7795-h3ulcb.dtb
+dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A7795) += r8a7795-es1-salvator-x.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-x.dtb r8a7796-m3ulcb.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
index 14f965c..f37101d 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the Salvator-X board on r8a7795 ES1.x
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
*
* This file is based on the arch/arm64/boot/dts/renesas/r8a7795-es1-salvator-x.dts
*
@@ -118,6 +118,15 @@
compatible = "renesas,mmngrbuf";
};
+ avb-mch {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ };
+
x12_clk: x12_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -617,7 +626,6 @@
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
- uart-has-rtscts;
/* Please use exclusively to the hscif1 node */
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 2fab335..a1fca6a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7795 ES1.x SoC
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
*
* This file is based on the arch/arm64/boot/dts/renesas/r8a7795.dtsi
*
@@ -807,9 +807,6 @@
reg = <0 0xe6260000 0 0x0200>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eicr0";
- clocks = <&cpg CPG_MOD 213>;
- clock-names = "mfis";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "okay";
};
@@ -817,8 +814,6 @@
compatible = "renesas,mfis-lock-r8a7795",
"renesas,mfis-lock";
reg = <0 0xe62600c0 0 0x0020>;
- clocks = <&cpg CPG_MOD 213>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "okay";
};
@@ -1884,6 +1879,7 @@
reg = <0 0xfe940000 0 0x2400>, <0 0xfe950000 0 0x200>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>, <&cpg CPG_MOD 615>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
renesas,#ch = <0>;
};
@@ -1893,6 +1889,7 @@
reg = <0 0xfe944000 0 0x2400>, <0 0xfe951000 0 0x200>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>, <&cpg CPG_MOD 614>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
renesas,#ch = <1>;
};
@@ -1902,6 +1899,7 @@
reg = <0 0xfe948000 0 0x2400>, <0 0xfe952000 0 0x200>;
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 117>, <&cpg CPG_MOD 613>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
renesas,#ch = <2>;
};
@@ -2640,6 +2638,7 @@
reg = <0 0xfe920000 0 0x8000>, <0 0xfe92f000 0 0x200>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 624>, <&cpg CPG_MOD 606>;
+ clock-names = "vsp", "fcp";
renesas,#ch = <4>;
renesas,#rpf = <31>;
renesas,#rpf_clut = <4>;
@@ -2667,7 +2666,7 @@
reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>, <&cpg CPG_MOD 607>;
-
+ clock-names = "vsp", "fcp";
renesas,#ch = <3>;
renesas,#rpf = <31>;
renesas,#rpf_clut = <4>;
@@ -2695,7 +2694,7 @@
reg = <0 0xfe9a0000 0 0x8000>, <0 0xfe9af000 0 0x200>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>, <&cpg CPG_MOD 611>;
-
+ clock-names = "vsp", "fcp";
renesas,#ch = <0>;
renesas,#rpf = <1>;
renesas,#rpf_clut = <1>;
@@ -2731,7 +2730,7 @@
reg = <0 0xfe9b0000 0 0x8000>, <0 0xfe9bf000 0 0x200>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 630>, <&cpg CPG_MOD 610>;
-
+ clock-names = "vsp", "fcp";
renesas,#ch = <1>;
renesas,#rpf = <1>;
renesas,#rpf_clut = <1>;
@@ -2767,7 +2766,7 @@
reg = <0 0xfe9c0000 0 0x8000>, <0 0xfe9cf000 0 0x200>;
interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>, <&cpg CPG_MOD 609>;
-
+ clock-names = "vsp", "fcp";
renesas,#ch = <2>;
renesas,#rpf = <1>;
renesas,#rpf_clut = <1>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index bad9bad..1a233b8 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -434,6 +434,7 @@
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
index e568fac..b93bbc5 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the Salvator-X board
*
- * Copyright (C) 2015-2016 Renesas Electronics Corp.
+ * Copyright (C) 2015-2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -114,6 +114,15 @@
compatible = "renesas,mmngrbuf";
};
+ avb-mch {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ };
+
x12_clk: x12_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -613,7 +622,6 @@
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
- uart-has-rtscts;
/* Please use exclusively to the hscif1 node */
status = "okay";
};
@@ -801,6 +809,7 @@
vmmc-supply = <®_3p3v>;
vqmmc-supply = <®_1p8v>;
mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
bus-width = <8>;
non-removable;
status = "okay";
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
index aeba4eb..a35d48c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-xs.dts
@@ -1,15 +1,39 @@
/*
* Device Tree Source for the Salvator-X 2nd version board
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
+/*
+ * SSI-AK4613
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
/dts-v1/;
#include "r8a7795.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Salvator-X 2nd version board based on r8a7795 es2.0";
@@ -18,6 +42,7 @@
aliases {
serial0 = &scif2;
serial1 = &scif1;
+ ethernet0 = &avb;
};
chosen {
@@ -30,28 +55,562 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+
+ memory@500000000 {
+ device_type = "memory";
+ reg = <0x5 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@600000000 {
+ device_type = "memory";
+ reg = <0x6 0x00000000 0x0 0x40000000>;
+ };
+
+ memory@700000000 {
+ device_type = "memory";
+ reg = <0x7 0x00000000 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* device specific region for Lossy Decompression */
+ lossy_decompress: linux,lossy_decompress {
+ no-map;
+ reg = <0x00000000 0x54000000 0x0 0x03000000>;
+ };
+
+ /* For Audio DSP */
+ adsp_reserved: linux,adsp {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x57000000 0x0 0x01000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x58000000 0x0 0x18000000>;
+ linux,cma-default;
+ };
+
+ /* device specific region for contiguous allocations */
+ mmp_reserved: linux,multimedia {
+ compatible = "shared-dma-pool";
+ reusable;
+ reg = <0x00000000 0x70000000 0x0 0x10000000>;
+ };
+ };
+
+ mmngr {
+ compatible = "renesas,mmngr";
+ memory-region = <&mmp_reserved>, <&lossy_decompress>;
+ };
+
+ mmngrbuf {
+ compatible = "renesas,mmngrbuf";
+ };
+
+ avb-mch {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ };
+
+ reg_1p8v: regulator0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vcc_sdhi0: regulator-vcc-sdhi0 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi0: regulator-vccq-sdhi0 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vcc_sdhi3: regulator-vcc-sdhi3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "SDHI3 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhi3: regulator-vccq-sdhi3 {
+ compatible = "regulator-gpio";
+
+ regulator-name = "SDHI3 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+
+ vbus0_usb2: regulator-vbus0-usb2 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "USB20_VBUS0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ x12_clk: x12_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24576000>;
+ };
+
+ audio_clkout: audio_clkout {
+ /*
+ * This is same as <&rcar_sound 0>
+ * but needed to avoid cs2000/rcar_sound probe dead-lock
+ */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <11289600>;
+ };
+
+ rsnd_ak4613: sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,format = "left_j";
+ simple-audio-card,bitclock-master = <&sndcpu>;
+ simple-audio-card,frame-master = <&sndcpu>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&ak4613>;
+ };
+ };
+
+ vga-encoder {
+ compatible = "adi,adv7123";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7123_in: endpoint {
+ remote-endpoint = <&du_out_rgb>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ adv7123_out: endpoint {
+ remote-endpoint = <&vga_in>;
+ };
+ };
+ };
+ };
+
+ vga {
+ compatible = "vga-connector";
+
+ port {
+ vga_in: endpoint {
+ remote-endpoint = <&adv7123_out>;
+ };
+ };
+ };
+
+ vspm_if {
+ compatible = "renesas,vspm_if";
+ };
+
+ lvds-encoder {
+ compatible = "thine,thc63lvdm83d";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ lvds_enc_in: endpoint {
+ remote-endpoint = <&du_out_lvds0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ lvds_enc_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+ };
+
+ lvds {
+ compatible = "lvds-connector", "panel-lvds";
+
+ width-mm = <210>;
+ height-mm = <158>;
+
+ data-mapping = "jeida-24";
+
+ panel-timing {
+ /* 1024x768 @60Hz */
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hsync-len = <136>;
+ hfront-porch = <20>;
+ hback-porch = <160>;
+ vfront-porch = <3>;
+ vback-porch = <29>;
+ vsync-len = <6>;
+ };
+
+ port {
+ lvds_in: endpoint {
+ remote-endpoint = <&lvds_enc_out>;
+ };
+ };
+ };
+
+ hdmi0-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi0_con: endpoint {
+ remote-endpoint = <&rcar_dw_hdmi0_out>;
+ };
+ };
+ };
+
+ hdmi1-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi1_con: endpoint {
+ remote-endpoint = <&rcar_dw_hdmi1_out>;
+ };
+ };
+ };
+};
+
+&du_dotclkin0 {
+ clock-frequency = <148500000>;
+};
+
+&du_dotclkin1 {
+ clock-frequency = <33000000>;
+};
+
+&du_dotclkin2 {
+ clock-frequency = <33000000>;
+};
+
+&du_dotclkin3 {
+ clock-frequency = <108000000>;
+};
+
+&a57_0 {
+ cpu-supply = <&vdd_dvfs>;
+};
+
+&pwm1 {
+ pinctrl-0 = <&pwm1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pwm2 {
+ pinctrl-0 = <&pwm2_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&du {
+ pinctrl-0 = <&du_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* update <du_dotclkin0/3> to <programmable_clk0/1> */
+ clocks = <&cpg CPG_MOD 724>,
+ <&cpg CPG_MOD 723>,
+ <&cpg CPG_MOD 722>,
+ <&cpg CPG_MOD 721>,
+ <&cpg CPG_MOD 727>,
+ <&programmable_clk0>, <&du_dotclkin1>, <&du_dotclkin2>,
+ <&programmable_clk1>;
+
+ backlight-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ port@0 {
+ endpoint {
+ remote-endpoint = <&adv7123_in>;
+ };
+ };
+ port@1 {
+ endpoint {
+ remote-endpoint = <&rcar_dw_hdmi0_in>;
+ };
+ };
+ port@2 {
+ endpoint {
+ remote-endpoint = <&rcar_dw_hdmi1_in>;
+ };
+ };
+ port@3 {
+ lvds_connector: endpoint {
+ remote-endpoint = <&lvds_enc_in>;
+ };
+ };
+ };
+};
+
+&hdmi0 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ rcar_dw_hdmi0_in: endpoint {
+ remote-endpoint = <&du_out_hdmi0>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi0_con>;
+ };
+ };
+ };
+};
+
+&hdmi1 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ rcar_dw_hdmi1_in: endpoint {
+ remote-endpoint = <&du_out_hdmi1>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ rcar_dw_hdmi1_out: endpoint {
+ remote-endpoint = <&hdmi1_con>;
+ };
+ };
+ };
};
&extal_clk {
- clock-frequency = <16666666>;
+ clock-frequency = <16640000>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
};
&pfc {
+ pinctrl-0 = <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ pwm1_pins: pwm1 {
+ groups = "pwm1_a", "pwm1_b";
+ function = "pwm1";
+ };
+
+ pwm2_pins: pwm2 {
+ groups = "pwm2_a", "pwm2_b";
+ function = "pwm2";
+ };
+
scif1_pins: scif1 {
- renesas,groups = "scif1_data_a", "scif1_ctrl";
- renesas,function = "scif1";
+ groups = "scif1_data_a", "scif1_ctrl";
+ function = "scif1";
};
scif2_pins: scif2 {
- renesas,groups = "scif2_data_a";
- renesas,function = "scif2";
+ groups = "scif2_data_a";
+ function = "scif2";
};
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_a";
+ function = "scif_clk";
+ };
+
+ hscif1_pins: hscif1 {
+ groups = "hscif1_data_a", "hscif1_ctrl_a";
+ function = "hscif1";
+ };
+
+ i2c2_pins: i2c2 {
+ groups = "i2c2_a";
+ function = "i2c2";
+ };
+
+ avb_pins: avb {
+ groups = "avb_mdc";
+ function = "avb";
+ };
+
+ du_pins: du {
+ groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";
+ function = "du";
+ };
+
+ sdhi0_pins: sd0 {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <3300>;
+ };
+
+ sdhi0_pins_uhs: sd0_uhs {
+ groups = "sdhi0_data4", "sdhi0_ctrl";
+ function = "sdhi0";
+ power-source = <1800>;
+ };
+
+ sdhi2_pins: sd2 {
+ groups = "sdhi2_data8", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <3300>;
+ };
+
+ sdhi2_pins_uhs: sd2_uhs {
+ groups = "sdhi2_data8", "sdhi2_ctrl";
+ function = "sdhi2";
+ power-source = <1800>;
+ };
+
+ sdhi3_pins: sd3 {
+ groups = "sdhi3_data4", "sdhi3_ctrl";
+ function = "sdhi3";
+ power-source = <3300>;
+ };
+
+ sdhi3_pins_uhs: sd3_uhs {
+ groups = "sdhi3_data4", "sdhi3_ctrl";
+ function = "sdhi3";
+ power-source = <1800>;
+ };
+
+ msiof0_pins: spi1 {
+ groups = "msiof0_clk", "msiof0_sync",
+ "msiof0_rxd", "msiof0_txd";
+ function = "msiof0";
+ };
+
+ msiof1_pins: spi2 {
+ groups = "msiof1_clk_c", "msiof1_sync_c",
+ "msiof1_rxd_c", "msiof1_txd_c";
+ function = "msiof1";
+ };
+
+ msiof2_pins: spi3 {
+ groups = "msiof2_clk_b", "msiof2_sync_b",
+ "msiof2_rxd_b", "msiof2_txd_b";
+ function = "msiof2";
+ };
+
+ msiof3_pins: spi4 {
+ groups = "msiof3_clk_d", "msiof3_sync_d",
+ "msiof3_rxd_d", "msiof3_txd_d";
+ function = "msiof3";
+ };
+
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";
+ function = "ssi";
+ };
+
+ sound_clk_pins: sound_clk {
+ groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a",
+ "audio_clkout_a", "audio_clkout3_a";
+ function = "audio_clk";
+ };
+
+ usb0_pins: usb0 {
+ groups = "usb0";
+ function = "usb0";
+ };
+
+ usb1_pins: usb1 {
+ groups = "usb1";
+ function = "usb1";
+ };
+
+ usb2_pins: usb2 {
+ groups = "usb2";
+ function = "usb2";
+ };
+
+ usb3_pins: usb3 {
+ groups = "usb3";
+ function = "usb3";
+ };
+};
+
+&adsp {
+ status = "okay";
+ memory-region = <&adsp_reserved>;
};
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
-
+ /* Please use exclusively to the hscif1 node */
status = "okay";
};
@@ -61,3 +620,496 @@
status = "okay";
};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+ status = "okay";
+};
+
+&hscif1 {
+ pinctrl-0 = <&hscif1_pins>;
+ pinctrl-names = "default";
+ /* Please use exclusively to the scif1 node */
+ /* status = "okay"; */
+};
+
+&i2c2 {
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ ak4613: codec@10 {
+ compatible = "asahi-kasei,ak4613";
+ #sound-dai-cells = <0>;
+ reg = <0x10>;
+ clocks = <&rcar_sound 3>;
+
+ asahi-kasei,in1-single-end;
+ asahi-kasei,in2-single-end;
+ asahi-kasei,out1-single-end;
+ asahi-kasei,out2-single-end;
+ asahi-kasei,out3-single-end;
+ asahi-kasei,out4-single-end;
+ asahi-kasei,out5-single-end;
+ asahi-kasei,out6-single-end;
+ };
+
+ cs2000: clk_multiplier@4f {
+ #clock-cells = <0>;
+ compatible = "cirrus,cs2000-cp";
+ reg = <0x4f>;
+ clocks = <&audio_clkout>, <&x12_clk>;
+ clock-names = "clk_in", "ref_clk";
+
+ assigned-clocks = <&cs2000>;
+ assigned-clock-rates = <24576000>; /* 1/1 divide */
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ adv7482_1: hdmi-in@34 {
+ compatible = "adi,adv7482";
+ reg = <0x34>;
+
+ adi,virtual-channel = <0>;
+ adi,input-interface = "rgb888";
+ adi,input-hdmi = "on";
+ adi,input-sdp = "on";
+ adi,sw-reset = "on";
+
+ port {
+ adv7482_1_out: endpoint@1 {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&csi2_40_0_in>;
+ };
+ };
+ };
+
+ adv7482_2: composite-in@70 {
+ compatible = "adi,adv7482";
+ reg = <0x70>;
+
+ adi,virtual-channel = <0>;
+ adi,input-interface = "ycbcr422";
+ adi,input-hdmi = "on";
+ adi,input-sdp = "on";
+ adi,sw-reset = "on";
+
+ port {
+ adv7482_2_out: endpoint@1 {
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ remote-endpoint = <&csi2_20_0_in>;
+ };
+ };
+ };
+
+ clk_5p49v5923a: programmable_clk@6a {
+ compatible = "idt,5p49v5923a";
+ reg = <0x6a>;
+
+ programmable_clk0: 5p49v5923a_clk1@6a {
+ #clock-cells = <0>;
+ clocks = <&du_dotclkin0>;
+ };
+
+ programmable_clk1: 5p49v5923a_clk2@6a {
+ #clock-cells = <0>;
+ clocks = <&du_dotclkin3>;
+ };
+ };
+};
+
+&rcar_sound {
+ pinctrl-0 = <&sound_pins &sound_clk_pins>;
+ pinctrl-names = "default";
+
+ /* Single DAI */
+ #sound-dai-cells = <0>;
+
+ /* audio_clkout0/1/2/3 */
+ #clock-cells = <1>;
+ clock-frequency = <11289600>;
+ clkout-lr-synchronous;
+
+ status = "okay";
+
+ /* update <audio_clk_b> to <cs2000> */
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
+ <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
+ <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
+ <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
+ <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clk_a>, <&cs2000>,
+ <&audio_clk_c>,
+ <&cpg CPG_CORE R8A7795_CLK_S0D4>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi0 &src0 &dvc0>;
+ capture = <&ssi1 &src1 &dvc1>;
+ };
+ };
+};
+
+&sata {
+ /* Please use exclusively to pciec1 node */
+ /* status = "okay"; */
+};
+
+&sdhi0 {
+ pinctrl-0 = <&sdhi0_pins>;
+ pinctrl-1 = <&sdhi0_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi0>;
+ vqmmc-supply = <&vccq_sdhi0>;
+ cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&sdhi2 {
+ /* used for on-board 8bit eMMC */
+ pinctrl-0 = <&sdhi2_pins>;
+ pinctrl-1 = <&sdhi2_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&sdhi3 {
+ pinctrl-0 = <&sdhi3_pins>;
+ pinctrl-1 = <&sdhi3_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
+
+ vmmc-supply = <&vcc_sdhi3>;
+ vqmmc-supply = <&vccq_sdhi3>;
+ cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&ssi1 {
+ shared-pin;
+};
+
+&wdt0 {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
+&audio_clk_a {
+ clock-frequency = <22579200>;
+};
+
+&i2c_dvfs {
+ status = "okay";
+
+ clock-frequency = <400000>;
+
+ vdd_dvfs: regulator@30 {
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ status = "okay";
+ phy-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+
+ phy0: ethernet-phy@0 {
+ rxc-skew-ps = <1500>;
+ rxdv-skew-ps = <420>; /* default */
+ rxd0-skew-ps = <420>; /* default */
+ rxd1-skew-ps = <420>; /* default */
+ rxd2-skew-ps = <420>; /* default */
+ rxd3-skew-ps = <420>; /* default */
+ txc-skew-ps = <900>; /* default */
+ txen-skew-ps = <420>; /* default */
+ txd0-skew-ps = <420>; /* default */
+ txd1-skew-ps = <420>; /* default */
+ txd2-skew-ps = <420>; /* default */
+ txd3-skew-ps = <420>; /* default */
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ pinctrl-0 = <&usb0_pins>;
+ pinctrl-names = "default";
+
+ vbus-supply = <&vbus0_usb2>;
+ status = "okay";
+};
+
+&usb2_phy1 {
+ pinctrl-0 = <&usb1_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy2 {
+ pinctrl-0 = <&usb2_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&usb2_phy3 {
+ pinctrl-0 = <&usb3_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&hsusb0 {
+ status = "okay";
+};
+
+&hsusb3 {
+ status = "okay";
+};
+
+&msiof_ref_clk {
+ clock-frequency = <66666666>;
+};
+
+&msiof0 {
+ pinctrl-0 = <&msiof0_pins>;
+ pinctrl-names = "default";
+ /* Please use exclusively to the rcar_sound node */
+ /* status = "okay"; */
+
+ spidev@0 {
+ compatible = "renesas,sh-msiof";
+ reg = <0>;
+ spi-max-frequency = <66666666>;
+ spi-cpha;
+ spi-cpol;
+ };
+};
+
+&msiof1 {
+ pinctrl-0 = <&msiof1_pins>;
+ pinctrl-names = "default";
+ /* In case of using this node, please enable this property */
+ /* status = "okay"; */
+
+ spidev@0 {
+ compatible = "renesas,sh-msiof";
+ reg = <0>;
+ spi-max-frequency = <66666666>;
+ spi-cpha;
+ spi-cpol;
+ };
+};
+
+&msiof2 {
+ pinctrl-0 = <&msiof2_pins>;
+ pinctrl-names = "default";
+ /* In case of using this node, please enable this property */
+ /* status = "okay"; */
+
+ spidev@0 {
+ compatible = "renesas,sh-msiof";
+ reg = <0>;
+ spi-max-frequency = <66666666>;
+ spi-cpha;
+ spi-cpol;
+ };
+};
+
+&msiof3 {
+ pinctrl-0 = <&msiof3_pins>;
+ pinctrl-names = "default";
+ /* In case of using this node, please enable this property */
+ /* status = "okay"; */
+
+ spidev@0 {
+ compatible = "renesas,sh-msiof";
+ reg = <0>;
+ spi-max-frequency = <66666666>;
+ spi-cpha;
+ spi-cpol;
+ };
+};
+
+&pcie_bus_clk {
+ clock-frequency = <100000000>;
+ status = "okay";
+};
+
+&pciec0 {
+ status = "okay";
+};
+
+&pciec1 {
+ /* Please use exclusively to sata node */
+ status = "okay";
+};
+
+&vin0 {
+ status = "okay";
+};
+
+&vin1 {
+ status = "okay";
+};
+
+&vin2 {
+ status = "okay";
+};
+
+&vin3 {
+ status = "okay";
+};
+
+&vin4 {
+ status = "okay";
+};
+
+&vin5 {
+ status = "okay";
+};
+
+&vin6 {
+ status = "okay";
+};
+
+&vin7 {
+ status = "okay";
+};
+
+&csi2_20 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi2_20_0_in: endpoint@0 {
+ clock-lanes = <0>;
+ data-lanes = <1>;
+ virtual-channel-number = <1>;
+ remote-endpoint = <&adv7482_2_out>;
+ };
+ };
+ };
+};
+
+&csi2_40 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi2_40_0_in: endpoint@0 {
+ clock-lanes = <0>;
+ data-lanes = <1 2 3 4>;
+ virtual-channel-number = <1>;
+ remote-endpoint = <&adv7482_1_out>;
+ };
+ };
+ };
+};
+
+&vspbc {
+ status = "okay";
+};
+
+&vspbd {
+ status = "okay";
+};
+
+&vspi0 {
+ status = "okay";
+};
+
+&vspi1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 86e9744..c920dd6 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7795 SoC
*
- * Copyright (C) 2015 Renesas Electronics Corp.
+ * Copyright (C) 2015-2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -802,9 +802,6 @@
reg = <0 0xe6260000 0 0x0200>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eicr0";
- clocks = <&cpg CPG_MOD 213>;
- clock-names = "mfis";
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "okay";
};
@@ -812,8 +809,6 @@
compatible = "renesas,mfis-lock-r8a7795",
"renesas,mfis-lock";
reg = <0 0xe62600c0 0 0x0020>;
- clocks = <&cpg CPG_MOD 213>;
- power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
status = "okay";
};
@@ -872,7 +867,7 @@
};
ipmmu_vc0: mmu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a7795";
+ compatible = "renesas,ipmmu-pmb-r8a7795";
reg = <0 0xfe6b0000 0 0x1000>; /* IPMMU-VC0 */
renesas,ipmmu-main = <&ipmmu_mm 12>;
#iommu-cells = <1>;
@@ -1853,7 +1848,7 @@
clocks = <&cpg CPG_MOD 128>;
power-domains = <&sysc R8A7795_PD_A2VC0>;
renesas,#ch = <2>;
- renesas,#fcp_ch = <1>;
+ renesas,#fcp_ch = <0>;
};
fcpcs: vcp4@fe90f000 {
@@ -1864,19 +1859,12 @@
renesas,#ch = <0>;
};
- fcpci0: vcp4@fe8df000 {
- compatible = "renesas,vcp4-fcpci0";
- reg = <0 0xfe8df000 0 0x200>;
- clocks = <&cpg CPG_MOD 617>;
- power-domains = <&sysc R8A7795_PD_A3VC>;
- renesas,#ch = <1>;
- };
-
fdp0: fdpm@fe940000 {
compatible = "renesas,fdpm";
reg = <0 0xfe940000 0 0x2400>, <0 0xfe950000 0 0x200>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>, <&cpg CPG_MOD 615>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
renesas,#ch = <0>;
};
@@ -1886,6 +1874,7 @@
reg = <0 0xfe944000 0 0x2400>, <0 0xfe951000 0 0x200>;
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 118>, <&cpg CPG_MOD 614>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7795_PD_A3VP>;
renesas,#ch = <1>;
};
@@ -2310,7 +2299,7 @@
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 329>;
+ clocks = <&cpg CPG_MOD 326>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <2>;
@@ -2323,7 +2312,7 @@
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch0", "ch1";
- clocks = <&cpg CPG_MOD 326>;
+ clocks = <&cpg CPG_MOD 329>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
#dma-cells = <1>;
dma-channels = <2>;
@@ -2585,11 +2574,24 @@
compatible = "renesas,qos";
};
+ vsp@fe920000 {
+ compatible = "renesas,vspm-vsp2";
+ reg = <0 0xfe920000 0 0x8000>;
+ renesas,has-bru;
+ renesas,has-lut;
+ renesas,has-clu;
+ renesas,has-hgo;
+ renesas,#rpf = <5>;
+ renesas,#uds = <0>;
+ renesas,#wpf = <1>;
+ };
+
vspbc: vspm@fe920000 {
compatible = "renesas,vspm";
reg = <0 0xfe920000 0 0x8000>, <0 0xfe92f000 0 0x200>;
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 624>, <&cpg CPG_MOD 606>;
+ clock-names = "vsp", "fcp";
renesas,#ch = <4>;
renesas,#rpf = <31>;
renesas,#rpf_clut = <6>;
@@ -2618,7 +2620,7 @@
reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>, <&cpg CPG_MOD 607>;
-
+ clock-names = "vsp", "fcp";
renesas,#ch = <3>;
renesas,#rpf = <31>;
renesas,#rpf_clut = <6>;
@@ -2647,7 +2649,7 @@
reg = <0 0xfe9a0000 0 0x8000>, <0 0xfe9af000 0 0x200>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>, <&cpg CPG_MOD 611>;
-
+ clock-names = "vsp", "fcp";
renesas,#ch = <0>;
renesas,#rpf = <1>;
renesas,#rpf_clut = <1>;
@@ -2684,7 +2686,7 @@
reg = <0 0xfe9b0000 0 0x8000>, <0 0xfe9bf000 0 0x200>;
interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 630>, <&cpg CPG_MOD 610>;
-
+ clock-names = "vsp", "fcp";
renesas,#ch = <1>;
renesas,#rpf = <1>;
renesas,#rpf_clut = <1>;
@@ -2704,18 +2706,6 @@
status = "disabled";
};
- vsp@fe9c0000 {
- compatible = "renesas,vspm-vsp2";
- reg = <0 0xfe9c0000 0 0x8000>;
- renesas,has-lut;
- renesas,has-clu;
- renesas,has-hgo;
- renesas,has-hgt;
- renesas,#rpf = <1>;
- renesas,#uds = <1>;
- renesas,#wpf = <1>;
- };
-
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x4000>;
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
index 49de260..b3ecbd3 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts
@@ -352,6 +352,7 @@
cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
sd-uhs-sdr50;
+ sd-uhs-sdr104;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
index 27163ff..3b70fa5 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the Salvator-X board
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -104,6 +104,15 @@
compatible = "renesas,mmngrbuf";
};
+ avb-mch {
+ compatible = "renesas,avb-mch-gen3";
+ reg = <0 0xec5a0100 0 0x100>; /* ADG_AVB */
+ reg-name = "adg_avb";
+
+ clocks = <&cpg CPG_MOD 922>;
+ clock-names = "adg";
+ };
+
reg_1p8v: regulator0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
@@ -904,6 +913,10 @@
status = "okay";
};
+&vin0 {
+ status = "okay";
+};
+
&vin1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 9978874..bf3d232 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for the r8a7796 SoC
*
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -678,9 +678,6 @@
reg = <0 0xe6260000 0 0x0200>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eicr0";
- clocks = <&cpg CPG_MOD 213>;
- clock-names = "mfis";
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "okay";
};
@@ -688,8 +685,6 @@
compatible = "renesas,mfis-lock-r8a7796",
"renesas,mfis-lock";
reg = <0 0xe62600c0 0 0x0020>;
- clocks = <&cpg CPG_MOD 213>;
- power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
status = "okay";
};
@@ -1981,6 +1976,7 @@
reg = <0 0xfe940000 0 0x2400>, <0 0xfe950000 0 0x200>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 119>, <&cpg CPG_MOD 615>;
+ clock-names = "fdp", "fcp";
power-domains = <&sysc R8A7796_PD_A3VC>;
renesas,#ch = <0>;
};
@@ -2409,6 +2405,7 @@
reg = <0 0xfe960000 0 0x8000>, <0 0xfe96f000 0 0x200>;
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 626>, <&cpg CPG_MOD 607>;
+ clock-names = "vsp", "fcp";
renesas,#ch = <3>;
renesas,#rpf = <31>;
renesas,#rpf_clut = <6>;
@@ -2440,6 +2437,7 @@
reg = <0 0xfe9a0000 0 0x8000>, <0 0xfe9af000 0 0x200>;
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 631>, <&cpg CPG_MOD 611>;
+ clock-names = "vsp", "fcp";
renesas,#ch = <0>;
renesas,#rpf = <1>;
renesas,#rpf_clut = <1>;
