| /* |
| * asm/soc-tz1090/defs.h |
| * |
| * Useful defines for TZ1090 SoC Configuration |
| * |
| * Copyright (C) 2009 Imagination Technologies Ltd. |
| */ |
| |
| #ifndef _TZ1090_DEFS_H_ |
| #define _TZ1090_DEFS_H_ |
| |
| #ifndef __ASSEMBLY__ |
| #include <asm/soc-tz1090/irqnums.h> |
| #endif |
| |
| /* Peripheral Addresses */ |
| #define CR_PERIP_BASE_ADDR 0x02004000 |
| #define CR_PERIP_SIZE 0x400 |
| #define CR_PERIP_SRST (CR_PERIP_BASE_ADDR + 0x00) |
| #define CR_PERIP_USB_PHY_PON_RESET_BIT (1 << 18) |
| #define CR_PERIP_USB_PHY_PORTRESET_BIT (1 << 17) |
| #define CR_PERIP_RESET_CFG (CR_PERIP_BASE_ADDR + 0x04) |
| #define CR_PERIP_RESET_CFG_FXTAL_BITS 0x00000F00 |
| #define CR_PERIP_RESET_CFG_FXTAL_SHIFT 8 |
| #define CR_PERIP_DMA_ROUTE_SEL2_REG (CR_PERIP_BASE_ADDR + 0x88) |
| #define CR_PERIP_USB_PHY_TUNE_CONTROL (CR_PERIP_BASE_ADDR + 0x204) |
| #define CR_PERIP_USB_VMT_VBUSVALID 0x10000000 |
| #define CR_PERIP_USB_PHY_STRAP_CONTROL (CR_PERIP_BASE_ADDR + 0x208) |
| #define CR_PERIP_USB_ISO_PHY_BIT (1 << 12) |
| #define CR_PERIP_USB_REFCLKSEL_BITS 0x00000030 |
| #define CR_PERIP_USB_REFCLKSEL_SHIFT 4 |
| #define CR_PERIP_USB_REFCLKDIV_BITS 0x00000003 |
| #define CR_PERIP_USB_REFCLKDIV_SHIFT 0 |
| #define CR_PERIP_SDHOST_DMA_RDATA (CR_PERIP_BASE_ADDR + 0x220) |
| #define CR_PERIP_SDHOST_DMA_WDATA (CR_PERIP_BASE_ADDR + 0x224) |
| #define CR_PERIP_RNG_CTRL (CR_PERIP_BASE_ADDR + 0x280) |
| #define CR_PERIP_RNG_SINGLE_STEP_BITS 0x00000040 /* not in ES1 */ |
| #define CR_PERIP_RNG_RO_ALT_BITS 0x00000020 |
| #define CR_PERIP_RNG_RNG_ALT_BITS 0x00000010 |
| #define CR_PERIP_RNG_PSEED_DIS_BITS 0x00000008 |
| #define CR_PERIP_RNG_RSEED_DIS_BITS 0x00000004 |
| #define CR_PERIP_RNG_RING_DIS_BITS 0x00000002 |
| #define CR_PERIP_RNG_START_BITS 0x00000001 |
| #define CR_PERIP_RNG_SEED (CR_PERIP_BASE_ADDR + 0x284) |
| #define CR_PERIP_RNG_NUM (CR_PERIP_BASE_ADDR + 0x288) |
| #define CR_COMET_CORE_REV (CR_PERIP_BASE_ADDR + 0x2D0) |
| #define CR_COMET_CORE_REV_MAJOR_BITS 0x00FF0000 |
| #define CR_COMET_CORE_REV_MAJOR_SHIFT 16 |
| #define CR_COMET_CORE_REV_MAJOR_ES1 (0x00 << CR_COMET_CORE_REV_MAJOR_SHIFT) |
| #define CR_COMET_CORE_REV_MAJOR_PS1 (0x01 << CR_COMET_CORE_REV_MAJOR_SHIFT) |
| |
| |
| #define SCB0_BASE_ADDR 0x02004400 |
| #define SCB0_SIZE 0x1ff |
| |
| #define SCB1_BASE_ADDR 0x02004600 |
| #define SCB1_SIZE 0x1ff |
| |
| #define SCB2_BASE_ADDR 0x02004800 |
| #define SCB2_SIZE 0x1ff |
| |
| #define SDIO_DEV_BASE_ADDR 0x02004A00 |
| #define SDIO_DEV_SIZE 0xff |
| |
| #define UART0_BASE_ADDR 0x02004B00 |
| #define UART0_SIZE 0xff |
| |
| #define UART1_BASE_ADDR 0x02004C00 |
| #define UART1_SIZE 0xff |
| |
| #define SPI_MS_BASE_ADDR 0x02004D00 |
| #define SPI_MS_SIZE 0xff |
| |
| #define SPI_MASTER_BASE_ADDR 0x02004E00 |
| #define SPI_MASTER_SIZE 0xff |
| |
| #define AUDIO_OUT_BASE_ADDR 0x02004F00 |
| #define AUDIO_OUT_SIZE 0xff |
| |
| #define AUDIO_IN_BASE_ADDR 0x02005000 |
| #define AUDIO_IN_SIZE 0xff |
| |
| #define LCD_BASE_ADDR 0x02005200 |
| #define LCD_SIZE 0xff |
| |
| #define EVENT_TS_BASE_ADDR 0x02005300 |
| #define EVENT_TS_SIZE 0xff |
| |
| #define SDIO_HOST_BASE_ADDR 0x02005400 |
| #define SDIO_HOST_SIZE 0x1ff |
| |
| #define GPIO_CRTOP_BASE_ADDR 0x02005800 |
| #define GPIO_CRTOP_SIZE 0x1ff |
| #define CR_PADS_GPIO_DIR0 (GPIO_CRTOP_BASE_ADDR + 0x00) |
| #define CR_PADS_GPIO_DIR1 (GPIO_CRTOP_BASE_ADDR + 0x04) |
| #define CR_PADS_GPIO_DIR2 (GPIO_CRTOP_BASE_ADDR + 0x08) |
| #define CR_PADS_GPIO_SELECT0 (GPIO_CRTOP_BASE_ADDR + 0x10) |
| #define CR_PADS_GPIO_SELECT1 (GPIO_CRTOP_BASE_ADDR + 0x14) |
| #define CR_PADS_GPIO_SELECT2 (GPIO_CRTOP_BASE_ADDR + 0x18) |
| #define CR_PADS_DBGEN (GPIO_CRTOP_BASE_ADDR + 0x1c) |
| #define CR_PADS_IRQ_PLRT0 (GPIO_CRTOP_BASE_ADDR + 0x20) |
| #define CR_PADS_IRQ_PLRT1 (GPIO_CRTOP_BASE_ADDR + 0x24) |
| #define CR_PADS_IRQ_PLRT2 (GPIO_CRTOP_BASE_ADDR + 0x28) |
| #define CR_PADS_IRQ_TYPE0 (GPIO_CRTOP_BASE_ADDR + 0x30) |
| #define CR_PADS_IRQ_TYPE1 (GPIO_CRTOP_BASE_ADDR + 0x34) |
| #define CR_PADS_IRQ_TYPE2 (GPIO_CRTOP_BASE_ADDR + 0x38) |
| #define CR_PADS_IRQ_EN0 (GPIO_CRTOP_BASE_ADDR + 0x40) |
| #define CR_PADS_IRQ_EN1 (GPIO_CRTOP_BASE_ADDR + 0x44) |
| #define CR_PADS_IRQ_EN2 (GPIO_CRTOP_BASE_ADDR + 0x48) |
| #define CR_PADS_IRQ_STS0 (GPIO_CRTOP_BASE_ADDR + 0x50) |
| #define CR_PADS_IRQ_STS1 (GPIO_CRTOP_BASE_ADDR + 0x54) |
| #define CR_PADS_IRQ_STS2 (GPIO_CRTOP_BASE_ADDR + 0x58) |
| #define CR_PADS_GPIO_BIT_EN0 (GPIO_CRTOP_BASE_ADDR + 0x60) |
| #define CR_PADS_GPIO_BIT_EN1 (GPIO_CRTOP_BASE_ADDR + 0x64) |
| #define CR_PADS_GPIO_BIT_EN2 (GPIO_CRTOP_BASE_ADDR + 0x68) |
| #define CR_PADS_GPIO_DIN0 (GPIO_CRTOP_BASE_ADDR + 0x70) |
| #define CR_PADS_GPIO_DIN1 (GPIO_CRTOP_BASE_ADDR + 0x74) |
| #define CR_PADS_GPIO_DIN2 (GPIO_CRTOP_BASE_ADDR + 0x78) |
| #define CR_PADS_GPIO_DOUT0 (GPIO_CRTOP_BASE_ADDR + 0x80) |
| #define CR_PADS_GPIO_DOUT1 (GPIO_CRTOP_BASE_ADDR + 0x84) |
| #define CR_PADS_GPIO_DOUT2 (GPIO_CRTOP_BASE_ADDR + 0x88) |
| #define CR_PADS_SCHMITT_EN0 (GPIO_CRTOP_BASE_ADDR + 0x90) |
| #define CR_PADS_DBGSEL0 (GPIO_CRTOP_BASE_ADDR + 0x94) |
| #define CR_PADS_DBGSEL1 (GPIO_CRTOP_BASE_ADDR + 0x98) |
| #define CR_PADS_DBGSEL2 (GPIO_CRTOP_BASE_ADDR + 0x9c) |
| #define CR_PADS_PU_PD_0 (GPIO_CRTOP_BASE_ADDR + 0xa0) |
| #define CR_PADS_PU_PD_1 (GPIO_CRTOP_BASE_ADDR + 0xa4) |
| #define CR_PADS_PU_PD_2 (GPIO_CRTOP_BASE_ADDR + 0xa8) |
| #define CR_PADS_PU_PD_3 (GPIO_CRTOP_BASE_ADDR + 0xac) |
| #define CR_PADS_PU_PD_4 (GPIO_CRTOP_BASE_ADDR + 0xb0) |
| #define CR_PADS_PU_PD_5 (GPIO_CRTOP_BASE_ADDR + 0xb4) |
| #define CR_PADS_PU_PD_6 (GPIO_CRTOP_BASE_ADDR + 0xb8) |
| #define CR_PADS_PU_PD_6 (GPIO_CRTOP_BASE_ADDR + 0xb8) |
| #define CR_PADS_SR_0 (GPIO_CRTOP_BASE_ADDR + 0xc0) |
| #define CR_PADS_DBGSEL4 (GPIO_CRTOP_BASE_ADDR + 0xc4) |
| #define CR_PADS_DBGSEL5 (GPIO_CRTOP_BASE_ADDR + 0xc8) |
| #define CR_PADS_DBGSEL6 (GPIO_CRTOP_BASE_ADDR + 0xcc) |
| #define CR_PADS_DR_0 (GPIO_CRTOP_BASE_ADDR + 0xd0) |
| #define GPIO_SEL2_SDH_CLKIN 0x20000000 /*bit 29*/ |
| #define GPIO_SEL2_TFT 0x00003fff /*bits 13-0*/ |
| #define GPIO_SEL2_RF 0x3fffc000 /*bits 12-14*/ |
| #define CR_DDR_CTRL (GPIO_CRTOP_BASE_ADDR + 0xe4) |
| #define CR_DDR_POWERDOWN_BIT 2 |
| #define CR_PADS_GPIO_DOUT0 (GPIO_CRTOP_BASE_ADDR + 0x80) |
| #define CR_PADS_GPIO_DOUT1 (GPIO_CRTOP_BASE_ADDR + 0x84) |
| #define CR_PADS_GPIO_DOUT2 (GPIO_CRTOP_BASE_ADDR + 0x88) |
| #define CR_IF_CTL0 (GPIO_CRTOP_BASE_ADDR + 0xe0) |
| #define CR_PADS_SDIO_CTL_BIT 16 |
| |
| #define PDC_BASE_ADDR 0x02006000 |
| #define PDC_SIZE 0xfff |
| #define PDC_IR_BASE_ADDR 0x02006200 |
| #define PDC_IR_SIZE 0xff |
| #define PDC_SOC_BOOTSTRAP_SYS_CLKSEL 0x00000002 |
| #define PDC_SOC_BOOTSTRAP_SAFE_MODE 0x00000001 |
| #define PDC_SOC_GPIO0_RTC_SW 0x40000000 |
| #define PDC_SOC_GPIO0_XTAL1_DIV 0x07ff0000 |
| #define PDC_SOC_GPIO0_XTAL1_DIV_SHIFT 16 |
| #define PDC_SOC_GPIO2_PU_PD_GPIO0 0x00030000 |
| #define PDC_SOC_GPIO2_PU_PD_GPIO0_SHIFT 16 |
| #define PDC_SOC_GPIO2_XTAL3_BYPASS 0x00000400 |
| #define PDC_SOC_GPIO2_XTAL3_EN 0x00000200 |
| #define PDC_SOC_GPIO2_XTAL2_BYPASS 0x00000100 |
| #define PDC_SOC_GPIO2_XTAL2_EN 0x00000080 |
| #define PDC_SOC_GPIO2_XTAL1_BYPASS 0x00000040 |
| #define PDC_SOC_GPIO2_XTAL1_EN 0x00000020 |
| |
| #define PDP_BASE_ADDR 0x02008000 |
| #define PDP_SIZE 0x7ff |
| |
| #define PDI_BASE_ADDR 0x02008800 |
| #define PDI_SIZE 0xff |
| |
| #define TWOD_BASE_ADDR 0x02008900 |
| #define TWOD_SIZE 0xff |
| #define TWOD_SLAVE_PORT_OFFSET 0x000 |
| #define TWOD_SLAVE_PORT (TWOD_BASE_ADDR + TWOD_SLAVE_PORT_OFFSET) |
| |
| #define HEP_BASE_ADDR 0x02008c00 |
| #define HEP_SIZE 0x3ff |
| #define CR_HEP_SRST_OFFSET 0x000 |
| #define CR_HEP_SRST (HEP_BASE_ADDR + CR_HEP_SRST_OFFSET) |
| #define CR_2D_SOFT_RESET 0x00000002 |
| #define CR_2D_SOFT_RESET_SHIFT 1 |
| #define CR_PDP_PDI_SOFT_RESET 0x00000001 |
| #define CR_PDP_PDI_SOFT_RESET_SHIFT 0 |
| #define CR_HEP_CLK_EN_OFFSET 0x004 |
| #define CR_HEP_CLK_EN (HEP_BASE_ADDR + CR_HEP_CLK_EN_OFFSET) |
| #define CR_PDP_PDI_CLK_EN 0x00000004 |
| #define CR_DDR_CLK_EN 0x00000002 |
| #define CR_2D_CLK_EN 0x00000001 |
| #define CR_2D_SETTINGS_OFFSET 0x008 |
| #define CR_2D_SETTINGS (HEP_BASE_ADDR + CR_2D_SETTINGS_OFFSET) |
| #define CR_2D_CLK_RATIO 0x00000006 |
| #define CR_2D_CLK_RATIO_SHIFT 1 |
| #define CR_2D_CLKGATESTATUS 0x00000001 |
| #define CR_2D_STATUS_OFFSET 0x00c |
| #define CR_2D_BLIT_STATUS_COMPLETE 0x0ffffff0 |
| #define CR_2D_BLIT_STATUS_COMPLETE_SHIFT 4 |
| #define CR_2D_BLIT_STATUS_BUSY 0x00000004 |
| #define CR_2D_BLIT_STATUS_BUSY_SHIFT 2 |
| #define CR_2D_IDLE 0x00000002 |
| #define CR_2D_IDLE_SHIFT 1 |
| #define CR_PDP_MEM_BASE_ADDR_OFFSET 0x020 |
| #define CR_PDP_MEM_BASE_ADDR (HEP_BASE_ADDR + CR_PDP_MEM_BASE_ADDR_OFFSET) |
| #define CR_2D_MEM_BASE_ADDR_OFFSET 0x024 |
| #define CR_SOCIF_TIMEOUT_OFFSET 0x02c |
| #define CR_SOCIF_TIMEOUT_ADDR (HEP_BASE_ADDR + CR_SOCIF_TIMEOUT_OFFSET) |
| #define CR_SOCIF_FLUSH 0x2000 |
| #define CR_SOCIF_TIMEOUT_ENABLE 0x1000 |
| #define CR_SOCIF_TIMEOUT_PERIOD 0x0fff |
| #define CR_SOCIF_TIMEOUT_PERIOD_SHIFT 0 |
| #define CR_SOCIF_STATUS_OFFSET 0x030 |
| #define CR_SOCIF_STATUS_ADDR (HEP_BASE_ADDR + CR_SOCIF_STATUS_OFFSET) |
| #define CR_SOCIF_STATUS 0x1 |
| #define CR_DDRC_EMR_OFFSET 0x1bc |
| #define CR_DDRC_EMR (HEP_BASE_ADDR + CR_DDRC_EMR_OFFSET) |
| #define CR_DDRC_SELFREF_EN_OFFSET 0x248 |
| #define CR_DDRC_SELFREF_EN (HEP_BASE_ADDR + CR_DDRC_SELFREF_EN_OFFSET) |
| #define CR_DDRC_OPERATING_MODE_OFFSET 0x26c |
| #define CR_DDRC_OPERATING_MODE (HEP_BASE_ADDR + CR_DDRC_OPERATING_MODE_OFFSET) |
| #define CR_DDRC_OPERATING_MODE_SELFREF 0x3 |
| /* CR_DDRC_PADS not in ES1 */ |
| #define CR_DDRC_PADS_OFFSET 0x2ac |
| #define CR_DDRC_PADS (HEP_BASE_ADDR + CR_DDRC_PADS_OFFSET) |
| #define CR_DDRC_PADS_MDDR_E2 0x10 |
| #define CR_DDRC_PADS_MDDR_E1 0x08 |
| #define CR_DDRC_PADS_ODTEN 0x04 |
| #define CR_DDRC_PADS_ODTSEL 0x02 |
| #define CR_DDRC_PADS_ODT (CR_DDRC_PADS_ODTEN | CR_DDRC_PADS_ODTSEL) |
| #define CR_DDRC_PDAS_ODT_DISABLED 0 |
| #define CR_DDRC_PADS_ODT_75_OHM CR_DDRC_PADS_ODTEN |
| #define CR_DDRC_PADS_ODT_150_OHM CR_DDRC_PADS_ODTSEL |
| #define CR_DDRC_PDAS_ODT_50_OHM (CR_DDRC_PADS_ODTEN | CR_DDRC_PADS_ODTSEL) |
| #define CR_DDRC_PADS_DRIVESEL 0x01 |
| |
| #define SYS_INF_BASE_ADDR 0x02009000 |
| #define SYS_INF_SIZE 0xff |
| |
| #define MDC_BASE_ADDR 0x0200c000 |
| #define MDC_SIZE 0xfff |
| |
| #define UCC0_HOST_BASE_ADDR 0x02010000 |
| #define UCC0_HOST_SIZE 0x2fff |
| |
| #define UCC0_MC_BASE_ADDR 0x02013000 |
| #define UCC0_MC_SIZE 0xfff |
| #define UCC0_MC_REQ_MAX 8 |
| |
| #define UCC1_HOST_BASE_ADDR 0x02014000 |
| #define UCC1_HOST_SIZE 0x2fff |
| |
| #define UCC1_MC_BASE_ADDR 0x02017000 |
| #define UCC1_MC_SIZE 0xfff |
| #define UCC1_MC_REQ_MAX 8 |
| |
| #define USB_BASE_ADDR 0x02020000 |
| #define USB_SIZE 0xefff |
| |
| /*TOP LEVEL Clock Control registers*/ |
| #define CR_TOP_CLKSWITCH (GPIO_CRTOP_BASE_ADDR + 0x0108) |
| #define CR_TOP_CLKENAB (GPIO_CRTOP_BASE_ADDR + 0x010C) |
| #define CR_TOP_CLKDELETE (GPIO_CRTOP_BASE_ADDR + 0x0110) |
| #define CR_TOP_SYSCLK_DIV (GPIO_CRTOP_BASE_ADDR + 0x0114) |
| #define CR_TOP_META_CLKDIV (GPIO_CRTOP_BASE_ADDR + 0x0118) |
| #define CR_TOP_META_CLKDELETE (GPIO_CRTOP_BASE_ADDR + 0x011c) |
| #define CR_TOP_AFE_DIV (GPIO_CRTOP_BASE_ADDR + 0x0120) |
| #define CR_TOP_ADC_PLLDIV (GPIO_CRTOP_BASE_ADDR + 0x0124) |
| #define CR_TOP_UART_CLK_DIV (GPIO_CRTOP_BASE_ADDR + 0x0128) |
| #define CR_TOP_PDMCK_CTL (GPIO_CRTOP_BASE_ADDR + 0x0130) |
| #define CR_TOP_SPICLK_DIV (GPIO_CRTOP_BASE_ADDR + 0x0134) |
| #define CR_TOP_SPI1CLK_DIV (GPIO_CRTOP_BASE_ADDR + 0x0138) |
| #define CR_TOP_I2SCLK_DIV (GPIO_CRTOP_BASE_ADDR + 0x013C) |
| #define CR_TOP_USB_PLLDIV (GPIO_CRTOP_BASE_ADDR + 0x0140) |
| #define CR_TOP_SDHOSTCLK_DIV (GPIO_CRTOP_BASE_ADDR + 0x0144) |
| #define CR_TOP_SYSPLL_CTL0 (GPIO_CRTOP_BASE_ADDR + 0x0150) |
| #define CR_TOP_SYSPLL_CTL1 (GPIO_CRTOP_BASE_ADDR + 0x0154) |
| #define CR_TOP_ADCPLL_CTL0 (GPIO_CRTOP_BASE_ADDR + 0x0158) |
| #define CR_TOP_ADCPLL_CTL1 (GPIO_CRTOP_BASE_ADDR + 0x015C) |
| #define CR_TOP_CLKSWITCH2 (GPIO_CRTOP_BASE_ADDR + 0x0188) |
| #define CR_TOP_CLKENAB2 (GPIO_CRTOP_BASE_ADDR + 0x018C) |
| #define CR_TOP_I2S_DIV2 (GPIO_CRTOP_BASE_ADDR + 0x0190) |
| #define CR_TOP_PIXEL_CLK_DIV (GPIO_CRTOP_BASE_ADDR + 0x0198) |
| #define CR_TOP_DDR_CLKDIV (GPIO_CRTOP_BASE_ADDR + 0x01AC) |
| #define CR_TOP_AUDGTI_CTRL (GPIO_CRTOP_BASE_ADDR + 0x01B8) |
| #define CR_TOP_AUDGTI_DOUT (GPIO_CRTOP_BASE_ADDR + 0x01BC) |
| |
| /* AFE control registers */ |
| #define CR_AFE_CTRL (GPIO_CRTOP_BASE_ADDR + 0x01C0) |
| #define CR_AFE_AUXDACPD (1 << 6) |
| #define CR_AFE_AUXDACSTBY (1 << 5) |
| #define CR_AFE_AUXDAC (GPIO_CRTOP_BASE_ADDR + 0x01C4) |
| #define CR_AFE_AUXDACSEL 0x00030000 |
| #define CR_AFE_AUXDACSEL_SHIFT 16 |
| #define CR_AFE_AUXDACSEL_UCC0_EXT_CTL_1 2 |
| #define CR_AFE_AUXDACSEL_UCC0_EXT_GAIN_1 1 |
| #define CR_AFE_AUXDACSEL_CR_AFE_AUXDACIN 0 |
| #define CR_AFE_AUXDACIN 0x000000FF |
| #define CR_AFE_AUXDACIN_SHIFT 0 |
| |
| /* Audio control registers */ |
| #define CR_AUDIO_ADC_CTRL (GPIO_CRTOP_BASE_ADDR + 0x01E0) |
| #define CR_AUDIO_PSCNTADC_L_SHIFT 0 |
| #define CR_AUDIO_PSCNTADC_L_MASK 0x1 |
| #define CR_AUDIO_PSCNTADC_R_SHIFT 1 |
| #define CR_AUDIO_PSCNTADC_R_MASK 0x1 |
| #define CR_AUDIO_PSCNTADC_L_SHIFT 0 |
| #define CR_AUDIO_PSCNTADC_L_MASK 0x1 |
| #define CR_AUDIO_GAINCTRL_MIC_P_SHIFT 8 |
| #define CR_AUDIO_GAINCTRL_MIC_P_MASK 0x7 |
| #define CR_AUDIO_GAINCTRL_MIC_N_SHIFT 12 |
| #define CR_AUDIO_GAINCTRL_MIC_N_MASK 0x7 |
| #define CR_AUDIO_GAINCTRL_LINE_L_SHIFT 16 |
| #define CR_AUDIO_GAINCTRL_LINE_L_MASK 0x7 |
| #define CR_AUDIO_GAINCTRL_LINE_R_SHIFT 20 |
| #define CR_AUDIO_GAINCTRL_LINE_R_MASK 0x7 |
| #define CR_AUDIO_GAINCTRL_ADC_L_SHIFT 24 |
| #define CR_AUDIO_GAINCTRL_ADC_L_MASK 0x7 |
| #define CR_AUDIO_GAINCTRL_ADC_R_SHIFT 28 |
| #define CR_AUDIO_GAINCTRL_ADC_R_MASK 0x7 |
| |
| #define CR_AUDIO_HP_CTRL (GPIO_CRTOP_BASE_ADDR + 0x01E4) |
| #define CR_AUDIO_PSCNTHP_L_SHIFT 0 |
| #define CR_AUDIO_PSCNTHP_L_MASK 0x1 |
| #define CR_AUDIO_PSCNTHP_R_SHIFT 1 |
| #define CR_AUDIO_PSCNTHP_R_MASK 0x1 |
| #define CR_AUDIO_RSTB_DIG_IP_SHIFT 5 |
| #define CR_AUDIO_RSTB_DIG_IP_MASK 0x1 |
| #define CR_AUDIO_RSTB_ANA_IP_SHIFT 6 |
| #define CR_AUDIO_RSTB_ANA_IP_MASK 0x1 |
| #define CR_AUDIO_RSTB_DIG_OP_SHIFT 7 |
| #define CR_AUDIO_RSTB_DIG_OP_MASK 0x1 |
| #define CR_AUDIO_RSTB_ANA_OP_SHIFT 8 |
| #define CR_AUDIO_RSTB_ANA_OP_MASK 0x1 |
| #define CR_AUDIO_PSCNT_PWM_A_SHIFT 9 |
| #define CR_AUDIO_PSCNT_PWM_A_MASK 0x1 |
| #define CR_AUDIO_PSCNT_PWM_B_SHIFT 10 |
| #define CR_AUDIO_PSCNT_PWM_B_MASK 0x1 |
| #define CR_AUDIO_PSCNT_PWM_C_SHIFT 11 |
| #define CR_AUDIO_PSCNT_PWM_C_MASK 0x1 |
| #define CR_AUDIO_PSCNT_PWM_D_SHIFT 12 |
| #define CR_AUDIO_PSCNT_PWM_D_MASK 0x1 |
| #define CR_AUDIO_PSCNT_PWM_E_SHIFT 13 |
| #define CR_AUDIO_PSCNT_PWM_E_MASK 0x1 |
| #define CR_AUDIO_PSCNT_PWM_F_SHIFT 14 |
| #define CR_AUDIO_PSCNT_PWM_F_MASK 0x1 |
| #define CR_AUDIO_PGA_MODE_SHIFT 16 |
| #define CR_AUDIO_PGA_MODE_MASK 0x7 |
| #define CR_AUDIO_RST_BG_IP_SHIFT 20 |
| #define CR_AUDIO_RST_BG_IP_MASK 0x1 |
| #define CR_AUDIO_PWDN_BG_IP_SHIFT 21 |
| #define CR_AUDIO_PWDN_BG_IP_MASK 0x1 |
| #define CR_AUDIO_RST_BG_OP_SHIFT 22 |
| #define CR_AUDIO_RST_BG_OP_MASK 0x1 |
| #define CR_AUDIO_PWDN_BG_OP_SHIFT 23 |
| #define CR_AUDIO_PWDN_BG_OP_MASK 0x1 |
| #define CR_AUDIO_I2S_EXT_SHIFT 24 |
| #define CR_AUDIO_I2S_EXT_MASK 0x1 |
| #define CR_AUDIO_PWDN_PLL_SHIFT 28 |
| #define CR_AUDIO_PWDN_PLL_MASK 0x1 |
| |
| #define CR_AUDIO_GAIN0 (GPIO_CRTOP_BASE_ADDR + 0x01e8) |
| #define CR_AUDIO_GAIN1 (GPIO_CRTOP_BASE_ADDR + 0x01ec) |
| #define CR_AUDIO_MUTE (GPIO_CRTOP_BASE_ADDR + 0x01f4) |
| |
| |
| /* CR_TOP_CLKSWITCH */ |
| #define CR_TOP_USBPLL_CLK_3_SW_BIT 29 |
| #define CR_TOP_USBPLL_CLK_2_SW_BIT 28 |
| #define CR_TOP_USBPLL_CLK_1_SW_BIT 27 |
| #define CR_TOP_USBPLL_CLK_0_SW_BIT 26 |
| #define CR_TOP_ADCPLL_CLK_0_SW_BIT 22 |
| #define CR_TOP_UART_SW_BIT 14 |
| #define CR_TOP_SCB_SW_BIT 13 |
| #define CR_TOP_I2S_1_SW_BIT 12 |
| #define CR_TOP_I2S_0_SW_BIT 11 |
| #define CR_TOP_I2S_2_SW_BIT 10 |
| #define CR_TOP_SYSCLK1_SW_BIT 1 |
| /* CR_TOP_CLKENAB */ |
| #ifdef CONFIG_SOC_COMET_ES1 |
| #define CR_TOP_USBPLL_CLK_3_EN_BIT 29 |
| #endif |
| #define CR_TOP_USB_CLK_1_EN_BIT 19 |
| #define CR_TOP_UART_EN_BIT 14 |
| #define CR_TOP_SCB_EN_BIT 13 |
| #define CR_TOP_I2S_1_EN_BIT 12 |
| #define CR_TOP_CLKOUT1_3_EN_BIT 9 |
| #define CR_TOP_CLKOUT0_3_EN_BIT 5 |
| /* CR_TOP_SYSPLL_CTL1 */ |
| #define CR_TOP_SYSPLL_PWRDN_BIT 24 |
| /* CR_TOP_ADCPLL_CTL0 */ |
| #define CR_TOP_ADCPLL_BWADJ_SHIFT 20 |
| #define CR_TOP_ADCPLL_BWADJ_MASK 0xfff |
| #define CR_TOP_ADCPLL_CLKF_SHIFT 4 |
| #define CR_TOP_ADCPLL_CLKF_MASK 0x1fff |
| #define CR_TOP_ADCPLL_CLKOD_SHIFT 0 |
| #define CR_TOP_ADCPLL_CLKOD_MASK 0x7 |
| /* CR_TOP_ADCPLL_CTL1 */ |
| #define CR_TOP_ADCPLL_RESET_BIT 28 |
| #define CR_TOP_ADCPLL_FASTEN_BIT 27 |
| #define CR_TOP_ADCPLL_ENSAT_BIT 26 |
| #define CR_TOP_ADCPLL_BYPASS_BIT 25 |
| #define CR_TOP_ADCPLL_PWRDN_BIT 24 |
| #define CR_TOP_ADCPLL_CLKR_SHIFT 0 |
| #define CR_TOP_ADCPLL_CLKR_MASK 0x3f |
| /* CR_TOP_CLKSWITCH2 */ |
| #define CR_TOP_PIXEL_CLK_0_SW_BIT 0 |
| #define CR_TOP_PIXEL_CLK_1_SW_BIT 1 |
| #define CR_TOP_PIXEL_CLK_2_SW_BIT 2 |
| /* CR_TOP_CLKENAB2 */ |
| #define CR_TOP_PIXEL_CLK_2_EN_BIT 2 |
| |
| /*Peripheral Clock control*/ |
| #define CR_PERIP_CLK_EN (CR_PERIP_BASE_ADDR + 0x0010) |
| #define CR_PERIP_USB_CLK_EN_BIT 13 |
| #define CR_PERIP_SDHOST_CLK_EN_BIT 12 |
| #define CR_PERIP_LCD_CLK_EN_BIT 11 |
| #define CR_PERIP_I2SIN_CLK_EN_BIT 10 |
| #define CR_PERIP_I2SOUT_CLK_EN_BIT 9 |
| #define CR_PERIP_SPIM1_CLK_EN_BIT 8 |
| #define CR_PERIP_SPIS0_CLK_EN_BIT 7 |
| #define CR_PERIP_SPIM0_CLK_EN_BIT 6 |
| #define CR_PERIP_UART1_CLK_EN_BIT 5 |
| #define CR_PERIP_UART0_CLK_EN_BIT 4 |
| #define CR_PERIP_SDIO_CLK_EN_BIT 3 |
| #define CR_PERIP_I2C2_CLK_EN_BIT 2 |
| #define CR_PERIP_I2C1_CLK_EN_BIT 1 |
| #define CR_PERIP_I2C0_CLK_EN_BIT 0 |
| |
| |
| /* Peripheral DMA Channel Mux values. |
| * Comet has a top-level mux which allows assigning any peripheral to |
| * any DMA channel. |
| */ |
| |
| #define DMA_MUX_SDIO_DEV_WR 1 |
| #define DMA_MUX_SDIO_DEV_RD 2 |
| #define DMA_MUX_SPI_MASTER0_WR 3 |
| #define DMA_MUX_SPI_MASTER0_RD 4 |
| #define DMA_MUX_SPI_SLAVE_WR 5 |
| #define DMA_MUX_SPI_SLAVE_RD 6 |
| #define DMA_MUX_SPI_MASTER1_RD 7 |
| #define DMA_MUX_SPI_MASTER1_WR 8 |
| #define DMA_MUX_I2S_WR 9 |
| #define DMA_MUX_I2S_RD 10 |
| #define DMA_MUX_LCD_WR 11 |
| #define DMA_MUX_SDIO_HOST_RD 12 |
| #define DMA_MUX_SDIO_HOST_WR 13 |
| |
| /* UCC address blocks */ |
| |
| #define UCCP_BASE_ADDR 0xe0200000 |
| #define UCCP_SIZE 0x00150000 |
| |
| #define UCCP_SYSINT_BASE_ADDR 0xe0200000 |
| #define UCCP_SYSINT_SIZE 0x00060000 |
| |
| #define UCCP0_MTX_BASE_ADDR 0xe0260000 |
| #define UCCP0_MTX_SIZE 0x00050000 |
| |
| #define UCCP0_MCP16BIT_BASE_ADDR 0xe02b0000 |
| #define UCCP0_MCP16BIT_SIZE 0x00008e00 |
| |
| #define UCCP0_MCP24BIT_BASE_ADDR 0xe02c0000 |
| #define UCCP0_MCP24BIT_SIZE 0x0002b800 |
| |
| #define UCCP1_MTX_BASE_ADDR 0xe0300000 |
| #define UCCP1_MTX_SIZE 0x00050000 |
| |
| |
| |
| #endif /* _TZ1090_DEFS_H_ */ |
