| From c0d96aed8c6dd925afe9ea35491a0cd458642a86 Mon Sep 17 00:00:00 2001 |
| From: Jason Chen <jason.chen@linaro.org> |
| Date: Wed, 30 Nov 2011 11:34:27 +0800 |
| Subject: MXC PWM: should active during DOZE/WAIT/DBG mode |
| |
| From: Jason Chen <jason.chen@linaro.org> |
| |
| commit c0d96aed8c6dd925afe9ea35491a0cd458642a86 upstream. |
| |
| Signed-off-by: Jason Chen <jason.chen@linaro.org> |
| Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> |
| |
| --- |
| arch/arm/plat-mxc/pwm.c | 7 ++++++- |
| 1 file changed, 6 insertions(+), 1 deletion(-) |
| |
| --- a/arch/arm/plat-mxc/pwm.c |
| +++ b/arch/arm/plat-mxc/pwm.c |
| @@ -31,6 +31,9 @@ |
| #define MX3_PWMSAR 0x0C /* PWM Sample Register */ |
| #define MX3_PWMPR 0x10 /* PWM Period Register */ |
| #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4) |
| +#define MX3_PWMCR_DOZEEN (1 << 24) |
| +#define MX3_PWMCR_WAITEN (1 << 23) |
| +#define MX3_PWMCR_DBGEN (1 << 22) |
| #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16) |
| #define MX3_PWMCR_CLKSRC_IPG (1 << 16) |
| #define MX3_PWMCR_EN (1 << 0) |
| @@ -76,7 +79,9 @@ int pwm_config(struct pwm_device *pwm, i |
| writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR); |
| writel(period_cycles, pwm->mmio_base + MX3_PWMPR); |
| |
| - cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN; |
| + cr = MX3_PWMCR_PRESCALER(prescale) | |
| + MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN | |
| + MX3_PWMCR_DBGEN | MX3_PWMCR_EN; |
| |
| if (cpu_is_mx25()) |
| cr |= MX3_PWMCR_CLKSRC_IPG; |
