| From 26cdd302915c704f32e777984735e86a2b311909 Mon Sep 17 00:00:00 2001 |
| From: Frank Rowand <frank.rowand@am.sony.com> |
| Date: Mon, 19 Sep 2011 14:51:14 -0700 |
| Subject: [PATCH 018/274] preempt-rt: Convert arm boot_lock to raw |
| |
| The arm boot_lock is used by the secondary processor startup code. The locking |
| task is the idle thread, which has idle->sched_class == &idle_sched_class. |
| idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the |
| lock, the attempt to wake it when the lock becomes available will fail: |
| |
| try_to_wake_up() |
| ... |
| activate_task() |
| enqueue_task() |
| p->sched_class->enqueue_task(rq, p, flags) |
| |
| Fix by converting boot_lock to a raw spin lock. |
| |
| Signed-off-by: Frank Rowand <frank.rowand@am.sony.com> |
| Link: http://lkml.kernel.org/r/4E77B952.3010606@am.sony.com |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| --- |
| arch/arm/mach-exynos/platsmp.c | 12 ++++++------ |
| arch/arm/mach-msm/platsmp.c | 10 +++++----- |
| arch/arm/mach-omap2/omap-smp.c | 10 +++++----- |
| arch/arm/mach-ux500/platsmp.c | 10 +++++----- |
| arch/arm/plat-versatile/platsmp.c | 10 +++++----- |
| 5 files changed, 26 insertions(+), 26 deletions(-) |
| |
| diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c |
| index 36c3984..77499ea 100644 |
| --- a/arch/arm/mach-exynos/platsmp.c |
| +++ b/arch/arm/mach-exynos/platsmp.c |
| @@ -62,7 +62,7 @@ static void __iomem *scu_base_addr(void) |
| return (void __iomem *)(S5P_VA_SCU); |
| } |
| |
| -static DEFINE_SPINLOCK(boot_lock); |
| +static DEFINE_RAW_SPINLOCK(boot_lock); |
| |
| void __cpuinit platform_secondary_init(unsigned int cpu) |
| { |
| @@ -82,8 +82,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) |
| /* |
| * Synchronise with the boot thread. |
| */ |
| - spin_lock(&boot_lock); |
| - spin_unlock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| } |
| |
| int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| @@ -94,7 +94,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * Set synchronisation state between this boot processor |
| * and the secondary one |
| */ |
| - spin_lock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| |
| /* |
| * The secondary processor is waiting to be released from |
| @@ -123,7 +123,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| |
| if (timeout == 0) { |
| printk(KERN_ERR "cpu1 power enable failed"); |
| - spin_unlock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| return -ETIMEDOUT; |
| } |
| } |
| @@ -151,7 +151,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * now the secondary core is starting up let it run its |
| * calibrations, then wait for it to finish |
| */ |
| - spin_unlock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| |
| return pen_release != -1 ? -ENOSYS : 0; |
| } |
| diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c |
| index db0117e..87daf5f 100644 |
| --- a/arch/arm/mach-msm/platsmp.c |
| +++ b/arch/arm/mach-msm/platsmp.c |
| @@ -40,7 +40,7 @@ extern void msm_secondary_startup(void); |
| */ |
| volatile int pen_release = -1; |
| |
| -static DEFINE_SPINLOCK(boot_lock); |
| +static DEFINE_RAW_SPINLOCK(boot_lock); |
| |
| static inline int get_core_count(void) |
| { |
| @@ -70,8 +70,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) |
| /* |
| * Synchronise with the boot thread. |
| */ |
| - spin_lock(&boot_lock); |
| - spin_unlock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| } |
| |
| static __cpuinit void prepare_cold_cpu(unsigned int cpu) |
| @@ -108,7 +108,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * set synchronisation state between this boot processor |
| * and the secondary one |
| */ |
| - spin_lock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| |
| /* |
| * The secondary processor is waiting to be released from |
| @@ -142,7 +142,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * now the secondary core is starting up let it run its |
| * calibrations, then wait for it to finish |
| */ |
| - spin_unlock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| |
| return pen_release != -1 ? -ENOSYS : 0; |
| } |
| diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c |
| index deffbf1..81ca676 100644 |
| --- a/arch/arm/mach-omap2/omap-smp.c |
| +++ b/arch/arm/mach-omap2/omap-smp.c |
| @@ -34,7 +34,7 @@ |
| /* SCU base address */ |
| static void __iomem *scu_base; |
| |
| -static DEFINE_SPINLOCK(boot_lock); |
| +static DEFINE_RAW_SPINLOCK(boot_lock); |
| |
| void __iomem *omap4_get_scu_base(void) |
| { |
| @@ -65,8 +65,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) |
| /* |
| * Synchronise with the boot thread. |
| */ |
| - spin_lock(&boot_lock); |
| - spin_unlock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| } |
| |
| int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| @@ -77,7 +77,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * Set synchronisation state between this boot processor |
| * and the secondary one |
| */ |
| - spin_lock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| |
| /* |
| * Update the AuxCoreBoot0 with boot state for secondary core. |
| @@ -117,7 +117,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * Now the secondary core is starting up let it run its |
| * calibrations, then wait for it to finish |
| */ |
| - spin_unlock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| |
| return 0; |
| } |
| diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c |
| index eff5842..acc9da2 100644 |
| --- a/arch/arm/mach-ux500/platsmp.c |
| +++ b/arch/arm/mach-ux500/platsmp.c |
| @@ -58,7 +58,7 @@ static void __iomem *scu_base_addr(void) |
| return NULL; |
| } |
| |
| -static DEFINE_SPINLOCK(boot_lock); |
| +static DEFINE_RAW_SPINLOCK(boot_lock); |
| |
| void __cpuinit platform_secondary_init(unsigned int cpu) |
| { |
| @@ -78,8 +78,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) |
| /* |
| * Synchronise with the boot thread. |
| */ |
| - spin_lock(&boot_lock); |
| - spin_unlock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| } |
| |
| int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| @@ -90,7 +90,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * set synchronisation state between this boot processor |
| * and the secondary one |
| */ |
| - spin_lock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| |
| /* |
| * The secondary processor is waiting to be released from |
| @@ -111,7 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * now the secondary core is starting up let it run its |
| * calibrations, then wait for it to finish |
| */ |
| - spin_unlock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| |
| return pen_release != -1 ? -ENOSYS : 0; |
| } |
| diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c |
| index 49c7db4..1f7a3d2 100644 |
| --- a/arch/arm/plat-versatile/platsmp.c |
| +++ b/arch/arm/plat-versatile/platsmp.c |
| @@ -38,7 +38,7 @@ static void __cpuinit write_pen_release(int val) |
| outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); |
| } |
| |
| -static DEFINE_SPINLOCK(boot_lock); |
| +static DEFINE_RAW_SPINLOCK(boot_lock); |
| |
| void __cpuinit platform_secondary_init(unsigned int cpu) |
| { |
| @@ -58,8 +58,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) |
| /* |
| * Synchronise with the boot thread. |
| */ |
| - spin_lock(&boot_lock); |
| - spin_unlock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| } |
| |
| int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| @@ -70,7 +70,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * Set synchronisation state between this boot processor |
| * and the secondary one |
| */ |
| - spin_lock(&boot_lock); |
| + raw_spin_lock(&boot_lock); |
| |
| /* |
| * This is really belt and braces; we hold unintended secondary |
| @@ -100,7 +100,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) |
| * now the secondary core is starting up let it run its |
| * calibrations, then wait for it to finish |
| */ |
| - spin_unlock(&boot_lock); |
| + raw_spin_unlock(&boot_lock); |
| |
| return pen_release != -1 ? -ENOSYS : 0; |
| } |
| -- |
| 1.7.10.4 |
| |