| From 54b559b571104a7ae3c968be6a054996f9ddd0f5 Mon Sep 17 00:00:00 2001 |
| From: Felipe Balbi <felipe.balbi@linux.intel.com> |
| Date: Tue, 20 Dec 2016 14:08:48 +0200 |
| Subject: [PATCH] usb: dwc3: ep0: explicitly call dwc3_ep0_prepare_one_trb() |
| |
| commit 19ec31230eb3084431bc2e565fd085f79f564274 upstream. |
| |
| Let's call dwc3_ep0_prepare_one_trb() explicitly |
| because there are occasions where we will need more |
| than one TRB to handle an EP0 transfer. |
| |
| A follow-up patch will fix one bug related to |
| multiple-TRB Data Phases when it comes to |
| mapping/unmapping requests for DMA. |
| |
| Cc: <stable@vger.kernel.org> |
| Reported-by: Janusz Dziedzic <januszx.dziedzic@linux.intel.com> |
| Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c |
| index 5ac5b3a2704a..ef2d5cc01bd5 100644 |
| --- a/drivers/usb/dwc3/ep0.c |
| +++ b/drivers/usb/dwc3/ep0.c |
| @@ -85,8 +85,7 @@ static void dwc3_ep0_prepare_one_trb(struct dwc3 *dwc, u8 epnum, |
| trace_dwc3_prepare_trb(dep, trb); |
| } |
| |
| -static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, |
| - u32 len, u32 type, bool chain) |
| +static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum) |
| { |
| struct dwc3_gadget_ep_cmd_params params; |
| struct dwc3_ep *dep; |
| @@ -96,8 +95,6 @@ static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma, |
| if (dep->flags & DWC3_EP_BUSY) |
| return 0; |
| |
| - dwc3_ep0_prepare_one_trb(dwc, epnum, buf_dma, len, type, chain); |
| - |
| memset(¶ms, 0, sizeof(params)); |
| params.param0 = upper_32_bits(dwc->ep0_trb_addr); |
| params.param1 = lower_32_bits(dwc->ep0_trb_addr); |
| @@ -312,8 +309,9 @@ void dwc3_ep0_out_start(struct dwc3 *dwc) |
| { |
| int ret; |
| |
| - ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8, |
| + dwc3_ep0_prepare_one_trb(dwc, 0, dwc->ctrl_req_addr, 8, |
| DWC3_TRBCTL_CONTROL_SETUP, false); |
| + ret = dwc3_ep0_start_trans(dwc, 0); |
| WARN_ON(ret < 0); |
| } |
| |
| @@ -884,9 +882,9 @@ static void dwc3_ep0_complete_data(struct dwc3 *dwc, |
| |
| dwc->ep0_next_event = DWC3_EP0_COMPLETE; |
| |
| - ret = dwc3_ep0_start_trans(dwc, epnum, |
| - dwc->ctrl_req_addr, 0, |
| - DWC3_TRBCTL_CONTROL_DATA, false); |
| + dwc3_ep0_prepare_one_trb(dwc, epnum, dwc->ctrl_req_addr, |
| + 0, DWC3_TRBCTL_CONTROL_DATA, false); |
| + ret = dwc3_ep0_start_trans(dwc, epnum); |
| WARN_ON(ret < 0); |
| } |
| } |
| @@ -970,9 +968,10 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
| req->direction = !!dep->number; |
| |
| if (req->request.length == 0) { |
| - ret = dwc3_ep0_start_trans(dwc, dep->number, |
| + dwc3_ep0_prepare_one_trb(dwc, dep->number, |
| dwc->ctrl_req_addr, 0, |
| DWC3_TRBCTL_CONTROL_DATA, false); |
| + ret = dwc3_ep0_start_trans(dwc, dep->number); |
| } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) |
| && (dep->number == 0)) { |
| u32 transfer_size = 0; |
| @@ -990,7 +989,7 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
| if (req->request.length > DWC3_EP0_BOUNCE_SIZE) { |
| transfer_size = ALIGN(req->request.length - maxpacket, |
| maxpacket); |
| - ret = dwc3_ep0_start_trans(dwc, dep->number, |
| + dwc3_ep0_prepare_one_trb(dwc, dep->number, |
| req->request.dma, |
| transfer_size, |
| DWC3_TRBCTL_CONTROL_DATA, |
| @@ -1002,9 +1001,10 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
| |
| dwc->ep0_bounced = true; |
| |
| - ret = dwc3_ep0_start_trans(dwc, dep->number, |
| + dwc3_ep0_prepare_one_trb(dwc, dep->number, |
| dwc->ep0_bounce_addr, transfer_size, |
| DWC3_TRBCTL_CONTROL_DATA, false); |
| + ret = dwc3_ep0_start_trans(dwc, dep->number); |
| } else { |
| ret = usb_gadget_map_request(&dwc->gadget, &req->request, |
| dep->number); |
| @@ -1013,9 +1013,10 @@ static void __dwc3_ep0_do_control_data(struct dwc3 *dwc, |
| return; |
| } |
| |
| - ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma, |
| + dwc3_ep0_prepare_one_trb(dwc, dep->number, req->request.dma, |
| req->request.length, DWC3_TRBCTL_CONTROL_DATA, |
| false); |
| + ret = dwc3_ep0_start_trans(dwc, dep->number); |
| } |
| |
| WARN_ON(ret < 0); |
| @@ -1029,8 +1030,9 @@ static int dwc3_ep0_start_control_status(struct dwc3_ep *dep) |
| type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3 |
| : DWC3_TRBCTL_CONTROL_STATUS2; |
| |
| - return dwc3_ep0_start_trans(dwc, dep->number, |
| + dwc3_ep0_prepare_one_trb(dwc, dep->number, |
| dwc->ctrl_req_addr, 0, type, false); |
| + return dwc3_ep0_start_trans(dwc, dep->number); |
| } |
| |
| static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep) |
| -- |
| 2.10.1 |
| |