| From bf953672366998a8b096f339568f71e27b2c071b Mon Sep 17 00:00:00 2001 |
| From: CQ Tang <cq.tang@intel.com> |
| Date: Mon, 30 Jan 2017 09:39:52 -0800 |
| Subject: [PATCH] iommu/vt-d: Fix some macros that are incorrectly specified in |
| intel-iommu |
| |
| commit aaa59306b0b7e0ca4ba92cc04c5db101cbb1c096 upstream. |
| |
| Some of the macros are incorrect with wrong bit-shifts resulting in picking |
| the incorrect invalidation granularity. Incorrect Source-ID in extended |
| devtlb invalidation caused device side errors. |
| |
| To: Joerg Roedel <joro@8bytes.org> |
| To: David Woodhouse <dwmw2@infradead.org> |
| Cc: iommu@lists.linux-foundation.org |
| Cc: linux-kernel@vger.kernel.org |
| Cc: stable@vger.kernel.org |
| Cc: CQ Tang <cq.tang@intel.com> |
| Cc: Ashok Raj <ashok.raj@intel.com> |
| |
| Fixes: 2f26e0a9 ("iommu/vt-d: Add basic SVM PASID support") |
| Signed-off-by: CQ Tang <cq.tang@intel.com> |
| Signed-off-by: Ashok Raj <ashok.raj@intel.com> |
| Tested-by: CQ Tang <cq.tang@intel.com> |
| Signed-off-by: Joerg Roedel <jroedel@suse.de> |
| Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> |
| |
| diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h |
| index d49e26c6cdc7..23e129ef6726 100644 |
| --- a/include/linux/intel-iommu.h |
| +++ b/include/linux/intel-iommu.h |
| @@ -153,8 +153,8 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) |
| #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60) |
| #define DMA_TLB_DSI_FLUSH (((u64)2) << 60) |
| #define DMA_TLB_PSI_FLUSH (((u64)3) << 60) |
| -#define DMA_TLB_IIRG(type) ((type >> 60) & 7) |
| -#define DMA_TLB_IAIG(val) (((val) >> 57) & 7) |
| +#define DMA_TLB_IIRG(type) ((type >> 60) & 3) |
| +#define DMA_TLB_IAIG(val) (((val) >> 57) & 3) |
| #define DMA_TLB_READ_DRAIN (((u64)1) << 49) |
| #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48) |
| #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32) |
| @@ -164,9 +164,9 @@ static inline void dmar_writeq(void __iomem *addr, u64 val) |
| |
| /* INVALID_DESC */ |
| #define DMA_CCMD_INVL_GRANU_OFFSET 61 |
| -#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3) |
| -#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3) |
| -#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3) |
| +#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4) |
| +#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4) |
| +#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4) |
| #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7) |
| #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6) |
| #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16))) |
| @@ -316,8 +316,8 @@ enum { |
| #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) |
| #define QI_DEV_EIOTLB_GLOB(g) ((u64)g) |
| #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) |
| -#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32) |
| -#define QI_DEV_EIOTLB_QDEP(qd) (((qd) & 0x1f) << 16) |
| +#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) |
| +#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) |
| #define QI_DEV_EIOTLB_MAX_INVS 32 |
| |
| #define QI_PGRP_IDX(idx) (((u64)(idx)) << 55) |
| -- |
| 2.12.0 |
| |