| From 98f42221501353067251fbf11e732707dbb68ce3 Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali.rohar@gmail.com> |
| Date: Fri, 19 Feb 2016 10:35:39 -0800 |
| Subject: ARM: OMAP3: Add cpuidle parameters table for omap3430 |
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| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Pali Rohár <pali.rohar@gmail.com> |
| |
| commit 98f42221501353067251fbf11e732707dbb68ce3 upstream. |
| |
| Based on CPU type choose generic omap3 or omap3430 specific cpuidle |
| parameters. Parameters for omap3430 were measured on Nokia N900 device and |
| added by commit 5a1b1d3a9efa ("OMAP3: RX-51: Pass cpu idle parameters") |
| which were later removed by commit 231900afba52 ("ARM: OMAP3: cpuidle - |
| remove rx51 cpuidle parameters table") due to huge code complexity. |
| |
| This patch brings cpuidle parameters for omap3430 devices again, but uses |
| simple condition based on CPU type. |
| |
| Fixes: 231900afba52 ("ARM: OMAP3: cpuidle - remove rx51 cpuidle |
| parameters table") |
| Signed-off-by: Pali Rohár <pali.rohar@gmail.com> |
| Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> |
| Signed-off-by: Tony Lindgren <tony@atomide.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/mach-omap2/cpuidle34xx.c | 69 +++++++++++++++++++++++++++++++++++++- |
| 1 file changed, 68 insertions(+), 1 deletion(-) |
| |
| --- a/arch/arm/mach-omap2/cpuidle34xx.c |
| +++ b/arch/arm/mach-omap2/cpuidle34xx.c |
| @@ -34,6 +34,7 @@ |
| #include "pm.h" |
| #include "control.h" |
| #include "common.h" |
| +#include "soc.h" |
| |
| /* Mach specific information to be recorded in the C-state driver_data */ |
| struct omap3_idle_statedata { |
| @@ -322,6 +323,69 @@ static struct cpuidle_driver omap3_idle_ |
| .safe_state_index = 0, |
| }; |
| |
| +/* |
| + * Numbers based on measurements made in October 2009 for PM optimized kernel |
| + * with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP, |
| + * and worst case latencies). |
| + */ |
| +static struct cpuidle_driver omap3430_idle_driver = { |
| + .name = "omap3430_idle", |
| + .owner = THIS_MODULE, |
| + .states = { |
| + { |
| + .enter = omap3_enter_idle_bm, |
| + .exit_latency = 110 + 162, |
| + .target_residency = 5, |
| + .name = "C1", |
| + .desc = "MPU ON + CORE ON", |
| + }, |
| + { |
| + .enter = omap3_enter_idle_bm, |
| + .exit_latency = 106 + 180, |
| + .target_residency = 309, |
| + .name = "C2", |
| + .desc = "MPU ON + CORE ON", |
| + }, |
| + { |
| + .enter = omap3_enter_idle_bm, |
| + .exit_latency = 107 + 410, |
| + .target_residency = 46057, |
| + .name = "C3", |
| + .desc = "MPU RET + CORE ON", |
| + }, |
| + { |
| + .enter = omap3_enter_idle_bm, |
| + .exit_latency = 121 + 3374, |
| + .target_residency = 46057, |
| + .name = "C4", |
| + .desc = "MPU OFF + CORE ON", |
| + }, |
| + { |
| + .enter = omap3_enter_idle_bm, |
| + .exit_latency = 855 + 1146, |
| + .target_residency = 46057, |
| + .name = "C5", |
| + .desc = "MPU RET + CORE RET", |
| + }, |
| + { |
| + .enter = omap3_enter_idle_bm, |
| + .exit_latency = 7580 + 4134, |
| + .target_residency = 484329, |
| + .name = "C6", |
| + .desc = "MPU OFF + CORE RET", |
| + }, |
| + { |
| + .enter = omap3_enter_idle_bm, |
| + .exit_latency = 7505 + 15274, |
| + .target_residency = 484329, |
| + .name = "C7", |
| + .desc = "MPU OFF + CORE OFF", |
| + }, |
| + }, |
| + .state_count = ARRAY_SIZE(omap3_idle_data), |
| + .safe_state_index = 0, |
| +}; |
| + |
| /* Public functions */ |
| |
| /** |
| @@ -340,5 +404,8 @@ int __init omap3_idle_init(void) |
| if (!mpu_pd || !core_pd || !per_pd || !cam_pd) |
| return -ENODEV; |
| |
| - return cpuidle_register(&omap3_idle_driver, NULL); |
| + if (cpu_is_omap3430()) |
| + return cpuidle_register(&omap3430_idle_driver, NULL); |
| + else |
| + return cpuidle_register(&omap3_idle_driver, NULL); |
| } |