| From ab4d536890853ab6675ede65db40e2c0980cb0ea Mon Sep 17 00:00:00 2001 |
| From: Will Deacon <will.deacon@arm.com> |
| Date: Fri, 20 Apr 2012 17:22:11 +0100 |
| Subject: ARM: 7398/1: l2x0: only write to debug registers on PL310 |
| |
| From: Will Deacon <will.deacon@arm.com> |
| |
| commit ab4d536890853ab6675ede65db40e2c0980cb0ea upstream. |
| |
| PL310 errata #588369 and #727915 require writes to the debug registers |
| of the cache controller to work around known problems. Writing these |
| registers on L220 may cause deadlock, so ensure that we only perform |
| this operation when we identify a PL310 at probe time. |
| |
| Signed-off-by: Will Deacon <will.deacon@arm.com> |
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/mm/cache-l2x0.c | 13 ++++++++----- |
| 1 file changed, 8 insertions(+), 5 deletions(-) |
| |
| --- a/arch/arm/mm/cache-l2x0.c |
| +++ b/arch/arm/mm/cache-l2x0.c |
| @@ -81,10 +81,13 @@ static inline void l2x0_inv_line(unsigne |
| } |
| |
| #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915) |
| +static inline void debug_writel(unsigned long val) |
| +{ |
| + if (outer_cache.set_debug) |
| + outer_cache.set_debug(val); |
| +} |
| |
| -#define debug_writel(val) outer_cache.set_debug(val) |
| - |
| -static void l2x0_set_debug(unsigned long val) |
| +static void pl310_set_debug(unsigned long val) |
| { |
| writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL); |
| } |
| @@ -94,7 +97,7 @@ static inline void debug_writel(unsigned |
| { |
| } |
| |
| -#define l2x0_set_debug NULL |
| +#define pl310_set_debug NULL |
| #endif |
| |
| #ifdef CONFIG_PL310_ERRATA_588369 |
| @@ -331,6 +334,7 @@ void __init l2x0_init(void __iomem *base |
| /* Unmapped register. */ |
| sync_reg_offset = L2X0_DUMMY_REG; |
| #endif |
| + outer_cache.set_debug = pl310_set_debug; |
| break; |
| case L2X0_CACHE_ID_PART_L210: |
| ways = (aux >> 13) & 0xf; |
| @@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base |
| outer_cache.flush_all = l2x0_flush_all; |
| outer_cache.inv_all = l2x0_inv_all; |
| outer_cache.disable = l2x0_disable; |
| - outer_cache.set_debug = l2x0_set_debug; |
| |
| printk(KERN_INFO "%s cache controller enabled\n", type); |
| printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", |