| From a5964396190d0c40dd549c23848c282fffa5d1f2 Mon Sep 17 00:00:00 2001 |
| From: Rajmohan Mani <rajmohan.mani@intel.com> |
| Date: Wed, 18 Nov 2015 10:48:20 +0200 |
| Subject: xhci: Workaround to get Intel xHCI reset working more reliably |
| |
| From: Rajmohan Mani <rajmohan.mani@intel.com> |
| |
| commit a5964396190d0c40dd549c23848c282fffa5d1f2 upstream. |
| |
| Existing Intel xHCI controllers require a delay of 1 mS, |
| after setting the CMD_RESET bit in command register, before |
| accessing any HC registers. This allows the HC to complete |
| the reset operation and be ready for HC register access. |
| Without this delay, the subsequent HC register access, |
| may result in a system hang, very rarely. |
| |
| Verified CherryView / Braswell platforms go through over |
| 5000 warm reboot cycles (which was not possible without |
| this patch), without any xHCI reset hang. |
| |
| Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> |
| Tested-by: Joe Lawrence <joe.lawrence@stratus.com> |
| Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/usb/host/xhci.c | 10 ++++++++++ |
| 1 file changed, 10 insertions(+) |
| |
| --- a/drivers/usb/host/xhci.c |
| +++ b/drivers/usb/host/xhci.c |
| @@ -175,6 +175,16 @@ int xhci_reset(struct xhci_hcd *xhci) |
| command |= CMD_RESET; |
| writel(command, &xhci->op_regs->command); |
| |
| + /* Existing Intel xHCI controllers require a delay of 1 mS, |
| + * after setting the CMD_RESET bit, and before accessing any |
| + * HC registers. This allows the HC to complete the |
| + * reset operation and be ready for HC register access. |
| + * Without this delay, the subsequent HC register access, |
| + * may result in a system hang very rarely. |
| + */ |
| + if (xhci->quirks & XHCI_INTEL_HOST) |
| + udelay(1000); |
| + |
| ret = xhci_handshake(&xhci->op_regs->command, |
| CMD_RESET, 0, 10 * 1000 * 1000); |
| if (ret) |