| From 998dd7c719f62dcfa91d7bf7f4eb9c160e03d817 Mon Sep 17 00:00:00 2001 |
| From: Yu Zhao <yu.zhao@intel.com> |
| Date: Wed, 25 Feb 2009 13:15:52 +0800 |
| Subject: PCI: fix incorrect mask of PM No_Soft_Reset bit |
| |
| From: Yu Zhao <yu.zhao@intel.com> |
| |
| commit 998dd7c719f62dcfa91d7bf7f4eb9c160e03d817 upstream. |
| |
| Reviewed-by: Matthew Wilcox <matthew@wil.cx> |
| Signed-off-by: Yu Zhao <yu.zhao@intel.com> |
| Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> |
| |
| --- |
| include/linux/pci_regs.h | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/include/linux/pci_regs.h |
| +++ b/include/linux/pci_regs.h |
| @@ -234,7 +234,7 @@ |
| #define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */ |
| #define PCI_PM_CTRL 4 /* PM control and status register */ |
| #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */ |
| -#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */ |
| +#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */ |
| #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */ |
| #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */ |
| #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */ |
