x86/cpuid: Add CPUID(0x80000005) leaf

Signed-off-by: Borislav Petkov <bp@suse.de>

arch/x86/include/asm/cpuid.h

diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h
index 46aefb7..6dc0741 100644
--- a/arch/x86/include/asm/cpuid.h
+++ b/arch/x86/include/asm/cpuid.h
@@ -255,6 +255,18 @@ struct cpuid_range_ext {
 		nx	  : 1, __rsvd9	: 1, mmxext	: 1, mmx	: 1,
 		fxsr	  : 1, ffxsr	: 1, page1gb	: 1, rdtscp	: 1,
 		__rsvd10  : 1, lm	: 1, _3dnowext	: 1, _3dnow	: 1;
+
+	/* Function 0x8000_0005 */
+	union {
+		struct {
+			u32 l1itlb24msz : 8, l1itlb24mas: 8, l1dtlb24msz: 8, l1dtlb24mas: 8;
+		};
+		u32 all;
+	} lf5_eax;
+
+	u32	l1itlb4ksz : 8, l1itlb4kas : 8, l1dtlb4ksz : 8, l1dtlb4kas : 8;
+	u32	l1dclsz    : 8, l1dclntag  : 8, l1dcassoc  : 8, l1dcsz     : 8;
+	u32	l1iclsz    : 8, l1iclntag  : 8, l1icassoc  : 8, l1icsz     : 8;
 } __packed;
 
 

arch/x86/kernel/cpu/amd.c

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 725b8c9..3f770e3 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -526,12 +526,12 @@ static void bsp_init_amd(struct cpuinfo_x86 *c)
 	}
 
 	if (c->x86 == 0x15) {
-		unsigned long upperbit;
-		u32 cpuid, assoc;
-
-		cpuid	 = cpuid_edx(0x80000005);
-		assoc	 = cpuid >> 16 & 0xff;
-		upperbit = ((cpuid >> 24) << 10) / assoc;
+		/*
+		 * Compute the upper bit used for the selection of the cache
+		 * index.
+		 */
+		unsigned long upperbit = (cpuid_info.ext.l1icsz << 10) /
+					  cpuid_info.ext.l1icassoc;
 
 		va_align.mask	  = (upperbit - 1) & PAGE_MASK;
 		va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;
@@ -944,7 +944,7 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
 
 	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
 	if (!((eax >> 16) & mask))
-		tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
+		tlb_lld_2m[ENTRIES] = cpuid_info.ext.lf5_eax.l1dtlb24msz;
 	else
 		tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
 
@@ -957,8 +957,7 @@ static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
 			tlb_lli_2m[ENTRIES] = 1024;
 		} else {
-			cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
-			tlb_lli_2m[ENTRIES] = eax & 0xff;
+			tlb_lli_2m[ENTRIES] = cpuid_info.ext.lf5_eax.l1itlb24msz;
 		}
 	} else
 		tlb_lli_2m[ENTRIES] = eax & mask;

arch/x86/kernel/cpu/centaur.c

diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index b696f1a..7e953a8 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -184,10 +184,8 @@ static void init_centaur(struct cpuinfo_x86 *c)
 			set_cpu_cap(c, X86_FEATURE_3DNOW);
 		/* See if we can find out some more. */
 		if (cpuid_info.ext.max_lvl >= 0x80000005) {
-			/* Yes, we can. */
-			cpuid(0x80000005, &aa, &bb, &cc, &dd);
-			/* Add L1 data and code cache sizes. */
-			c->x86_cache_size = (cc>>24)+(dd>>24);
+			/* Yes, we can, add L1 data and code cache sizes. */
+			c->x86_cache_size = cpuid_info.ext.l1dcsz + cpuid_info.ext.l1icsz;
 		}
 		sprintf(x86_model_id, "WinChip %s", name);
 		break;

arch/x86/kernel/cpu/cpuid.c

diff --git a/arch/x86/kernel/cpu/cpuid.c b/arch/x86/kernel/cpu/cpuid.c
index 2643286..e0f74cb 100644
--- a/arch/x86/kernel/cpu/cpuid.c
+++ b/arch/x86/kernel/cpu/cpuid.c
@@ -34,6 +34,7 @@ void cpuid_read_leaf(unsigned int l)
 
 	case 0x80000000:	p = (u32 *)&cpuid_info.ext.max_lvl;		break;
 	case 0x80000001:	p = (u32 *)&cpuid_info.ext.lf1_eax;		break;
+	case 0x80000005:	p = (u32 *)&cpuid_info.ext.lf5_eax;		break;
 
         default:
                 WARN_ON(1);
@@ -56,4 +57,5 @@ void cpuid_read_all_leafs(void)
 
 	cpuid_read_leaf(0x80000000);
 	cpuid_read_leaf(0x80000001);
+	cpuid_read_leaf(0x80000005);
 }