| From: Thomas Gleixner <tglx@linutronix.de> |
| Date: Thu, 10 May 2018 16:26:00 +0200 |
| Subject: x86/cpufeatures: Add FEATURE_ZEN |
| |
| commit d1035d971829dcf80e8686ccde26f94b0a069472 upstream. |
| |
| Add a ZEN feature bit so family-dependent static_cpu_has() optimizations |
| can be built for ZEN. |
| |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Reviewed-by: Borislav Petkov <bp@suse.de> |
| Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> |
| Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| [bwh: Backported to 3.16: |
| - Use the next available bit number in CPU feature word 7 |
| - Adjust filename, context] |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| arch/x86/include/asm/cpufeature.h | 1 + |
| arch/x86/kernel/cpu/amd.c | 1 + |
| 2 files changed, 2 insertions(+) |
| |
| --- a/arch/x86/include/asm/cpufeature.h |
| +++ b/arch/x86/include/asm/cpufeature.h |
| @@ -198,6 +198,7 @@ |
| #define X86_FEATURE_STIBP (7*32+18) /* Single Thread Indirect Branch Predictors */ |
| #define X86_FEATURE_MSR_SPEC_CTRL (7*32+19) /* "" MSR SPEC_CTRL is implemented */ |
| #define X86_FEATURE_SSBD (7*32+20) /* Speculative Store Bypass Disable */ |
| +#define X86_FEATURE_ZEN (7*32+21) /* "" CPU is AMD family 0x17 (Zen) */ |
| |
| #define X86_FEATURE_RETPOLINE (7*32+29) /* "" Generic Retpoline mitigation for Spectre variant 2 */ |
| #define X86_FEATURE_RETPOLINE_AMD (7*32+30) /* "" AMD Retpoline mitigation for Spectre variant 2 */ |
| --- a/arch/x86/kernel/cpu/amd.c |
| +++ b/arch/x86/kernel/cpu/amd.c |
| @@ -556,6 +556,7 @@ static void init_amd_ln(struct cpuinfo_x |
| |
| static void init_amd_zn(struct cpuinfo_x86 *c) |
| { |
| + set_cpu_cap(c, X86_FEATURE_ZEN); |
| /* |
| * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects |
| * all up to and including B1. |