| From: Hans de Goede <hdegoede@redhat.com> |
| Date: Thu, 26 Apr 2018 14:10:24 +0200 |
| Subject: ACPI / LPSS: Add missing prv_offset setting for byt/cht PWM devices |
| |
| commit fdcb613d49321b5bf5d5a1bd0fba8e7c241dcc70 upstream. |
| |
| The LPSS PWM device on on Bay Trail and Cherry Trail devices has a set |
| of private registers at offset 0x800, the current lpss_device_desc for |
| them already sets the LPSS_SAVE_CTX flag to have these saved/restored |
| over device-suspend, but the current lpss_device_desc was not setting |
| the prv_offset field, leading to the regular device registers getting |
| saved/restored instead. |
| |
| This is causing the PWM controller to no longer work, resulting in a black |
| screen, after a suspend/resume on systems where the firmware clears the |
| APB clock and reset bits at offset 0x804. |
| |
| This commit fixes this by properly setting prv_offset to 0x800 for |
| the PWM devices. |
| |
| Fixes: e1c748179754 ("ACPI / LPSS: Add Intel BayTrail ACPI mode PWM") |
| Fixes: 1bfbd8eb8a7f ("ACPI / LPSS: Add ACPI IDs for Intel Braswell") |
| Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
| Acked-by: Rafael J . Wysocki <rjw@rjwysocki.net> |
| Signed-off-by: Thierry Reding <thierry.reding@gmail.com> |
| [bwh: Backported to 3.16: |
| - Drop changes for Braswell |
| - Adjust context] |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| --- a/drivers/acpi/acpi_lpss.c |
| +++ b/drivers/acpi/acpi_lpss.c |
| @@ -150,6 +150,7 @@ static struct lpss_shared_clock pwm_cloc |
| |
| static struct lpss_device_desc byt_pwm_dev_desc = { |
| .clk_required = true, |
| + .prv_offset = 0x800, |
| .save_ctx = true, |
| .shared_clock = &pwm_clock, |
| }; |
