| From: Evan Green <evgreen@chromium.org> |
| Date: Fri, 13 Apr 2018 13:33:36 -0700 |
| Subject: clk: qcom: Base rcg parent rate off plan frequency |
| |
| commit c7d2a0eb6c028ba064bfe92d7667977418142c7c upstream. |
| |
| _freq_tbl_determine_rate uses the pre_div found in the clock plan |
| multiplied by the requested rate from the caller to determine the |
| best parent rate to set. If the requested rate is not exactly equal |
| to the rate that was found in the clock plan, then using the requested |
| rate in parent rate calculations is incorrect. For instance, if 150MHz |
| was requested, but 200MHz was the match found, and that plan had a |
| pre_div of 3, then the parent should be set to 600MHz, not 450MHz. |
| |
| Signed-off-by: Evan Green <evgreen@chromium.org> |
| Fixes: bcd61c0f535a ("clk: qcom: Add support for root clock generators (RCGs)") |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| drivers/clk/qcom/clk-rcg2.c | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| --- a/drivers/clk/qcom/clk-rcg2.c |
| +++ b/drivers/clk/qcom/clk-rcg2.c |
| @@ -199,6 +199,7 @@ static long _freq_tbl_determine_rate(str |
| clk_flags = __clk_get_flags(hw->clk); |
| *p = clk_get_parent_by_index(hw->clk, f->src); |
| if (clk_flags & CLK_SET_RATE_PARENT) { |
| + rate = f->freq; |
| if (f->pre_div) { |
| rate /= 2; |
| rate *= f->pre_div + 1; |