| From: =?UTF-8?q?Pawe=C5=82=20Chmiel?= <pawel.mikolaj.chmiel@gmail.com> |
| Date: Mon, 16 Apr 2018 17:52:45 +0200 |
| Subject: pinctrl: samsung: Correct EINTG banks order |
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| |
| commit 5cf9a338db94cfd570aa2607bef1b30996f188e3 upstream. |
| |
| All banks with GPIO interrupts should be at beginning of bank array and |
| without any other types of banks between them. This order is expected |
| by exynos_eint_gpio_irq, when doing interrupt group to bank translation. |
| Otherwise, kernel NULL pointer dereference would happen when trying to |
| handle interrupt, due to wrong bank being looked up. Observed on |
| s5pv210, when trying to handle gpj0 interrupt, where kernel was mapping |
| it to gpi bank. |
| |
| Fixes: 023e06dfa688 ("pinctrl: exynos: add exynos5410 SoC specific data") |
| Fixes: 608a26a7bc04 ("pinctrl: Add s5pv210 support to pinctrl-exynos) |
| Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> |
| Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> |
| Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> |
| [bwh: Backported to 3.16: |
| - Drop change to exynos5410_pin_banks0 |
| - Adjust filename] |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| --- a/drivers/pinctrl/pinctrl-exynos.c |
| +++ b/drivers/pinctrl/pinctrl-exynos.c |
| @@ -679,12 +679,12 @@ static struct samsung_pin_bank s5pv210_p |
| EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38), |
| EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c), |
| EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40), |
| - EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), |
| EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44), |
| EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48), |
| EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c), |
| EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50), |
| EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54), |
| + EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"), |
| EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"), |
| EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"), |
| EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"), |
