| From: "Aneesh Kumar K.V" <aneesh.kumar@linux.ibm.com> |
| Date: Wed, 30 May 2018 18:48:04 +0530 |
| Subject: powerpc/mm/hash: Add missing isync prior to kernel stack SLB switch |
| |
| commit 91d06971881f71d945910de128658038513d1b24 upstream. |
| |
| Currently we do not have an isync, or any other context synchronizing |
| instruction prior to the slbie/slbmte in _switch() that updates the |
| SLB entry for the kernel stack. |
| |
| However that is not correct as outlined in the ISA. |
| |
| From Power ISA Version 3.0B, Book III, Chapter 11, page 1133: |
| |
| "Changing the contents of ... the contents of SLB entries ... can |
| have the side effect of altering the context in which data |
| addresses and instruction addresses are interpreted, and in which |
| instructions are executed and data accesses are performed. |
| ... |
| These side effects need not occur in program order, and therefore |
| may require explicit synchronization by software. |
| ... |
| The synchronizing instruction before the context-altering |
| instruction ensures that all instructions up to and including that |
| synchronizing instruction are fetched and executed in the context |
| that existed before the alteration." |
| |
| And page 1136: |
| |
| "For data accesses, the context synchronizing instruction before the |
| slbie, slbieg, slbia, slbmte, tlbie, or tlbiel instruction ensures |
| that all preceding instructions that access data storage have |
| completed to a point at which they have reported all exceptions |
| they will cause." |
| |
| We're not aware of any bugs caused by this, but it should be fixed |
| regardless. |
| |
| Add the missing isync when updating kernel stack SLB entry. |
| |
| Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> |
| [mpe: Flesh out change log with more ISA text & explanation] |
| Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| arch/powerpc/kernel/entry_64.S | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| --- a/arch/powerpc/kernel/entry_64.S |
| +++ b/arch/powerpc/kernel/entry_64.S |
| @@ -525,6 +525,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEG |
| * actually hit this code path. |
| */ |
| |
| + isync |
| slbie r6 |
| slbie r6 /* Workaround POWER5 < DD2.1 issue */ |
| slbmte r7,r0 |