| From: "H. Peter Anvin" <hpa@linux.intel.com> |
| Date: Tue, 21 Feb 2012 17:25:50 -0800 |
| Subject: x86, cpufeature: Add CPU features from Intel document 319433-012A |
| |
| commit 513c4ec6e4759aa33c90af0658b82eb4d2027871 upstream. |
| |
| Add CPU features from the Intel Archicture Instruction Set Extensions |
| Programming Reference version 012A (Feb 2012), document number 319433-012A. |
| |
| Signed-off-by: H. Peter Anvin <hpa@linux.intel.com> |
| Signed-off-by: Hugh Dickins <hughd@google.com> |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| arch/x86/include/asm/cpufeature.h | 3 +++ |
| 1 file changed, 3 insertions(+) |
| |
| diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h |
| index b8a5fe545f95..6f254f2fcd40 100644 |
| --- a/arch/x86/include/asm/cpufeature.h |
| +++ b/arch/x86/include/asm/cpufeature.h |
| @@ -198,8 +198,11 @@ |
| |
| /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */ |
| #define X86_FEATURE_FSGSBASE (9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/ |
| +#define X86_FEATURE_HLE (9*32+ 4) /* Hardware Lock Elision */ |
| #define X86_FEATURE_SMEP (9*32+ 7) /* Supervisor Mode Execution Protection */ |
| #define X86_FEATURE_ERMS (9*32+ 9) /* Enhanced REP MOVSB/STOSB */ |
| +#define X86_FEATURE_INVPCID (9*32+10) /* Invalidate Processor Context ID */ |
| +#define X86_FEATURE_RTM (9*32+11) /* Restricted Transactional Memory */ |
| |
| #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| |
| |
