| From: Paul Parsons <lost.distance@yahoo.com> |
| Date: Sat, 2 Apr 2016 12:32:30 +0100 |
| Subject: drm/radeon: Fix PCIe lane width calculation |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| commit 85e290d92b4b794d0c758c53007eb4248d385386 upstream. |
| |
| Two years ago I tried an AMD Radeon E8860 embedded GPU with the drm driver. |
| The dmesg output included driver warnings about an invalid PCIe lane width. |
| Tracking the problem back led to si_set_pcie_lane_width_in_smc(). |
| The calculation of the lane widths via ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and |
| ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting |
| value, per the comment in pptable.h ("lanes - 1"), and per usage elsewhere. |
| Applying the increment silenced the warnings. |
| The code has not changed since, so either my analysis was incorrect or the |
| bug has gone unnoticed. Hence submitting this as an RFC. |
| |
| Acked-by: Christian Kรถnig <christian.koenig@amd.com> |
| Acked-by: Chunming Zhou <david1.zhou@amd.com> |
| Signed-off-by: Paul Parsons <lost.distance@yahoo.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| drivers/gpu/drm/radeon/si_dpm.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/radeon/si_dpm.c |
| +++ b/drivers/gpu/drm/radeon/si_dpm.c |
| @@ -5828,9 +5828,9 @@ static void si_set_pcie_lane_width_in_sm |
| { |
| u32 lane_width; |
| u32 new_lane_width = |
| - (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; |
| + ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
| u32 current_lane_width = |
| - (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT; |
| + ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; |
| |
| if (new_lane_width != current_lane_width) { |
| radeon_set_pcie_lanes(rdev, new_lane_width); |
