| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2021 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx8ulp.dtsi" |
| |
| / { |
| model = "NXP i.MX8ULP EVK"; |
| compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp"; |
| |
| chosen { |
| stdout-path = &lpuart5; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x0 0x80000000 0 0x80000000>; |
| }; |
| }; |
| |
| &lpuart5 { |
| /* console */ |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_lpuart5>; |
| pinctrl-1 = <&pinctrl_lpuart5>; |
| status = "okay"; |
| }; |
| |
| &usdhc0 { |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_usdhc0>; |
| pinctrl-1 = <&pinctrl_usdhc0>; |
| non-removable; |
| bus-width = <8>; |
| status = "okay"; |
| }; |
| |
| &iomuxc1 { |
| pinctrl_lpuart5: lpuart5grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTF14__LPUART5_TX 0x3 |
| MX8ULP_PAD_PTF15__LPUART5_RX 0x3 |
| >; |
| }; |
| |
| pinctrl_usdhc0: usdhc0grp { |
| fsl,pins = < |
| MX8ULP_PAD_PTD1__SDHC0_CMD 0x43 |
| MX8ULP_PAD_PTD2__SDHC0_CLK 0x10042 |
| MX8ULP_PAD_PTD10__SDHC0_D0 0x43 |
| MX8ULP_PAD_PTD9__SDHC0_D1 0x43 |
| MX8ULP_PAD_PTD8__SDHC0_D2 0x43 |
| MX8ULP_PAD_PTD7__SDHC0_D3 0x43 |
| MX8ULP_PAD_PTD6__SDHC0_D4 0x43 |
| MX8ULP_PAD_PTD5__SDHC0_D5 0x43 |
| MX8ULP_PAD_PTD4__SDHC0_D6 0x43 |
| MX8ULP_PAD_PTD3__SDHC0_D7 0x43 |
| MX8ULP_PAD_PTD11__SDHC0_DQS 0x10042 |
| >; |
| }; |
| }; |
