Merge tag 'v5.14-rc1-dts-raw'
Linux 5.14-rc1
diff --git a/Bindings/arm/amlogic,scpi.txt b/Bindings/arm/amlogic,scpi.txt
deleted file mode 100644
index 5ab59da..0000000
--- a/Bindings/arm/amlogic,scpi.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-System Control and Power Interface (SCPI) Message Protocol
-(in addition to the standard binding in [0])
-----------------------------------------------------------
-Required properties
-
-- compatible : should be "amlogic,meson-gxbb-scpi"
-
-AMLOGIC SRAM and Shared Memory for SCPI
-------------------------------------
-
-Required properties:
-- compatible : should be "amlogic,meson-gxbb-sram"
-
-Each sub-node represents the reserved area for SCPI.
-
-Required sub-node properties:
-- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
- memory on Amlogic GXBB SoC.
-
-Sensor bindings for the sensors based on SCPI Message Protocol
---------------------------------------------------------------
-SCPI provides an API to access the various sensors on the SoC.
-
-Required properties:
-- compatible : should be "amlogic,meson-gxbb-scpi-sensors".
-
-[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
diff --git a/Bindings/arm/amlogic.yaml b/Bindings/arm/amlogic.yaml
index 97fb962..6423377 100644
--- a/Bindings/arm/amlogic.yaml
+++ b/Bindings/arm/amlogic.yaml
@@ -167,6 +167,7 @@
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items:
- enum:
+ - bananapi,bpi-m5
- hardkernel,odroid-c4
- hardkernel,odroid-hc4
- khadas,vim3l
diff --git a/Bindings/arm/arm,scmi.txt b/Bindings/arm/arm,scmi.txt
deleted file mode 100644
index 667d58e..0000000
--- a/Bindings/arm/arm,scmi.txt
+++ /dev/null
@@ -1,239 +0,0 @@
-System Control and Management Interface (SCMI) Message Protocol
-----------------------------------------------------------
-
-The SCMI is intended to allow agents such as OSPM to manage various functions
-that are provided by the hardware platform it is running on, including power
-and performance functions.
-
-This binding is intended to define the interface the firmware implementing
-the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
-and Management Interface Platform Design Document")[0] provide for OSPM in
-the device tree.
-
-Required properties:
-
-The scmi node with the following properties shall be under the /firmware/ node.
-
-- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
-- mboxes: List of phandle and mailbox channel specifiers. It should contain
- exactly one or two mailboxes, one for transmitting messages("tx")
- and another optional for receiving the notifications("rx") if
- supported.
-- shmem : List of phandle pointing to the shared memory(SHM) area as per
- generic mailbox client binding.
-- #address-cells : should be '1' if the device has sub-nodes, maps to
- protocol identifier for a given sub-node.
-- #size-cells : should be '0' as 'reg' property doesn't have any size
- associated with it.
-- arm,smc-id : SMC id required when using smc or hvc transports
-
-Optional properties:
-
-- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
-
-- interrupts : when using smc or hvc transports, this optional
- property indicates that msg completion by the platform is indicated
- by an interrupt rather than by the return of the smc call. This
- should not be used except when the platform requires such behavior.
-
-- interrupt-names : if "interrupts" is present, interrupt-names must also
- be present and have the value "a2p".
-
-See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
-about the generic mailbox controller and client driver bindings.
-
-The mailbox is the only permitted method of calling the SCMI firmware.
-Mailbox doorbell is used as a mechanism to alert the presence of a
-messages and/or notification.
-
-Each protocol supported shall have a sub-node with corresponding compatible
-as described in the following sections. If the platform supports dedicated
-communication channel for a particular protocol, the 3 properties namely:
-mboxes, mbox-names and shmem shall be present in the sub-node corresponding
-to that protocol.
-
-Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding uses the common clock binding[1].
-
-Required properties:
-- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
-
-Power domain bindings for the power domains based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding for the SCMI power domain providers uses the generic power
-domain binding[2].
-
-Required properties:
- - #power-domain-cells : Should be 1. Contains the device or the power
- domain ID value used by SCMI commands.
-
-Regulator bindings for the SCMI Regulator based on SCMI Message Protocol
-------------------------------------------------------------
-An SCMI Regulator is permanently bound to a well defined SCMI Voltage Domain,
-and should be always positioned as a root regulator.
-It does not support any current operation.
-
-SCMI Regulators are grouped under a 'regulators' node which in turn is a child
-of the SCMI Voltage protocol node inside the desired SCMI instance node.
-
-This binding uses the common regulator binding[6].
-
-Required properties:
- - reg : shall identify an existent SCMI Voltage Domain.
-
-Sensor bindings for the sensors based on SCMI Message Protocol
---------------------------------------------------------------
-SCMI provides an API to access the various sensors on the SoC.
-
-Required properties:
-- #thermal-sensor-cells: should be set to 1. This property follows the
- thermal device tree bindings[3].
-
- Valid cell values are raw identifiers (Sensor ID)
- as used by the firmware. Refer to platform details
- for your implementation for the IDs to use.
-
-Reset signal bindings for the reset domains based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding for the SCMI reset domain providers uses the generic reset
-signal binding[5].
-
-Required properties:
- - #reset-cells : Should be 1. Contains the reset domain ID value used
- by SCMI commands.
-
-SRAM and Shared Memory for SCMI
--------------------------------
-
-A small area of SRAM is reserved for SCMI communication between application
-processors and SCP.
-
-The properties should follow the generic mmio-sram description found in [4]
-
-Each sub-node represents the reserved area for SCMI.
-
-Required sub-node properties:
-- reg : The base offset and size of the reserved area with the SRAM
-- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
- shared memory
-
-[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/power/power-domain.yaml
-[3] Documentation/devicetree/bindings/thermal/thermal*.yaml
-[4] Documentation/devicetree/bindings/sram/sram.yaml
-[5] Documentation/devicetree/bindings/reset/reset.txt
-[6] Documentation/devicetree/bindings/regulator/regulator.yaml
-
-Example:
-
-sram@50000000 {
- compatible = "mmio-sram";
- reg = <0x0 0x50000000 0x0 0x10000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x50000000 0x10000>;
-
- cpu_scp_lpri: scp-shmem@0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x200>;
- };
-
- cpu_scp_hpri: scp-shmem@200 {
- compatible = "arm,scmi-shmem";
- reg = <0x200 0x200>;
- };
-};
-
-mailbox@40000000 {
- ....
- #mbox-cells = <1>;
- reg = <0x0 0x40000000 0x0 0x10000>;
-};
-
-firmware {
-
- ...
-
- scmi {
- compatible = "arm,scmi";
- mboxes = <&mailbox 0 &mailbox 1>;
- mbox-names = "tx", "rx";
- shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_devpd: protocol@11 {
- reg = <0x11>;
- #power-domain-cells = <1>;
- };
-
- scmi_dvfs: protocol@13 {
- reg = <0x13>;
- #clock-cells = <1>;
- };
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_sensors0: protocol@15 {
- reg = <0x15>;
- #thermal-sensor-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
-
- scmi_voltage: protocol@17 {
- reg = <0x17>;
-
- regulators {
- regulator_devX: regulator@0 {
- reg = <0x0>;
- regulator-max-microvolt = <3300000>;
- };
-
- regulator_devY: regulator@9 {
- reg = <0x9>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <4200000>;
- };
-
- ...
- };
- };
- };
-};
-
-cpu@0 {
- ...
- reg = <0 0>;
- clocks = <&scmi_dvfs 0>;
-};
-
-hdlcd@7ff60000 {
- ...
- reg = <0 0x7ff60000 0 0x1000>;
- clocks = <&scmi_clk 4>;
- power-domains = <&scmi_devpd 1>;
- resets = <&scmi_reset 10>;
-};
-
-thermal-zones {
- soc_thermal {
- polling-delay-passive = <100>;
- polling-delay = <1000>;
- /* sensor ID */
- thermal-sensors = <&scmi_sensors0 3>;
- ...
- };
-};
diff --git a/Bindings/arm/arm,scpi.txt b/Bindings/arm/arm,scpi.txt
deleted file mode 100644
index bcd6c3e..0000000
--- a/Bindings/arm/arm,scpi.txt
+++ /dev/null
@@ -1,219 +0,0 @@
-System Control and Power Interface (SCPI) Message Protocol
-----------------------------------------------------------
-
-Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
-("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
-by Linux to initiate various system control and power operations.
-
-Required properties:
-
-- compatible : should be
- * "arm,scpi" : For implementations complying to SCPI v1.0 or above
- * "arm,scpi-pre-1.0" : For implementations complying to all
- unversioned releases prior to SCPI v1.0
-- mboxes: List of phandle and mailbox channel specifiers
- All the channels reserved by remote SCP firmware for use by
- SCPI message protocol should be specified in any order
-- shmem : List of phandle pointing to the shared memory(SHM) area between the
- processors using these mailboxes for IPC, one for each mailbox
- SHM can be any memory reserved for the purpose of this communication
- between the processors.
-
-See Documentation/devicetree/bindings/mailbox/mailbox.txt
-for more details about the generic mailbox controller and
-client driver bindings.
-
-Clock bindings for the clocks based on SCPI Message Protocol
-------------------------------------------------------------
-
-This binding uses the common clock binding[1].
-
-Container Node
-==============
-Required properties:
-- compatible : should be "arm,scpi-clocks"
- All the clocks provided by SCP firmware via SCPI message
- protocol much be listed as sub-nodes under this node.
-
-Sub-nodes
-=========
-Required properties:
-- compatible : shall include one of the following
- "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
- These clocks don't provide an entire range of values between the
- limits but only discrete points within the range. The firmware
- provides the mapping for each such operating frequency and the
- index associated with it. The firmware also manages the
- voltage scaling appropriately with the clock scaling.
- "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
- range within the specified range. The firmware provides the
- range of values within a specified range.
-
-Other required properties for all clocks(all from common clock binding):
-- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands.
-- clock-output-names : shall be the corresponding names of the outputs.
-- clock-indices: The identifying number for the clocks(i.e.clock_id) in the
- node. It can be non linear and hence provide the mapping of identifiers
- into the clock-output-names array.
-
-SRAM and Shared Memory for SCPI
--------------------------------
-
-A small area of SRAM is reserved for SCPI communication between application
-processors and SCP.
-
-The properties should follow the generic mmio-sram description found in [3]
-
-Each sub-node represents the reserved area for SCPI.
-
-Required sub-node properties:
-- reg : The base offset and size of the reserved area with the SRAM
-- compatible : should be "arm,scp-shmem" for Non-secure SRAM based
- shared memory
-
-Sensor bindings for the sensors based on SCPI Message Protocol
---------------------------------------------------------------
-SCPI provides an API to access the various sensors on the SoC.
-
-Required properties:
-- compatible : should be "arm,scpi-sensors".
-- #thermal-sensor-cells: should be set to 1. This property follows the
- thermal device tree bindings[2].
-
- Valid cell values are raw identifiers (Sensor ID)
- as used by the firmware. Refer to platform details
- for your implementation for the IDs to use.
-
-Power domain bindings for the power domains based on SCPI Message Protocol
-------------------------------------------------------------
-
-This binding uses the generic power domain binding[4].
-
-PM domain providers
-===================
-
-Required properties:
- - #power-domain-cells : Should be 1. Contains the device or the power
- domain ID value used by SCPI commands.
- - num-domains: Total number of power domains provided by SCPI. This is
- needed as the SCPI message protocol lacks a mechanism to
- query this information at runtime.
-
-PM domain consumers
-===================
-
-Required properties:
- - power-domains : A phandle and PM domain specifier as defined by bindings of
- the power controller specified by phandle.
-
-[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/thermal/thermal*.yaml
-[3] Documentation/devicetree/bindings/sram/sram.yaml
-[4] Documentation/devicetree/bindings/power/power-domain.yaml
-
-Example:
-
-sram: sram@50000000 {
- compatible = "arm,juno-sram-ns", "mmio-sram";
- reg = <0x0 0x50000000 0x0 0x10000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x50000000 0x10000>;
-
- cpu_scp_lpri: scp-shmem@0 {
- compatible = "arm,juno-scp-shmem";
- reg = <0x0 0x200>;
- };
-
- cpu_scp_hpri: scp-shmem@200 {
- compatible = "arm,juno-scp-shmem";
- reg = <0x200 0x200>;
- };
-};
-
-mailbox: mailbox0@40000000 {
- ....
- #mbox-cells = <1>;
-};
-
-scpi_protocol: scpi@2e000000 {
- compatible = "arm,scpi";
- mboxes = <&mailbox 0 &mailbox 1>;
- shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
-
- clocks {
- compatible = "arm,scpi-clocks";
-
- scpi_dvfs: scpi_clocks@0 {
- compatible = "arm,scpi-dvfs-clocks";
- #clock-cells = <1>;
- clock-indices = <0>, <1>, <2>;
- clock-output-names = "atlclk", "aplclk","gpuclk";
- };
- scpi_clk: scpi_clocks@3 {
- compatible = "arm,scpi-variable-clocks";
- #clock-cells = <1>;
- clock-indices = <3>, <4>;
- clock-output-names = "pxlclk0", "pxlclk1";
- };
- };
-
- scpi_sensors0: sensors {
- compatible = "arm,scpi-sensors";
- #thermal-sensor-cells = <1>;
- };
-
- scpi_devpd: scpi-power-domains {
- compatible = "arm,scpi-power-domains";
- num-domains = <2>;
- #power-domain-cells = <1>;
- };
-};
-
-cpu@0 {
- ...
- reg = <0 0>;
- clocks = <&scpi_dvfs 0>;
-};
-
-hdlcd@7ff60000 {
- ...
- reg = <0 0x7ff60000 0 0x1000>;
- clocks = <&scpi_clk 4>;
- power-domains = <&scpi_devpd 1>;
-};
-
-thermal-zones {
- soc_thermal {
- polling-delay-passive = <100>;
- polling-delay = <1000>;
-
- /* sensor ID */
- thermal-sensors = <&scpi_sensors0 3>;
- ...
- };
-};
-
-In the above example, the #clock-cells is set to 1 as required.
-scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0,
-1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0
-and pxlclk1 with 3 and 4 as clock-indices.
-
-The first consumer in the example is cpu@0 and it has '0' as the clock
-specifier which points to the first entry in the output clocks of
-scpi_dvfs i.e. "atlclk".
-
-Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input
-clock. '4' in the clock specifier here points to the second entry
-in the output clocks of scpi_clocks i.e. "pxlclk1"
-
-The thermal-sensors property in the soc_thermal node uses the
-temperature sensor provided by SCP firmware to setup a thermal
-zone. The ID "3" is the sensor identifier for the temperature sensor
-as used by the firmware.
-
-The num-domains property in scpi-power-domains domain specifies that
-SCPI provides 2 power domains. The hdlcd node uses the power domain with
-domain ID 1.
diff --git a/Bindings/arm/arm,scu.yaml b/Bindings/arm/arm,scu.yaml
new file mode 100644
index 0000000..dae2aa2
--- /dev/null
+++ b/Bindings/arm/arm,scu.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Snoop Control Unit (SCU)
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
+ with a Snoop Control Unit. The register range is usually 256 (0x100)
+ bytes.
+
+ References:
+ - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
+ Revision r2p0
+ - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
+ Revision r0p1
+ - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
+ Manial Revision r2p0
+
+properties:
+ compatible:
+ enum:
+ - arm,cortex-a9-scu
+ - arm,cortex-a5-scu
+ - arm,arm11mp-scu
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ scu@a0410000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xa0410000 0x100>;
+ };
diff --git a/Bindings/arm/bcm/bcm2835.yaml b/Bindings/arm/bcm/bcm2835.yaml
index 812ae8c..230b80d 100644
--- a/Bindings/arm/bcm/bcm2835.yaml
+++ b/Bindings/arm/bcm/bcm2835.yaml
@@ -18,6 +18,7 @@
- description: BCM2711 based Boards
items:
- enum:
+ - raspberrypi,400
- raspberrypi,4-model-b
- const: brcm,bcm2711
diff --git a/Bindings/arm/cpus.yaml b/Bindings/arm/cpus.yaml
index f3c7249..9a2432a 100644
--- a/Bindings/arm/cpus.yaml
+++ b/Bindings/arm/cpus.yaml
@@ -257,6 +257,13 @@
where voltage is in V, frequency is in MHz.
+ performance-domains:
+ maxItems: 1
+ description:
+ List of phandles and performance domain specifiers, as defined by
+ bindings of the performance domain provider. See also
+ dvfs/performance-domain.yaml.
+
power-domains:
description:
List of phandles and PM domain specifiers, as defined by bindings of the
diff --git a/Bindings/arm/firmware/linaro,optee-tz.txt b/Bindings/arm/firmware/linaro,optee-tz.txt
deleted file mode 100644
index d38834c..0000000
--- a/Bindings/arm/firmware/linaro,optee-tz.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-OP-TEE Device Tree Bindings
-
-OP-TEE is a piece of software using hardware features to provide a Trusted
-Execution Environment. The security can be provided with ARM TrustZone, but
-also by virtualization or a separate chip.
-
-We're using "linaro" as the first part of the compatible property for
-the reference implementation maintained by Linaro.
-
-* OP-TEE based on ARM TrustZone required properties:
-
-- compatible : should contain "linaro,optee-tz"
-
-- method : The method of calling the OP-TEE Trusted OS. Permitted
- values are:
-
- "smc" : SMC #0, with the register assignments specified
- in drivers/tee/optee/optee_smc.h
-
- "hvc" : HVC #0, with the register assignments specified
- in drivers/tee/optee/optee_smc.h
-
-
-
-Example:
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
diff --git a/Bindings/arm/firmware/linaro,optee-tz.yaml b/Bindings/arm/firmware/linaro,optee-tz.yaml
new file mode 100644
index 0000000..c24047c
--- /dev/null
+++ b/Bindings/arm/firmware/linaro,optee-tz.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OP-TEE Device Tree Bindings
+
+maintainers:
+ - Jens Wiklander <jens.wiklander@linaro.org>
+
+description: |
+ OP-TEE is a piece of software using hardware features to provide a Trusted
+ Execution Environment. The security can be provided with ARM TrustZone, but
+ also by virtualization or a separate chip.
+
+ We're using "linaro" as the first part of the compatible property for
+ the reference implementation maintained by Linaro.
+
+properties:
+ $nodename:
+ const: optee
+
+ compatible:
+ const: linaro,optee-tz
+
+ method:
+ enum: [smc, hvc]
+ description: |
+ The method of calling the OP-TEE Trusted OS depending on smc or hvc
+ instruction usage.
+ SMC #0, register assignments
+ or
+ HVC #0, register assignments
+ register assignments are specified in drivers/tee/optee/optee_smc.h
+
+required:
+ - compatible
+ - method
+
+additionalProperties: false
+
+examples:
+ - |
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ - |
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "hvc";
+ };
+ };
diff --git a/Bindings/arm/freescale/fsl,scu.txt b/Bindings/arm/freescale/fsl,scu.txt
index 395359d..fd00617 100644
--- a/Bindings/arm/freescale/fsl,scu.txt
+++ b/Bindings/arm/freescale/fsl,scu.txt
@@ -86,13 +86,11 @@
Required properties:
- compatible: Should be one of:
- "fsl,imx8qm-clock"
- "fsl,imx8qxp-clock"
+ "fsl,imx8qm-clk"
+ "fsl,imx8qxp-clk"
followed by "fsl,scu-clk"
-- #clock-cells: Should be either
- 2: Contains the Resource and Clock ID value.
- or
- 1: Contains the Clock ID value. (DEPRECATED)
+- #clock-cells: Should be 2.
+ Contains the Resource and Clock ID value.
- clocks: List of clock specifiers, must contain an entry for
each required entry in clock-names
- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz"
diff --git a/Bindings/arm/fsl.yaml b/Bindings/arm/fsl.yaml
index e3c50f2..1c827c1 100644
--- a/Bindings/arm/fsl.yaml
+++ b/Bindings/arm/fsl.yaml
@@ -197,6 +197,7 @@
- boundary,imx6q-nitrogen6x
- compulab,cm-fx6 # CompuLab CM-FX6
- dmo,imx6q-edmqmx6 # Data Modul eDM-QMX6 Board
+ - ds,imx6q-sbc # Da Sheng COM-9XX Modules
- embest,imx6q-marsboard # Embest MarS Board i.MX6Dual
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
@@ -400,6 +401,17 @@
- const: armadeus,imx6dl-apf6 # APF6 (Solo) SoM
- const: fsl,imx6dl
+ - description: i.MX6DL based congatec QMX6 Boards
+ items:
+ - enum:
+ - ge,imx6dl-b105v2 # General Electric B105v2
+ - ge,imx6dl-b105pv2 # General Electric B105Pv2
+ - ge,imx6dl-b125v2 # General Electric B125v2
+ - ge,imx6dl-b125pv2 # General Electric B125Pv2
+ - ge,imx6dl-b155v2 # General Electric B155v2
+ - const: congatec,qmx6
+ - const: fsl,imx6dl
+
- description: i.MX6DL based DFI FS700-M60-6DL Board
items:
- const: dfi,fs700-m60-6dl
@@ -685,6 +697,7 @@
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw72xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
+ - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- const: fsl,imx8mm
diff --git a/Bindings/arm/intel,keembay.yaml b/Bindings/arm/intel,keembay.yaml
index 69cd308..107e686 100644
--- a/Bindings/arm/intel,keembay.yaml
+++ b/Bindings/arm/intel,keembay.yaml
@@ -11,6 +11,8 @@
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
properties:
+ $nodename:
+ const: '/'
compatible:
items:
- enum:
diff --git a/Bindings/arm/intel-ixp4xx.yaml b/Bindings/arm/intel-ixp4xx.yaml
index d72e92b..230bffe 100644
--- a/Bindings/arm/intel-ixp4xx.yaml
+++ b/Bindings/arm/intel-ixp4xx.yaml
@@ -17,6 +17,7 @@
- items:
- enum:
- linksys,nslu2
+ - welltech,epbx100
- const: intel,ixp42x
- items:
- enum:
diff --git a/Bindings/arm/juno,scpi.txt b/Bindings/arm/juno,scpi.txt
deleted file mode 100644
index 2ace869..0000000
--- a/Bindings/arm/juno,scpi.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-System Control and Power Interface (SCPI) Message Protocol
-(in addition to the standard binding in [0])
-
-Juno SRAM and Shared Memory for SCPI
-------------------------------------
-
-Required properties:
-- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
-
-Each sub-node represents the reserved area for SCPI.
-
-Required sub-node properties:
-- reg : The base offset and size of the reserved area with the SRAM
-- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
- shared memory on Juno platforms
-
-Sensor bindings for the sensors based on SCPI Message Protocol
---------------------------------------------------------------
-Required properties:
-- compatible : should be "arm,scpi-sensors".
-- #thermal-sensor-cells: should be set to 1.
- For Juno R0 and Juno R1 refer to [1] for the
- sensor identifiers
-
-[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
-[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
diff --git a/Bindings/arm/keystone/ti,sci.txt b/Bindings/arm/keystone/ti,sci.txt
deleted file mode 100644
index 6f0cd31..0000000
--- a/Bindings/arm/keystone/ti,sci.txt
+++ /dev/null
@@ -1,86 +0,0 @@
-Texas Instruments System Control Interface (TI-SCI) Message Protocol
---------------------------------------------------------------------
-
-Texas Instrument's processors including those belonging to Keystone generation
-of processors have separate hardware entity which is now responsible for the
-management of the System on Chip (SoC) system. These include various system
-level functions as well.
-
-An example of such an SoC is K2G, which contains the system control hardware
-block called Power Management Micro Controller (PMMC). This hardware block is
-initialized early into boot process and provides services to Operating Systems
-on multiple processors including ones running Linux.
-
-See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
-
-TI-SCI controller Device Node:
-=============================
-
-The TI-SCI node describes the Texas Instrument's System Controller entity node.
-This parent node may optionally have additional children nodes which describe
-specific functionality such as clocks, power domain, reset or additional
-functionality as may be required for the SoC. This hierarchy also describes the
-relationship between the TI-SCI parent node to the child node.
-
-Required properties:
--------------------
-- compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
- should be "ti,am654-sci" for for TI AM654 SoC
-- mbox-names:
- "rx" - Mailbox corresponding to receive path
- "tx" - Mailbox corresponding to transmit path
-
-- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
- property should contain a phandle to the mailbox controller device
- node and an args specifier that will be the phandle to the intended
- sub-mailbox child node to be used for communication.
-
-See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
-about the generic mailbox controller and client driver bindings. Also see
-Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical
-controller that is used to communicate with this System controllers.
-
-Optional Properties:
--------------------
-- reg-names:
- debug_messages - Map the Debug message region
-- reg: register space corresponding to the debug_messages
-- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot
-- ti,host-id: Integer value corresponding to the host ID assigned by Firmware
- for identification of host processing entities such as virtual
- machines
-
-Example (K2G):
--------------
- pmmc: pmmc {
- compatible = "ti,k2g-sci";
- ti,host-id = <2>;
- mbox-names = "rx", "tx";
- mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,
- <&msgmgr &msgmgr_proxy_pmmc_tx>;
- reg-names = "debug_messages";
- reg = <0x02921800 0x800>;
- };
-
-
-TI-SCI Client Device Node:
-=========================
-
-Client nodes are maintained as children of the relevant TI-SCI device node.
-
-Example (K2G):
--------------
- pmmc: pmmc {
- compatible = "ti,k2g-sci";
- ...
-
- my_clk_node: clk_node {
- ...
- ...
- };
-
- my_pd_node: pd_node {
- ...
- ...
- };
- };
diff --git a/Bindings/arm/keystone/ti,sci.yaml b/Bindings/arm/keystone/ti,sci.yaml
new file mode 100644
index 0000000..34f5f87
--- /dev/null
+++ b/Bindings/arm/keystone/ti,sci.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI controller device node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Texas Instrument's processors including those belonging to Keystone generation
+ of processors have separate hardware entity which is now responsible for the
+ management of the System on Chip (SoC) system. These include various system
+ level functions as well.
+
+ An example of such an SoC is K2G, which contains the system control hardware
+ block called Power Management Micro Controller (PMMC). This hardware block is
+ initialized early into boot process and provides services to Operating Systems
+ on multiple processors including ones running Linux.
+
+ See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
+
+ The TI-SCI node describes the Texas Instrument's System Controller entity node.
+ This parent node may optionally have additional children nodes which describe
+ specific functionality such as clocks, power domain, reset or additional
+ functionality as may be required for the SoC. This hierarchy also describes the
+ relationship between the TI-SCI parent node to the child node.
+
+properties:
+ $nodename:
+ pattern: "^system-controller@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - description: System controller on TI 66AK2G SoC and other K3 SoCs
+ items:
+ - const: ti,k2g-sci
+ - description: System controller on TI AM654 SoC
+ items:
+ - const: ti,am654-sci
+
+ reg-names:
+ description: |
+ Specifies the debug messages memory mapped region that is optionally
+ made available from TI-SCI controller.
+ const: debug_messages
+
+ reg:
+ minItems: 1
+
+ mbox-names:
+ description: |
+ Specifies the mailboxes used to communicate with TI-SCI Controller
+ made available from TI-SCI controller.
+ items:
+ - const: rx
+ - const: tx
+
+ mboxes:
+ minItems: 2
+
+ ti,system-reboot-controller:
+ description: Determines If system reboot can be triggered by SoC reboot
+ type: boolean
+
+ ti,host-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Value corresponding to the host ID assigned by Firmware
+ for identification of host processing entities such as virtual machines.
+
+ power-controller:
+ type: object
+ $ref: /schemas/soc/ti/sci-pm-domain.yaml#
+
+ clock-controller:
+ type: object
+ $ref: /schemas/clock/ti,sci-clk.yaml#
+
+ reset-controller:
+ type: object
+ $ref: /schemas/reset/ti,sci-reset.yaml#
+
+required:
+ - compatible
+ - mbox-names
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ pmmc: system-controller@2921800 {
+ compatible = "ti,k2g-sci";
+ ti,system-reboot-controller;
+ mbox-names = "rx", "tx";
+ mboxes= <&msgmgr 5 2>,
+ <&msgmgr 0 0>;
+ reg-names = "debug_messages";
+ reg = <0x02921800 0x800>;
+ };
+
+ - |
+ dmsc: system-controller@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x44083000 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
diff --git a/Bindings/arm/mediatek.yaml b/Bindings/arm/mediatek.yaml
index aff57a8..80a05f6 100644
--- a/Bindings/arm/mediatek.yaml
+++ b/Bindings/arm/mediatek.yaml
@@ -122,6 +122,10 @@
- enum:
- mediatek,mt8195-evb
- const: mediatek,mt8195
+ - description: Google Burnet (HP Chromebook x360 11MK G3 EE)
+ items:
+ - const: google,burnet
+ - const: mediatek,mt8183
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
items:
- enum:
@@ -133,9 +137,19 @@
items:
- const: google,damu
- const: mediatek,mt8183
- - description: Google Juniper (Acer Chromebook Spin 311)
+ - description: Google Fennel (Lenovo IdeaPad 3 Chromebook)
items:
- - const: google,juniper-sku16
+ - enum:
+ - google,fennel-sku0
+ - google,fennel-sku1
+ - google,fennel-sku6
+ - const: google,fennel
+ - const: mediatek,mt8183
+ - description: Google Juniper (Acer Chromebook Spin 311) / Kenzo (Acer Chromebook 311)
+ items:
+ - enum:
+ - google,juniper-sku16
+ - google,juniper-sku17
- const: google,juniper
- const: mediatek,mt8183
- description: Google Kakadu (ASUS Chromebook Detachable CM3)
@@ -144,6 +158,10 @@
- const: google,kakadu-rev2
- const: google,kakadu
- const: mediatek,mt8183
+ - description: Google Kappa (HP Chromebook 11a)
+ items:
+ - const: google,kappa
+ - const: mediatek,mt8183
- description: Google Kodama (Lenovo 10e Chromebook Tablet)
items:
- enum:
@@ -153,6 +171,13 @@
- google,kodama-sku32
- const: google,kodama
- const: mediatek,mt8183
+ - description: Google Willow (Acer Chromebook 311 C722/C722T)
+ items:
+ - enum:
+ - google,willow-sku0
+ - google,willow-sku1
+ - const: google,willow
+ - const: mediatek,mt8183
- items:
- enum:
- mediatek,mt8183-pumpkin
diff --git a/Bindings/arm/msm/qcom,saw2.txt b/Bindings/arm/msm/qcom,saw2.txt
index ae4afc6..94d50a9 100644
--- a/Bindings/arm/msm/qcom,saw2.txt
+++ b/Bindings/arm/msm/qcom,saw2.txt
@@ -25,6 +25,7 @@
"qcom,saw2"
A more specific value could be one of:
"qcom,apq8064-saw2-v1.1-cpu"
+ "qcom,msm8226-saw2-v2.1-cpu"
"qcom,msm8974-saw2-v2.1-cpu"
"qcom,apq8084-saw2-v2.1-cpu"
diff --git a/Bindings/arm/qcom.yaml b/Bindings/arm/qcom.yaml
index 9b27e99..9720b00 100644
--- a/Bindings/arm/qcom.yaml
+++ b/Bindings/arm/qcom.yaml
@@ -36,17 +36,20 @@
msm8992
msm8994
msm8996
+ sa8155p
sc7180
sc7280
sdm630
sdm660
sdm845
sdx55
+ sm8150
sm8250
sm8350
The 'board' element must be one of the following strings:
+ adp
cdp
cp01-c1
dragonboard
@@ -178,6 +181,7 @@
- items:
- enum:
- qcom,sc7280-idp
+ - google,senor
- const: qcom,sc7280
- items:
@@ -200,6 +204,16 @@
- items:
- enum:
+ - qcom,sa8155p-adp
+ - const: qcom,sa8155p
+
+ - items:
+ - enum:
+ - qcom,sm8150-mtp
+ - const: qcom,sm8150
+
+ - items:
+ - enum:
- qcom,qrb5165-rb5
- qcom,sm8250-mtp
- const: qcom,sm8250
diff --git a/Bindings/arm/renesas.yaml b/Bindings/arm/renesas.yaml
index 5fd0696..a0cce4e 100644
--- a/Bindings/arm/renesas.yaml
+++ b/Bindings/arm/renesas.yaml
@@ -302,6 +302,24 @@
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
- const: renesas,r9a06g032
+ - description: RZ/G2UL (R9A07G043)
+ items:
+ - enum:
+ - renesas,r9a07g043u11 # RZ/G2UL Type-1
+ - renesas,r9a07g043u12 # RZ/G2UL Type-2
+ - const: renesas,r9a07g043
+
+ - description: RZ/G2{L,LC} (R9A07G044)
+ items:
+ - enum:
+ - renesas,smarc-evk # SMARC EVK
+ - enum:
+ - renesas,r9a07g044c1 # Single Cortex-A55 RZ/G2LC
+ - renesas,r9a07g044c2 # Dual Cortex-A55 RZ/G2LC
+ - renesas,r9a07g044l1 # Single Cortex-A55 RZ/G2L
+ - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
+ - const: renesas,r9a07g044
+
additionalProperties: true
...
diff --git a/Bindings/arm/rockchip.yaml b/Bindings/arm/rockchip.yaml
index 4a6f772..6546b01 100644
--- a/Bindings/arm/rockchip.yaml
+++ b/Bindings/arm/rockchip.yaml
@@ -600,6 +600,11 @@
- const: zkmagic,a95x-z2
- const: rockchip,rk3318
+ - description: Rockchip RK3568 Evaluation board
+ items:
+ - const: rockchip,rk3568-evb1-v10
+ - const: rockchip,rk3568
+
additionalProperties: true
...
diff --git a/Bindings/arm/rockchip/pmu.txt b/Bindings/arm/rockchip/pmu.txt
deleted file mode 100644
index 3ee9b42..0000000
--- a/Bindings/arm/rockchip/pmu.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Rockchip power-management-unit:
--------------------------------
-
-The pmu is used to turn off and on different power domains of the SoCs
-This includes the power to the CPU cores.
-
-Required node properties:
-- compatible value : = "rockchip,rk3066-pmu";
-- reg : physical base address and the size of the registers window
-
-Example:
-
- pmu@20004000 {
- compatible = "rockchip,rk3066-pmu";
- reg = <0x20004000 0x100>;
- };
diff --git a/Bindings/arm/rockchip/pmu.yaml b/Bindings/arm/rockchip/pmu.yaml
new file mode 100644
index 0000000..53115b9
--- /dev/null
+++ b/Bindings/arm/rockchip/pmu.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/rockchip/pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Power Management Unit (PMU)
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The PMU is used to turn on and off different power domains of the SoCs.
+ This includes the power to the CPU cores.
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,px30-pmu
+ - rockchip,rk3066-pmu
+ - rockchip,rk3288-pmu
+ - rockchip,rk3399-pmu
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - rockchip,px30-pmu
+ - rockchip,rk3066-pmu
+ - rockchip,rk3288-pmu
+ - rockchip,rk3399-pmu
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: true
+
+examples:
+ - |
+ pmu@20004000 {
+ compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
+ reg = <0x20004000 0x100>;
+ };
diff --git a/Bindings/arm/scu.txt b/Bindings/arm/scu.txt
deleted file mode 100644
index 74d0a78..0000000
--- a/Bindings/arm/scu.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* ARM Snoop Control Unit (SCU)
-
-As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
-with a Snoop Control Unit. The register range is usually 256 (0x100)
-bytes.
-
-References:
-
-- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
- Revision r2p0
-- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
- Revision r0p1
-- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
- Manial Revision r2p0
-
-- compatible : Should be:
- "arm,cortex-a9-scu"
- "arm,cortex-a5-scu"
- "arm,arm11mp-scu"
-
-- reg : Specify the base address and the size of the SCU register window.
-
-Example:
-
-scu@a0410000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0xa0410000 0x100>;
-};
diff --git a/Bindings/arm/sunxi.yaml b/Bindings/arm/sunxi.yaml
index ac75002..889128a 100644
--- a/Bindings/arm/sunxi.yaml
+++ b/Bindings/arm/sunxi.yaml
@@ -224,6 +224,12 @@
- const: empire-electronix,m712
- const: allwinner,sun5i-a13
+ - description: Forlinx OKA40i-C Development board
+ items:
+ - const: forlinx,oka40i-c
+ - const: forlinx,feta40i-c
+ - const: allwinner,sun8i-r40
+
- description: FriendlyARM NanoPi A64
items:
- const: friendlyarm,nanopi-a64
@@ -269,6 +275,11 @@
- const: friendlyarm,nanopi-r1
- const: allwinner,sun8i-h3
+ - description: FriendlyARM NanoPi R1S H5
+ items:
+ - const: friendlyarm,nanopi-r1s-h5
+ - const: allwinner,sun50i-h5
+
- description: FriendlyARM ZeroPi
items:
- const: friendlyarm,zeropi
diff --git a/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 43fd2f8..0afec83 100644
--- a/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -301,6 +301,33 @@
additionalProperties: false
+ core-domain:
+ type: object
+ description: |
+ The vast majority of hardware blocks of Tegra SoC belong to a
+ Core power domain, which has a dedicated voltage rail that powers
+ the blocks.
+
+ properties:
+ operating-points-v2:
+ description:
+ Should contain level, voltages and opp-supported-hw property.
+ The supported-hw is a bitfield indicating SoC speedo or process
+ ID mask.
+
+ "#power-domain-cells":
+ const: 0
+
+ required:
+ - operating-points-v2
+ - "#power-domain-cells"
+
+ additionalProperties: false
+
+ core-supply:
+ description:
+ Phandle to voltage regulator connected to the SoC Core power rail.
+
required:
- compatible
- reg
@@ -325,6 +352,7 @@
tegra_pmc: pmc@7000e400 {
compatible = "nvidia,tegra210-pmc";
reg = <0x7000e400 0x400>;
+ core-supply = <®ulator>;
clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
clock-names = "pclk", "clk32k_in";
#clock-cells = <1>;
@@ -338,17 +366,24 @@
nvidia,core-power-req-active-high;
nvidia,sys-clock-req-active-high;
+ pd_core: core-domain {
+ operating-points-v2 = <&core_opp_table>;
+ #power-domain-cells = <0>;
+ };
+
powergates {
pd_audio: aud {
clocks = <&tegra_car TEGRA210_CLK_APE>,
<&tegra_car TEGRA210_CLK_APB2APE>;
resets = <&tegra_car 198>;
+ power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+ power-domains = <&pd_core>;
#power-domain-cells = <0>;
};
};
diff --git a/Bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Bindings/arm/tegra/nvidia,tegra30-actmon.txt
deleted file mode 100644
index 897eedf..0000000
--- a/Bindings/arm/tegra/nvidia,tegra30-actmon.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-NVIDIA Tegra Activity Monitor
-
-The activity monitor block collects statistics about the behaviour of other
-components in the system. This information can be used to derive the rate at
-which the external memory needs to be clocked in order to serve all requests
-from the monitored clients.
-
-Required properties:
-- compatible: should be "nvidia,tegra<chip>-actmon"
-- reg: offset and length of the register set for the device
-- interrupts: standard interrupt property
-- clocks: Must contain a phandle and clock specifier pair for each entry in
-clock-names. See ../../clock/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
- - actmon
- - emc
-- resets: Must contain an entry for each entry in reset-names. See
-../../reset/reset.txt for details.
-- reset-names: Must include the following entries:
- - actmon
-- operating-points-v2: See ../bindings/opp/opp.txt for details.
-- interconnects: Should contain entries for memory clients sitting on
- MC->EMC memory interconnect path.
-- interconnect-names: Should include name of the interconnect path for each
- interconnect entry. Consult TRM documentation for
- information about available memory clients, see MEMORY
- CONTROLLER section.
-
-For each opp entry in 'operating-points-v2' table:
-- opp-supported-hw: bitfield indicating SoC speedo ID mask
-- opp-peak-kBps: peak bandwidth of the memory channel
-
-Example:
- dfs_opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp@12750000 {
- opp-hz = /bits/ 64 <12750000>;
- opp-supported-hw = <0x000F>;
- opp-peak-kBps = <51000>;
- };
- ...
- };
-
- actmon@6000c800 {
- compatible = "nvidia,tegra124-actmon";
- reg = <0x0 0x6000c800 0x0 0x400>;
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&tegra_car TEGRA124_CLK_ACTMON>,
- <&tegra_car TEGRA124_CLK_EMC>;
- clock-names = "actmon", "emc";
- resets = <&tegra_car 119>;
- reset-names = "actmon";
- operating-points-v2 = <&dfs_opp_table>;
- interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
- interconnect-names = "cpu";
- };
diff --git a/Bindings/arm/ux500/boards.txt b/Bindings/arm/ux500/boards.txt
index 89408de..18d5553 100644
--- a/Bindings/arm/ux500/boards.txt
+++ b/Bindings/arm/ux500/boards.txt
@@ -20,13 +20,13 @@
compatible = "ste,dbx500-backupram"
scu:
- see binding for arm/scu.txt
+ see binding for arm/arm,scu.yaml
interrupt-controller:
see binding for interrupt-controller/arm,gic.txt
timer:
- see binding for timer/arm,twd.txt
+ see binding for timer/arm,twd-timer.yaml
clocks:
see binding for clocks/ux500.txt
diff --git a/Bindings/ata/nvidia,tegra-ahci.yaml b/Bindings/ata/nvidia,tegra-ahci.yaml
index a75e9a8..3c7a242 100644
--- a/Bindings/ata/nvidia,tegra-ahci.yaml
+++ b/Bindings/ata/nvidia,tegra-ahci.yaml
@@ -20,7 +20,6 @@
reg:
minItems: 2
- maxItems: 3
items:
- description: AHCI registers
- description: SATA configuration and IPFS registers
diff --git a/Bindings/ata/renesas,rcar-sata.yaml b/Bindings/ata/renesas,rcar-sata.yaml
index d06096a..c060c79 100644
--- a/Bindings/ata/renesas,rcar-sata.yaml
+++ b/Bindings/ata/renesas,rcar-sata.yaml
@@ -53,6 +53,17 @@
- reg
- interrupts
- clocks
+ - power-domains
+
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: renesas,sata-r8a7779
+then:
+ required:
+ - resets
additionalProperties: false
diff --git a/Bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
index a27025c..c4b7243 100644
--- a/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -51,7 +51,6 @@
clocks:
minItems: 2
- maxItems: 4
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
@@ -60,7 +59,6 @@
clock-names:
minItems: 2
- maxItems: 4
items:
- const: hosc
- const: losc
diff --git a/Bindings/clock/brcm,iproc-clocks.txt b/Bindings/clock/brcm,iproc-clocks.txt
deleted file mode 100644
index ab730ea..0000000
--- a/Bindings/clock/brcm,iproc-clocks.txt
+++ /dev/null
@@ -1,313 +0,0 @@
-Broadcom iProc Family Clocks
-
-This binding uses the common clock binding:
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The iProc clock controller manages clocks that are common to the iProc family.
-An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
-LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
-comprises of several leaf clocks
-
-Required properties for a PLL and its leaf clocks:
-
-- compatible:
- Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
-Cygnus has a compatible string of "brcm,cygnus-genpll"
-
-- #clock-cells:
- Have a value of <1> since there are more than 1 leaf clock of a given PLL
-
-- reg:
- Define the base and range of the I/O address space that contain the iProc
-clock control registers required for the PLL
-
-- clocks:
- The input parent clock phandle for the PLL. For most iProc PLLs, this is an
-onboard crystal with a fixed rate
-
-- clock-output-names:
- An ordered list of strings defining the names of the clocks
-
-Example:
-
- osc: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- };
-
- genpll: genpll {
- #clock-cells = <1>;
- compatible = "brcm,cygnus-genpll";
- reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
- clocks = <&osc>;
- clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
- "enet_sw", "audio_125", "can";
- };
-
-Required properties for ASIU clocks:
-
-ASIU clocks are a special case. These clocks are derived directly from the
-reference clock of the onboard crystal
-
-- compatible:
- Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
-clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
-
-- #clock-cells:
- Have a value of <1> since there are more than 1 ASIU clocks
-
-- reg:
- Define the base and range of the I/O address space that contain the iProc
-clock control registers required for ASIU clocks
-
-- clocks:
- The input parent clock phandle for the ASIU clock, i.e., the onboard
-crystal
-
-- clock-output-names:
- An ordered list of strings defining the names of the ASIU clocks
-
-Example:
-
- osc: oscillator {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <25000000>;
- };
-
- asiu_clks: asiu_clks {
- #clock-cells = <1>;
- compatible = "brcm,cygnus-asiu-clk";
- reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
- clocks = <&osc>;
- clock-output-names = "keypad", "adc/touch", "pwm";
- };
-
-Cygnus
-------
-PLL and leaf clock compatible strings for Cygnus are:
- "brcm,cygnus-armpll"
- "brcm,cygnus-genpll"
- "brcm,cygnus-lcpll0"
- "brcm,cygnus-mipipll"
- "brcm,cygnus-asiu-clk"
- "brcm,cygnus-audiopll"
-
-The following table defines the set of PLL/clock index and ID for Cygnus.
-These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-cygnus.h"
-
- Clock Source (Parent) Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- armpll crystal N/A N/A
-
- keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
- adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
- pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
-
- genpll crystal 0 BCM_CYGNUS_GENPLL
- axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
- 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
- ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
- enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
- audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
- can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
-
- lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
- pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
- ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
- sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
- usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
- smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
- ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
-
- mipipll crystal 0 BCM_CYGNUS_MIPIPLL
- ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
- ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
- ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
- ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
- ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
- ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
-
- audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
- ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
- ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
- ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
-
-Hurricane 2
-------
-PLL and leaf clock compatible strings for Hurricane 2 are:
- "brcm,hr2-armpll"
-
-The following table defines the set of PLL/clock for Hurricane 2:
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- armpll crystal N/A N/A
-
-
-Northstar and Northstar Plus
-------
-PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
- "brcm,nsp-armpll"
- "brcm,nsp-genpll"
- "brcm,nsp-lcpll0"
-
-The following table defines the set of PLL/clock index and ID for Northstar and
-Northstar Plus. These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-nsp.h"
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- armpll crystal N/A N/A
-
- genpll crystal 0 BCM_NSP_GENPLL
- phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
- ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
- usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
- iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
- sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
- sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
-
- lcpll0 crystal 0 BCM_NSP_LCPLL0
- pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
- sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
- ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
-
-Northstar 2
------------
-PLL and leaf clock compatible strings for Northstar 2 are:
- "brcm,ns2-genpll-scr"
- "brcm,ns2-genpll-sw"
- "brcm,ns2-lcpll-ddr"
- "brcm,ns2-lcpll-ports"
-
-The following table defines the set of PLL/clock index and ID for Northstar 2.
-These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-ns2.h"
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
-
- genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
- scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
- fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
- audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
- ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
- ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
- ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
-
- genpll_sw crystal 0 BCM_NS2_GENPLL_SW
- rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
- 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
- nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
- chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
- port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
- sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
-
- lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
- pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
- ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
- ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
- ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
- ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
- ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
-
- lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
- wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
- rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
- ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
- ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
- ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
- ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
-
-BCM63138
---------
-PLL and leaf clock compatible strings for BCM63138 are:
- "brcm,bcm63138-armpll"
-
-Stingray
------------
-PLL and leaf clock compatible strings for Stingray are:
- "brcm,sr-genpll0"
- "brcm,sr-genpll1"
- "brcm,sr-genpll2"
- "brcm,sr-genpll3"
- "brcm,sr-genpll4"
- "brcm,sr-genpll5"
- "brcm,sr-genpll6"
-
- "brcm,sr-lcpll0"
- "brcm,sr-lcpll1"
- "brcm,sr-lcpll-pcie"
-
-
-The following table defines the set of PLL/clock index and ID for Stingray.
-These clock IDs are defined in:
- "include/dt-bindings/clock/bcm-sr.h"
-
- Clock Source Index ID
- --- ----- ----- ---------
- crystal N/A N/A N/A
- crmu_ref25m crystal N/A N/A
-
- genpll0 crystal 0 BCM_SR_GENPLL0
- clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
- clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
- clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
- clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
- clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
- clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
-
- genpll1 crystal 0 BCM_SR_GENPLL1
- clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
- clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
-
- genpll2 crystal 0 BCM_SR_GENPLL2
- clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
- clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
- clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
- clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
- clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
- clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
-
- genpll3 crystal 0 BCM_SR_GENPLL3
- clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
- clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
-
- genpll4 crystal 0 BCM_SR_GENPLL4
- clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
- clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
- clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
- clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
- clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
-
- genpll5 crystal 0 BCM_SR_GENPLL5
- clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
- clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
- clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
-
- genpll6 crystal 0 BCM_SR_GENPLL6
- clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
-
- lcpll0 crystal 0 BCM_SR_LCPLL0
- clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
- clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
- clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
- clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
-
- lcpll1 crystal 0 BCM_SR_LCPLL1
- clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
- clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
- clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
-
- lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
- clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
diff --git a/Bindings/clock/brcm,iproc-clocks.yaml b/Bindings/clock/brcm,iproc-clocks.yaml
new file mode 100644
index 0000000..8dc7b40
--- /dev/null
+++ b/Bindings/clock/brcm,iproc-clocks.yaml
@@ -0,0 +1,395 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom iProc Family Clocks
+
+maintainers:
+ - Ray Jui <rjui@broadcom.com>
+ - Scott Branden <sbranden@broadcom.com>
+
+description: |
+ The iProc clock controller manages clocks that are common to the iProc family.
+ An SoC from the iProc family may have several PLLs, e.g., ARMPLL, GENPLL,
+ LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
+ comprises of several leaf clocks
+
+ ASIU clocks are a special case. These clocks are derived directly from the
+ reference clock of the onboard crystal.
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm63138-armpll
+ - brcm,cygnus-armpll
+ - brcm,cygnus-genpll
+ - brcm,cygnus-lcpll0
+ - brcm,cygnus-mipipll
+ - brcm,cygnus-asiu-clk
+ - brcm,cygnus-audiopll
+ - brcm,hr2-armpll
+ - brcm,nsp-armpll
+ - brcm,nsp-genpll
+ - brcm,nsp-lcpll0
+ - brcm,ns2-genpll-scr
+ - brcm,ns2-genpll-sw
+ - brcm,ns2-lcpll-ddr
+ - brcm,ns2-lcpll-ports
+ - brcm,sr-genpll0
+ - brcm,sr-genpll1
+ - brcm,sr-genpll2
+ - brcm,sr-genpll3
+ - brcm,sr-genpll4
+ - brcm,sr-genpll5
+ - brcm,sr-genpll6
+ - brcm,sr-lcpll0
+ - brcm,sr-lcpll1
+ - brcm,sr-lcpll-pcie
+
+ reg:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: base register
+ - description: power register
+ - description: ASIU or split status register
+
+ clocks:
+ description: The input parent clock phandle for the PLL / ASIU clock. For
+ most iProc PLLs, this is an onboard crystal with a fixed rate.
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ clock-output-names:
+ minItems: 1
+ maxItems: 45
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,cygnus-armpll
+ - brcm,cygnus-genpll
+ - brcm,cygnus-lcpll0
+ - brcm,cygnus-mipipll
+ - brcm,cygnus-asiu-clk
+ - brcm,cygnus-audiopll
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Cygnus.
+ These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-cygnus.h"
+
+ Clock Source (Parent) Index ID
+ ----- --------------- ----- --
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+
+ keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
+ adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
+ pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
+
+ genpll crystal 0 BCM_CYGNUS_GENPLL
+ axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
+ 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
+ ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
+ enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
+ audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
+ can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
+
+ lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
+ pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
+ ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
+ sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
+ usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
+ smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
+ ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
+
+ mipipll crystal 0 BCM_CYGNUS_MIPIPLL
+ ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
+ ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
+ ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
+ ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
+ ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
+ ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
+
+ audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
+ ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
+ ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
+ ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,hr2-armpll
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock for Hurricane 2:
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,nsp-armpll
+ - brcm,nsp-genpll
+ - brcm,nsp-lcpll0
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Northstar and
+ Northstar Plus. These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-nsp.h"
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+
+ armpll crystal N/A N/A
+
+ genpll crystal 0 BCM_NSP_GENPLL
+ phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
+ ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
+ usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
+ iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
+ sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
+ sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
+
+ lcpll0 crystal 0 BCM_NSP_LCPLL0
+ pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
+ sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
+ ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,ns2-genpll-scr
+ - brcm,ns2-genpll-sw
+ - brcm,ns2-lcpll-ddr
+ - brcm,ns2-lcpll-ports
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Northstar 2.
+ These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-ns2.h"
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+
+ genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
+ scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
+ fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
+ audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
+ ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
+ ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
+ ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
+
+ genpll_sw crystal 0 BCM_NS2_GENPLL_SW
+ rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
+ 250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
+ nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
+ chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
+ port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
+ sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
+
+ lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
+ pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
+ ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
+ ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
+ ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
+ ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
+ ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
+
+ lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
+ wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
+ rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
+ ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
+ ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
+ ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
+ ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,sr-genpll0
+ - brcm,sr-genpll1
+ - brcm,sr-genpll2
+ - brcm,sr-genpll3
+ - brcm,sr-genpll4
+ - brcm,sr-genpll5
+ - brcm,sr-genpll6
+ - brcm,sr-lcpll0
+ - brcm,sr-lcpll1
+ - brcm,sr-lcpll-pcie
+ then:
+ properties:
+ clock-output-names:
+ description: |
+ The following table defines the set of PLL/clock index and ID for Stingray.
+ These clock IDs are defined in:
+ "include/dt-bindings/clock/bcm-sr.h"
+
+ Clock Source Index ID
+ ----- ------ ----- --
+ crystal N/A N/A N/A
+ crmu_ref25m crystal N/A N/A
+
+ genpll0 crystal 0 BCM_SR_GENPLL0
+ clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
+ clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
+ clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
+ clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
+ clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
+ clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
+
+ genpll1 crystal 0 BCM_SR_GENPLL1
+ clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
+ clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
+
+ genpll2 crystal 0 BCM_SR_GENPLL2
+ clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
+ clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
+ clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
+ clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
+ clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
+ clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
+
+ genpll3 crystal 0 BCM_SR_GENPLL3
+ clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
+ clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
+
+ genpll4 crystal 0 BCM_SR_GENPLL4
+ clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
+ clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
+ clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
+ clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
+ clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
+
+ genpll5 crystal 0 BCM_SR_GENPLL5
+ clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
+ clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
+ clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
+
+ genpll6 crystal 0 BCM_SR_GENPLL6
+ clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
+
+ lcpll0 crystal 0 BCM_SR_LCPLL0
+ clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
+ clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
+ clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
+ clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
+
+ lcpll1 crystal 0 BCM_SR_LCPLL1
+ clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
+ clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
+ clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
+
+ lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
+ clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,cygnus-genpll
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: genpll
+ - const: axi21
+ - const: 250mhz
+ - const: ihost_sys
+ - const: enet_sw
+ - const: audio_125
+ - const: can
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,nsp-lcpll0
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: lcpll0
+ - const: pcie_phy
+ - const: sdio
+ - const: ddr_phy
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,nsp-genpll
+ then:
+ properties:
+ clock-output-names:
+ items:
+ - const: genpll
+ - const: phy
+ - const: ethernetclk
+ - const: usbclk
+ - const: iprocfast
+ - const: sata1
+ - const: sata2
+
+required:
+ - reg
+ - clocks
+ - '#clock-cells'
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ osc1: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ genpll@301d000 {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x301d000 0x2c>, <0x301c020 0x4>;
+ clocks = <&os1c>;
+ clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
+ "enet_sw", "audio_125", "can";
+ };
+ - |
+ osc2: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ asiu_clks@301d048 {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-asiu-clk";
+ reg = <0x301d048 0xc>, <0x180aa024 0x4>;
+ clocks = <&osc2>;
+ clock-output-names = "keypad", "adc/touch", "pwm";
+ };
diff --git a/Bindings/clock/gpio-mux-clock.txt b/Bindings/clock/gpio-mux-clock.txt
deleted file mode 100644
index 2be1e03..0000000
--- a/Bindings/clock/gpio-mux-clock.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Binding for simple gpio clock multiplexer.
-
-This binding uses the common clock binding[1].
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Required properties:
-- compatible : shall be "gpio-mux-clock".
-- clocks: list of two references to parent clocks.
-- #clock-cells : from common clock binding; shall be set to 0.
-- select-gpios : GPIO reference for selecting the parent clock.
-
-Example:
- clock {
- compatible = "gpio-mux-clock";
- clocks = <&parentclk1>, <&parentclk2>;
- #clock-cells = <0>;
- select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
- };
diff --git a/Bindings/clock/gpio-mux-clock.yaml b/Bindings/clock/gpio-mux-clock.yaml
new file mode 100644
index 0000000..1e21f8b
--- /dev/null
+++ b/Bindings/clock/gpio-mux-clock.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Simple GPIO clock multiplexer
+
+maintainers:
+ - Sergej Sawazki <ce3a@gmx.de>
+
+properties:
+ compatible:
+ const: gpio-mux-clock
+
+ clocks:
+ items:
+ - description: First parent clock
+ - description: Second parent clock
+
+ '#clock-cells':
+ const: 0
+
+ select-gpios:
+ description: GPIO reference for selecting the parent clock.
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - '#clock-cells'
+ - select-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ clock {
+ compatible = "gpio-mux-clock";
+ clocks = <&parentclk1>, <&parentclk2>;
+ #clock-cells = <0>;
+ select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/Bindings/clock/hisilicon,hi3559av100-clock.yaml b/Bindings/clock/hisilicon,hi3559av100-clock.yaml
new file mode 100644
index 0000000..3ceb29c
--- /dev/null
+++ b/Bindings/clock/hisilicon,hi3559av100-clock.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/hisilicon,hi3559av100-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon SOC Clock for HI3559AV100
+
+maintainers:
+ - Dongjiu Geng <gengdongjiu@huawei.com>
+
+description: |
+ Hisilicon SOC clock control module which supports the clocks, resets and
+ power domains on HI3559AV100.
+
+ See also:
+ dt-bindings/clock/hi3559av100-clock.h
+
+properties:
+ compatible:
+ enum:
+ - hisilicon,hi3559av100-clock
+ - hisilicon,hi3559av100-shub-clock
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 2
+ description: |
+ First cell is reset request register offset.
+ Second cell is bit offset in reset request register.
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@12010000 {
+ compatible = "hisilicon,hi3559av100-clock";
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+ reg = <0x0 0x12010000 0x0 0x10000>;
+ };
+ };
+...
diff --git a/Bindings/clock/idt,versaclock5.yaml b/Bindings/clock/idt,versaclock5.yaml
index 28675b0..26ed040 100644
--- a/Bindings/clock/idt,versaclock5.yaml
+++ b/Bindings/clock/idt,versaclock5.yaml
@@ -84,6 +84,7 @@
idt,slew-percent:
description: The Slew rate control for CMOS single-ended.
enum: [ 80, 85, 90, 100 ]
+ additionalProperties: false
required:
- compatible
@@ -139,13 +140,13 @@
clock-names = "xin";
OUT1 {
- idt,drive-mode = <VC5_CMOSD>;
- idt,voltage-microvolts = <1800000>;
+ idt,mode = <VC5_CMOSD>;
+ idt,voltage-microvolt = <1800000>;
idt,slew-percent = <80>;
};
OUT4 {
- idt,drive-mode = <VC5_LVDS>;
+ idt,mode = <VC5_LVDS>;
};
};
};
diff --git a/Bindings/clock/ingenic,cgu.yaml b/Bindings/clock/ingenic,cgu.yaml
index c65b945..6e80dbc 100644
--- a/Bindings/clock/ingenic,cgu.yaml
+++ b/Bindings/clock/ingenic,cgu.yaml
@@ -22,6 +22,8 @@
enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
+ - ingenic,jz4760-cgu
+ - ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu
@@ -49,6 +51,8 @@
- enum:
- ingenic,jz4740-cgu
- ingenic,jz4725b-cgu
+ - ingenic,jz4760-cgu
+ - ingenic,jz4760b-cgu
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu
@@ -93,6 +97,8 @@
patternProperties:
"^usb-phy@[a-f0-9]+$":
allOf: [ $ref: "../phy/ingenic,phy-usb.yaml#" ]
+ "^mac-phy-ctrl@[a-f0-9]+$":
+ allOf: [ $ref: "../net/ingenic,mac.yaml#" ]
additionalProperties: false
diff --git a/Bindings/clock/nvidia,tegra114-car.txt b/Bindings/clock/nvidia,tegra114-car.txt
deleted file mode 100644
index 9acea9d..0000000
--- a/Bindings/clock/nvidia,tegra114-car.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-NVIDIA Tegra114 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra114-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra114-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra114-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA114_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-};
diff --git a/Bindings/clock/nvidia,tegra124-car.txt b/Bindings/clock/nvidia,tegra124-car.txt
deleted file mode 100644
index 7f02fb4..0000000
--- a/Bindings/clock/nvidia,tegra124-car.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-NVIDIA Tegra124 and Tegra132 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in the header files
- <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common
- to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>
- (for Tegra124-specific clocks).
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-- nvidia,external-memory-controller : phandle of the EMC driver.
-
-The node should contain a "emc-timings" subnode for each supported RAM type (see
-field RAM_CODE in register PMC_STRAPPING_OPT_A).
-
-Required properties for "emc-timings" nodes :
-- nvidia,ram-code : Should contain the value of RAM_CODE this timing set
- is used for.
-
-Each "emc-timings" node should contain a "timing" subnode for every supported
-EMC clock rate.
-
-Required properties for "timing" nodes :
-- clock-frequency : Should contain the memory clock rate to which this timing
-relates.
-- nvidia,parent-clock-frequency : Should contain the rate at which the current
-parent of the EMC clock should be running at this timing.
-- clocks : Must contain an entry for each entry in clock-names.
- See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries:
- - emc-parent : the clock that should be the parent of the EMC clock at this
-timing.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock@60006000 {
- compatible = "nvidia,tegra124-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- nvidia,external-memory-controller = <&emc>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA124_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <112400000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-
- clock@60006000 {
- emc-timings-3 {
- nvidia,ram-code = <3>;
-
- timing-12750000 {
- clock-frequency = <12750000>;
- nvidia,parent-clock-frequency = <408000000>;
- clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "emc-parent";
- };
- timing-20400000 {
- clock-frequency = <20400000>;
- nvidia,parent-clock-frequency = <408000000>;
- clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
- clock-names = "emc-parent";
- };
- };
- };
-};
diff --git a/Bindings/clock/nvidia,tegra124-car.yaml b/Bindings/clock/nvidia,tegra124-car.yaml
new file mode 100644
index 0000000..ec7ab14
--- /dev/null
+++ b/Bindings/clock/nvidia,tegra124-car.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Clock and Reset Controller
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The Clock and Reset (CAR) is the HW module responsible for muxing and gating
+ Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
+
+ CLKGEN provides the registers to program the PLLs. It controls most of
+ the clock source programming and most of the clock dividers.
+
+ CLKGEN input signals include the external clock for the reference frequency
+ (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
+
+ Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
+
+ RSTGEN provides the registers needed to control resetting of each block in
+ the Tegra system.
+
+properties:
+ compatible:
+ const: nvidia,tegra124-car
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ nvidia,external-memory-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle of the external memory controller node
+
+patternProperties:
+ "^emc-timings-[0-9]+$":
+ type: object
+ properties:
+ nvidia,ram-code:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
+ this timing set is used for
+
+ patternProperties:
+ "^timing-[0-9]+$":
+ type: object
+ properties:
+ clock-frequency:
+ description:
+ external memory clock rate in Hz
+ minimum: 1000000
+ maximum: 1000000000
+
+ nvidia,parent-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ rate of parent clock in Hz
+ minimum: 1000000
+ maximum: 1000000000
+
+ clocks:
+ items:
+ - description: parent clock of EMC
+
+ clock-names:
+ items:
+ - const: emc-parent
+
+ required:
+ - clock-frequency
+ - nvidia,parent-clock-frequency
+ - clocks
+ - clock-names
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra124-car.h>
+
+ car: clock-controller@60006000 {
+ compatible = "nvidia,tegra124-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ usb-controller@c5004000 {
+ compatible = "nvidia,tegra20-ehci";
+ reg = <0xc5004000 0x4000>;
+ clocks = <&car TEGRA124_CLK_USB2>;
+ resets = <&car TEGRA124_CLK_USB2>;
+ };
diff --git a/Bindings/clock/nvidia,tegra20-car.txt b/Bindings/clock/nvidia,tegra20-car.txt
deleted file mode 100644
index 6c5901b..0000000
--- a/Bindings/clock/nvidia,tegra20-car.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-NVIDIA Tegra20 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra20-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra20-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra20-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA20_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-};
diff --git a/Bindings/clock/nvidia,tegra20-car.yaml b/Bindings/clock/nvidia,tegra20-car.yaml
new file mode 100644
index 0000000..459d2a5
--- /dev/null
+++ b/Bindings/clock/nvidia,tegra20-car.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nvidia,tegra20-car.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra Clock and Reset Controller
+
+maintainers:
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The Clock and Reset (CAR) is the HW module responsible for muxing and gating
+ Tegra's clocks, and setting their rates. It comprises CLKGEN and RSTGEN units.
+
+ CLKGEN provides the registers to program the PLLs. It controls most of
+ the clock source programming and most of the clock dividers.
+
+ CLKGEN input signals include the external clock for the reference frequency
+ (12 MHz, 26 MHz) and the external clock for the Real Time Clock (32.768 KHz).
+
+ Outputs from CLKGEN are inputs clock of the h/w blocks in the Tegra system.
+
+ RSTGEN provides the registers needed to control resetting of each block in
+ the Tegra system.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra20-car
+ - nvidia,tegra30-car
+ - nvidia,tegra114-car
+ - nvidia,tegra210-car
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/tegra20-car.h>
+
+ car: clock-controller@60006000 {
+ compatible = "nvidia,tegra20-car";
+ reg = <0x60006000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ usb-controller@c5004000 {
+ compatible = "nvidia,tegra20-ehci";
+ reg = <0xc5004000 0x4000>;
+ clocks = <&car TEGRA20_CLK_USB2>;
+ resets = <&car TEGRA20_CLK_USB2>;
+ };
diff --git a/Bindings/clock/nvidia,tegra210-car.txt b/Bindings/clock/nvidia,tegra210-car.txt
deleted file mode 100644
index 26f237f..0000000
--- a/Bindings/clock/nvidia,tegra210-car.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-NVIDIA Tegra210 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra210-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra210-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra210-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA210_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k>;
- };
-};
diff --git a/Bindings/clock/nvidia,tegra30-car.txt b/Bindings/clock/nvidia,tegra30-car.txt
deleted file mode 100644
index 63618cd..0000000
--- a/Bindings/clock/nvidia,tegra30-car.txt
+++ /dev/null
@@ -1,63 +0,0 @@
-NVIDIA Tegra30 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra30-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the
- CAR. The assignments may be found in header file
- <dt-bindings/clock/tegra30-car.h>.
-- #reset-cells : Should be 1.
- In clock consumers, this cell represents the bit number in the CAR's
- array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra30-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car TEGRA30_CLK_USB2>;
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-};
diff --git a/Bindings/clock/qcom,camcc-sm8250.yaml b/Bindings/clock/qcom,camcc-sm8250.yaml
new file mode 100644
index 0000000..9f239c3
--- /dev/null
+++ b/Bindings/clock/qcom,camcc-sm8250.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,camcc-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller Binding for SM8250
+
+maintainers:
+ - Jonathan Marek <jonathan@marek.ca>
+
+description: |
+ Qualcomm camera clock control module which supports the clocks, resets and
+ power domains on SM8250.
+
+ See also dt-bindings/clock/qcom,camcc-sm8250.h
+
+properties:
+ compatible:
+ const: qcom,sm8250-camcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: sleep_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@ad00000 {
+ compatible = "qcom,sm8250-camcc";
+ reg = <0x0ad00000 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Bindings/clock/qcom,dispcc-sm8x50.yaml b/Bindings/clock/qcom,dispcc-sm8x50.yaml
index 0cdf53f..6667261 100644
--- a/Bindings/clock/qcom,dispcc-sm8x50.yaml
+++ b/Bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -20,6 +20,7 @@
properties:
compatible:
enum:
+ - qcom,sc8180x-dispcc
- qcom,sm8150-dispcc
- qcom,sm8250-dispcc
diff --git a/Bindings/clock/qcom,gcc-apq8064.yaml b/Bindings/clock/qcom,gcc-apq8064.yaml
index eacccc8..8e2eac6 100644
--- a/Bindings/clock/qcom,gcc-apq8064.yaml
+++ b/Bindings/clock/qcom,gcc-apq8064.yaml
@@ -46,7 +46,6 @@
nvmem-cell-names:
minItems: 1
- maxItems: 2
items:
- const: calib
- const: calib_backup
diff --git a/Bindings/clock/qcom,gcc-sdx55.yaml b/Bindings/clock/qcom,gcc-sdx55.yaml
index 1121b39..b0d1c65 100644
--- a/Bindings/clock/qcom,gcc-sdx55.yaml
+++ b/Bindings/clock/qcom,gcc-sdx55.yaml
@@ -27,7 +27,6 @@
- description: Sleep clock source
- description: PLL test clock source (Optional clock)
minItems: 2
- maxItems: 3
clock-names:
items:
@@ -35,7 +34,6 @@
- const: sleep_clk
- const: core_bi_pll_test_se # Optional clock
minItems: 2
- maxItems: 3
'#clock-cells':
const: 1
diff --git a/Bindings/clock/qcom,gcc-sm6125.yaml b/Bindings/clock/qcom,gcc-sm6125.yaml
new file mode 100644
index 0000000..ab12b39
--- /dev/null
+++ b/Bindings/clock/qcom,gcc-sm6125.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SM6125
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@somainline.org>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on SM6125.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-sm6125.h
+
+properties:
+ compatible:
+ const: qcom,gcc-sm6125
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+ clock-names:
+ items:
+ - const: bi_tcxo
+ - const: sleep_clk
+
+ '#clock-cells':
+ const: 1
+
+ '#reset-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+ protected-clocks:
+ description:
+ Protected clock specifier list as per common clock binding.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - reg
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ clock-controller@1400000 {
+ compatible = "qcom,gcc-sm6125";
+ reg = <0x01400000 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
+ };
+...
diff --git a/Bindings/clock/qcom,gcc-sm8350.yaml b/Bindings/clock/qcom,gcc-sm8350.yaml
index 78f3583..1122700 100644
--- a/Bindings/clock/qcom,gcc-sm8350.yaml
+++ b/Bindings/clock/qcom,gcc-sm8350.yaml
@@ -36,7 +36,6 @@
- description: USB3 phy wrapper pipe clock source (Optional clock)
- description: USB3 phy sec pipe clock source (Optional clock)
minItems: 2
- maxItems: 13
clock-names:
items:
@@ -54,7 +53,6 @@
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
minItems: 2
- maxItems: 13
'#clock-cells':
const: 1
diff --git a/Bindings/clock/qcom,gcc.yaml b/Bindings/clock/qcom,gcc.yaml
index 490edad..8453eed 100644
--- a/Bindings/clock/qcom,gcc.yaml
+++ b/Bindings/clock/qcom,gcc.yaml
@@ -26,9 +26,10 @@
- dt-bindings/reset/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8660.h
- dt-bindings/reset/qcom,gcc-msm8660.h
- - dt-bindings/clock/qcom,gcc-msm8974.h
- - dt-bindings/reset/qcom,gcc-msm8974.h
+ - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+ - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- dt-bindings/clock/qcom,gcc-msm8994.h
+ - dt-bindings/clock/qcom,gcc-mdm9607.h
- dt-bindings/clock/qcom,gcc-mdm9615.h
- dt-bindings/reset/qcom,gcc-mdm9615.h
- dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
@@ -40,6 +41,8 @@
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-ipq8064
+ - qcom,gcc-mdm9607
+ - qcom,gcc-msm8226
- qcom,gcc-msm8660
- qcom,gcc-msm8916
- qcom,gcc-msm8939
diff --git a/Bindings/clock/qcom,rpmcc.txt b/Bindings/clock/qcom,rpmcc.txt
index b44a062..6cf5a7e 100644
--- a/Bindings/clock/qcom,rpmcc.txt
+++ b/Bindings/clock/qcom,rpmcc.txt
@@ -12,6 +12,7 @@
"qcom,rpmcc-msm8660", "qcom,rpmcc"
"qcom,rpmcc-apq8060", "qcom,rpmcc"
+ "qcom,rpmcc-msm8226", "qcom,rpmcc"
"qcom,rpmcc-msm8916", "qcom,rpmcc"
"qcom,rpmcc-msm8936", "qcom,rpmcc"
"qcom,rpmcc-msm8974", "qcom,rpmcc"
diff --git a/Bindings/clock/renesas,emev2-smu.txt b/Bindings/clock/renesas,emev2-smu.txt
deleted file mode 100644
index 268ca61..0000000
--- a/Bindings/clock/renesas,emev2-smu.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-Device tree Clock bindings for Renesas EMMA Mobile EV2
-
-This binding uses the common clock binding.
-
-* SMU
-System Management Unit described in user's manual R19UH0037EJ1000_SMU.
-This is not a clock provider, but clocks under SMU depend on it.
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu"
-- reg: Address and Size of SMU registers
-
-* SMU_CLKDIV
-Function block with an input mux and a divider, which corresponds to
-"Serial clock generator" in fig."Clock System Overview" of the manual,
-and "xxx frequency division setting register" (XXXCLKDIV) registers.
-This makes internal (neither input nor output) clock that is provided
-to input of xxxGCLK block.
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu-clkdiv"
-- reg: Byte offset from SMU base and Bit position in the register
-- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
-- #clock-cells: Should be <0>
-
-* SMU_GCLK
-Clock gating node shown as "Clock stop processing block" in the
-fig."Clock System Overview" of the manual.
-Registers are "xxx clock gate control register" (XXXGCLKCTRL).
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu-gclk"
-- reg: Byte offset from SMU base and Bit position in the register
-- clocks: Input clock as described in clock-bindings.txt
-- #clock-cells: Should be <0>
-
-Example of provider:
-
-usia_u0_sclkdiv: usia_u0_sclkdiv {
- compatible = "renesas,emev2-smu-clkdiv";
- reg = <0x610 0>;
- clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
- #clock-cells = <0>;
-};
-
-usia_u0_sclk: usia_u0_sclk {
- compatible = "renesas,emev2-smu-gclk";
- reg = <0x4a0 1>;
- clocks = <&usia_u0_sclkdiv>;
- #clock-cells = <0>;
-};
-
-Example of consumer:
-
-serial@e1020000 {
- compatible = "renesas,em-uart";
- reg = <0xe1020000 0x38>;
- interrupts = <0 8 0>;
- clocks = <&usia_u0_sclk>;
- clock-names = "sclk";
-};
-
-Example of clock-tree description:
-
- This describes a clock path in the clock tree
- c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
-
-smu@e0110000 {
- compatible = "renesas,emev2-smu";
- reg = <0xe0110000 0x10000>;
- #address-cells = <2>;
- #size-cells = <0>;
-
- c32ki: c32ki {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- #clock-cells = <0>;
- };
- pll3_fo: pll3_fo {
- compatible = "fixed-factor-clock";
- clocks = <&c32ki>;
- clock-div = <1>;
- clock-mult = <7000>;
- #clock-cells = <0>;
- };
- usia_u0_sclkdiv: usia_u0_sclkdiv {
- compatible = "renesas,emev2-smu-clkdiv";
- reg = <0x610 0>;
- clocks = <&pll3_fo>;
- #clock-cells = <0>;
- };
- usia_u0_sclk: usia_u0_sclk {
- compatible = "renesas,emev2-smu-gclk";
- reg = <0x4a0 1>;
- clocks = <&usia_u0_sclkdiv>;
- #clock-cells = <0>;
- };
-};
diff --git a/Bindings/clock/renesas,emev2-smu.yaml b/Bindings/clock/renesas,emev2-smu.yaml
new file mode 100644
index 0000000..4d9a648
--- /dev/null
+++ b/Bindings/clock/renesas,emev2-smu.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile EV2 System Management Unit
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
+ This is not a clock provider, but clocks under SMU depend on it.
+
+properties:
+ compatible:
+ const: renesas,emev2-smu
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+patternProperties:
+ ".*sclkdiv@.*":
+ type: object
+
+ description: |
+ Function block with an input mux and a divider, which corresponds to
+ "Serial clock generator" in fig. "Clock System Overview" of the manual,
+ and "xxx frequency division setting register" (XXXCLKDIV) registers.
+ This makes internal (neither input nor output) clock that is provided
+ to input of xxxGCLK block.
+
+ properties:
+ compatible:
+ const: renesas,emev2-smu-clkdiv
+
+ reg:
+ maxItems: 1
+ description:
+ Byte offset from SMU base and Bit position in the register.
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ '#clock-cells':
+ const: 0
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ ".*sclk@.*":
+ type: object
+
+ description: |
+ Clock gating node shown as "Clock stop processing block" in the
+ fig. "Clock System Overview" of the manual.
+ Registers are "xxx clock gate control register" (XXXGCLKCTRL).
+
+ properties:
+ compatible:
+ const: renesas,emev2-smu-gclk
+
+ reg:
+ maxItems: 1
+ description:
+ Byte offset from SMU base and Bit position in the register.
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+ additionalProperties: false
+
+additionalProperties: true
+
+examples:
+ - |
+ // Example of clock-tree description:
+ //
+ // This describes a clock path in the clock tree
+ // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
+ clocks@e0110000 {
+ compatible = "renesas,emev2-smu";
+ reg = <0xe0110000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ c32ki: c32ki {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+ pll3_fo: pll3_fo {
+ compatible = "fixed-factor-clock";
+ clocks = <&c32ki>;
+ clock-div = <1>;
+ clock-mult = <7000>;
+ #clock-cells = <0>;
+ };
+ usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
+ compatible = "renesas,emev2-smu-clkdiv";
+ reg = <0x610 0>;
+ clocks = <&pll3_fo>;
+ #clock-cells = <0>;
+ };
+ usia_u0_sclk: usia_u0_sclk@4a0,1 {
+ compatible = "renesas,emev2-smu-gclk";
+ reg = <0x4a0 1>;
+ clocks = <&usia_u0_sclkdiv>;
+ #clock-cells = <0>;
+ };
+ };
diff --git a/Bindings/clock/renesas,r9a06g032-sysctrl.txt b/Bindings/clock/renesas,r9a06g032-sysctrl.txt
deleted file mode 100644
index aed713c..0000000
--- a/Bindings/clock/renesas,r9a06g032-sysctrl.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Renesas R9A06G032 SYSCTRL
-
-Required Properties:
-
- - compatible: Must be:
- - "renesas,r9a06g032-sysctrl"
- - reg: Base address and length of the SYSCTRL IO block.
- - #clock-cells: Must be 1
- - clocks: References to the parent clocks:
- - external 40mhz crystal.
- - external (optional) 32.768khz
- - external (optional) jtag input
- - external (optional) RGMII_REFCLK
- - clock-names: Must be:
- clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
- - #power-domain-cells: Must be 0
-
-Examples
---------
-
- - SYSCTRL node:
-
- sysctrl: system-controller@4000c000 {
- compatible = "renesas,r9a06g032-sysctrl";
- reg = <0x4000c000 0x1000>;
- #clock-cells = <1>;
-
- clocks = <&ext_mclk>, <&ext_rtc_clk>,
- <&ext_jtag_clk>, <&ext_rgmii_ref>;
- clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
- #power-domain-cells = <0>;
- };
-
- - Other nodes can use the clocks provided by SYSCTRL as in:
-
- #include <dt-bindings/clock/r9a06g032-sysctrl.h>
- uart0: serial@40060000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x40060000 0x400>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- power-domains = <&sysctrl>;
- };
diff --git a/Bindings/clock/renesas,r9a06g032-sysctrl.yaml b/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
new file mode 100644
index 0000000..25dbb0f
--- /dev/null
+++ b/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/N1D (R9A06G032) System Controller
+
+maintainers:
+ - Gareth Williams <gareth.williams.jx@renesas.com>
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+properties:
+ compatible:
+ const: renesas,r9a06g032-sysctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: External 40 MHz crystal
+ - description: Optional external 32.768 kHz crystal
+ - description: Optional external JTAG input
+ - description: Optional external RGMII_REFCLK
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: mclk
+ - const: rtc
+ - const: jtag
+ - const: rgmii_ref_ext
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>,
+ <&ext_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ };
diff --git a/Bindings/clock/renesas,rzg2l-cpg.yaml b/Bindings/clock/renesas,rzg2l-cpg.yaml
new file mode 100644
index 0000000..30b2e3d
--- /dev/null
+++ b/Bindings/clock/renesas,rzg2l-cpg.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description: |
+ On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module
+ Standby Mode share the same register block.
+
+ They provide the following functionalities:
+ - The CPG block generates various core clocks,
+ - The Module Standby Mode block provides two functions:
+ 1. Module Standby, providing a Clock Domain to control the clock supply
+ to individual SoC devices,
+ 2. Reset Control, to perform a software reset of individual SoC devices.
+
+properties:
+ compatible:
+ const: renesas,r9a07g044-cpg # RZ/G2{L,LC}
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ description:
+ Clock source to CPG can be either from external clock input (EXCLK) or
+ crystal oscillator (XIN/XOUT).
+ const: extal
+
+ '#clock-cells':
+ description: |
+ - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+ and a core clock reference, as defined in
+ <dt-bindings/clock/r9a07g044-cpg.h>
+ - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+ a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.
+ const: 2
+
+ '#power-domain-cells':
+ description:
+ SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
+ can be power-managed through Module Standby should refer to the CPG device
+ node in their "power-domains" property, as documented by the generic PM
+ Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
+ const: 0
+
+ '#reset-cells':
+ description:
+ The single reset specifier cell must be the module number, as defined in
+ the <dt-bindings/clock/r9a07g044-cpg.h>.
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g044-cpg";
+ reg = <0x11010000 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/clock/silabs,si5341.txt b/Bindings/clock/silabs,si5341.txt
index 504cce3..ce55aba 100644
--- a/Bindings/clock/silabs,si5341.txt
+++ b/Bindings/clock/silabs,si5341.txt
@@ -24,9 +24,8 @@
The device type, speed grade and revision are determined runtime by probing.
-The driver currently only supports XTAL input mode, and does not support any
-fancy input configurations. They can still be programmed into the chip and
-the driver will leave them "as is".
+The driver currently does not support any fancy input configurations. They can
+still be programmed into the chip and the driver will leave them "as is".
==I2C device node==
@@ -45,9 +44,9 @@
corresponding to inputs. Use a fixed clock for the "xtal" input.
At least one must be present.
- clock-names: One of: "xtal", "in0", "in1", "in2"
-- vdd-supply: Regulator node for VDD
Optional properties:
+- vdd-supply: Regulator node for VDD
- vdda-supply: Regulator node for VDDA
- vdds-supply: Regulator node for VDDS
- silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
@@ -60,7 +59,14 @@
be initialized, and always performs the soft-reset routine. Since this will
temporarily stop all output clocks, don't do this if the chip is generating
the CPU clock for example.
+- silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
+ in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
- interrupts: Interrupt for INTRb pin.
+- silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
+ rather than 1.8V thresholds.
+- vddoX-supply (where X is an output index): Regulator node for VDDO for the
+ specified output. The driver selects the output VDD_SEL setting based on this
+ voltage.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
@@ -77,8 +83,6 @@
- reg: number of clock output.
Optional child node properties:
-- vdd-supply: Regulator node for VDD for this output. The driver selects default
- values for common-mode and amplitude based on the voltage.
- silabs,format: Output format, one of:
1 = differential (defaults to LVDS levels)
2 = low-power (defaults to HCSL levels)
diff --git a/Bindings/clock/sprd,sc9863a-clk.yaml b/Bindings/clock/sprd,sc9863a-clk.yaml
index 4069e09..47e1ab0 100644
--- a/Bindings/clock/sprd,sc9863a-clk.yaml
+++ b/Bindings/clock/sprd,sc9863a-clk.yaml
@@ -40,7 +40,6 @@
clock-names:
minItems: 1
- maxItems: 4
items:
- const: ext-26m
- const: ext-32k
diff --git a/Bindings/clock/st,stm32mp1-rcc.yaml b/Bindings/clock/st,stm32mp1-rcc.yaml
index 4e38550..8b1ecb2 100644
--- a/Bindings/clock/st,stm32mp1-rcc.yaml
+++ b/Bindings/clock/st,stm32mp1-rcc.yaml
@@ -54,7 +54,9 @@
compatible:
items:
- - const: st,stm32mp1-rcc
+ - enum:
+ - st,stm32mp1-rcc-secure
+ - st,stm32mp1-rcc
- const: syscon
reg:
@@ -71,7 +73,7 @@
examples:
- |
rcc: rcc@50000000 {
- compatible = "st,stm32mp1-rcc", "syscon";
+ compatible = "st,stm32mp1-rcc-secure", "syscon";
reg = <0x50000000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/Bindings/clock/st/st,clkgen-pll.txt b/Bindings/clock/st/st,clkgen-pll.txt
index f207053..d0fa1e0 100644
--- a/Bindings/clock/st/st,clkgen-pll.txt
+++ b/Bindings/clock/st/st,clkgen-pll.txt
@@ -10,7 +10,10 @@
- compatible : shall be:
"st,clkgen-pll0"
+ "st,clkgen-pll0-a0"
+ "st,clkgen-pll0-c0"
"st,clkgen-pll1"
+ "st,clkgen-pll1-c0"
"st,stih407-clkgen-plla9"
"st,stih418-clkgen-plla9"
diff --git a/Bindings/clock/st/st,flexgen.txt b/Bindings/clock/st/st,flexgen.txt
index 7ff77fc..55a1893 100644
--- a/Bindings/clock/st/st,flexgen.txt
+++ b/Bindings/clock/st/st,flexgen.txt
@@ -64,6 +64,16 @@
audio use case)
"st,flexgen-video", "st,flexgen" (enable clock propagation on parent
and activate synchronous mode)
+ "st,flexgen-stih407-a0"
+ "st,flexgen-stih410-a0"
+ "st,flexgen-stih407-c0"
+ "st,flexgen-stih410-c0"
+ "st,flexgen-stih418-c0"
+ "st,flexgen-stih407-d0"
+ "st,flexgen-stih410-d0"
+ "st,flexgen-stih407-d2"
+ "st,flexgen-stih418-d2"
+ "st,flexgen-stih407-d3"
- #clock-cells : from common clock binding; shall be set to 1 (multiple clock
outputs).
diff --git a/Bindings/clock/st/st,quadfs.txt b/Bindings/clock/st/st,quadfs.txt
index d93d493..c4ba2ad 100644
--- a/Bindings/clock/st/st,quadfs.txt
+++ b/Bindings/clock/st/st,quadfs.txt
@@ -12,6 +12,9 @@
Required properties:
- compatible : shall be:
"st,quadfs"
+ "st,quadfs-d0"
+ "st,quadfs-d2"
+ "st,quadfs-d3"
"st,quadfs-pll"
diff --git a/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml b/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
index 6b419a9..9b537bc 100644
--- a/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
+++ b/Bindings/clock/ti,am654-ehrpwm-tbclk.yaml
@@ -12,7 +12,9 @@
properties:
compatible:
items:
- - const: ti,am654-ehrpwm-tbclk
+ - enum:
+ - ti,am654-ehrpwm-tbclk
+ - ti,am64-epwm-tbclk
- const: syscon
"#clock-cells":
diff --git a/Bindings/clock/ti,lmk04832.yaml b/Bindings/clock/ti,lmk04832.yaml
new file mode 100644
index 0000000..bd81738
--- /dev/null
+++ b/Bindings/clock/ti,lmk04832.yaml
@@ -0,0 +1,209 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti,lmk04832.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Clock bindings for the Texas Instruments LMK04832
+
+maintainers:
+ - Liam Beguin <liambeguin@gmail.com>
+
+description: |
+ Devicetree binding for the LMK04832, a clock conditioner with JEDEC JESD204B
+ support. The LMK04832 is pin compatible with the LMK0482x family.
+
+ Link to datasheet, https://www.ti.com/lit/ds/symlink/lmk04832.pdf
+
+properties:
+ compatible:
+ enum:
+ - ti,lmk04832
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#clock-cells':
+ const: 1
+
+ spi-max-frequency:
+ maximum: 5000000
+
+ clocks:
+ items:
+ - description: PLL2 reference clock.
+
+ clock-names:
+ items:
+ - const: oscin
+
+ reset-gpios:
+ maxItems: 1
+
+ ti,spi-4wire-rdbk:
+ description: |
+ Select SPI 4wire readback pin configuration.
+ Available readback pins are,
+ CLKin_SEL0 0
+ CLKin_SEL1 1
+ RESET 2
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ default: 1
+
+ ti,vco-hz:
+ description: Optional to set VCO frequency of the PLL in Hertz.
+
+ ti,sysref-ddly:
+ description: SYSREF digital delay value.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 8
+ maximum: 8191
+ default: 8
+
+ ti,sysref-mux:
+ description: |
+ SYSREF Mux configuration.
+ Available options are,
+ Normal SYNC 0
+ Re-clocked 1
+ SYSREF Pulser 2
+ SYSREF Continuous 3
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ default: 3
+
+ ti,sync-mode:
+ description: SYNC pin configuration.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2]
+ default: 1
+
+ ti,sysref-pulse-count:
+ description:
+ Number of SYSREF pulses to send when SYSREF is not in continuous mode.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 4, 8]
+ default: 4
+
+patternProperties:
+ "@[0-9a-d]+$":
+ type: object
+ description:
+ Child nodes used to configure output clocks.
+
+ properties:
+ reg:
+ description:
+ clock output identifier.
+ minimum: 0
+ maximum: 13
+
+ ti,clkout-fmt:
+ description:
+ Clock output format.
+ Available options are,
+ Powerdown 0x00
+ LVDS 0x01
+ HSDS 6 mA 0x02
+ HSDS 8 mA 0x03
+ LVPECL 1600 mV 0x04
+ LVPECL 2000 mV 0x05
+ LCPECL 0x06
+ CML 16 mA 0x07
+ CML 24 mA 0x08
+ CML 32 mA 0x09
+ CMOS (Off/Inverted) 0x0a
+ CMOS (Normal/Off) 0x0b
+ CMOS (Inverted/Inverted) 0x0c
+ CMOS (Inverted/Normal) 0x0d
+ CMOS (Normal/Inverted) 0x0e
+ CMOS (Normal/Normal) 0x0f
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+
+ ti,clkout-sysref:
+ description:
+ Select SYSREF clock path for output clock.
+ type: boolean
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clocks {
+ lmk04832_oscin: oscin {
+ compatible = "fixed-clock";
+
+ #clock-cells = <0>;
+ clock-frequency = <122880000>;
+ clock-output-names = "lmk04832-oscin";
+ };
+ };
+
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lmk04832: clock-controller@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+
+ compatible = "ti,lmk04832";
+ spi-max-frequency = <781250>;
+
+ reset-gpios = <&gpio_lmk 0 0 0>;
+
+ #clock-cells = <1>;
+ clocks = <&lmk04832_oscin>;
+ clock-names = "oscin";
+
+ ti,spi-4wire-rdbk = <0>;
+ ti,vco-hz = <2457600000>;
+
+ assigned-clocks =
+ <&lmk04832 0>, <&lmk04832 1>,
+ <&lmk04832 2>, <&lmk04832 3>,
+ <&lmk04832 4>,
+ <&lmk04832 6>, <&lmk04832 7>,
+ <&lmk04832 10>, <&lmk04832 11>;
+ assigned-clock-rates =
+ <122880000>, <384000>,
+ <122880000>, <384000>,
+ <122880000>,
+ <153600000>, <384000>,
+ <614400000>, <384000>;
+
+ clkout0@0 {
+ reg = <0>;
+ ti,clkout-fmt = <0x01>; // LVDS
+ };
+
+ clkout1@1 {
+ reg = <1>;
+ ti,clkout-fmt = <0x01>; // LVDS
+ ti,clkout-sysref;
+ };
+ };
+ };
diff --git a/Bindings/clock/ti,sci-clk.txt b/Bindings/clock/ti,sci-clk.txt
deleted file mode 100644
index 4e59dc6..0000000
--- a/Bindings/clock/ti,sci-clk.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Texas Instruments TI-SCI Clocks
-===============================
-
-All clocks on Texas Instruments' SoCs that contain a System Controller,
-are only controlled by this entity. Communication between a host processor
-running an OS and the System Controller happens through a protocol known
-as TI-SCI[1]. This clock implementation plugs into the common clock
-framework and makes use of the TI-SCI protocol on clock API requests.
-
-[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
-
-Required properties:
--------------------
-- compatible: Must be "ti,k2g-sci-clk"
-- #clock-cells: Shall be 2.
- In clock consumers, this cell represents the device ID and clock ID
- exposed by the PM firmware. The list of valid values for the device IDs
- and clocks IDs for 66AK2G SoC are documented at
- http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
-
-Examples:
---------
-
-pmmc: pmmc {
- compatible = "ti,k2g-sci";
-
- k2g_clks: clocks {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-};
-
-uart0: serial@2530c00 {
- compatible = "ns16550a";
- clocks = <&k2g_clks 0x2c 0>;
-};
diff --git a/Bindings/clock/ti,sci-clk.yaml b/Bindings/clock/ti,sci-clk.yaml
new file mode 100644
index 0000000..0e37028
--- /dev/null
+++ b/Bindings/clock/ti,sci-clk.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI clock controller node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Some TI SoCs contain a system controller (like the Power Management Micro
+ Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+ the state of the various hardware modules present on the SoC. Communication
+ between the host processor running an OS and the system controller happens
+ through a protocol called TI System Control Interface (TI-SCI protocol).
+
+ This clock controller node uses the TI SCI protocol to perform various clock
+ management of various hardware modules (devices) present on the SoC. This
+ node must be a child node of the associated TI-SCI system controller node.
+
+properties:
+ $nodename:
+ pattern: "^clock-controller$"
+
+ compatible:
+ const: ti,k2g-sci-clk
+
+ "#clock-cells":
+ const: 2
+ description:
+ The two cells represent values that the TI-SCI controller defines.
+
+ The first cell should contain the device ID.
+
+ The second cell should contain the clock ID.
+
+ Please see http://processors.wiki.ti.com/index.php/TISCI for
+ protocol documentation for the values to be used for different devices.
+
+additionalProperties: false
+
+examples:
+ - |
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
diff --git a/Bindings/clock/ti/dpll.txt b/Bindings/clock/ti/dpll.txt
index df57009..37a7cb6 100644
--- a/Bindings/clock/ti/dpll.txt
+++ b/Bindings/clock/ti/dpll.txt
@@ -42,6 +42,11 @@
"idlest" - contains the idle status register base address
"mult-div1" - contains the multiplier / divider register base address
"autoidle" - contains the autoidle register base address (optional)
+ "ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
+ the frequency spreading register base address (optional)
+ "ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
+ the modulation frequency register base address
+ (optional)
ti,am3-* dpll types do not have autoidle register
ti,omap2-* dpll type does not support idlest / autoidle registers
@@ -51,6 +56,14 @@
- ti,low-power-stop : DPLL supports low power stop mode, gating output
- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
- ti,lock : DPLL locks in programmed rate
+ - ti,min-div : the minimum divisor to start from to round the DPLL
+ target rate
+ - ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
+ spreading in permille (10th of a percent)
+ - ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
+ spectrum modulation frequency
+ - ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
+ to enable the downspread feature
Examples:
dpll_core_ck: dpll_core_ck@44e00490 {
@@ -83,3 +96,10 @@
clocks = <&sys_ck>, <&sys_ck>;
reg = <0x0500>, <0x0540>;
};
+
+ dpll_disp_ck: dpll_disp_ck {
+ #clock-cells = <0>;
+ compatible = "ti,am3-dpll-no-gate-clock";
+ clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+ reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
+ };
diff --git a/Bindings/cpufreq/cpufreq-mediatek.txt b/Bindings/cpufreq/cpufreq-mediatek.txt
index ea4994b..ef68711 100644
--- a/Bindings/cpufreq/cpufreq-mediatek.txt
+++ b/Bindings/cpufreq/cpufreq-mediatek.txt
@@ -202,11 +202,11 @@
cpu2: cpu@100 {
device_type = "cpu";
- compatible = "arm,cortex-a57";
+ compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;
@@ -214,11 +214,11 @@
cpu3: cpu@101 {
device_type = "cpu";
- compatible = "arm,cortex-a57";
+ compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
- clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ clocks = <&infracfg CLK_INFRA_CA72SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cpu_opp_table_b>;
diff --git a/Bindings/crypto/allwinner,sun8i-ce.yaml b/Bindings/crypto/allwinner,sun8i-ce.yaml
index 6ab07eb..00648f9 100644
--- a/Bindings/crypto/allwinner,sun8i-ce.yaml
+++ b/Bindings/crypto/allwinner,sun8i-ce.yaml
@@ -30,7 +30,6 @@
- description: Module clock
- description: MBus clock
minItems: 2
- maxItems: 3
clock-names:
items:
@@ -38,7 +37,6 @@
- const: mod
- const: ram
minItems: 2
- maxItems: 3
resets:
maxItems: 1
diff --git a/Bindings/crypto/arm,cryptocell.yaml b/Bindings/crypto/arm,cryptocell.yaml
new file mode 100644
index 0000000..9c97874
--- /dev/null
+++ b/Bindings/crypto/arm,cryptocell.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/arm,cryptocell.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm TrustZone CryptoCell cryptographic engine
+
+maintainers:
+ - Gilad Ben-Yossef <gilad@benyossef.com>
+
+properties:
+ compatible:
+ enum:
+ - arm,cryptocell-713-ree
+ - arm,cryptocell-703-ree
+ - arm,cryptocell-712-ree
+ - arm,cryptocell-710-ree
+ - arm,cryptocell-630p-ree
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ arm_cc712: crypto@80000000 {
+ compatible = "arm,cryptocell-712-ree";
+ reg = <0x80000000 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/Bindings/crypto/arm-cryptocell.txt b/Bindings/crypto/arm-cryptocell.txt
deleted file mode 100644
index 6130e6e..0000000
--- a/Bindings/crypto/arm-cryptocell.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Arm TrustZone CryptoCell cryptographic engine
-
-Required properties:
-- compatible: Should be one of -
- "arm,cryptocell-713-ree"
- "arm,cryptocell-703-ree"
- "arm,cryptocell-712-ree"
- "arm,cryptocell-710-ree"
- "arm,cryptocell-630p-ree"
-- reg: Base physical address of the engine and length of memory mapped region.
-- interrupts: Interrupt number for the device.
-
-Optional properties:
-- clocks: Reference to the crypto engine clock.
-- dma-coherent: Present if dma operations are coherent.
-
-Examples:
-
- arm_cc712: crypto@80000000 {
- compatible = "arm,cryptocell-712-ree";
- interrupt-parent = <&intc>;
- interrupts = < 0 30 4 >;
- reg = < 0x80000000 0x10000 >;
-
- };
diff --git a/Bindings/crypto/cortina,sl3516-crypto.yaml b/Bindings/crypto/cortina,sl3516-crypto.yaml
new file mode 100644
index 0000000..b633b8d
--- /dev/null
+++ b/Bindings/crypto/cortina,sl3516-crypto.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/cortina,sl3516-crypto.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SL3516 cryptographic offloader driver
+
+maintainers:
+ - Corentin Labbe <clabbe@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - cortina,sl3516-crypto
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/clock/cortina,gemini-clock.h>
+ #include <dt-bindings/reset/cortina,gemini-reset.h>
+
+ crypto@62000000 {
+ compatible = "cortina,sl3516-crypto";
+ reg = <0x62000000 0x10000>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon GEMINI_RESET_SECURITY>;
+ clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
+ };
diff --git a/Bindings/crypto/fsl-dcp.yaml b/Bindings/crypto/fsl-dcp.yaml
index a30bf38..99be015 100644
--- a/Bindings/crypto/fsl-dcp.yaml
+++ b/Bindings/crypto/fsl-dcp.yaml
@@ -27,7 +27,6 @@
- description: MXS DCP DCP interrupt
- description: MXS DCP secure interrupt
minItems: 2
- maxItems: 3
clocks:
maxItems: 1
diff --git a/Bindings/crypto/intel,ixp4xx-crypto.yaml b/Bindings/crypto/intel,ixp4xx-crypto.yaml
new file mode 100644
index 0000000..9c53c27
--- /dev/null
+++ b/Bindings/crypto/intel,ixp4xx-crypto.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2018 Linaro Ltd.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel IXP4xx cryptographic engine
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
+ (Network Processing Engine). Since it is not a device on its own
+ it is defined as a subnode of the NPE, if crypto support is
+ available on the platform.
+
+properties:
+ compatible:
+ const: intel,ixp4xx-crypto
+
+ intel,npe-handle:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: phandle to the NPE this crypto engine is using, the cell
+ describing the NPE instance to be used.
+
+ queue-rx:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ description: phandle to the RX queue on the NPE, the cell describing
+ the queue instance to be used.
+
+ queue-txready:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+ description: phandle to the TX READY queue on the NPE, the cell describing
+ the queue instance to be used.
+
+required:
+ - compatible
+ - intel,npe-handle
+ - queue-rx
+ - queue-txready
+
+additionalProperties: false
diff --git a/Bindings/devfreq/nvidia,tegra30-actmon.yaml b/Bindings/devfreq/nvidia,tegra30-actmon.yaml
new file mode 100644
index 0000000..e3379d1
--- /dev/null
+++ b/Bindings/devfreq/nvidia,tegra30-actmon.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/nvidia,tegra30-actmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra30 Activity Monitor
+
+maintainers:
+ - Dmitry Osipenko <digetx@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The activity monitor block collects statistics about the behaviour of other
+ components in the system. This information can be used to derive the rate at
+ which the external memory needs to be clocked in order to serve all requests
+ from the monitored clients.
+
+properties:
+ compatible:
+ enum:
+ - nvidia,tegra30-actmon
+ - nvidia,tegra114-actmon
+ - nvidia,tegra124-actmon
+ - nvidia,tegra210-actmon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: actmon
+ - const: emc
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: actmon
+
+ interrupts:
+ maxItems: 1
+
+ interconnects:
+ minItems: 1
+ maxItems: 12
+
+ interconnect-names:
+ minItems: 1
+ maxItems: 12
+ description:
+ Should include name of the interconnect path for each interconnect
+ entry. Consult TRM documentation for information about available
+ memory clients, see MEMORY CONTROLLER and ACTIVITY MONITOR sections.
+
+ operating-points-v2:
+ description:
+ Should contain freqs and voltages and opp-supported-hw property, which
+ is a bitfield indicating SoC speedo ID mask.
+
+ "#cooling-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - interrupts
+ - interconnects
+ - interconnect-names
+ - operating-points-v2
+ - "#cooling-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/memory/tegra30-mc.h>
+
+ mc: memory-controller@7000f000 {
+ compatible = "nvidia,tegra30-mc";
+ reg = <0x7000f000 0x400>;
+ clocks = <&clk 32>;
+ clock-names = "mc";
+
+ interrupts = <0 77 4>;
+
+ #iommu-cells = <1>;
+ #reset-cells = <1>;
+ #interconnect-cells = <1>;
+ };
+
+ emc: external-memory-controller@7000f400 {
+ compatible = "nvidia,tegra30-emc";
+ reg = <0x7000f400 0x400>;
+ interrupts = <0 78 4>;
+ clocks = <&clk 57>;
+
+ nvidia,memory-controller = <&mc>;
+ operating-points-v2 = <&dvfs_opp_table>;
+ power-domains = <&domain>;
+
+ #interconnect-cells = <0>;
+ };
+
+ actmon@6000c800 {
+ compatible = "nvidia,tegra30-actmon";
+ reg = <0x6000c800 0x400>;
+ interrupts = <0 45 4>;
+ clocks = <&clk 119>, <&clk 57>;
+ clock-names = "actmon", "emc";
+ resets = <&rst 119>;
+ reset-names = "actmon";
+ operating-points-v2 = <&dvfs_opp_table>;
+ interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
+ interconnect-names = "cpu-read";
+ #cooling-cells = <2>;
+ };
diff --git a/Bindings/display/allwinner,sun4i-a10-display-backend.yaml b/Bindings/display/allwinner,sun4i-a10-display-backend.yaml
index 12a7df0..3d8ea3c 100644
--- a/Bindings/display/allwinner,sun4i-a10-display-backend.yaml
+++ b/Bindings/display/allwinner,sun4i-a10-display-backend.yaml
@@ -26,14 +26,12 @@
reg:
minItems: 1
- maxItems: 2
items:
- description: Display Backend registers
- description: SAT registers
reg-names:
minItems: 1
- maxItems: 2
items:
- const: be
- const: sat
@@ -43,7 +41,6 @@
clocks:
minItems: 3
- maxItems: 4
items:
- description: The backend interface clock
- description: The backend module clock
@@ -52,7 +49,6 @@
clock-names:
minItems: 3
- maxItems: 4
items:
- const: ahb
- const: mod
@@ -61,14 +57,12 @@
resets:
minItems: 1
- maxItems: 2
items:
- description: The Backend reset line
- description: The SAT reset line
reset-names:
minItems: 1
- maxItems: 2
items:
- const: be
- const: sat
diff --git a/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
index a738d7c..bf0bdf5 100644
--- a/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
+++ b/Bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
@@ -24,7 +24,6 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: Bus Clock
- description: Module Clock
diff --git a/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
index 907fb47..5d42d36 100644
--- a/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
+++ b/Bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
@@ -46,7 +46,6 @@
clocks:
minItems: 3
- maxItems: 6
items:
- description: Bus Clock
- description: Register Clock
@@ -57,7 +56,6 @@
clock-names:
minItems: 3
- maxItems: 6
items:
- const: iahb
- const: isfr
@@ -68,14 +66,12 @@
resets:
minItems: 1
- maxItems: 2
items:
- description: HDMI Controller Reset
- description: HDCP Reset
reset-names:
minItems: 1
- maxItems: 2
items:
- const: ctrl
- const: hdcp
diff --git a/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml b/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
index 501cec1..a97366a 100644
--- a/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
+++ b/Bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
@@ -27,7 +27,6 @@
clocks:
minItems: 2
- maxItems: 4
items:
- description: Bus Clock
- description: Module Clock
@@ -36,7 +35,6 @@
clock-names:
minItems: 2
- maxItems: 4
items:
- const: bus
- const: mod
diff --git a/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml
index ec21e8b..61ef7b3 100644
--- a/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml
+++ b/Bindings/display/allwinner,sun8i-r40-tcon-top.yaml
@@ -48,7 +48,6 @@
clocks:
minItems: 2
- maxItems: 6
items:
- description: The TCON TOP interface clock
- description: The TCON TOP TV0 clock
@@ -59,7 +58,6 @@
clock-names:
minItems: 2
- maxItems: 6
items:
- const: bus
- const: tcon-tv0
diff --git a/Bindings/display/brcm,bcm2835-vec.yaml b/Bindings/display/brcm,bcm2835-vec.yaml
index d900cc5..9b24081 100644
--- a/Bindings/display/brcm,bcm2835-vec.yaml
+++ b/Bindings/display/brcm,bcm2835-vec.yaml
@@ -11,7 +11,9 @@
properties:
compatible:
- const: brcm,bcm2835-vec
+ enum:
+ - brcm,bcm2711-vec
+ - brcm,bcm2835-vec
reg:
maxItems: 1
diff --git a/Bindings/display/bridge/adi,adv7511.txt b/Bindings/display/bridge/adi,adv7511.txt
deleted file mode 100644
index 659523f..0000000
--- a/Bindings/display/bridge/adi,adv7511.txt
+++ /dev/null
@@ -1,143 +0,0 @@
-Analog Devices ADV7511(W)/13/33/35 HDMI Encoders
-------------------------------------------------
-
-The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video
-transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space
-conversion, S/PDIF, CEC and HDCP. ADV7533/5 supports the DSI interface for input
-pixels, while the others support RGB interface.
-
-Required properties:
-
-- compatible: Should be one of:
- "adi,adv7511"
- "adi,adv7511w"
- "adi,adv7513"
- "adi,adv7533"
- "adi,adv7535"
-
-- reg: I2C slave addresses
- The ADV7511 internal registers are split into four pages exposed through
- different I2C addresses, creating four register maps. Each map has it own
- I2C address and acts as a standard slave device on the I2C bus. The main
- address is mandatory, others are optional and revert to defaults if not
- specified.
-
-
-The ADV7511 supports a large number of input data formats that differ by their
-color depth, color format, clock mode, bit justification and random
-arrangement of components on the data bus. The combination of the following
-properties describe the input and map directly to the video input tables of the
-ADV7511 datasheet that document all the supported combinations.
-
-- adi,input-depth: Number of bits per color component at the input (8, 10 or
- 12).
-- adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
- "yuv444".
-- adi,input-clock: The input clock type, one of "1x" (one clock cycle per
- pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
- data driven on both edges).
-
-The following input format properties are required except in "rgb 1x" and
-"yuv444 1x" modes, in which case they must not be specified.
-
-- adi,input-style: The input components arrangement variant (1, 2 or 3), as
- listed in the input format tables in the datasheet.
-- adi,input-justification: The input bit justification ("left", "evenly",
- "right").
-
-- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
-- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
-- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.
-- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V
- on the chip.
-- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
- needed only for ADV7511.
-
-The following properties are required for ADV7533 and ADV7535:
-
-- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
- be one of 1, 2, 3 or 4.
-- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.
-- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.
-- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be
- either 1.2V or 1.8V for ADV7533 but only 1.8V for ADV7535.
-
-Optional properties:
-
-- interrupts: Specifier for the ADV7511 interrupt
-- pd-gpios: Specifier for the GPIO connected to the power down signal
-
-- adi,clock-delay: Video data clock delay relative to the pixel clock, in ps
- (-1200 ps .. 1600 ps). Defaults to no delay.
-- adi,embedded-sync: The input uses synchronization signals embedded in the
- data stream (similar to BT.656). Defaults to separate H/V synchronization
- signals.
-- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the
- internal timing generator. The chip will rely on the sync signals in the
- DSI data lanes, rather than generate its own timings for HDMI output.
-- clocks: from common clock binding: reference to the CEC clock.
-- clock-names: from common clock binding: must be "cec".
-- reg-names : Names of maps with programmable addresses.
- It can contain any map needing a non-default address.
- Possible maps names are : "main", "edid", "cec", "packet"
-
-Required nodes:
-
-The ADV7511 has two video ports. Their connections are modelled using the OF
-graph bindings specified in Documentation/devicetree/bindings/graph.txt.
-
-- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533/5, the
- remote endpoint phandle should be a reference to a valid mipi_dsi_host device
- node.
-- Video port 1 for the HDMI output
-- Audio port 2 for the HDMI audio input
-
-
-Example
--------
-
- adv7511w: hdmi@39 {
- compatible = "adi,adv7511w";
- /*
- * The EDID page will be accessible on address 0x66 on the I2C
- * bus. All other maps continue to use their default addresses.
- */
- reg = <0x39>, <0x66>;
- reg-names = "main", "edid";
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
- clocks = <&cec_clock>;
- clock-names = "cec";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511w_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- codec_endpoint: endpoint {
- remote-endpoint = <&i2s0_cpu_endpoint>;
- };
- };
- };
- };
diff --git a/Bindings/display/bridge/adi,adv7511.yaml b/Bindings/display/bridge/adi,adv7511.yaml
new file mode 100644
index 0000000..d3dd7a7
--- /dev/null
+++ b/Bindings/display/bridge/adi,adv7511.yaml
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/adi,adv7511.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADV7511/11W/13 HDMI Encoders
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description: |
+ The ADV7511, ADV7511W and ADV7513 are HDMI audio and video
+ transmitters compatible with HDMI 1.4 and DVI 1.0. They support color
+ space conversion, S/PDIF, CEC and HDCP. The transmitter input is
+ parallel RGB or YUV data.
+
+properties:
+ compatible:
+ enum:
+ - adi,adv7511
+ - adi,adv7511w
+ - adi,adv7513
+
+ reg:
+ description: |
+ I2C slave addresses.
+
+ The ADV7511/11W/13 internal registers are split into four pages
+ exposed through different I2C addresses, creating four register
+ maps. Each map has it own I2C address and acts as a standard slave
+ device on the I2C bus. The main address is mandatory, others are
+ optional and revert to defaults if not specified.
+ minItems: 1
+ maxItems: 4
+
+ reg-names:
+ description:
+ Names of maps with programmable addresses. It can contain any map
+ needing a non-default address.
+ minItems: 1
+ items:
+ - const: main
+ - const: edid
+ - const: cec
+ - const: packet
+
+ clocks:
+ description: Reference to the CEC clock.
+ maxItems: 1
+
+ clock-names:
+ const: cec
+
+ interrupts:
+ maxItems: 1
+
+ pd-gpios:
+ description: GPIO connected to the power down signal.
+ maxItems: 1
+
+ avdd-supply:
+ description: A 1.8V supply that powers up the AVDD pin.
+
+ dvdd-supply:
+ description: A 1.8V supply that powers up the DVDD pin.
+
+ pvdd-supply:
+ description: A 1.8V supply that powers up the PVDD pin.
+
+ dvdd-3v-supply:
+ description: A 3.3V supply that powers up the DVDD_3V pin.
+
+ bgvdd-supply:
+ description: A 1.8V supply that powers up the BGVDD pin.
+
+ adi,input-depth:
+ description: Number of bits per color component at the input.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 8, 10, 12 ]
+
+ adi,input-colorspace:
+ description: Input color space.
+ enum: [ rgb, yuv422, yuv444 ]
+
+ adi,input-clock:
+ description: |
+ Input clock type.
+ "1x": one clock cycle per pixel
+ "2x": two clock cycles per pixel
+ "dd": one clock cycle per pixel, data driven on both edges
+ enum: [ 1x, 2x, dd ]
+
+ adi,clock-delay:
+ description:
+ Video data clock delay relative to the pixel clock, in ps
+ (-1200ps .. 1600 ps).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ adi,embedded-sync:
+ description:
+ If defined, the input uses synchronization signals embedded in the
+ data stream (similar to BT.656).
+ type: boolean
+
+ adi,input-style:
+ description:
+ Input components arrangement variant as listed in the input
+ format tables in the datasheet.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 3 ]
+
+ adi,input-justification:
+ description: Input bit justification.
+ enum: [ left, evenly, right ]
+
+ ports:
+ description:
+ The ADV7511(W)/13 has two video ports and one audio port. This node
+ models their connections as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+ type: object
+ properties:
+ port@0:
+ description: Video port for the RGB or YUV input.
+ type: object
+
+ port@1:
+ description: Video port for the HDMI output.
+ type: object
+
+ port@2:
+ description: Audio port for the HDMI output.
+ type: object
+
+# adi,input-colorspace and adi,input-clock are required except in
+# "rgb 1x" and "yuv444 1x" modes, in which case they must not be
+# specified.
+if:
+ not:
+ properties:
+ adi,input-colorspace:
+ contains:
+ enum: [ rgb, yuv444 ]
+ adi,input-clock:
+ contains:
+ const: 1x
+
+then:
+ required:
+ - adi,input-style
+ - adi,input-justification
+
+else:
+ properties:
+ adi,input-style: false
+ adi,input-justification: false
+
+
+required:
+ - compatible
+ - reg
+ - ports
+ - adi,input-depth
+ - adi,input-colorspace
+ - adi,input-clock
+ - avdd-supply
+ - dvdd-supply
+ - pvdd-supply
+ - dvdd-3v-supply
+ - bgvdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xe6500000>;
+
+ adv7511w: hdmi@39 {
+ compatible = "adi,adv7511w";
+ /*
+ * The EDID page will be accessible on address 0x66 on the I2C
+ * bus. All other maps continue to use their default addresses.
+ */
+ reg = <0x39>, <0x66>;
+ reg-names = "main", "edid";
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+ avdd-supply = <&v1v8>;
+ dvdd-supply = <&v1v8>;
+ pvdd-supply = <&v1v8>;
+ dvdd-3v-supply = <&v3v3>;
+ bgvdd-supply = <&v1v8>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "yuv422";
+ adi,input-clock = "1x";
+
+ adi,input-style = <3>;
+ adi,input-justification = "right";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511w_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ codec_endpoint: endpoint {
+ remote-endpoint = <&i2s0_cpu_endpoint>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/bridge/adi,adv7533.yaml b/Bindings/display/bridge/adi,adv7533.yaml
new file mode 100644
index 0000000..f362091
--- /dev/null
+++ b/Bindings/display/bridge/adi,adv7533.yaml
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/adi,adv7533.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADV7533/35 HDMI Encoders
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description: |
+ The ADV7533 and ADV7535 are HDMI audio and video transmitters
+ compatible with HDMI 1.4 and DVI 1.0. They support color space
+ conversion, S/PDIF, CEC and HDCP. The transmitter input is MIPI DSI.
+
+properties:
+ compatible:
+ enum:
+ - adi,adv7533
+ - adi,adv7535
+
+ reg:
+ description: |
+ I2C slave addresses.
+
+ The ADV7533/35 internal registers are split into four pages
+ exposed through different I2C addresses, creating four register
+ maps. Each map has it own I2C address and acts as a standard slave
+ device on the I2C bus. The main address is mandatory, others are
+ optional and revert to defaults if not specified.
+ minItems: 1
+ maxItems: 4
+
+ reg-names:
+ description:
+ Names of maps with programmable addresses. It can contain any map
+ needing a non-default address.
+ minItems: 1
+ items:
+ - const: main
+ - const: edid
+ - const: cec
+ - const: packet
+
+ clocks:
+ description: Reference to the CEC clock.
+ maxItems: 1
+
+ clock-names:
+ const: cec
+
+ interrupts:
+ maxItems: 1
+
+ pd-gpios:
+ description: GPIO connected to the power down signal.
+ maxItems: 1
+
+ avdd-supply:
+ description: A 1.8V supply that powers up the AVDD pin.
+
+ dvdd-supply:
+ description: A 1.8V supply that powers up the DVDD pin.
+
+ pvdd-supply:
+ description: A 1.8V supply that powers up the PVDD pin.
+
+ a2vdd-supply:
+ description: A 1.8V supply that powers up the A2VDD pin.
+
+ v3p3-supply:
+ description: A 3.3V supply that powers up the V3P3 pin.
+
+ v1p2-supply:
+ description:
+ A supply that powers up the V1P2 pin. It can be either 1.2V
+ or 1.8V for ADV7533 but only 1.8V for ADV7535.
+
+ adi,disable-timing-generator:
+ description:
+ Disables the internal timing generator. The chip will rely on the
+ sync signals in the DSI data lanes, rather than generating its own
+ timings for HDMI output.
+ type: boolean
+
+ adi,dsi-lanes:
+ description: Number of DSI data lanes connected to the DSI host.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 3, 4 ]
+
+ ports:
+ description:
+ The ADV7533/35 has two video ports and one audio port. This node
+ models their connections as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+ type: object
+ properties:
+ port@0:
+ description:
+ Video port for the DSI input. The remote endpoint phandle
+ should be a reference to a valid mipi_dsi_host_device.
+ type: object
+
+ port@1:
+ description: Video port for the HDMI output.
+ type: object
+
+ port@2:
+ description: Audio port for the HDMI output.
+ type: object
+
+required:
+ - compatible
+ - reg
+ - ports
+ - adi,dsi-lanes
+ - avdd-supply
+ - dvdd-supply
+ - pvdd-supply
+ - a2vdd-supply
+ - v3p3-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xe6500000>;
+
+ adv7533: hdmi@39 {
+ compatible = "adi,adv7533";
+ /*
+ * The EDID page will be accessible on address 0x66 on the I2C
+ * bus. All other maps continue to use their default addresses.
+ */
+ reg = <0x39>, <0x66>;
+ reg-names = "main", "edid";
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+ adi,dsi-lanes = <4>;
+ avdd-supply = <&v1v8>;
+ dvdd-supply = <&v1v8>;
+ pvdd-supply = <&v1v8>;
+ a2vdd-supply = <&v1v8>;
+ v3p3-supply = <&v3v3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7533_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7533_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ codec_endpoint: endpoint {
+ remote-endpoint = <&i2s0_cpu_endpoint>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/bridge/cdns,mhdp8546.yaml b/Bindings/display/bridge/cdns,mhdp8546.yaml
index 6342787..b2e8bc6 100644
--- a/Bindings/display/bridge/cdns,mhdp8546.yaml
+++ b/Bindings/display/bridge/cdns,mhdp8546.yaml
@@ -18,7 +18,6 @@
reg:
minItems: 1
- maxItems: 2
items:
- description:
Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
@@ -26,13 +25,15 @@
included in the associated PHY.
- description:
Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
+ - description:
+ Register block of mhdptx sapb registers.
reg-names:
minItems: 1
- maxItems: 2
items:
- const: mhdptx
- const: j721e-intg
+ - const: mhdptx-sapb
clocks:
maxItems: 1
@@ -99,14 +100,18 @@
properties:
reg:
minItems: 2
+ maxItems: 3
reg-names:
minItems: 2
+ maxItems: 3
else:
properties:
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
reg-names:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
required:
- compatible
diff --git a/Bindings/display/bridge/google,cros-ec-anx7688.yaml b/Bindings/display/bridge/google,cros-ec-anx7688.yaml
new file mode 100644
index 0000000..9f7cc6b
--- /dev/null
+++ b/Bindings/display/bridge/google,cros-ec-anx7688.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/google,cros-ec-anx7688.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ChromeOS EC ANX7688 HDMI to DP Converter through Type-C Port
+
+maintainers:
+ - Nicolas Boichat <drinkcat@chromium.org>
+ - Enric Balletbo i Serra <enric.balletbo@collabora.com>
+
+description: |
+ ChromeOS EC ANX7688 is a display bridge that converts HDMI 2.0 to
+ DisplayPort 1.3 Ultra-HDi (4096x2160p60). It is an Analogix ANX7688 chip
+ which is connected to and operated by the ChromeOS Embedded Controller
+ (See google,cros-ec.yaml). It is accessed using I2C tunneling through
+ the EC and therefore its node should be a child of an EC I2C tunnel node
+ (See google,cros-ec-i2c-tunnel.yaml).
+
+properties:
+ compatible:
+ const: google,cros-ec-anx7688
+
+ reg:
+ maxItems: 1
+ description: I2C address of the device.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for HDMI input.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: USB Type-c connector.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c_tunnel_b: i2c-tunnel1 {
+ compatible = "google,cros-ec-i2c-tunnel";
+ google,remote-bus = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ anx7688: anx7688@2c {
+ compatible = "google,cros-ec-anx7688";
+ reg = <0x2c>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ anx7688_in: endpoint {
+ remote-endpoint = <&hdmi0_out>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ anx7688_out: endpoint {
+ remote-endpoint = <&typec_connector>;
+ };
+ };
+ };
+ };
+ };
+
diff --git a/Bindings/display/bridge/ite,it66121.yaml b/Bindings/display/bridge/ite,it66121.yaml
new file mode 100644
index 0000000..6ec1d5f
--- /dev/null
+++ b/Bindings/display/bridge/ite,it66121.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ite,it66121.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ITE it66121 HDMI bridge Device Tree Bindings
+
+maintainers:
+ - Phong LE <ple@baylibre.com>
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+description: |
+ The IT66121 is a high-performance and low-power single channel HDMI
+ transmitter, fully compliant with HDMI 1.3a, HDCP 1.2 and backward compatible
+ to DVI 1.0 specifications.
+
+properties:
+ compatible:
+ const: ite,it66121
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to active low reset
+
+ vrf12-supply:
+ description: Regulator for 1.2V analog core power.
+
+ vcn33-supply:
+ description: Regulator for 3.3V digital core power.
+
+ vcn18-supply:
+ description: Regulator for 1.8V IO core power.
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: DPI input port.
+
+ properties:
+ endpoint:
+ $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ unevaluatedProperties: false
+
+ properties:
+ bus-width:
+ description:
+ Endpoint bus width.
+ enum:
+ - 12 # 12 data lines connected and dual-edge mode
+ - 24 # 24 data lines connected and single-edge mode
+ default: 24
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: HDMI Connector port.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vrf12-supply
+ - vcn33-supply
+ - vcn18-supply
+ - interrupts
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ it66121hdmitx: hdmitx@4c {
+ compatible = "ite,it66121";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ite_pins_default>;
+ vcn33-supply = <&mt6358_vcn33_wifi_reg>;
+ vcn18-supply = <&mt6358_vcn18_reg>;
+ vrf12-supply = <&mt6358_vrf12_reg>;
+ reset-gpios = <&pio 160 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&pio>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
+ reg = <0x4c>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ it66121_in: endpoint {
+ bus-width = <12>;
+ remote-endpoint = <&display_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ hdmi_conn_out: endpoint {
+ remote-endpoint = <&hdmi_conn_in>;
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/bridge/lontium,lt8912b.yaml b/Bindings/display/bridge/lontium,lt8912b.yaml
index 735d023..674891e 100644
--- a/Bindings/display/bridge/lontium,lt8912b.yaml
+++ b/Bindings/display/bridge/lontium,lt8912b.yaml
@@ -29,7 +29,8 @@
properties:
port@0:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
description:
Primary MIPI port for MIPI input
diff --git a/Bindings/display/bridge/ti,sn65dsi83.yaml b/Bindings/display/bridge/ti,sn65dsi83.yaml
new file mode 100644
index 0000000..d101233
--- /dev/null
+++ b/Bindings/display/bridge/ti,sn65dsi83.yaml
@@ -0,0 +1,159 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+description: |
+ Texas Instruments SN65DSI83 1x Single-link MIPI DSI
+ to 1x Single-link LVDS
+ https://www.ti.com/lit/gpn/sn65dsi83
+ Texas Instruments SN65DSI84 1x Single-link MIPI DSI
+ to 1x Dual-link or 2x Single-link LVDS
+ https://www.ti.com/lit/gpn/sn65dsi84
+
+properties:
+ compatible:
+ enum:
+ - ti,sn65dsi83
+ - ti,sn65dsi84
+
+ reg:
+ enum:
+ - 0x2c
+ - 0x2d
+
+ enable-gpios:
+ maxItems: 1
+ description: GPIO specifier for bridge_en pin (active high).
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for MIPI DSI Channel-A input
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ description: array of physical DSI data lane indexes.
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for MIPI DSI Channel-B input
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ description: array of physical DSI data lane indexes.
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for LVDS Channel-A output (panel or bridge).
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for LVDS Channel-B output (panel or bridge).
+
+ required:
+ - port@0
+ - port@2
+
+required:
+ - compatible
+ - reg
+ - enable-gpios
+ - ports
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,sn65dsi83
+ then:
+ properties:
+ ports:
+ properties:
+ port@1: false
+ port@3: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,sn65dsi84
+ then:
+ properties:
+ ports:
+ properties:
+ port@1: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@2d {
+ compatible = "ti,sn65dsi83";
+ reg = <0x2d>;
+
+ enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ endpoint {
+ remote-endpoint = <&dsi0_out>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/faraday,tve200.txt b/Bindings/display/faraday,tve200.txt
deleted file mode 100644
index 82e3bc0..0000000
--- a/Bindings/display/faraday,tve200.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-* Faraday TV Encoder TVE200
-
-Required properties:
-
-- compatible: must be one of:
- "faraday,tve200"
- "cortina,gemini-tvc", "faraday,tve200"
-
-- reg: base address and size of the control registers block
-
-- interrupts: contains an interrupt specifier for the interrupt
- line from the TVE200
-
-- clock-names: should contain "PCLK" for the clock line clocking the
- silicon and "TVE" for the 27MHz clock to the video driver
-
-- clocks: contains phandle and clock specifier pairs for the entries
- in the clock-names property. See
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Optional properties:
-
-- resets: contains the reset line phandle for the block
-
-Required sub-nodes:
-
-- port: describes LCD panel signals, following the common binding
- for video transmitter interfaces; see
- Documentation/devicetree/bindings/media/video-interfaces.txt
- This port should have the properties:
- reg = <0>;
- It should have one endpoint connected to a remote endpoint where
- the display is connected.
-
-Example:
-
-display-controller@6a000000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "faraday,tve200";
- reg = <0x6a000000 0x1000>;
- interrupts = <13 IRQ_TYPE_EDGE_RISING>;
- resets = <&syscon GEMINI_RESET_TVC>;
- clocks = <&syscon GEMINI_CLK_GATE_TVC>,
- <&syscon GEMINI_CLK_TVC>;
- clock-names = "PCLK", "TVE";
-
- port@0 {
- reg = <0>;
- display_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
diff --git a/Bindings/display/faraday,tve200.yaml b/Bindings/display/faraday,tve200.yaml
new file mode 100644
index 0000000..e2ee777
--- /dev/null
+++ b/Bindings/display/faraday,tve200.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/faraday,tve200.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Faraday TV Encoder TVE200
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+ compatible:
+ oneOf:
+ - const: faraday,tve200
+ - items:
+ - const: cortina,gemini-tvc
+ - const: faraday,tve200
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: PCLK
+ - const: TVE
+
+ clocks:
+ minItems: 2
+
+ resets:
+ minItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clock-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/cortina,gemini-clock.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/reset/cortina,gemini-reset.h>
+ display-controller@6a000000 {
+ compatible = "faraday,tve200";
+ reg = <0x6a000000 0x1000>;
+ interrupts = <13 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon GEMINI_RESET_TVC>;
+ clocks = <&syscon GEMINI_CLK_GATE_TVC>,
+ <&syscon GEMINI_CLK_TVC>;
+ clock-names = "PCLK", "TVE";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
diff --git a/Bindings/display/mediatek/mediatek,cec.yaml b/Bindings/display/mediatek/mediatek,cec.yaml
new file mode 100644
index 0000000..66288b9
--- /dev/null
+++ b/Bindings/display/mediatek/mediatek,cec.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,cec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI CEC Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+
+description: |
+ The HDMI CEC controller handles hotplug detection and CEC communication.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7623-cec
+ - mediatek,mt8167-cec
+ - mediatek,mt8173-cec
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ cec: cec@10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0x10013000 0xbc>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ };
+
+...
diff --git a/Bindings/display/mediatek/mediatek,hdmi-ddc.yaml b/Bindings/display/mediatek/mediatek,hdmi-ddc.yaml
new file mode 100644
index 0000000..b6fcdfb
--- /dev/null
+++ b/Bindings/display/mediatek/mediatek,hdmi-ddc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi-ddc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI DDC Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+
+description: |
+ The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt7623-hdmi-ddc
+ - mediatek,mt8167-hdmi-ddc
+ - mediatek,mt8173-hdmi-ddc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ddc-i2c
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ hdmi_ddc0: i2c@11012000 {
+ compatible = "mediatek,mt8173-hdmi-ddc";
+ reg = <0x11012000 0x1c>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_I2C5>;
+ clock-names = "ddc-i2c";
+ };
+
+...
diff --git a/Bindings/display/mediatek/mediatek,hdmi.txt b/Bindings/display/mediatek/mediatek,hdmi.txt
deleted file mode 100644
index b284ca5..0000000
--- a/Bindings/display/mediatek/mediatek,hdmi.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-Mediatek HDMI Encoder
-=====================
-
-The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
-its parallel input.
-
-Required properties:
-- compatible: Should be "mediatek,<chip>-hdmi".
-- the supported chips are mt2701, mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
-- clock-names: must contain "pixel", "pll", "bclk", and "spdif".
-- phys: phandle link to the HDMI PHY node.
- See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
-- phy-names: must contain "hdmi"
-- mediatek,syscon-hdmi: phandle link and register offset to the system
- configuration registers. For mt8173 this must be offset 0x900 into the
- MMSYS_CONFIG region: <&mmsys 0x900>.
-- ports: A node containing input and output port nodes with endpoint
- definitions as documented in Documentation/devicetree/bindings/graph.txt.
-- port@0: The input port in the ports node should be connected to a DPI output
- port.
-- port@1: The output port in the ports node should be connected to the input
- port of a connector node that contains a ddc-i2c-bus property, or to the
- input port of an attached bridge chip, such as a SlimPort transmitter.
-
-HDMI CEC
-========
-
-The HDMI CEC controller handles hotplug detection and CEC communication.
-
-Required properties:
-- compatible: Should be "mediatek,<chip>-cec"
-- the supported chips are mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- interrupts: The interrupt signal from the function block.
-- clocks: device clock
-
-HDMI DDC
-========
-
-The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
-The Mediatek's I2C controller is used to interface with I2C devices.
-
-Required properties:
-- compatible: Should be "mediatek,<chip>-hdmi-ddc"
-- the supported chips are mt7623 and mt8173
-- reg: Physical base address and length of the controller's registers
-- clocks: device clock
-- clock-names: Should be "ddc-i2c".
-
-HDMI PHY
-========
-See phy/mediatek,hdmi-phy.yaml
-
-Example:
-
-cec: cec@10013000 {
- compatible = "mediatek,mt8173-cec";
- reg = <0 0x10013000 0 0xbc>;
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_CEC>;
-};
-
-hdmi_phy: hdmi-phy@10209100 {
- compatible = "mediatek,mt8173-hdmi-phy";
- reg = <0 0x10209100 0 0x24>;
- clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
- clock-names = "pll_ref";
- clock-output-names = "hdmitx_dig_cts";
- mediatek,ibias = <0xa>;
- mediatek,ibias_up = <0x1c>;
- #clock-cells = <0>;
- #phy-cells = <0>;
-};
-
-hdmi_ddc0: i2c@11012000 {
- compatible = "mediatek,mt8173-hdmi-ddc";
- reg = <0 0x11012000 0 0x1c>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_I2C5>;
- clock-names = "ddc-i2c";
-};
-
-hdmi0: hdmi@14025000 {
- compatible = "mediatek,mt8173-hdmi";
- reg = <0 0x14025000 0 0x400>;
- interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
- <&mmsys CLK_MM_HDMI_PLLCK>,
- <&mmsys CLK_MM_HDMI_AUDIO>,
- <&mmsys CLK_MM_HDMI_SPDIF>;
- clock-names = "pixel", "pll", "bclk", "spdif";
- pinctrl-names = "default";
- pinctrl-0 = <&hdmi_pin>;
- phys = <&hdmi_phy>;
- phy-names = "hdmi";
- mediatek,syscon-hdmi = <&mmsys 0x900>;
- assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
- assigned-clock-parents = <&hdmi_phy>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- hdmi0_in: endpoint {
- remote-endpoint = <&dpi0_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- hdmi0_out: endpoint {
- remote-endpoint = <&hdmi_con_in>;
- };
- };
- };
-};
-
-connector {
- compatible = "hdmi-connector";
- type = "a";
- ddc-i2c-bus = <&hdmiddc0>;
-
- port {
- hdmi_con_in: endpoint {
- remote-endpoint = <&hdmi0_out>;
- };
- };
-};
diff --git a/Bindings/display/mediatek/mediatek,hdmi.yaml b/Bindings/display/mediatek/mediatek,hdmi.yaml
new file mode 100644
index 0000000..111967e
--- /dev/null
+++ b/Bindings/display/mediatek/mediatek,hdmi.yaml
@@ -0,0 +1,133 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek HDMI Encoder Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+
+description: |
+ The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
+ its parallel input.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt2701-hdmi
+ - mediatek,mt7623-hdmi
+ - mediatek,mt8167-hdmi
+ - mediatek,mt8173-hdmi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Pixel Clock
+ - description: HDMI PLL
+ - description: Bit Clock
+ - description: S/PDIF Clock
+
+ clock-names:
+ items:
+ - const: pixel
+ - const: pll
+ - const: bclk
+ - const: spdif
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: hdmi
+
+ mediatek,syscon-hdmi:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description: |
+ phandle link and register offset to the system configuration registers.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ Input port node. This port should be connected to a DPI output port.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: |
+ Output port node. This port should be connected to the input port of a connector
+ node that contains a ddc-i2c-bus property, or to the input port of an attached
+ bridge chip, such as a SlimPort transmitter.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - mediatek,syscon-hdmi
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8173-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ hdmi0: hdmi@14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0x14025000 0x400>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLLCK>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi0_out: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/msm/dp-controller.yaml b/Bindings/display/msm/dp-controller.yaml
new file mode 100644
index 0000000..64d8d9e
--- /dev/null
+++ b/Bindings/display/msm/dp-controller.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MSM Display Port Controller
+
+maintainers:
+ - Kuogee Hsieh <khsieh@codeaurora.org>
+
+description: |
+ Device tree bindings for DisplayPort host controller for MSM targets
+ that are compatible with VESA DisplayPort interface specification.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc7180-dp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AHB clock to enable register access
+ - description: Display Port AUX clock
+ - description: Display Port Link clock
+ - description: Link interface clock between DP and PHY
+ - description: Display Port Pixel clock
+
+ clock-names:
+ items:
+ - const: core_iface
+ - const: core_aux
+ - const: ctrl_link
+ - const: ctrl_link_iface
+ - const: stream_pixel
+
+ assigned-clocks:
+ items:
+ - description: link clock source
+ - description: pixel clock source
+
+ assigned-clock-parents:
+ items:
+ - description: phy 0 parent
+ - description: phy 1 parent
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: dp
+
+ operating-points-v2:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Input endpoint of the controller
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Output endpoint of the controller
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - "#sound-dai-cells"
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+ #include <dt-bindings/power/qcom-aoss-qmp.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ displayport-controller@ae90000 {
+ compatible = "qcom,sc7180-dp";
+ reg = <0xae90000 0x1400>;
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+
+ assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
+
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ power-domains = <&rpmhpd SC7180_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&typec>;
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/display/msm/dpu-sc7180.yaml b/Bindings/display/msm/dpu-sc7180.yaml
new file mode 100644
index 0000000..12a86b1
--- /dev/null
+++ b/Bindings/display/msm/dpu-sc7180.yaml
@@ -0,0 +1,228 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SC7180 target
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS and DPU are mentioned for SC7180 target.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sc7180-mdss
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: mdss
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock from dispcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interrupt-cells":
+ const: 1
+
+ iommus:
+ items:
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+
+ ranges: true
+
+ interconnects:
+ items:
+ - description: Interconnect path specifying the port ids for data bus
+
+ interconnect-names:
+ const: mdp0-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ description: Node containing the properties of DPU.
+
+ properties:
+ compatible:
+ items:
+ - const: qcom,sc7180-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display hf axi clock
+ - description: Display ahb clock
+ - description: Display rotator clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: rot
+ - const: lut
+ - const: core
+ - const: vsync
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ operating-points-v2: true
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF1 (DSI1)
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF0 (DP)
+
+ required:
+ - port@0
+
+ required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - interrupts
+ - power-domains
+ - operating-points-v2
+ - ports
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sdm845.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,sc7180-mdss";
+ reg = <0xae00000 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc MDSS_GDSC>;
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "mdp0-mem";
+
+ iommus = <&apps_smmu 0x800 0x2>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sc7180-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/display/msm/dpu-sdm845.yaml b/Bindings/display/msm/dpu-sdm845.yaml
new file mode 100644
index 0000000..b4ea7c9
--- /dev/null
+++ b/Bindings/display/msm/dpu-sdm845.yaml
@@ -0,0 +1,212 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DPU dt properties for SDM845 target
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS and DPU are mentioned for SDM845 target.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sdm845-mdss
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: mdss
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ "#interrupt-cells":
+ const: 1
+
+ iommus:
+ items:
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
+ - description: Phandle to apps_smmu node with SID mask for Hard-Fail port1
+
+ ranges: true
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ description: Node containing the properties of DPU.
+
+ properties:
+ compatible:
+ items:
+ - const: qcom,sdm845-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display ahb clock
+ - description: Display axi clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: vsync
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ operating-points-v2: true
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface.
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF1 (DSI1)
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: DPU_INTF2 (DSI2)
+
+ required:
+ - port@0
+ - port@1
+
+ required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - interrupts
+ - power-domains
+ - operating-points-v2
+ - ports
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@ae00000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,sdm845-mdss";
+ reg = <0x0ae00000 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x880 0x8>,
+ <&apps_smmu 0xc80 0x8>;
+ ranges;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0x0ae01000 0x8f000>,
+ <0x0aeb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+ power-domains = <&rpmhpd SDM845_CX>;
+ operating-points-v2 = <&mdp_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/display/msm/dpu.txt b/Bindings/display/msm/dpu.txt
deleted file mode 100644
index 586e6ea..0000000
--- a/Bindings/display/msm/dpu.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Qualcomm Technologies, Inc. DPU KMS
-
-Description:
-
-Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
-sub-blocks like DPU display controller, DSI and DP interfaces etc.
-The DPU display controller is found in SDM845 SoC.
-
-MDSS:
-Required properties:
-- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
-- reg: physical base address and length of controller's registers.
-- reg-names: register region names. The following region is required:
- * "mdss"
-- power-domains: a power domain consumer specifier according to
- Documentation/devicetree/bindings/power/power_domain.txt
-- clocks: list of clock specifiers for clocks needed by the device.
-- clock-names: device clock names, must be in same order as clocks property.
- The following clocks are required:
- * "iface"
- * "bus"
- * "core"
-- interrupts: interrupt signal from MDSS.
-- interrupt-controller: identifies the node as an interrupt controller.
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- iommus: phandle of iommu device node.
-- #address-cells: number of address cells for the MDSS children. Should be 1.
-- #size-cells: Should be 1.
-- ranges: parent bus address space is the same as the child bus address space.
-- interconnects : interconnect path specifier for MDSS according to
- Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
- 2 paths corresponding to 2 AXI ports.
-- interconnect-names : MDSS will have 2 port names to differentiate between the
- 2 interconnect paths defined with interconnect specifier.
-
-Optional properties:
-- assigned-clocks: list of clock specifiers for clocks needing rate assignment
-- assigned-clock-rates: list of clock frequencies sorted in the same order as
- the assigned-clocks property.
-
-MDP:
-Required properties:
-- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
-- reg: physical base address and length of controller's registers.
-- reg-names : register region names. The following region is required:
- * "mdp"
- * "vbif"
-- clocks: list of clock specifiers for clocks needed by the device.
-- clock-names: device clock names, must be in same order as clocks property.
- The following clocks are required.
- * "bus"
- * "iface"
- * "core"
- * "vsync"
-- interrupts: interrupt line from DPU to MDSS.
-- ports: contains the list of output ports from DPU device. These ports connect
- to interfaces that are external to the DPU hardware, such as DSI, DP etc.
-
- Each output port contains an endpoint that describes how it is connected to an
- external interface. These are described by the standard properties documented
- here:
- Documentation/devicetree/bindings/graph.txt
- Documentation/devicetree/bindings/media/video-interfaces.txt
-
- Port 0 -> DPU_INTF1 (DSI1)
- Port 1 -> DPU_INTF2 (DSI2)
-
-Optional properties:
-- assigned-clocks: list of clock specifiers for clocks needing rate assignment
-- assigned-clock-rates: list of clock frequencies sorted in the same order as
- the assigned-clocks property.
-
-Example:
-
- mdss: mdss@ae00000 {
- compatible = "qcom,sdm845-mdss";
- reg = <0xae00000 0x1000>;
- reg-names = "mdss";
-
- power-domains = <&clock_dispcc 0>;
-
- clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
- <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
- clock-names = "iface", "bus", "core";
-
- assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <300000000>;
-
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
- <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
-
- interconnect-names = "mdp0-mem", "mdp1-mem";
-
- iommus = <&apps_iommu 0>;
-
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0xae00000 0xb2008>;
-
- mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
- reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
- reg-names = "mdp", "vbif";
-
- clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
- <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
- <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
- <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
- clock-names = "iface", "bus", "core", "vsync";
-
- assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
- <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <0 0 300000000 19200000>;
-
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dpu_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
- };
- };
-
- port@1 {
- reg = <1>;
- dpu_intf2_out: endpoint {
- remote-endpoint = <&dsi1_in>;
- };
- };
- };
- };
- };
diff --git a/Bindings/display/msm/dsi-controller-main.yaml b/Bindings/display/msm/dsi-controller-main.yaml
new file mode 100644
index 0000000..76348b7
--- /dev/null
+++ b/Bindings/display/msm/dsi-controller-main.yaml
@@ -0,0 +1,185 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI controller
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+allOf:
+ - $ref: "../dsi-controller.yaml#"
+
+properties:
+ compatible:
+ items:
+ - const: qcom,mdss-dsi-ctrl
+
+ reg:
+ maxItems: 1
+
+ reg-names:
+ const: dsi_ctrl
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display byte clock
+ - description: Display byte interface clock
+ - description: Display pixel clock
+ - description: Display escape clock
+ - description: Display AHB clock
+ - description: Display AXI clock
+
+ clock-names:
+ items:
+ - const: byte
+ - const: byte_intf
+ - const: pixel
+ - const: core
+ - const: iface
+ - const: bus
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: dsi
+
+ "#address-cells": true
+
+ "#size-cells": true
+
+ syscon-sfpb:
+ description: A phandle to mmss_sfpb syscon node (only for DSIv2).
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+
+ qcom,dual-dsi-mode:
+ type: boolean
+ description: |
+ Indicates if the DSI controller is driving a panel which needs
+ 2 DSI links.
+
+ power-domains:
+ maxItems: 1
+
+ operating-points-v2: true
+
+ ports:
+ $ref: "/schemas/graph.yaml#/properties/ports"
+ description: |
+ Contains DSI controller input and output ports as children, each
+ containing one endpoint subnode.
+
+ properties:
+ port@0:
+ $ref: "/schemas/graph.yaml#/properties/port"
+ description: |
+ Input endpoints of the controller.
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+ properties:
+ data-lanes:
+ maxItems: 4
+ minItems: 4
+ items:
+ enum: [ 0, 1, 2, 3 ]
+
+ port@1:
+ $ref: "/schemas/graph.yaml#/properties/port"
+ description: |
+ Output endpoints of the controller.
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+ properties:
+ data-lanes:
+ maxItems: 4
+ minItems: 4
+ items:
+ enum: [ 0, 1, 2, 3 ]
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - power-domains
+ - operating-points-v2
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x0ae94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ power-domains = <&rpmhpd SC7180_CX>;
+ operating-points-v2 = <&dsi_opp_table>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&sn65dsi86_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/display/msm/dsi-phy-10nm.yaml b/Bindings/display/msm/dsi-phy-10nm.yaml
new file mode 100644
index 0000000..4a26bef
--- /dev/null
+++ b/Bindings/display/msm/dsi-phy-10nm.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 10nm PHY
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+allOf:
+ - $ref: dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-10nm
+ - const: qcom,dsi-phy-10nm-8998
+
+ reg:
+ items:
+ - description: dsi phy register set
+ - description: dsi phy lane register set
+ - description: dsi pll register set
+
+ reg-names:
+ items:
+ - const: dsi_phy
+ - const: dsi_phy_lane
+ - const: dsi_pll
+
+ vdds-supply:
+ description: |
+ Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
+ connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vdds-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+...
diff --git a/Bindings/display/msm/dsi-phy-14nm.yaml b/Bindings/display/msm/dsi-phy-14nm.yaml
new file mode 100644
index 0000000..72a00cc
--- /dev/null
+++ b/Bindings/display/msm/dsi-phy-14nm.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 14nm PHY
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+allOf:
+ - $ref: dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-14nm
+ - const: qcom,dsi-phy-14nm-660
+
+ reg:
+ items:
+ - description: dsi phy register set
+ - description: dsi phy lane register set
+ - description: dsi pll register set
+
+ reg-names:
+ items:
+ - const: dsi_phy
+ - const: dsi_phy_lane
+ - const: dsi_pll
+
+ vcca-supply:
+ description: Phandle to vcca regulator device node.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vcca-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-14nm";
+ reg = <0x0ae94400 0x200>,
+ <0x0ae94600 0x280>,
+ <0x0ae94a00 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vcca-supply = <&vcca_reg>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+...
diff --git a/Bindings/display/msm/dsi-phy-20nm.yaml b/Bindings/display/msm/dsi-phy-20nm.yaml
new file mode 100644
index 0000000..743806d
--- /dev/null
+++ b/Bindings/display/msm/dsi-phy-20nm.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 20nm PHY
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+allOf:
+ - $ref: dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-20nm
+
+ reg:
+ items:
+ - description: dsi pll register set
+ - description: dsi phy register set
+ - description: dsi phy regulator register set
+
+ reg-names:
+ items:
+ - const: dsi_pll
+ - const: dsi_phy
+ - const: dsi_phy_regulator
+
+ vcca-supply:
+ description: Phandle to vcca regulator device node.
+
+ vddio-supply:
+ description: Phandle to vdd-io regulator device node.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vddio-supply
+ - vcca-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@fd922a00 {
+ compatible = "qcom,dsi-phy-20nm";
+ reg = <0xfd922a00 0xd4>,
+ <0xfd922b00 0x2b0>,
+ <0xfd922d80 0x7b>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vcca-supply = <&vcca_reg>;
+ vddio-supply = <&vddio_reg>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+...
diff --git a/Bindings/display/msm/dsi-phy-28nm.yaml b/Bindings/display/msm/dsi-phy-28nm.yaml
new file mode 100644
index 0000000..b106007
--- /dev/null
+++ b/Bindings/display/msm/dsi-phy-28nm.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display DSI 28nm PHY
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+allOf:
+ - $ref: dsi-phy-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-28nm-hpm
+ - const: qcom,dsi-phy-28nm-lp
+ - const: qcom,dsi-phy-28nm-8960
+
+ reg:
+ items:
+ - description: dsi pll register set
+ - description: dsi phy register set
+ - description: dsi phy regulator register set
+
+ reg-names:
+ items:
+ - const: dsi_pll
+ - const: dsi_phy
+ - const: dsi_phy_regulator
+
+ vddio-supply:
+ description: Phandle to vdd-io regulator device node.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - vddio-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ dsi-phy@fd922a00 {
+ compatible = "qcom,dsi-phy-28nm-lp";
+ reg = <0xfd922a00 0xd4>,
+ <0xfd922b00 0x2b0>,
+ <0xfd922d80 0x7b>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vddio-supply = <&vddio_reg>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+...
diff --git a/Bindings/display/msm/dsi-phy-common.yaml b/Bindings/display/msm/dsi-phy-common.yaml
new file mode 100644
index 0000000..502bdda
--- /dev/null
+++ b/Bindings/display/msm/dsi-phy-common.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DSI PHY common dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ This defines the DSI PHY dt properties which are common for all
+ dsi phy versions.
+
+properties:
+ "#clock-cells":
+ const: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: Display AHB clock
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ref
+
+required:
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - "#phy-cells"
+
+additionalProperties: true
+...
diff --git a/Bindings/display/msm/dsi.txt b/Bindings/display/msm/dsi.txt
deleted file mode 100644
index b9a64d3..0000000
--- a/Bindings/display/msm/dsi.txt
+++ /dev/null
@@ -1,249 +0,0 @@
-Qualcomm Technologies Inc. adreno/snapdragon DSI output
-
-DSI Controller:
-Required properties:
-- compatible:
- * "qcom,mdss-dsi-ctrl"
-- reg: Physical base address and length of the registers of controller
-- reg-names: The names of register regions. The following regions are required:
- * "dsi_ctrl"
-- interrupts: The interrupt signal from the DSI block.
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: Phandles to device clocks.
-- clock-names: the following clocks are required:
- * "mdp_core"
- * "iface"
- * "bus"
- * "core_mmss"
- * "byte"
- * "pixel"
- * "core"
- For DSIv2, we need an additional clock:
- * "src"
- For DSI6G v2.0 onwards, we need also need the clock:
- * "byte_intf"
-- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
-- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
- by a DSI PHY block. See [1] for details on clock bindings.
-- vdd-supply: phandle to vdd regulator device node
-- vddio-supply: phandle to vdd-io regulator device node
-- vdda-supply: phandle to vdda regulator device node
-- phys: phandle to DSI PHY device node
-- phy-names: the name of the corresponding PHY device
-- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
-- ports: Contains 2 DSI controller ports as child nodes. Each port contains
- an endpoint subnode as defined in [2] and [3].
-
-Optional properties:
-- panel@0: Node of panel connected to this DSI controller.
- See files in [4] for each supported panel.
-- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
- driving a panel which needs 2 DSI links.
-- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
- the master link of the 2-DSI panel.
-- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
- driving a 2-DSI panel whose 2 links need receive command simultaneously.
-- pinctrl-names: the pin control state names; should contain "default"
-- pinctrl-0: the default pinctrl state (active)
-- pinctrl-n: the "sleep" pinctrl state
-- ports: contains DSI controller input and output ports as children, each
- containing one endpoint subnode.
-
- DSI Endpoint properties:
- - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
- input endpoint. For port@1, set to the MDP interface output. See [2] for
- device graph info.
-
- - data-lanes: this describes how the physical DSI data lanes are mapped
- to the logical lanes on the given platform. The value contained in
- index n describes what physical lane is mapped to the logical lane n
- (DATAn, where n lies between 0 and 3). The clock lane position is fixed
- and can't be changed. Hence, they aren't a part of the DT bindings. See
- [3] for more info on the data-lanes property.
-
- For example:
-
- data-lanes = <3 0 1 2>;
-
- The above mapping describes that the logical data lane DATA0 is mapped to
- the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
- to phys DATA1 and logic DATA3 to phys DATA2.
-
- There are only a limited number of physical to logical mappings possible:
- <0 1 2 3>
- <1 2 3 0>
- <2 3 0 1>
- <3 0 1 2>
- <0 3 2 1>
- <1 0 3 2>
- <2 1 0 3>
- <3 2 1 0>
-
-DSI PHY:
-Required properties:
-- compatible: Could be the following
- * "qcom,dsi-phy-28nm-hpm"
- * "qcom,dsi-phy-28nm-lp"
- * "qcom,dsi-phy-20nm"
- * "qcom,dsi-phy-28nm-8960"
- * "qcom,dsi-phy-14nm"
- * "qcom,dsi-phy-14nm-660"
- * "qcom,dsi-phy-10nm"
- * "qcom,dsi-phy-10nm-8998"
- * "qcom,dsi-phy-7nm"
- * "qcom,dsi-phy-7nm-8150"
-- reg: Physical base address and length of the registers of PLL, PHY. Some
- revisions require the PHY regulator base address, whereas others require the
- PHY lane base address. See below for each PHY revision.
-- reg-names: The names of register regions. The following regions are required:
- For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
- * "dsi_pll"
- * "dsi_phy"
- * "dsi_phy_regulator"
- For DSI 14nm, 10nm and 7nm PHYs:
- * "dsi_pll"
- * "dsi_phy"
- * "dsi_phy_lane"
-- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
- 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: Phandles to device clocks. See [1] for details on clock bindings.
-- clock-names: the following clocks are required:
- * "iface"
- * "ref" (only required for new DTS files/entries)
- For 28nm HPM/LP, 28nm 8960 PHYs:
-- vddio-supply: phandle to vdd-io regulator device node
- For 20nm PHY:
-- vddio-supply: phandle to vdd-io regulator device node
-- vcca-supply: phandle to vcca regulator device node
- For 14nm PHY:
-- vcca-supply: phandle to vcca regulator device node
- For 10nm and 7nm PHY:
-- vdds-supply: phandle to vdds regulator device node
-
-Optional properties:
-- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
- regulator is wanted.
-- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
- panels in microseconds. Driver uses this number to adjust
- the clock rate according to the expected transfer time.
- Increasing this value would slow down the mdp processing
- and can result in slower performance.
- Decreasing this value can speed up the mdp processing,
- but this can also impact power consumption.
- As a rule this time should not be higher than the time
- that would be expected with the processing at the
- dsi link rate since anyways this would be the maximum
- transfer time that could be achieved.
- If ping pong split is enabled, this time should not be higher
- than two times the dsi link rate time.
- If the property is not specified, then the default value is 14000 us.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/graph.txt
-[3] Documentation/devicetree/bindings/media/video-interfaces.txt
-[4] Documentation/devicetree/bindings/display/panel/
-
-Example:
- dsi0: dsi@fd922800 {
- compatible = "qcom,mdss-dsi-ctrl";
- qcom,dsi-host-index = <0>;
- interrupt-parent = <&mdp>;
- interrupts = <4 0>;
- reg-names = "dsi_ctrl";
- reg = <0xfd922800 0x200>;
- power-domains = <&mmcc MDSS_GDSC>;
- clock-names =
- "bus",
- "byte",
- "core",
- "core_mmss",
- "iface",
- "mdp_core",
- "pixel";
- clocks =
- <&mmcc MDSS_AXI_CLK>,
- <&mmcc MDSS_BYTE0_CLK>,
- <&mmcc MDSS_ESC0_CLK>,
- <&mmcc MMSS_MISC_AHB_CLK>,
- <&mmcc MDSS_AHB_CLK>,
- <&mmcc MDSS_MDP_CLK>,
- <&mmcc MDSS_PCLK0_CLK>;
-
- assigned-clocks =
- <&mmcc BYTE0_CLK_SRC>,
- <&mmcc PCLK0_CLK_SRC>;
- assigned-clock-parents =
- <&dsi_phy0 0>,
- <&dsi_phy0 1>;
-
- vdda-supply = <&pma8084_l2>;
- vdd-supply = <&pma8084_l22>;
- vddio-supply = <&pma8084_l12>;
-
- phys = <&dsi_phy0>;
- phy-names ="dsi-phy";
-
- qcom,dual-dsi-mode;
- qcom,master-dsi;
- qcom,sync-dual-dsi;
-
- qcom,mdss-mdp-transfer-time-us = <12000>;
-
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dsi_active>;
- pinctrl-1 = <&dsi_suspend>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&mdp_intf1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_out: endpoint {
- remote-endpoint = <&panel_in>;
- data-lanes = <0 1 2 3>;
- };
- };
- };
-
- panel: panel@0 {
- compatible = "sharp,lq101r1sx01";
- reg = <0>;
- link2 = <&secondary>;
-
- power-supply = <...>;
- backlight = <...>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
- };
- };
-
- dsi_phy0: dsi-phy@fd922a00 {
- compatible = "qcom,dsi-phy-28nm-hpm";
- qcom,dsi-phy-index = <0>;
- reg-names =
- "dsi_pll",
- "dsi_phy",
- "dsi_phy_regulator";
- reg = <0xfd922a00 0xd4>,
- <0xfd922b00 0x2b0>,
- <0xfd922d80 0x7b>;
- clock-names = "iface";
- clocks = <&mmcc MDSS_AHB_CLK>;
- #clock-cells = <1>;
- vddio-supply = <&pma8084_l12>;
-
- qcom,dsi-phy-regulator-ldo-mode;
- };
diff --git a/Bindings/display/panel/lvds.yaml b/Bindings/display/panel/lvds.yaml
index 3116460..49460c9 100644
--- a/Bindings/display/panel/lvds.yaml
+++ b/Bindings/display/panel/lvds.yaml
@@ -51,37 +51,37 @@
- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
[VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
- Slot 0 1 2 3 4 5 6
- ________________ _________________
- Clock \_______________________/
- ______ ______ ______ ______ ______ ______ ______
- DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
- DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
+ Slot 0 1 2 3 4 5 6
+ ________________ _________________
+ Clock \_______________________/
+ ______ ______ ______ ______ ______ ______ ______
+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
specifications. Data are transferred as follows on 4 LVDS lanes.
- Slot 0 1 2 3 4 5 6
- ________________ _________________
- Clock \_______________________/
- ______ ______ ______ ______ ______ ______ ______
- DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
- DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
- DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
+ Slot 0 1 2 3 4 5 6
+ ________________ _________________
+ Clock \_______________________/
+ ______ ______ ______ ______ ______ ______ ______
+ DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
+ DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
+ DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
Data are transferred as follows on 4 LVDS lanes.
- Slot 0 1 2 3 4 5 6
- ________________ _________________
- Clock \_______________________/
- ______ ______ ______ ______ ______ ______ ______
- DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
- DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
- DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
+ Slot 0 1 2 3 4 5 6
+ ________________ _________________
+ Clock \_______________________/
+ ______ ______ ______ ______ ______ ______ ______
+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
+ DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
Control signals are mapped as follows.
diff --git a/Bindings/display/panel/samsung,lms397kf04.yaml b/Bindings/display/panel/samsung,lms397kf04.yaml
new file mode 100644
index 0000000..4cb75a5
--- /dev/null
+++ b/Bindings/display/panel/samsung,lms397kf04.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,lms397kf04.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung LMS397KF04 display panel
+
+description: The datasheet claims this is based around a display controller
+ named DB7430 with a separate backlight controller.
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: samsung,lms397kf04
+
+ reg: true
+
+ reset-gpios: true
+
+ vci-supply:
+ description: regulator that supplies the VCI analog voltage
+ usually around 3.0 V
+
+ vccio-supply:
+ description: regulator that supplies the VCCIO voltage usually
+ around 1.8 V
+
+ backlight: true
+
+ spi-max-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: inherited as a SPI client node, the datasheet specifies
+ maximum 300 ns minimum cycle which gives around 3 MHz max frequency
+ maximum: 3000000
+
+ port: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel@0 {
+ compatible = "samsung,lms397kf04";
+ spi-max-frequency = <3000000>;
+ reg = <0>;
+ vci-supply = <&lcd_3v0_reg>;
+ vccio-supply = <&lcd_1v8_reg>;
+ reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ backlight = <&ktd259>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/renesas,du.yaml b/Bindings/display/renesas,du.yaml
index 121596f..5f4345d 100644
--- a/Bindings/display/renesas,du.yaml
+++ b/Bindings/display/renesas,du.yaml
@@ -55,7 +55,7 @@
maxItems: 1
ports:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/properties/ports
description: |
The connections to the DU output video ports are modeled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
diff --git a/Bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 75cd9c6..da3b889 100644
--- a/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -29,7 +29,6 @@
clocks:
minItems: 2
- maxItems: 5
items:
- {}
- {}
@@ -41,7 +40,6 @@
clock-names:
minItems: 2
- maxItems: 5
items:
- {}
- {}
diff --git a/Bindings/display/st,stm32-dsi.yaml b/Bindings/display/st,stm32-dsi.yaml
index 679daed..ed310bb 100644
--- a/Bindings/display/st,stm32-dsi.yaml
+++ b/Bindings/display/st,stm32-dsi.yaml
@@ -29,7 +29,6 @@
- description: DSI bus clock
- description: Pixel clock
minItems: 2
- maxItems: 3
clock-names:
items:
@@ -37,7 +36,6 @@
- const: ref
- const: px_clk
minItems: 2
- maxItems: 3
resets:
maxItems: 1
diff --git a/Bindings/display/st,stm32-ltdc.yaml b/Bindings/display/st,stm32-ltdc.yaml
index d54f9ca..4ae3d75 100644
--- a/Bindings/display/st,stm32-ltdc.yaml
+++ b/Bindings/display/st,stm32-ltdc.yaml
@@ -22,7 +22,6 @@
- description: events interrupt line.
- description: errors interrupt line.
minItems: 1
- maxItems: 2
clocks:
maxItems: 1
diff --git a/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
index 403d579..d88bd93 100644
--- a/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
+++ b/Bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
@@ -65,7 +65,6 @@
The APB clock and at least one video clock are mandatory, the audio clock
is optional.
minItems: 2
- maxItems: 4
items:
- description: dp_apb_clk is the APB clock
- description: dp_aud_clk is the Audio clock
@@ -78,13 +77,11 @@
clock-names:
oneOf:
- minItems: 2
- maxItems: 3
items:
- const: dp_apb_clk
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
- minItems: 3
- maxItems: 4
items:
- const: dp_apb_clk
- const: dp_aud_clk
@@ -116,7 +113,6 @@
maxItems: 2
phy-names:
minItems: 1
- maxItems: 2
items:
- const: dp-phy0
- const: dp-phy1
diff --git a/Bindings/dma/altr,msgdma.yaml b/Bindings/dma/altr,msgdma.yaml
new file mode 100644
index 0000000..a4f9fe2
--- /dev/null
+++ b/Bindings/dma/altr,msgdma.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera mSGDMA IP core
+
+maintainers:
+ - Olivier Dautricourt <olivier.dautricourt@orolia.com>
+
+description: |
+ Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
+ intellectual property (IP)
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ const: altr,socfpga-msgdma
+
+ reg:
+ items:
+ - description: Control and Status Register Slave Port
+ - description: Descriptor Slave Port
+ - description: Response Slave Port
+
+ reg-names:
+ items:
+ - const: csr
+ - const: desc
+ - const: resp
+
+ interrupts:
+ maxItems: 1
+
+ "#dma-cells":
+ const: 1
+ description:
+ The cell identifies the channel id (must be 0)
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ msgdma_controller: dma-controller@ff200b00 {
+ compatible = "altr,socfpga-msgdma";
+ reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
+ reg-names = "csr", "desc", "resp";
+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ };
diff --git a/Bindings/dma/arm-pl08x.txt b/Bindings/dma/arm-pl08x.txt
deleted file mode 100644
index 0ba81f7..0000000
--- a/Bindings/dma/arm-pl08x.txt
+++ /dev/null
@@ -1,59 +0,0 @@
-* ARM PrimeCells PL080 and PL081 and derivatives DMA controller
-
-Required properties:
-- compatible: "arm,pl080", "arm,primecell";
- "arm,pl081", "arm,primecell";
- "faraday,ftdmac020", "arm,primecell"
-- arm,primecell-periphid: on the FTDMAC020 the primecell ID is not hard-coded
- in the hardware and must be specified here as <0x0003b080>. This number
- follows the PrimeCell standard numbering using the JEP106 vendor code 0x38
- for Faraday Technology.
-- reg: Address range of the PL08x registers
-- interrupt: The PL08x interrupt number
-- clocks: The clock running the IP core clock
-- clock-names: Must contain "apb_pclk"
-- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
-- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
-- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
-- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
-- #dma-cells: must be <2>. First cell should contain the DMA request,
- second cell should contain either 1 or 2 depending on
- which AHB master that is used.
-
-Optional properties:
-- dma-channels: contains the total number of DMA channels supported by the DMAC
-- dma-requests: contains the total number of DMA requests supported by the DMAC
-- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
- 64, 128 or 256 bytes are legal values
-- memcpy-bus-width: the bus width used for memcpy in bits: 8, 16 or 32 are legal
- values, the Faraday FTDMAC020 can also accept 64 bits
-
-Clients
-Required properties:
-- dmas: List of DMA controller phandle, request channel and AHB master id
-- dma-names: Names of the aforementioned requested channels
-
-Example:
-
-dmac0: dma-controller@10130000 {
- compatible = "arm,pl080", "arm,primecell";
- reg = <0x10130000 0x1000>;
- interrupt-parent = <&vica>;
- interrupts = <15>;
- clocks = <&hclkdma0>;
- clock-names = "apb_pclk";
- lli-bus-interface-ahb1;
- lli-bus-interface-ahb2;
- mem-bus-interface-ahb2;
- memcpy-burst-size = <256>;
- memcpy-bus-width = <32>;
- #dma-cells = <2>;
-};
-
-device@40008000 {
- ...
- dmas = <&dmac0 0 2
- &dmac0 1 2>;
- dma-names = "tx", "rx";
- ...
-};
diff --git a/Bindings/dma/arm-pl08x.yaml b/Bindings/dma/arm-pl08x.yaml
new file mode 100644
index 0000000..3bd9eea
--- /dev/null
+++ b/Bindings/dma/arm-pl08x.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/arm-pl08x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM PrimeCells PL080 and PL081 and derivatives DMA controller
+
+maintainers:
+ - Vinod Koul <vkoul@kernel.org>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+# We need a select here so we don't match all nodes with 'arm,primecell'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - arm,pl080
+ - arm,pl081
+ required:
+ - compatible
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - arm,pl080
+ - arm,pl081
+ - const: arm,primecell
+ - items:
+ - const: faraday,ftdma020
+ - const: arm,pl080
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+ description: Address range of the PL08x registers
+
+ interrupts:
+ minItems: 1
+ description: The PL08x interrupt number
+
+ clocks:
+ minItems: 1
+ description: The clock running the IP core clock
+
+ clock-names:
+ maxItems: 1
+
+ lli-bus-interface-ahb1:
+ type: boolean
+ description: if AHB master 1 is eligible for fetching LLIs
+
+ lli-bus-interface-ahb2:
+ type: boolean
+ description: if AHB master 2 is eligible for fetching LLIs
+
+ mem-bus-interface-ahb1:
+ type: boolean
+ description: if AHB master 1 is eligible for fetching memory contents
+
+ mem-bus-interface-ahb2:
+ type: boolean
+ description: if AHB master 2 is eligible for fetching memory contents
+
+ memcpy-burst-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 1
+ - 4
+ - 8
+ - 16
+ - 32
+ - 64
+ - 128
+ - 256
+ description: the size of the bursts for memcpy
+
+ memcpy-bus-width:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum:
+ - 8
+ - 16
+ - 32
+ - 64
+ description: bus width used for memcpy in bits. FTDMAC020 also accept 64 bits
+
+required:
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#dma-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ dmac0: dma-controller@10130000 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x10130000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <15>;
+ clocks = <&hclkdma0>;
+ clock-names = "apb_pclk";
+ lli-bus-interface-ahb1;
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/reset/cortina,gemini-reset.h>
+ #include <dt-bindings/clock/cortina,gemini-clock.h>
+ dma-controller@67000000 {
+ compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell";
+ /* Faraday Technology FTDMAC020 variant */
+ arm,primecell-periphid = <0x0003b080>;
+ reg = <0x67000000 0x1000>;
+ interrupts = <9 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon GEMINI_RESET_DMAC>;
+ clocks = <&syscon GEMINI_CLK_AHB>;
+ clock-names = "apb_pclk";
+ /* Bus interface AHB1 (AHB0) is totally tilted */
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+ };
diff --git a/Bindings/dma/qcom,gpi.yaml b/Bindings/dma/qcom,gpi.yaml
index e302147..e614fe3 100644
--- a/Bindings/dma/qcom,gpi.yaml
+++ b/Bindings/dma/qcom,gpi.yaml
@@ -21,6 +21,7 @@
enum:
- qcom,sdm845-gpi-dma
- qcom,sm8150-gpi-dma
+ - qcom,sm8250-gpi-dma
reg:
maxItems: 1
diff --git a/Bindings/dma/renesas,rcar-dmac.yaml b/Bindings/dma/renesas,rcar-dmac.yaml
index 7f2a54b..d8142cb 100644
--- a/Bindings/dma/renesas,rcar-dmac.yaml
+++ b/Bindings/dma/renesas,rcar-dmac.yaml
@@ -52,7 +52,6 @@
interrupt-names:
minItems: 9
- maxItems: 17
items:
- const: error
- pattern: "^ch([0-9]|1[0-5])$"
diff --git a/Bindings/dma/renesas,shdma.txt b/Bindings/dma/renesas,shdma.txt
deleted file mode 100644
index a91920a..0000000
--- a/Bindings/dma/renesas,shdma.txt
+++ /dev/null
@@ -1,84 +0,0 @@
-* SHDMA Device Tree bindings
-
-Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
-instances, capable of serving any of a common set of DMA slave devices, using
-the same configuration. To describe this topology we require all compatible
-SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
-DMAC instances have the same number of channels and use the same DMA
-descriptors. Therefore respective DMA DT bindings can also all be placed in the
-multiplexer node. Even if there is only one such DMAC instance on a system, it
-still has to be placed under such a multiplexer node.
-
-* DMA multiplexer
-
-Required properties:
-- compatible: should be "renesas,shdma-mux"
-- #dma-cells: should be <1>, see "dmas" property below
-
-Optional properties (currently unused):
-- dma-channels: number of DMA channels
-- dma-requests: number of DMA request signals
-
-* DMA controller
-
-Required properties:
-- compatible: should be of the form "renesas,shdma-<soc>", where <soc> should
- be replaced with the desired SoC model, e.g.
- "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
-
-Example:
- dmac: dma-multiplexer@0 {
- compatible = "renesas,shdma-mux";
- #dma-cells = <1>;
- dma-channels = <20>;
- dma-requests = <256>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- dma0: dma-controller@e6700020 {
- compatible = "renesas,shdma-r8a73a4";
- reg = <0 0xe6700020 0 0x89e0>;
- interrupt-parent = <&gic>;
- interrupts = <0 220 4
- 0 200 4
- 0 201 4
- 0 202 4
- 0 203 4
- 0 204 4
- 0 205 4
- 0 206 4
- 0 207 4
- 0 208 4
- 0 209 4
- 0 210 4
- 0 211 4
- 0 212 4
- 0 213 4
- 0 214 4
- 0 215 4
- 0 216 4
- 0 217 4
- 0 218 4
- 0 219 4>;
- interrupt-names = "error",
- "ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5", "ch6", "ch7",
- "ch8", "ch9", "ch10", "ch11",
- "ch12", "ch13", "ch14", "ch15",
- "ch16", "ch17", "ch18", "ch19";
- };
- };
-
-* DMA client
-
-Required properties:
-- dmas: a list of <[DMA multiplexer phandle] [MID/RID value]> pairs,
- where MID/RID values are fixed handles, specified in the SoC
- manual
-- dma-names: a list of DMA channel names, one per "dmas" entry
-
-Example:
- dmas = <&dmac 0xd1
- &dmac 0xd2>;
- dma-names = "tx", "rx";
diff --git a/Bindings/dma/ti-edma.txt b/Bindings/dma/ti-edma.txt
index 29fcd37..f719e16 100644
--- a/Bindings/dma/ti-edma.txt
+++ b/Bindings/dma/ti-edma.txt
@@ -33,7 +33,7 @@
- power-domains:Should contain a phandle to a PM domain provider node
and an args specifier containing the device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Optional properties:
-------------------
@@ -70,7 +70,7 @@
- power-domains:Should contain a phandle to a PM domain provider node
and an args specifier containing the device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Optional properties:
-------------------
diff --git a/Bindings/dvfs/performance-domain.yaml b/Bindings/dvfs/performance-domain.yaml
new file mode 100644
index 0000000..c8b9120
--- /dev/null
+++ b/Bindings/dvfs/performance-domain.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dvfs/performance-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic performance domains
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+
+description: |+
+ This binding is intended for performance management of groups of devices or
+ CPUs that run in the same performance domain. Performance domains must not
+ be confused with power domains. A performance domain is defined by a set
+ of devices that always have to run at the same performance level. For a given
+ performance domain, there is a single point of control that affects all the
+ devices in the domain, making it impossible to set the performance level of
+ an individual device in the domain independently from other devices in
+ that domain. For example, a set of CPUs that share a voltage domain, and
+ have a common frequency control, is said to be in the same performance
+ domain.
+
+ This device tree binding can be used to bind performance domain consumer
+ devices with their performance domains provided by performance domain
+ providers. A performance domain provider can be represented by any node in
+ the device tree and can provide one or more performance domains. A consumer
+ node can refer to the provider by a phandle and a set of phandle arguments
+ (so called performance domain specifiers) of length specified by the
+ \#performance-domain-cells property in the performance domain provider node.
+
+select: true
+
+properties:
+ "#performance-domain-cells":
+ description:
+ Number of cells in a performance domain specifier. Typically 0 for nodes
+ representing a single performance domain and 1 for nodes providing
+ multiple performance domains (e.g. performance controllers), but can be
+ any value as specified by device tree binding documentation of particular
+ provider.
+ enum: [ 0, 1 ]
+
+ performance-domains:
+ $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ maxItems: 1
+ description:
+ A phandle and performance domain specifier as defined by bindings of the
+ performance controller/provider specified by phandle.
+
+additionalProperties: true
+
+examples:
+ - |
+ performance: performance-controller@12340000 {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0x12340000 0x1000>;
+ #performance-domain-cells = <1>;
+ };
+
+ // The node above defines a performance controller that is a performance
+ // domain provider and expects one cell as its phandle argument.
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ performance-domains = <&performance 1>;
+ };
+ };
diff --git a/Bindings/edac/amazon,al-mc-edac.yaml b/Bindings/edac/amazon,al-mc-edac.yaml
index 57e5270a..4cfc3a1 100644
--- a/Bindings/edac/amazon,al-mc-edac.yaml
+++ b/Bindings/edac/amazon,al-mc-edac.yaml
@@ -30,14 +30,12 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: uncorrectable error interrupt
- description: correctable error interrupt
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: ue
- const: ce
diff --git a/Bindings/eeprom/at24.yaml b/Bindings/eeprom/at24.yaml
index 021d8ae..914a423 100644
--- a/Bindings/eeprom/at24.yaml
+++ b/Bindings/eeprom/at24.yaml
@@ -32,7 +32,6 @@
oneOf:
- allOf:
- minItems: 1
- maxItems: 2
items:
- pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$"
- pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
diff --git a/Bindings/eeprom/at25.yaml b/Bindings/eeprom/at25.yaml
index 6a2dc8b..fbf99e3 100644
--- a/Bindings/eeprom/at25.yaml
+++ b/Bindings/eeprom/at25.yaml
@@ -4,14 +4,16 @@
$id: "http://devicetree.org/schemas/eeprom/at25.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
-title: SPI EEPROMs compatible with Atmel's AT25
+title: SPI EEPROMs or FRAMs compatible with Atmel's AT25
maintainers:
- Christian Eggers <ceggers@arri.de>
properties:
$nodename:
- pattern: "^eeprom@[0-9a-f]{1,2}$"
+ anyOf:
+ - pattern: "^eeprom@[0-9a-f]{1,2}$"
+ - pattern: "^fram@[0-9a-f]{1,2}$"
# There are multiple known vendors who manufacture EEPROM chips compatible
# with Atmel's AT25. The compatible string requires two items where the
@@ -31,6 +33,7 @@
- microchip,25lc040
- st,m95m02
- st,m95256
+ - cypress,fm25
- const: atmel,at25
@@ -47,7 +50,7 @@
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536, 131072]
description:
- Size of the eeprom page.
+ Size of the eeprom page. FRAMs don't have pages.
size:
$ref: /schemas/types.yaml#/definitions/uint32
@@ -100,9 +103,19 @@
- compatible
- reg
- spi-max-frequency
- - pagesize
- - size
- - address-width
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: cypress,fm25
+ then:
+ required:
+ - pagesize
+ - size
+ - address-width
additionalProperties: false
@@ -125,4 +138,10 @@
size = <32768>;
address-width = <16>;
};
+
+ fram@1 {
+ compatible = "cypress,fm25", "atmel,at25";
+ reg = <1>;
+ spi-max-frequency = <40000000>;
+ };
};
diff --git a/Bindings/example-schema.yaml b/Bindings/example-schema.yaml
index a97f391..ff6ec65 100644
--- a/Bindings/example-schema.yaml
+++ b/Bindings/example-schema.yaml
@@ -91,7 +91,6 @@
interrupts:
# Either 1 or 2 interrupts can be present
minItems: 1
- maxItems: 2
items:
- description: tx or combined interrupt
- description: rx interrupt
@@ -105,7 +104,6 @@
interrupt-names:
# minItems must be specified here because the default would be 2
minItems: 1
- maxItems: 2
items:
- const: tx irq
- const: rx irq
diff --git a/Bindings/extcon/extcon-sm5502.txt b/Bindings/extcon/extcon-sm5502.txt
deleted file mode 100644
index fc3888e..0000000
--- a/Bindings/extcon/extcon-sm5502.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-
-* SM5502 MUIC (Micro-USB Interface Controller) device
-
-The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device
-which can detect the state of external accessory when external accessory is
-attached or detached and button is pressed or released. It is interfaced to
-the host controller using an I2C interface.
-
-Required properties:
-- compatible: Should be "siliconmitus,sm5502-muic"
-- reg: Specifies the I2C slave address of the MUIC block. It should be 0x25
-- interrupts: Interrupt specifiers for detection interrupt sources.
-
-Example:
-
- sm5502@25 {
- compatible = "siliconmitus,sm5502-muic";
- interrupt-parent = <&gpx1>;
- interrupts = <5 0>;
- reg = <0x25>;
- };
diff --git a/Bindings/extcon/siliconmitus,sm5502-muic.yaml b/Bindings/extcon/siliconmitus,sm5502-muic.yaml
new file mode 100644
index 0000000..fd2e550
--- /dev/null
+++ b/Bindings/extcon/siliconmitus,sm5502-muic.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/extcon/siliconmitus,sm5502-muic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SM5502/SM5504 MUIC (Micro-USB Interface Controller) device
+
+maintainers:
+ - Chanwoo Choi <cw00.choi@samsung.com>
+
+description:
+ The Silicon Mitus SM5502 is a MUIC (Micro-USB Interface Controller) device
+ which can detect the state of external accessory when external accessory is
+ attached or detached and button is pressed or released. It is interfaced to
+ the host controller using an I2C interface.
+
+properties:
+ compatible:
+ enum:
+ - siliconmitus,sm5502-muic
+ - siliconmitus,sm5504-muic
+
+ reg:
+ maxItems: 1
+ description: I2C slave address of the device. Usually 0x25 for SM5502,
+ 0x14 for SM5504.
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ extcon@25 {
+ compatible = "siliconmitus,sm5502-muic";
+ reg = <0x25>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
diff --git a/Bindings/firmware/arm,scmi.yaml b/Bindings/firmware/arm,scmi.yaml
new file mode 100644
index 0000000..cebf6ff
--- /dev/null
+++ b/Bindings/firmware/arm,scmi.yaml
@@ -0,0 +1,341 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2021 ARM Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System Control and Management Interface (SCMI) Message Protocol bindings
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+
+description: |
+ The SCMI is intended to allow agents such as OSPM to manage various functions
+ that are provided by the hardware platform it is running on, including power
+ and performance functions.
+
+ This binding is intended to define the interface the firmware implementing
+ the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control
+ and Management Interface Platform Design Document")[0] provide for OSPM in
+ the device tree.
+
+ [0] https://developer.arm.com/documentation/den0056/latest
+
+properties:
+ $nodename:
+ const: scmi
+
+ compatible:
+ oneOf:
+ - description: SCMI compliant firmware with mailbox transport
+ items:
+ - const: arm,scmi
+ - description: SCMI compliant firmware with ARM SMC/HVC transport
+ items:
+ - const: arm,scmi-smc
+
+ interrupts:
+ description:
+ The interrupt that indicates message completion by the platform
+ rather than by the return of the smc call. This should not be used
+ except when the platform requires such behavior.
+ maxItems: 1
+
+ interrupt-names:
+ const: a2p
+
+ mbox-names:
+ description:
+ Specifies the mailboxes used to communicate with SCMI compliant
+ firmware.
+ items:
+ - const: tx
+ - const: rx
+
+ mboxes:
+ description:
+ List of phandle and mailbox channel specifiers. It should contain
+ exactly one or two mailboxes, one for transmitting messages("tx")
+ and another optional for receiving the notifications("rx") if supported.
+ minItems: 1
+ maxItems: 2
+
+ shmem:
+ description:
+ List of phandle pointing to the shared memory(SHM) area, for each
+ transport channel specified.
+ minItems: 1
+ maxItems: 2
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ arm,smc-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ SMC id required when using smc or hvc transports
+
+ protocol@11:
+ type: object
+ properties:
+ reg:
+ const: 0x11
+
+ '#power-domain-cells':
+ const: 1
+
+ required:
+ - '#power-domain-cells'
+
+ protocol@13:
+ type: object
+ properties:
+ reg:
+ const: 0x13
+
+ '#clock-cells':
+ const: 1
+
+ required:
+ - '#clock-cells'
+
+ protocol@14:
+ type: object
+ properties:
+ reg:
+ const: 0x14
+
+ '#clock-cells':
+ const: 1
+
+ required:
+ - '#clock-cells'
+
+ protocol@15:
+ type: object
+ properties:
+ reg:
+ const: 0x15
+
+ '#thermal-sensor-cells':
+ const: 1
+
+ required:
+ - '#thermal-sensor-cells'
+
+ protocol@16:
+ type: object
+ properties:
+ reg:
+ const: 0x16
+
+ '#reset-cells':
+ const: 1
+
+ required:
+ - '#reset-cells'
+
+ protocol@17:
+ type: object
+ properties:
+ reg:
+ const: 0x17
+
+ regulators:
+ type: object
+ description:
+ The list of all regulators provided by this SCMI controller.
+
+ patternProperties:
+ '^regulators@[0-9a-f]+$':
+ type: object
+ $ref: "../regulator/regulator.yaml#"
+
+ properties:
+ reg:
+ maxItems: 1
+ description: Identifier for the voltage regulator.
+
+ required:
+ - reg
+
+additionalProperties: false
+
+patternProperties:
+ '^protocol@[0-9a-f]+$':
+ type: object
+ description:
+ Each sub-node represents a protocol supported. If the platform
+ supports a dedicated communication channel for a particular protocol,
+ then the corresponding transport properties must be present.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ mbox-names:
+ items:
+ - const: tx
+ - const: rx
+
+ mboxes:
+ minItems: 1
+ maxItems: 2
+
+ shmem:
+ minItems: 1
+ maxItems: 2
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - shmem
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: arm,scmi
+then:
+ properties:
+ interrupts: false
+ interrupt-names: false
+
+ required:
+ - mboxes
+
+else:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: arm,scmi-smc
+ then:
+ required:
+ - arm,smc-id
+
+examples:
+ - |
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mhuB 0 0>,
+ <&mhuB 0 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri0>,
+ <&cpu_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+
+ mboxes = <&mhuB 1 0>,
+ <&mhuB 1 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_hpri0>,
+ <&cpu_scp_hpri1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensors: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+
+ scmi_voltage: protocol@17 {
+ reg = <0x17>;
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ regulator_devX: regulator@0 {
+ reg = <0x0>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator_devY: regulator@9 {
+ reg = <0x9>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <4200000>;
+ };
+ };
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri0: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ cpu_scp_lpri1: scp-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+
+ cpu_scp_hpri0: scp-sram-section@100 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x100 0x80>;
+ };
+
+ cpu_scp_hpri2: scp-sram-section@180 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x180 0x80>;
+ };
+ };
+ };
+
+ - |
+ firmware {
+ scmi {
+ compatible = "arm,scmi-smc";
+ shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
+ arm,smc-id = <0xc3000001>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd1: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ };
+ };
+
+...
diff --git a/Bindings/firmware/arm,scpi.yaml b/Bindings/firmware/arm,scpi.yaml
new file mode 100644
index 0000000..d7113b0
--- /dev/null
+++ b/Bindings/firmware/arm,scpi.yaml
@@ -0,0 +1,247 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2021 ARM Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/arm,scpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System Control and Power Interface (SCPI) Message Protocol bindings
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+
+description: |
+ Firmware implementing the SCPI described in ARM document number ARM DUI
+ 0922B ("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be
+ used by Linux to initiate various system control and power operations.
+
+ This binding is intended to define the interface the firmware implementing
+ the SCPI provide for OSPM in the device tree.
+
+ [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
+
+properties:
+ $nodename:
+ const: scpi
+
+ compatible:
+ description:
+ SCPI compliant firmware complying to SCPI v1.0 and above OR
+ SCPI compliant firmware complying to all unversioned releases
+ prior to SCPI v1.0
+ oneOf:
+ - const: arm,scpi # SCPI v1.0 and above
+ - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
+ - items:
+ - enum:
+ - amlogic,meson-gxbb-scpi
+ - const: arm,scpi-pre-1.0
+
+ mboxes:
+ description:
+ List of phandle and mailbox channel specifiers. All the channels reserved
+ by remote SCP firmware for use by SCPI message protocol should be
+ specified in any order.
+ minItems: 1
+
+ shmem:
+ description:
+ List of phandle pointing to the shared memory(SHM) area between the
+ processors using these mailboxes for IPC, one for each mailbox SHM can
+ be any memory reserved for the purpose of this communication between the
+ processors.
+ minItems: 1
+
+ power-controller:
+ type: object
+ description:
+ This sub-node represents SCPI power domain controller.
+
+ properties:
+ compatible:
+ const: arm,scpi-power-domains
+
+ '#power-domain-cells':
+ const: 1
+
+ num-domains:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Total number of power domains provided by SCPI. This is needed as
+ the SCPI message protocol lacks a mechanism to query this
+ information at runtime.
+
+ required:
+ - compatible
+ - '#power-domain-cells'
+ - num-domains
+
+ additionalProperties: false
+
+ sensors:
+ type: object
+ description: |
+ This sub-node represents SCPI sensors controller.
+
+ properties:
+ compatible:
+ oneOf:
+ - const: arm,scpi-sensors
+ - items:
+ - enum:
+ - amlogic,meson-gxbb-scpi-sensors
+ - const: arm,scpi-sensors
+
+ '#thermal-sensor-cells':
+ const: 1
+
+ required:
+ - compatible
+ - '#thermal-sensor-cells'
+
+ additionalProperties: false
+
+ clocks:
+ type: object
+ description:
+ This is the container node. Each sub-node represents one of the types
+ of clock controller - indexed or full range.
+
+ properties:
+ compatible:
+ const: arm,scpi-clocks
+
+ patternProperties:
+ "^clocks-[0-9a-f]+$":
+ type: object
+ description: |
+ This sub-node represents one of the types of clock controller
+ - indexed or full range.
+
+ "arm,scpi-dvfs-clocks" - all the clocks that are variable and index
+ based. These clocks don't provide an entire range of values between
+ the limits but only discrete points within the range. The firmware
+ provides the mapping for each such operating frequency and the index
+ associated with it. The firmware also manages the voltage scaling
+ appropriately with the clock scaling.
+
+ "arm,scpi-variable-clocks" - all the clocks that are variable and
+ provide full range within the specified range. The firmware provides
+ the range of values within a specified range.
+
+ properties:
+ compatible:
+ oneOf:
+ - const: arm,scpi-dvfs-clocks
+ - const: arm,scpi-variable-clocks
+
+ '#clock-cells':
+ const: 1
+
+ clock-output-names: true
+
+ clock-indices:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ The identifying number for the clocks(i.e.clock_id) in the node.
+ It can be non linear and hence provide the mapping of identifiers
+ into the clock-output-names array.
+
+ required:
+ - compatible
+ - '#clock-cells'
+ - clock-output-names
+ - clock-indices
+
+ additionalProperties: false
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - mboxes
+ - shmem
+
+examples:
+ - |
+ firmware {
+ scpi {
+ compatible = "arm,scpi";
+ mboxes = <&mhuA 1>;
+ shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
+
+ scpi_devpd: power-controller {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: clocks-0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>, <1>, <2>;
+ clock-output-names = "atlclk", "aplclk","gpuclk";
+ };
+
+ scpi_clk: clocks-1 {
+ compatible = "arm,scpi-variable-clocks";
+ #clock-cells = <1>;
+ clock-indices = <3>, <4>;
+ clock-output-names = "pxlclk0", "pxlclk1";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-sram-section@0 {
+ compatible = "arm,scp-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-sram-section@200 {
+ compatible = "arm,scp-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+ };
+
+ - |
+ firmware {
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ scpi_sensors1: sensors {
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
+...
diff --git a/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml b/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
index 1bd2870..c435c9f 100644
--- a/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
+++ b/Bindings/firmware/intel,ixp4xx-network-processing-engine.yaml
@@ -26,9 +26,16 @@
reg:
items:
- - description: NPE0 register range
- - description: NPE1 register range
- - description: NPE2 register range
+ - description: NPE0 (NPE-A) register range
+ - description: NPE1 (NPE-B) register range
+ - description: NPE2 (NPE-C) register range
+
+ crypto:
+ $ref: /schemas/crypto/intel,ixp4xx-crypto.yaml#
+ type: object
+ description: Optional node for the embedded crypto engine, the node
+ should be named with the instance number of the NPE engine used for
+ the crypto engine.
required:
- compatible
@@ -38,8 +45,15 @@
examples:
- |
- npe@c8006000 {
+ npe: npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+
+ crypto {
+ compatible = "intel,ixp4xx-crypto";
+ intel,npe-handle = <&npe 2>;
+ queue-rx = <&qmgr 30>;
+ queue-txready = <&qmgr 29>;
+ };
};
...
diff --git a/Bindings/firmware/qcom,scm.txt b/Bindings/firmware/qcom,scm.txt
index e747d73..a7333ad 100644
--- a/Bindings/firmware/qcom,scm.txt
+++ b/Bindings/firmware/qcom,scm.txt
@@ -12,6 +12,7 @@
* "qcom,scm-ipq4019"
* "qcom,scm-ipq806x"
* "qcom,scm-ipq8074"
+ * "qcom,scm-mdm9607"
* "qcom,scm-msm8660"
* "qcom,scm-msm8916"
* "qcom,scm-msm8960"
diff --git a/Bindings/fpga/fpga-region.txt b/Bindings/fpga/fpga-region.txt
index d787d57..7d35152 100644
--- a/Bindings/fpga/fpga-region.txt
+++ b/Bindings/fpga/fpga-region.txt
@@ -38,7 +38,7 @@
Partial Reconfiguration Region (PRR)
* Also called a "reconfigurable partition"
- * A PRR is a specific section of a FPGA reserved for reconfiguration.
+ * A PRR is a specific section of an FPGA reserved for reconfiguration.
* A base (or static) FPGA image may create a set of PRR's that later may
be independently reprogrammed many times.
* The size and specific location of each PRR is fixed.
@@ -105,7 +105,7 @@
Sequence
========
-When a DT overlay that targets a FPGA Region is applied, the FPGA Region will
+When a DT overlay that targets an FPGA Region is applied, the FPGA Region will
do the following:
1. Disable appropriate FPGA bridges.
@@ -134,8 +134,8 @@
FPGA while an operating system is running.
An FPGA Region that exists in the live Device Tree reflects the current state.
-If the live tree shows a "firmware-name" property or child nodes under a FPGA
-Region, the FPGA already has been programmed. A DTO that targets a FPGA Region
+If the live tree shows a "firmware-name" property or child nodes under an FPGA
+Region, the FPGA already has been programmed. A DTO that targets an FPGA Region
and adds the "firmware-name" property is taken as a request to reprogram the
FPGA. After reprogramming is successful, the overlay is accepted into the live
tree.
@@ -152,9 +152,9 @@
base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
this.
-If an FPGA Region does not specify a FPGA Manager, it will inherit the FPGA
+If an FPGA Region does not specify an FPGA Manager, it will inherit the FPGA
Manager specified by its ancestor FPGA Region. This supports both the case
-where the same FPGA Manager is used for all of a FPGA as well the case where
+where the same FPGA Manager is used for all of an FPGA as well the case where
a different FPGA Manager is used for each region.
FPGA Regions do not inherit their ancestor FPGA regions' bridges. This prevents
@@ -166,7 +166,7 @@
Required properties:
- compatible : should contain "fpga-region"
- fpga-mgr : should contain a phandle to an FPGA Manager. Child FPGA Regions
- inherit this property from their ancestor regions. A fpga-mgr property
+ inherit this property from their ancestor regions. An fpga-mgr property
in a region will override any inherited FPGA manager.
- #address-cells, #size-cells, ranges : must be present to handle address space
mapping for child nodes.
@@ -175,12 +175,12 @@
- firmware-name : should contain the name of an FPGA image file located on the
firmware search path. If this property shows up in a live device tree
it indicates that the FPGA has already been programmed with this image.
- If this property is in an overlay targeting a FPGA region, it is a
+ If this property is in an overlay targeting an FPGA region, it is a
request to program the FPGA with that image.
- fpga-bridges : should contain a list of phandles to FPGA Bridges that must be
controlled during FPGA programming along with the parent FPGA bridge.
This property is optional if the FPGA Manager handles the bridges.
- If the fpga-region is the child of a fpga-bridge, the list should not
+ If the fpga-region is the child of an fpga-bridge, the list should not
contain the parent bridge.
- partial-fpga-config : boolean, set if partial reconfiguration is to be done,
otherwise full reconfiguration is done.
@@ -279,7 +279,7 @@
In all cases the live DT must have the FPGA Manager, FPGA Bridges (if any), and
a FPGA Region. The target of the Device Tree Overlay is the FPGA Region. Some
-uses are specific to a FPGA device.
+uses are specific to an FPGA device.
* No FPGA Bridges
In this case, the FPGA Manager which programs the FPGA also handles the
@@ -300,7 +300,7 @@
bridges need to exist in the FPGA that can gate the buses going to each FPGA
region while the buses are enabled for other sections. Before any partial
reconfiguration can be done, a base FPGA image must be loaded which includes
- PRR's with FPGA bridges. The device tree should have a FPGA region for each
+ PRR's with FPGA bridges. The device tree should have an FPGA region for each
PRR.
Device Tree Examples
diff --git a/Bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Bindings/fpga/xilinx-zynq-fpga-mgr.txt
deleted file mode 100644
index 7018aa8..0000000
--- a/Bindings/fpga/xilinx-zynq-fpga-mgr.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Xilinx Zynq FPGA Manager
-
-Required properties:
-- compatible: should contain "xlnx,zynq-devcfg-1.0"
-- reg: base address and size for memory mapped io
-- interrupts: interrupt for the FPGA manager device
-- clocks: phandle for clocks required operation
-- clock-names: name for the clock, should be "ref_clk"
-- syscon: phandle for access to SLCR registers
-
-Example:
- devcfg: devcfg@f8007000 {
- compatible = "xlnx,zynq-devcfg-1.0";
- reg = <0xf8007000 0x100>;
- interrupts = <0 8 4>;
- clocks = <&clkc 12>;
- clock-names = "ref_clk";
- syscon = <&slcr>;
- };
diff --git a/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml
new file mode 100644
index 0000000..29daca4
--- /dev/null
+++ b/Bindings/fpga/xilinx-zynq-fpga-mgr.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq FPGA Manager Device Tree Bindings
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+properties:
+ compatible:
+ const: xlnx,zynq-devcfg-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ref_clk
+
+ syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to syscon block which provide access to SLCR registers
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ devcfg: devcfg@f8007000 {
+ compatible = "xlnx,zynq-devcfg-1.0";
+ reg = <0xf8007000 0x100>;
+ interrupts = <0 8 4>;
+ clocks = <&clkc 12>;
+ clock-names = "ref_clk";
+ syscon = <&slcr>;
+ };
diff --git a/Bindings/gpio/gpio-davinci.txt b/Bindings/gpio/gpio-davinci.txt
deleted file mode 100644
index 696ea46..0000000
--- a/Bindings/gpio/gpio-davinci.txt
+++ /dev/null
@@ -1,167 +0,0 @@
-Davinci/Keystone GPIO controller bindings
-
-Required Properties:
-- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs
- "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L,
- 66AK2E SoCs
- "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G
- "ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654
- "ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs
- "ti,am64-gpio", "ti,keystone-gpio": for AM64 SoCs
-
-- reg: Physical base address of the controller and the size of memory mapped
- registers.
-
-- gpio-controller : Marks the device node as a gpio controller.
-
-- #gpio-cells : Should be two.
- - first cell is the pin number
- - second cell is used to specify optional parameters (unused)
-
-- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are
- supported at a time.
-
-- ti,ngpio: The number of GPIO pins supported.
-
-- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt
- line to processor.
-
-- clocks: Should contain the device's input clock, and should be defined as per
- the appropriate clock bindings consumer usage in,
-
- Documentation/devicetree/bindings/clock/keystone-gate.txt
- for 66AK2HK/66AK2L/66AK2E SoCs or,
-
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
- for 66AK2G SoCs
-
-- clock-names: Name should be "gpio";
-
-Currently clock-names and clocks are needed for all keystone 2 platforms
-Davinci platforms do not have DT clocks as of now.
-
-The GPIO controller also acts as an interrupt controller. It uses the default
-two cells specifier as described in Documentation/devicetree/bindings/
-interrupt-controller/interrupts.txt.
-
-Example:
-
-gpio: gpio@1e26000 {
- compatible = "ti,dm6441-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x226000 0x1000>;
- interrupt-parent = <&intc>;
- interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH
- 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH
- 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH
- 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH
- 50 IRQ_TYPE_EDGE_BOTH>;
- ti,ngpio = <144>;
- ti,davinci-gpio-unbanked = <0>;
- interrupt-controller;
- #interrupt-cells = <2>;
-};
-
-leds {
- compatible = "gpio-leds";
-
- led1 {
- label = "davinci:green:usr1";
- gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
- ...
- };
-
- led2 {
- label = "davinci:red:debug1";
- gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
- ...
- };
-};
-
-Example for 66AK2G:
-
-gpio0: gpio@2603000 {
- compatible = "ti,k2g-gpio", "ti,keystone-gpio";
- reg = <0x02603000 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <144>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k2g_clks 0x001b 0x0>;
- clock-names = "gpio";
-};
-
-Example for 66AK2HK/66AK2L/66AK2E:
-
-gpio0: gpio@260bf00 {
- compatible = "ti,keystone-gpio";
- reg = <0x0260bf00 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- /* HW Interrupts mapped to GPIO pins */
- interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
- clocks = <&clkgpio>;
- clock-names = "gpio";
- ti,ngpio = <32>;
- ti,davinci-gpio-unbanked = <32>;
-};
-
-Example for K3 AM654:
-
-wkup_gpio0: wkup_gpio0@42110000 {
- compatible = "ti,am654-gpio", "ti,keystone-gpio";
- reg = <0x42110000 0x100>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-parent = <&intr_wkup_gpio>;
- interrupts = <59 128>, <59 129>, <59 130>, <59 131>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,ngpio = <56>;
- ti,davinci-gpio-unbanked = <0>;
- clocks = <&k3_clks 59 0>;
- clock-names = "gpio";
-};
diff --git a/Bindings/gpio/gpio-davinci.yaml b/Bindings/gpio/gpio-davinci.yaml
new file mode 100644
index 0000000..f32e09e
--- /dev/null
+++ b/Bindings/gpio/gpio-davinci.yaml
@@ -0,0 +1,185 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO controller for Davinci and keystone devices
+
+maintainers:
+ - Keerthy <j-keerthy@ti.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - ti,k2g-gpio
+ - ti,am654-gpio
+ - ti,j721e-gpio
+ - ti,am64-gpio
+ - const: ti,keystone-gpio
+
+ - items:
+ - enum:
+ - ti,dm6441-gpio
+ - ti,keystone-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ gpio-ranges: true
+
+ gpio-line-names:
+ description: strings describing the names of each gpio line.
+ minItems: 1
+ maxItems: 100
+
+ "#gpio-cells":
+ const: 2
+ description:
+ first cell is the pin number and second cell is used to specify optional parameters (unused).
+
+ interrupts:
+ description:
+ The interrupts are specified as per the interrupt parent. Only banked
+ or unbanked IRQs are supported at a time. If the interrupts are
+ banked then provide list of interrupts corresponding to each bank, else
+ provide the list of interrupts for each gpio.
+ minItems: 1
+ maxItems: 100
+
+ ti,ngpio:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The number of GPIO pins supported consecutively.
+ minimum: 1
+
+ ti,davinci-gpio-unbanked:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The number of GPIOs that have an individual interrupt line to processor.
+ minimum: 0
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: gpio
+
+ interrupt-controller: true
+
+ power-domains:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 2
+
+patternProperties:
+ "^(.+-hog(-[0-9]+)?)$":
+ type: object
+
+ required:
+ - gpio-hog
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupts
+ - ti,ngpio
+ - ti,davinci-gpio-unbanked
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include<dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpio0: gpio@2603000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x02603000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <144>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k2g_clks 0x001b 0x0>;
+ clock-names = "gpio";
+ };
+
+ - |
+ #include<dt-bindings/interrupt-controller/arm-gic.h>
+
+ gpio1: gpio@260bf00 {
+ compatible = "ti,keystone-gpio";
+ reg = <0x0260bf00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ /* HW Interrupts mapped to GPIO pins */
+ interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkgpio>;
+ clock-names = "gpio";
+ ti,ngpio = <32>;
+ ti,davinci-gpio-unbanked = <32>;
+ };
+
+ - |
+ wkup_gpio0: gpio0@42110000 {
+ compatible = "ti,am654-gpio", "ti,keystone-gpio";
+ reg = <0x42110000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&intr_wkup_gpio>;
+ interrupts = <60>, <61>, <62>, <63>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <56>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k3_clks 59 0>;
+ clock-names = "gpio";
+ };
diff --git a/Bindings/gpio/gpio-omap.txt b/Bindings/gpio/gpio-omap.txt
deleted file mode 100644
index e57b2cb..0000000
--- a/Bindings/gpio/gpio-omap.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-OMAP GPIO controller bindings
-
-Required properties:
-- compatible:
- - "ti,omap2-gpio" for OMAP2 controllers
- - "ti,omap3-gpio" for OMAP3 controllers
- - "ti,omap4-gpio" for OMAP4 controllers
-- reg : Physical base address of the controller and length of memory mapped
- region.
-- gpio-controller : Marks the device node as a GPIO controller.
-- #gpio-cells : Should be two.
- - first cell is the pin number
- - second cell is used to specify optional parameters (unused)
-- interrupt-controller: Mark the device node as an interrupt controller.
-- #interrupt-cells : Should be 2.
- The first cell is the GPIO number.
- The second cell is used to specify flags:
- bits[3:0] trigger type and level flags:
- 1 = low-to-high edge triggered.
- 2 = high-to-low edge triggered.
- 4 = active high level-sensitive.
- 8 = active low level-sensitive.
-- interrupts : The interrupt the controller is rising as output when an
- interrupt occures
-
-OMAP specific properties:
-- ti,hwmods: Name of the hwmod associated to the GPIO:
- "gpio<X>", <X> being the 1-based instance number
- from the HW spec.
-- ti,gpio-always-on: Indicates if a GPIO bank is always powered and
- so will never lose its logic state.
-
-
-Example:
-
-gpio0: gpio@44e07000 {
- compatible = "ti,omap4-gpio";
- reg = <0x44e07000 0x1000>;
- ti,hwmods = "gpio1";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <96>;
-};
diff --git a/Bindings/gpio/gpio-pcf857x.txt b/Bindings/gpio/gpio-pcf857x.txt
deleted file mode 100644
index a482455..0000000
--- a/Bindings/gpio/gpio-pcf857x.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-* PCF857x-compatible I/O expanders
-
-The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
-driven high by a pull-up current source or driven low to ground. This combines
-the direction and output level into a single bit per line, which can't be read
-back. We can't actually know at initialization time whether a line is configured
-(a) as output and driving the signal low/high, or (b) as input and reporting a
-low/high value, without knowing the last value written since the chip came out
-of reset (if any). The only reliable solution for setting up line direction is
-thus to do it explicitly.
-
-Required Properties:
-
- - compatible: should be one of the following.
- - "maxim,max7328": For the Maxim MAX7378
- - "maxim,max7329": For the Maxim MAX7329
- - "nxp,pca8574": For the NXP PCA8574
- - "nxp,pca8575": For the NXP PCA8575
- - "nxp,pca9670": For the NXP PCA9670
- - "nxp,pca9671": For the NXP PCA9671
- - "nxp,pca9672": For the NXP PCA9672
- - "nxp,pca9673": For the NXP PCA9673
- - "nxp,pca9674": For the NXP PCA9674
- - "nxp,pca9675": For the NXP PCA9675
- - "nxp,pcf8574": For the NXP PCF8574
- - "nxp,pcf8574a": For the NXP PCF8574A
- - "nxp,pcf8575": For the NXP PCF8575
-
- - reg: I2C slave address.
-
- - gpio-controller: Marks the device node as a gpio controller.
- - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
- cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
- GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
-
-Optional Properties:
-
- - lines-initial-states: Bitmask that specifies the initial state of each
- line. When a bit is set to zero, the corresponding line will be initialized to
- the input (pulled-up) state. When the bit is set to one, the line will be
- initialized the low-level output state. If the property is not specified
- all lines will be initialized to the input state.
-
- The I/O expander can detect input state changes, and thus optionally act as
- an interrupt controller. When the expander interrupt line is connected all the
- following properties must be set. For more information please see the
- interrupt controller device tree bindings documentation available at
- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt.
-
- - interrupt-controller: Identifies the node as an interrupt controller.
- - #interrupt-cells: Number of cells to encode an interrupt source, shall be 2.
- - interrupts: Interrupt specifier for the controllers interrupt.
-
-
-Please refer to gpio.txt in this directory for details of the common GPIO
-bindings used by client devices.
-
-Example: PCF8575 I/O expander node
-
- pcf8575: gpio@20 {
- compatible = "nxp,pcf8575";
- reg = <0x20>;
- interrupt-parent = <&irqpin2>;
- interrupts = <3 0>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
diff --git a/Bindings/gpio/gpio-stp-xway.txt b/Bindings/gpio/gpio-stp-xway.txt
deleted file mode 100644
index 78458ad..0000000
--- a/Bindings/gpio/gpio-stp-xway.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Lantiq SoC Serial To Parallel (STP) GPIO controller
-
-The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
-peripheral controller used to drive external shift register cascades. At most
-3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
-to drive the 2 LSBs of the cascade automatically.
-
-
-Required properties:
-- compatible : Should be "lantiq,gpio-stp-xway"
-- reg : Address and length of the register set for the device
-- #gpio-cells : Should be two. The first cell is the pin number and
- the second cell is used to specify optional parameters (currently
- unused).
-- gpio-controller : Marks the device node as a gpio controller.
-
-Optional properties:
-- lantiq,shadow : The default value that we shall assume as already set on the
- shift register cascade.
-- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled
- in the shift register cascade.
-- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
- property can enable this feature.
-- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade.
-- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade.
-- lantiq,rising : use rising instead of falling edge for the shift register
-
-Example:
-
-gpio1: stp@e100bb0 {
- compatible = "lantiq,gpio-stp-xway";
- reg = <0xE100BB0 0x40>;
- #gpio-cells = <2>;
- gpio-controller;
-
- lantiq,shadow = <0xffff>;
- lantiq,groups = <0x7>;
- lantiq,dsl = <0x3>;
- lantiq,phy1 = <0x7>;
- lantiq,phy2 = <0x7>;
- /* lantiq,rising; */
-};
diff --git a/Bindings/gpio/gpio-stp-xway.yaml b/Bindings/gpio/gpio-stp-xway.yaml
new file mode 100644
index 0000000..d565c4b
--- /dev/null
+++ b/Bindings/gpio/gpio-stp-xway.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-stp-xway.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Lantiq SoC Serial To Parallel (STP) GPIO controller
+
+description: |
+ The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
+ peripheral controller used to drive external shift register cascades. At most
+ 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
+ and Ethernet PHYs to drive some bytes of the cascade automatically.
+
+maintainers:
+ - John Crispin <john@phrozen.org>
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ const: lantiq,gpio-stp-xway
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ description:
+ The first cell is the pin number and the second cell is used to specify
+ consumer flags.
+ const: 2
+
+ lantiq,shadow:
+ description:
+ The default value that we shall assume as already set on the
+ shift register cascade.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x000000
+ maximum: 0xffffff
+
+ lantiq,groups:
+ description:
+ Set the 3 bit mask to select which of the 3 groups are enabled
+ in the shift register cascade.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x0
+ maximum: 0x7
+
+ lantiq,dsl:
+ description:
+ The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit
+ property can enable this feature.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x0
+ maximum: 0x3
+
+ lantiq,rising:
+ description:
+ Use rising instead of falling edge for the shift register.
+ type: boolean
+
+patternProperties:
+ "^lantiq,phy[1-4]$":
+ description:
+ The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
+ phy[1-2] are available, in xRX330 phy[1-3] and in XRX330 phy[1-4].
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x0
+ maximum: 0x7
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@e100bb0 {
+ compatible = "lantiq,gpio-stp-xway";
+ reg = <0xE100BB0 0x40>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ pinctrl-0 = <&stp_pins>;
+ pinctrl-names = "default";
+
+ lantiq,shadow = <0xffffff>;
+ lantiq,groups = <0x7>;
+ lantiq,dsl = <0x3>;
+ lantiq,phy1 = <0x7>;
+ lantiq,phy2 = <0x7>;
+ };
+...
diff --git a/Bindings/gpio/gpio-zynq.txt b/Bindings/gpio/gpio-zynq.txt
deleted file mode 100644
index f693e82..0000000
--- a/Bindings/gpio/gpio-zynq.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Xilinx Zynq GPIO controller Device Tree Bindings
--------------------------------------------
-
-Required properties:
-- #gpio-cells : Should be two
- - First cell is the GPIO line number
- - Second cell is used to specify optional
- parameters (unused)
-- compatible : Should be "xlnx,zynq-gpio-1.0" or
- "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
- or "xlnx,pmc-gpio-1.0
-- clocks : Clock specifier (see clock bindings for details)
-- gpio-controller : Marks the device node as a GPIO controller.
-- interrupts : Interrupt specifier (see interrupt bindings for
- details)
-- interrupt-controller : Marks the device node as an interrupt controller.
-- #interrupt-cells : Should be 2. The first cell is the GPIO number.
- The second cell bits[3:0] is used to specify trigger type and level flags:
- 1 = low-to-high edge triggered.
- 2 = high-to-low edge triggered.
- 4 = active high level-sensitive.
- 8 = active low level-sensitive.
-- reg : Address and length of the register set for the device
-
-Example:
- gpio@e000a000 {
- #gpio-cells = <2>;
- compatible = "xlnx,zynq-gpio-1.0";
- clocks = <&clkc 42>;
- gpio-controller;
- interrupt-parent = <&intc>;
- interrupts = <0 20 4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0xe000a000 0x1000>;
- };
diff --git a/Bindings/gpio/gpio-zynq.yaml b/Bindings/gpio/gpio-zynq.yaml
new file mode 100644
index 0000000..378da26
--- /dev/null
+++ b/Bindings/gpio/gpio-zynq.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-zynq.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq GPIO controller Device Tree Bindings
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+properties:
+ compatible:
+ const: xlnx,zynq-gpio-1.0
+
+ reg:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ gpio-controller: true
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#gpio-cells"
+ - interrupts
+ - gpio-controller
+ - interrupt-controller
+ - "#interrupt-cells"
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@e000a000 {
+ #gpio-cells = <2>;
+ compatible = "xlnx,zynq-gpio-1.0";
+ clocks = <&clkc 42>;
+ gpio-controller;
+ interrupt-parent = <&intc>;
+ interrupts = <0 20 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xe000a000 0x1000>;
+ };
diff --git a/Bindings/gpio/idt,32434-gpio.yaml b/Bindings/gpio/idt,32434-gpio.yaml
new file mode 100644
index 0000000..d38de81
--- /dev/null
+++ b/Bindings/gpio/idt,32434-gpio.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/idt,32434-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: IDT 79RC32434 GPIO controller
+
+maintainers:
+ - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
+
+properties:
+ compatible:
+ const: idt,32434-gpio
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: gpio
+ - const: pic
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ ngpios:
+ minimum: 1
+ maximum: 32
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio0: gpio@50004 {
+ compatible = "idt,32434-gpio";
+ reg = <0x50004 0x10>, <0x38030 0x0c>;
+ reg-names = "gpio", "pic";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <6>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ngpios = <14>;
+ };
diff --git a/Bindings/gpio/nxp,pcf8575.yaml b/Bindings/gpio/nxp,pcf8575.yaml
new file mode 100644
index 0000000..f0ff66c
--- /dev/null
+++ b/Bindings/gpio/nxp,pcf8575.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/nxp,pcf8575.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PCF857x-compatible I/O expanders
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+
+description:
+ The PCF857x-compatible chips have "quasi-bidirectional" I/O lines that can be
+ driven high by a pull-up current source or driven low to ground. This
+ combines the direction and output level into a single bit per line, which
+ can't be read back. We can't actually know at initialization time whether a
+ line is configured (a) as output and driving the signal low/high, or (b) as
+ input and reporting a low/high value, without knowing the last value written
+ since the chip came out of reset (if any). The only reliable solution for
+ setting up line direction is thus to do it explicitly.
+
+properties:
+ compatible:
+ enum:
+ - maxim,max7328
+ - maxim,max7329
+ - nxp,pca8574
+ - nxp,pca8575
+ - nxp,pca9670
+ - nxp,pca9671
+ - nxp,pca9672
+ - nxp,pca9673
+ - nxp,pca9674
+ - nxp,pca9675
+ - nxp,pcf8574
+ - nxp,pcf8574a
+ - nxp,pcf8575
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+ description:
+ The first cell is the GPIO number and the second cell specifies GPIO
+ flags, as defined in <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH
+ and GPIO_ACTIVE_LOW flags are supported.
+
+ lines-initial-states:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Bitmask that specifies the initial state of each line.
+ When a bit is set to zero, the corresponding line will be initialized to
+ the input (pulled-up) state.
+ When the bit is set to one, the line will be initialized to the
+ low-level output state.
+ If the property is not specified all lines will be initialized to the
+ input state.
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ wakeup-source: true
+
+patternProperties:
+ "^(.+-hog(-[0-9]+)?)$":
+ type: object
+
+ required:
+ - gpio-hog
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pcf8575: gpio@20 {
+ compatible = "nxp,pcf8575";
+ reg = <0x20>;
+ interrupt-parent = <&irqpin2>;
+ interrupts = <3 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
diff --git a/Bindings/gpio/rockchip,rk3328-grf-gpio.txt b/Bindings/gpio/rockchip,rk3328-grf-gpio.txt
deleted file mode 100644
index f9231df..0000000
--- a/Bindings/gpio/rockchip,rk3328-grf-gpio.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Rockchip RK3328 GRF (General Register Files) GPIO controller.
-
-In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute
-control, can also be used for general purpose. It is manipulated by the
-GRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can
-also be set in the same way.
-
-Currently this GPIO controller only supports the mute pin. If needed in the
-future, the HDMI pins support can also be added.
-
-Required properties:
-- compatible: Should contain "rockchip,rk3328-grf-gpio".
-- gpio-controller: Marks the device node as a gpio controller.
-- #gpio-cells: Should be 2. The first cell is the pin number and
- the second cell is used to specify the gpio polarity:
- 0 = Active high,
- 1 = Active low.
-
-Example:
-
- grf: syscon@ff100000 {
- compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
-
- grf_gpio: grf-gpio {
- compatible = "rockchip,rk3328-grf-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
- };
-
-Note: The grf_gpio node should be declared as the child of the GRF (General
-Register File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>.
diff --git a/Bindings/gpio/rockchip,rk3328-grf-gpio.yaml b/Bindings/gpio/rockchip,rk3328-grf-gpio.yaml
new file mode 100644
index 0000000..d8cce73
--- /dev/null
+++ b/Bindings/gpio/rockchip,rk3328-grf-gpio.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip RK3328 General Register Files GPIO controller
+
+description:
+ The Rockchip RK3328 General Register File (GRF) outputs only the
+ GPIO_MUTE pin, originally for codec mute control, but it can also be used
+ for general purpose. It is manipulated by the GRF_SOC_CON10 register.
+ If needed in the future support for the HDMI pins can also be added.
+ The GPIO node should be declared as the child of the GRF node.
+
+ The GPIO_MUTE pin is referred to in the format
+
+ <&grf_gpio 0 GPIO_ACTIVE_LOW>
+
+ The first cell is the pin number and
+ the second cell is used to specify the GPIO polarity
+ 0 = Active high
+ 1 = Active low
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ const: rockchip,rk3328-grf-gpio
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+required:
+ - compatible
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ grf_gpio: gpio {
+ compatible = "rockchip,rk3328-grf-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
diff --git a/Bindings/gpio/ti,omap-gpio.yaml b/Bindings/gpio/ti,omap-gpio.yaml
new file mode 100644
index 0000000..7087e4a
--- /dev/null
+++ b/Bindings/gpio/ti,omap-gpio.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/ti,omap-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OMAP GPIO controller bindings
+
+maintainers:
+ - Grygorii Strashko <grygorii.strashko@ti.com>
+
+description: |
+ The general-purpose interface combines general-purpose input/output (GPIO) banks.
+ Each GPIO banks provides up to 32 dedicated general-purpose pins with input
+ and output capabilities; interrupt generation in active mode and wake-up
+ request generation in idle mode upon the detection of external events.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ti,omap2-gpio
+ - ti,omap3-gpio
+ - ti,omap4-gpio
+ - items:
+ - const: ti,am4372-gpio
+ - const: ti,omap4-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ gpio-ranges: true
+
+ gpio-line-names:
+ minItems: 1
+ maxItems: 32
+
+ ti,gpio-always-on:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicates if a GPIO bank is always powered and will never lose its logic state.
+
+ ti,hwmods:
+ $ref: /schemas/types.yaml#/definitions/string
+ deprecated: true
+ description:
+ Name of the hwmod associated with the GPIO. Needed on some legacy OMAP
+ SoCs which have not been converted to the ti,sysc interconnect hierarachy.
+
+ ti,no-reset-on-init:
+ $ref: /schemas/types.yaml#/definitions/flag
+ deprecated: true
+ description:
+ Do not reset on init. Used with ti,hwmods on some legacy OMAP SoCs which
+ have not been converted to the ti,sysc interconnect hierarachy.
+
+patternProperties:
+ "^(.+-hog(-[0-9]+)?)$":
+ type: object
+
+ required:
+ - gpio-hog
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ gpio0: gpio@0 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <96>;
+ ti,gpio-always-on;
+
+ ls-buf-en-hog {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "LS_BUF_EN";
+ };
+ };
diff --git a/Bindings/gpu/arm,mali-bifrost.yaml b/Bindings/gpu/arm,mali-bifrost.yaml
index 894ba21..0f73f43 100644
--- a/Bindings/gpu/arm,mali-bifrost.yaml
+++ b/Bindings/gpu/arm,mali-bifrost.yaml
@@ -17,6 +17,7 @@
items:
- enum:
- amlogic,meson-g12a-mali
+ - mediatek,mt8183-mali
- realtek,rtd1619-mali
- rockchip,px30-mali
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@@ -41,10 +42,13 @@
mali-supply: true
+ sram-supply: true
+
operating-points-v2: true
power-domains:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
resets:
maxItems: 2
@@ -89,6 +93,30 @@
then:
required:
- resets
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8183-mali
+ then:
+ properties:
+ power-domains:
+ minItems: 3
+ power-domain-names:
+ items:
+ - const: core0
+ - const: core1
+ - const: core2
+
+ required:
+ - sram-supply
+ - power-domains
+ - power-domain-names
+ else:
+ properties:
+ power-domains:
+ maxItems: 1
+ sram-supply: false
examples:
- |
diff --git a/Bindings/gpu/brcm,bcm-v3d.yaml b/Bindings/gpu/brcm,bcm-v3d.yaml
index 9d72264..e6485f7 100644
--- a/Bindings/gpu/brcm,bcm-v3d.yaml
+++ b/Bindings/gpu/brcm,bcm-v3d.yaml
@@ -34,7 +34,6 @@
- enum: [ bridge, gca ]
- enum: [ bridge, gca ]
minItems: 2
- maxItems: 4
interrupts:
items:
diff --git a/Bindings/gpu/vivante,gc.yaml b/Bindings/gpu/vivante,gc.yaml
index 3ed1726..93e7244 100644
--- a/Bindings/gpu/vivante,gc.yaml
+++ b/Bindings/gpu/vivante,gc.yaml
@@ -36,7 +36,6 @@
- description: AHB/slave interface clock (only required if GPU can gate
slave interface independently)
minItems: 1
- maxItems: 4
clock-names:
items:
diff --git a/Bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml b/Bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
new file mode 100644
index 0000000..10e5a53
--- /dev/null
+++ b/Bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwlock/allwinner,sun6i-a31-hwspinlock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SUN6I hardware spinlock driver for Allwinner sun6i compatible SoCs
+
+maintainers:
+ - Wilken Gottwalt <wilken.gottwalt@posteo.net>
+
+description:
+ The hardware unit provides semaphores between the ARM cores and the embedded
+ companion core on the SoC.
+
+properties:
+ compatible:
+ const: allwinner,sun6i-a31-hwspinlock
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
+ #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
+
+ hwlock@1c18000 {
+ compatible = "allwinner,sun6i-a31-hwspinlock";
+ reg = <0x01c18000 0x1000>;
+ clocks = <&ccu CLK_BUS_SPINLOCK>;
+ resets = <&ccu RST_BUS_SPINLOCK>;
+ };
+...
diff --git a/Bindings/hwmon/lm75.yaml b/Bindings/hwmon/lm75.yaml
index 96eed5c..72980d0 100644
--- a/Bindings/hwmon/lm75.yaml
+++ b/Bindings/hwmon/lm75.yaml
@@ -30,6 +30,7 @@
- st,stds75
- st,stlm75
- microchip,tcn75
+ - ti,tmp1075
- ti,tmp100
- ti,tmp101
- ti,tmp105
diff --git a/Bindings/i2c/aspeed,i2c.yaml b/Bindings/i2c/aspeed,i2c.yaml
new file mode 100644
index 0000000..ea643e6
--- /dev/null
+++ b/Bindings/i2c/aspeed,i2c.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs Device Tree Bindings
+
+maintainers:
+ - Rayn Chen <rayn_chen@aspeedtech.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-i2c-bus
+ - aspeed,ast2500-i2c-bus
+ - aspeed,ast2600-i2c-bus
+
+ reg:
+ minItems: 1
+ items:
+ - description: address offset and range of bus
+ - description: address offset and range of bus buffer
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ root clock of bus, should reference the APB
+ clock in the second cell
+
+ resets:
+ maxItems: 1
+
+ bus-frequency:
+ minimum: 500
+ maximum: 4000000
+ default: 100000
+ description: frequency of the bus clock in Hz defaults to 100 kHz when not
+ specified
+
+ multi-master:
+ type: boolean
+ description:
+ states that there is another master active on this bus
+
+required:
+ - reg
+ - compatible
+ - clocks
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+ i2c0: i2c-bus@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ reg = <0x40 0x40>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <0>;
+ interrupt-parent = <&i2c_ic>;
+ };
diff --git a/Bindings/i2c/brcm,brcmstb-i2c.yaml b/Bindings/i2c/brcm,brcmstb-i2c.yaml
index edbca24..7070c04 100644
--- a/Bindings/i2c/brcm,brcmstb-i2c.yaml
+++ b/Bindings/i2c/brcm,brcmstb-i2c.yaml
@@ -21,7 +21,6 @@
reg:
minItems: 1
- maxItems: 2
items:
- description: BSC register range
- description: Auto-I2C register range
diff --git a/Bindings/i2c/i2c-aspeed.txt b/Bindings/i2c/i2c-aspeed.txt
deleted file mode 100644
index b47f6cc..0000000
--- a/Bindings/i2c/i2c-aspeed.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Device tree configuration for the I2C busses on the AST24XX, AST25XX, and AST26XX SoCs.
-
-Required Properties:
-- #address-cells : should be 1
-- #size-cells : should be 0
-- reg : address offset and range of bus
-- compatible : should be "aspeed,ast2400-i2c-bus"
- or "aspeed,ast2500-i2c-bus"
- or "aspeed,ast2600-i2c-bus"
-- clocks : root clock of bus, should reference the APB
- clock in the second cell
-- resets : phandle to reset controller with the reset number in
- the second cell
-- interrupts : interrupt number
-
-Optional Properties:
-- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
- specified
-- multi-master : states that there is another master active on this bus.
-
-Example:
-
-i2c {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1e78a000 0x1000>;
-
- i2c_ic: interrupt-controller@0 {
- #interrupt-cells = <1>;
- compatible = "aspeed,ast2400-i2c-ic";
- reg = <0x0 0x40>;
- interrupts = <12>;
- interrupt-controller;
- };
-
- i2c0: i2c-bus@40 {
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- reg = <0x40 0x40>;
- compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&syscon ASPEED_CLK_APB>;
- resets = <&syscon ASPEED_RESET_I2C>;
- bus-frequency = <100000>;
- interrupts = <0>;
- interrupt-parent = <&i2c_ic>;
- };
-};
diff --git a/Bindings/i2c/i2c-at91.txt b/Bindings/i2c/i2c-at91.txt
index 96c914e..2015f50 100644
--- a/Bindings/i2c/i2c-at91.txt
+++ b/Bindings/i2c/i2c-at91.txt
@@ -73,7 +73,7 @@
pinctrl-0 = <&pinctrl_i2c0>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
- scl-gpios = <&pioA 31 GPIO_ACTIVE_HIGH>;
+ scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
wm8731: wm8731@1a {
compatible = "wm8731";
diff --git a/Bindings/i2c/i2c-davinci.txt b/Bindings/i2c/i2c-davinci.txt
index b745f37..6590501 100644
--- a/Bindings/i2c/i2c-davinci.txt
+++ b/Bindings/i2c/i2c-davinci.txt
@@ -8,7 +8,7 @@
- reg : Offset and length of the register set for the device
- clocks: I2C functional clock phandle.
For 66AK2G this property should be set per binding,
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
SoC-specific Required Properties:
@@ -17,7 +17,7 @@
- power-domains: Should contain a phandle to a PM domain provider node
and an args specifier containing the I2C device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Recommended properties :
- interrupts : standard interrupt property.
diff --git a/Bindings/i2c/i2c-demux-pinctrl.txt b/Bindings/i2c/i2c-demux-pinctrl.txt
index 81b5d55..86b2e43 100644
--- a/Bindings/i2c/i2c-demux-pinctrl.txt
+++ b/Bindings/i2c/i2c-demux-pinctrl.txt
@@ -27,7 +27,7 @@
- i2c-bus-name: The name of this bus. Also needed as pinctrl-name for the I2C
parents.
-Furthermore, I2C mux properties and child nodes. See i2c-mux.txt in this
+Furthermore, I2C mux properties and child nodes. See i2c-mux.yaml in this
directory.
Example:
diff --git a/Bindings/i2c/i2c-mt65xx.txt b/Bindings/i2c/i2c-mt65xx.txt
index 7f0194f..5ea216a 100644
--- a/Bindings/i2c/i2c-mt65xx.txt
+++ b/Bindings/i2c/i2c-mt65xx.txt
@@ -15,6 +15,7 @@
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
"mediatek,mt8192-i2c": for MediaTek MT8192
+ "mediatek,mt8195-i2c", "mediatek,mt8192-i2c": for MediaTek MT8195
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
@@ -32,6 +33,7 @@
- mediatek,have-pmic: platform can control i2c form special pmic side.
Only mt6589 and mt8135 support this feature.
- mediatek,use-push-pull: IO config use push-pull mode.
+ - vbus-supply: phandle to the regulator that provides power to SCL/SDA.
Example:
diff --git a/Bindings/i2c/i2c-mux-gpio.txt b/Bindings/i2c/i2c-mux-gpio.txt
index 21da3ec..d4cf105 100644
--- a/Bindings/i2c/i2c-mux-gpio.txt
+++ b/Bindings/i2c/i2c-mux-gpio.txt
@@ -22,8 +22,8 @@
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
- mux-gpios: list of gpios used to control the muxer
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.yaml in this directory.
+* I2C child bus nodes. See i2c-mux.yaml in this directory.
Optional properties:
- idle-state: value to set the muxer to when idle. When no value is
@@ -62,7 +62,6 @@
reg = <0x3c>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7 1>;
- reset-active-low;
};
};
diff --git a/Bindings/i2c/i2c-mux-gpmux.txt b/Bindings/i2c/i2c-mux-gpmux.txt
deleted file mode 100644
index 8b444b9..0000000
--- a/Bindings/i2c/i2c-mux-gpmux.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-General Purpose I2C Bus Mux
-
-This binding describes an I2C bus multiplexer that uses a mux controller
-from the mux subsystem to route the I2C signals.
-
- .-----. .-----.
- | dev | | dev |
- .------------. '-----' '-----'
- | SoC | | |
- | | .--------+--------'
- | .------. | .------+ child bus A, on MUX value set to 0
- | | I2C |-|--| Mux |
- | '------' | '--+---+ child bus B, on MUX value set to 1
- | .------. | | '----------+--------+--------.
- | | MUX- | | | | | |
- | | Ctrl |-|-----+ .-----. .-----. .-----.
- | '------' | | dev | | dev | | dev |
- '------------' '-----' '-----' '-----'
-
-Required properties:
-- compatible: i2c-mux
-- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
- port is connected to.
-- mux-controls: The phandle of the mux controller to use for operating the
- mux.
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number
- is also the mux-controller state described in ../mux/mux-controller.txt
-
-Optional properties:
-- mux-locked: If present, explicitly allow unrelated I2C transactions on the
- parent I2C adapter at these times:
- + during setup of the multiplexer
- + between setup of the multiplexer and the child bus I2C transaction
- + between the child bus I2C transaction and releasing of the multiplexer
- + during releasing of the multiplexer
- However, I2C transactions to devices behind all I2C multiplexers connected
- to the same parent adapter that this multiplexer is connected to are blocked
- for the full duration of the complete multiplexed I2C transaction (i.e.
- including the times covered by the above list).
- If mux-locked is not present, the multiplexer is assumed to be parent-locked.
- This means that no unrelated I2C transactions are allowed on the parent I2C
- adapter for the complete multiplexed I2C transaction.
- The properties of mux-locked and parent-locked multiplexers are discussed
- in more detail in Documentation/i2c/i2c-topology.rst.
-
-For each i2c child node, an I2C child bus will be created. They will
-be numbered based on their order in the device tree.
-
-Whenever an access is made to a device on a child bus, the value set
-in the relevant node's reg property will be set as the state in the
-mux controller.
-
-Example:
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- i2c-mux {
- compatible = "i2c-mux";
- mux-locked;
- i2c-parent = <&i2c1>;
-
- mux-controls = <&mux>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ssd1307: oled@3c {
- compatible = "solomon,ssd1307fb-i2c";
- reg = <0x3c>;
- pwms = <&pwm 4 3000>;
- reset-gpios = <&gpio2 7 1>;
- reset-active-low;
- };
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pca9555: pca9555@20 {
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
- };
- };
- };
diff --git a/Bindings/i2c/i2c-mux-gpmux.yaml b/Bindings/i2c/i2c-mux-gpmux.yaml
new file mode 100644
index 0000000..9b0603a
--- /dev/null
+++ b/Bindings/i2c/i2c-mux-gpmux.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: General Purpose I2C Bus Mux
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ This binding describes an I2C bus multiplexer that uses a mux controller
+ from the mux subsystem to route the I2C signals.
+
+ .-----. .-----.
+ | dev | | dev |
+ .------------. '-----' '-----'
+ | SoC | | |
+ | | .--------+--------'
+ | .------. | .------+ child bus A, on MUX value set to 0
+ | | I2C |-|--| Mux |
+ | '------' | '--+---+ child bus B, on MUX value set to 1
+ | .------. | | '----------+--------+--------.
+ | | MUX- | | | | | |
+ | | Ctrl |-|-----+ .-----. .-----. .-----.
+ | '------' | | dev | | dev | | dev |
+ '------------' '-----' '-----' '-----'
+
+
+
+allOf:
+ - $ref: /schemas/i2c/i2c-mux.yaml#
+
+properties:
+ compatible:
+ const: i2c-mux
+
+ i2c-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle of the I2C bus that this multiplexer's master-side port is
+ connected to.
+
+ mux-controls:
+ maxItems: 1
+ description:
+ The mux-controller states are the I2C sub-bus numbers.
+
+ mux-locked:
+ type: boolean
+ description: |
+ Explicitly allow unrelated I2C transactions on the parent I2C adapter at
+ these times:
+ - during setup of the multiplexer
+ - between setup of the multiplexer and the child bus I2C transaction
+ - between the child bus I2C transaction and releasing of the multiplexer
+ - during releasing of the multiplexer
+
+ However, I2C transactions to devices behind all I2C multiplexers connected
+ to the same parent adapter that this multiplexer is connected to are blocked
+ for the full duration of the complete multiplexed I2C transaction (i.e.
+ including the times covered by the above list).
+ If mux-locked is not present, the multiplexer is assumed to be parent-locked.
+ This means that no unrelated I2C transactions are allowed on the parent I2C
+ adapter for the complete multiplexed I2C transaction.
+ The properties of mux-locked and parent-locked multiplexers are discussed
+ in more detail in Documentation/i2c/i2c-topology.rst.
+
+required:
+ - compatible
+ - i2c-parent
+ - mux-controls
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ mux-locked;
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ };
+...
diff --git a/Bindings/i2c/i2c-mux-ltc4306.txt b/Bindings/i2c/i2c-mux-ltc4306.txt
index 8b1e49c..29c4550 100644
--- a/Bindings/i2c/i2c-mux-ltc4306.txt
+++ b/Bindings/i2c/i2c-mux-ltc4306.txt
@@ -8,8 +8,8 @@
The following required properties are defined externally:
- - Standard I2C mux properties. See i2c-mux.txt in this directory.
- - I2C child bus nodes. See i2c-mux.txt in this directory.
+ - Standard I2C mux properties. See i2c-mux.yaml in this directory.
+ - I2C child bus nodes. See i2c-mux.yaml in this directory.
Optional Properties:
diff --git a/Bindings/i2c/i2c-mux-pca954x.txt b/Bindings/i2c/i2c-mux-pca954x.txt
deleted file mode 100644
index 7abda50..0000000
--- a/Bindings/i2c/i2c-mux-pca954x.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-* NXP PCA954x I2C bus switch
-
-The driver supports NXP PCA954x and PCA984x I2C mux/switch devices.
-
-Required Properties:
-
- - compatible: Must contain one of the following.
- "nxp,pca9540",
- "nxp,pca9542",
- "nxp,pca9543",
- "nxp,pca9544",
- "nxp,pca9545",
- "nxp,pca9546", "nxp,pca9846",
- "nxp,pca9547", "nxp,pca9847",
- "nxp,pca9548", "nxp,pca9848",
- "nxp,pca9849"
-
- - reg: The I2C address of the device.
-
- The following required properties are defined externally:
-
- - Standard I2C mux properties. See i2c-mux.txt in this directory.
- - I2C child bus nodes. See i2c-mux.txt in this directory.
-
-Optional Properties:
-
- - reset-gpios: Reference to the GPIO connected to the reset input.
- - idle-state: if present, overrides i2c-mux-idle-disconnect,
- Please refer to Documentation/devicetree/bindings/mux/mux-controller.txt
- - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
- children in idle state. This is necessary for example, if there are several
- multiplexers on the bus and the devices behind them use same I2C addresses.
- - interrupts: Interrupt mapping for IRQ.
- - interrupt-controller: Marks the device node as an interrupt controller.
- - #interrupt-cells : Should be two.
- - first cell is the pin number
- - second cell is used to specify flags.
- See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-Example:
-
- i2c-switch@74 {
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x74>;
-
- interrupt-parent = <&ipic>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- eeprom@54 {
- compatible = "atmel,24c08";
- reg = <0x54>;
- };
- };
-
- i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
- };
diff --git a/Bindings/i2c/i2c-mux-pca954x.yaml b/Bindings/i2c/i2c-mux-pca954x.yaml
new file mode 100644
index 0000000..9f1726d
--- /dev/null
+++ b/Bindings/i2c/i2c-mux-pca954x.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP PCA954x I2C bus switch
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description:
+ The binding supports NXP PCA954x and PCA984x I2C mux/switch devices.
+
+allOf:
+ - $ref: /schemas/i2c/i2c-mux.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nxp,pca9540
+ - nxp,pca9542
+ - nxp,pca9543
+ - nxp,pca9544
+ - nxp,pca9545
+ - nxp,pca9546
+ - nxp,pca9547
+ - nxp,pca9548
+ - nxp,pca9846
+ - nxp,pca9847
+ - nxp,pca9848
+ - nxp,pca9849
+ - items:
+ - const: nxp,pca9646
+ - const: nxp,pca9546
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupt-controller: true
+
+ reset-gpios:
+ maxItems: 1
+
+ i2c-mux-idle-disconnect:
+ type: boolean
+ description: Forces mux to disconnect all children in idle state. This is
+ necessary for example, if there are several multiplexers on the bus and
+ the devices behind them use same I2C addresses.
+
+ idle-state:
+ description: if present, overrides i2c-mux-idle-disconnect
+ $ref: /schemas/mux/mux-controller.yaml#/properties/idle-state
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+
+ interrupt-parent = <&ipic>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/i2c/i2c-mux-pinctrl.txt b/Bindings/i2c/i2c-mux-pinctrl.txt
index 33119a9..997a287 100644
--- a/Bindings/i2c/i2c-mux-pinctrl.txt
+++ b/Bindings/i2c/i2c-mux-pinctrl.txt
@@ -28,9 +28,9 @@
* Standard pinctrl properties that specify the pin mux state for each child
bus. See ../pinctrl/pinctrl-bindings.txt.
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.yaml in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory.
+* I2C child bus nodes. See i2c-mux.yaml in this directory.
For each named state defined in the pinctrl-names property, an I2C child bus
will be created. I2C child bus numbers are assigned based on the index into
diff --git a/Bindings/i2c/i2c-mux-reg.txt b/Bindings/i2c/i2c-mux-reg.txt
index de00d7f..b9d9755 100644
--- a/Bindings/i2c/i2c-mux-reg.txt
+++ b/Bindings/i2c/i2c-mux-reg.txt
@@ -7,8 +7,8 @@
- compatible: i2c-mux-reg
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.yaml in this directory.
+* I2C child bus nodes. See i2c-mux.yaml in this directory.
Optional properties:
- reg: this pair of <offset size> specifies the register to control the mux.
diff --git a/Bindings/i2c/i2c-mux.txt b/Bindings/i2c/i2c-mux.txt
deleted file mode 100644
index b38f58a..0000000
--- a/Bindings/i2c/i2c-mux.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-Common i2c bus multiplexer/switch properties.
-
-An i2c bus multiplexer/switch will have several child busses that are
-numbered uniquely in a device dependent manner. The nodes for an i2c bus
-multiplexer/switch will have one child node for each child bus.
-
-Optional properties:
-- #address-cells = <1>;
- This property is required if the i2c-mux child node does not exist.
-
-- #size-cells = <0>;
- This property is required if the i2c-mux child node does not exist.
-
-- i2c-mux
- For i2c multiplexers/switches that have child nodes that are a mixture
- of both i2c child busses and other child nodes, the 'i2c-mux' subnode
- can be used for populating the i2c child busses. If an 'i2c-mux'
- subnode is present, only subnodes of this will be considered as i2c
- child busses.
-
-Required properties for the i2c-mux child node:
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Required properties for i2c child bus nodes:
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg : The sub-bus number.
-
-Optional properties for i2c child bus nodes:
-- Other properties specific to the multiplexer/switch hardware.
-- Child nodes conforming to i2c bus binding
-
-
-Example :
-
- /*
- An NXP pca9548 8 channel I2C multiplexer at address 0x70
- with two NXP pca8574 GPIO expanders attached, one each to
- ports 3 and 4.
- */
-
- mux@70 {
- compatible = "nxp,pca9548";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- gpio1: gpio@38 {
- compatible = "nxp,pca8574";
- reg = <0x38>;
- #gpio-cells = <2>;
- gpio-controller;
- };
- };
- i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
-
- gpio2: gpio@38 {
- compatible = "nxp,pca8574";
- reg = <0x38>;
- #gpio-cells = <2>;
- gpio-controller;
- };
- };
- };
diff --git a/Bindings/i2c/i2c-mux.yaml b/Bindings/i2c/i2c-mux.yaml
new file mode 100644
index 0000000..24cac36
--- /dev/null
+++ b/Bindings/i2c/i2c-mux.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common i2c bus multiplexer/switch properties.
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ An i2c bus multiplexer/switch will have several child busses that are numbered
+ uniquely in a device dependent manner. The nodes for an i2c bus
+ multiplexer/switch will have one child node for each child bus.
+
+ For i2c multiplexers/switches that have child nodes that are a mixture of both
+ i2c child busses and other child nodes, the 'i2c-mux' subnode can be used for
+ populating the i2c child busses. If an 'i2c-mux' subnode is present, only
+ subnodes of this will be considered as i2c child busses.
+
+properties:
+ $nodename:
+ pattern: '^(i2c-?)?mux'
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^i2c@[0-9a-f]+$':
+ $ref: /schemas/i2c/i2c-controller.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description: The mux selector sub-bus number for the child I2C bus.
+ maxItems: 1
+
+additionalProperties: true
+
+examples:
+ - |
+ /*
+ * An NXP pca9548 8 channel I2C multiplexer at address 0x70
+ * with two NXP pca8574 GPIO expanders attached, one each to
+ * ports 3 and 4.
+ */
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/i2c/i2c-omap.txt b/Bindings/i2c/i2c-omap.txt
deleted file mode 100644
index a425b91..0000000
--- a/Bindings/i2c/i2c-omap.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-I2C for OMAP platforms
-
-Required properties :
-- compatible : Must be
- "ti,omap2420-i2c" for OMAP2420 SoCs
- "ti,omap2430-i2c" for OMAP2430 SoCs
- "ti,omap3-i2c" for OMAP3 SoCs
- "ti,omap4-i2c" for OMAP4+ SoCs
- "ti,am654-i2c", "ti,omap4-i2c" for AM654 SoCs
- "ti,j721e-i2c", "ti,omap4-i2c" for J721E SoCs
- "ti,am64-i2c", "ti,omap4-i2c" for AM64 SoCs
-- ti,hwmods : Must be "i2c<n>", n being the instance number (1-based)
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Recommended properties :
-- clock-frequency : Desired I2C bus clock frequency in Hz. Otherwise
- the default 100 kHz frequency will be used.
-
-Optional properties:
-- Child nodes conforming to i2c bus binding
-
-Note: Current implementation will fetch base address, irq and dma
-from omap hwmod data base during device registration.
-Future plan is to migrate hwmod data base contents into device tree
-blob so that, all the required data will be used from device tree dts
-file.
-
-Examples :
-
-i2c1: i2c@0 {
- compatible = "ti,omap3-i2c";
- #address-cells = <1>;
- #size-cells = <0>;
- ti,hwmods = "i2c1";
- clock-frequency = <400000>;
-};
diff --git a/Bindings/i2c/i2c-pxa-pci-ce4100.txt b/Bindings/i2c/i2c-pxa-pci-ce4100.txt
index 569b162..1ff6f84 100644
--- a/Bindings/i2c/i2c-pxa-pci-ce4100.txt
+++ b/Bindings/i2c/i2c-pxa-pci-ce4100.txt
@@ -71,7 +71,7 @@
/* This I2C controller has one gpio controller */
gpio@26 {
#gpio-cells = <2>;
- compatible = "ti,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
};
@@ -85,7 +85,7 @@
gpio@26 {
#gpio-cells = <2>;
- compatible = "ti,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
};
diff --git a/Bindings/i2c/i2c-qcom-cci.txt b/Bindings/i2c/i2c-qcom-cci.txt
index c6668b7..7b9fc0c 100644
--- a/Bindings/i2c/i2c-qcom-cci.txt
+++ b/Bindings/i2c/i2c-qcom-cci.txt
@@ -9,6 +9,7 @@
"qcom,msm8916-cci"
"qcom,msm8996-cci"
"qcom,sdm845-cci"
+ "qcom,sm8250-cci"
- reg
Usage: required
@@ -41,8 +42,8 @@
SUBNODES:
-The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996 and
-sdm845), described as subdevices named "i2c-bus@0" and "i2c-bus@1".
+The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996,
+sdm845 and sm8250), described as subdevices named "i2c-bus@0" and "i2c-bus@1".
PROPERTIES:
diff --git a/Bindings/i2c/i2c-rk3x.yaml b/Bindings/i2c/i2c-rk3x.yaml
index 7f254d7..5339dd4 100644
--- a/Bindings/i2c/i2c-rk3x.yaml
+++ b/Bindings/i2c/i2c-rk3x.yaml
@@ -36,6 +36,7 @@
- rockchip,px30-i2c
- rockchip,rk3308-i2c
- rockchip,rk3328-i2c
+ - rockchip,rk3568-i2c
- const: rockchip,rk3399-i2c
reg:
diff --git a/Bindings/i2c/i2c.txt b/Bindings/i2c/i2c.txt
index df41f72..b864916 100644
--- a/Bindings/i2c/i2c.txt
+++ b/Bindings/i2c/i2c.txt
@@ -89,8 +89,11 @@
- smbus
states that additional SMBus restrictions and features apply to this bus.
- Examples of features are SMBusHostNotify and SMBusAlert. Examples of
- restrictions are more reserved addresses and timeout definitions.
+ An example of feature is SMBusHostNotify. Examples of restrictions are
+ more reserved addresses and timeout definitions.
+
+- smbus-alert
+ states that the optional SMBus-Alert feature apply to this bus.
Required properties (per child device)
--------------------------------------
diff --git a/Bindings/i2c/marvell,mv64xxx-i2c.yaml b/Bindings/i2c/marvell,mv64xxx-i2c.yaml
index eb72dd5..f771c09 100644
--- a/Bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -43,14 +43,12 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: Reference clock for the I2C bus
- description: Bus clock (Only for Armada 7K/8K)
clock-names:
minItems: 1
- maxItems: 2
items:
- const: core
- const: reg
diff --git a/Bindings/i2c/mellanox,i2c-mlxbf.yaml b/Bindings/i2c/mellanox,i2c-mlxbf.yaml
index d2b401d..93198d5 100644
--- a/Bindings/i2c/mellanox,i2c-mlxbf.yaml
+++ b/Bindings/i2c/mellanox,i2c-mlxbf.yaml
@@ -20,7 +20,6 @@
reg:
minItems: 3
- maxItems: 4
items:
- description: Smbus block registers
- description: Cause master registers
diff --git a/Bindings/i2c/renesas,i2c.txt b/Bindings/i2c/renesas,i2c.txt
deleted file mode 100644
index 5762d2d..0000000
--- a/Bindings/i2c/renesas,i2c.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-I2C for R-Car platforms
-
-Required properties:
-- compatible:
- "renesas,i2c-r8a7742" if the device is a part of a R8A7742 SoC.
- "renesas,i2c-r8a7743" if the device is a part of a R8A7743 SoC.
- "renesas,i2c-r8a7744" if the device is a part of a R8A7744 SoC.
- "renesas,i2c-r8a7745" if the device is a part of a R8A7745 SoC.
- "renesas,i2c-r8a77470" if the device is a part of a R8A77470 SoC.
- "renesas,i2c-r8a774a1" if the device is a part of a R8A774A1 SoC.
- "renesas,i2c-r8a774b1" if the device is a part of a R8A774B1 SoC.
- "renesas,i2c-r8a774c0" if the device is a part of a R8A774C0 SoC.
- "renesas,i2c-r8a774e1" if the device is a part of a R8A774E1 SoC.
- "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
- "renesas,i2c-r8a7779" if the device is a part of a R8A7779 SoC.
- "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
- "renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC.
- "renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC.
- "renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC.
- "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
- "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
- "renesas,i2c-r8a7796" if the device is a part of a R8A77960 SoC.
- "renesas,i2c-r8a77961" if the device is a part of a R8A77961 SoC.
- "renesas,i2c-r8a77965" if the device is a part of a R8A77965 SoC.
- "renesas,i2c-r8a77970" if the device is a part of a R8A77970 SoC.
- "renesas,i2c-r8a77980" if the device is a part of a R8A77980 SoC.
- "renesas,i2c-r8a77990" if the device is a part of a R8A77990 SoC.
- "renesas,i2c-r8a77995" if the device is a part of a R8A77995 SoC.
- "renesas,i2c-r8a779a0" if the device is a part of a R8A779A0 SoC.
- "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
- "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 or RZ/G1 compatible
- device.
- "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 or RZ/G2 compatible
- device.
- "renesas,i2c-rcar" (deprecated)
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first followed
- by the generic version.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-- interrupts: interrupt specifier.
-
-Optional properties:
-- clock-frequency: desired I2C bus clock frequency in Hz. The absence of this
- property indicates the default frequency 100 kHz.
-- clocks: clock specifier.
-- dmas: Must contain a list of two references to DMA specifiers, one for
- transmission, and one for reception.
-- dma-names: Must contain a list of two DMA names, "tx" and "rx".
-
-- i2c-scl-falling-time-ns: see i2c.txt
-- i2c-scl-internal-delay-ns: see i2c.txt
-- i2c-scl-rising-time-ns: see i2c.txt
-
-Examples :
-
-i2c0: i2c@e6508000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
- reg = <0 0xe6508000 0 0x40>;
- interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
- clock-frequency = <400000>;
-};
diff --git a/Bindings/i2c/renesas,iic-emev2.txt b/Bindings/i2c/renesas,iic-emev2.txt
deleted file mode 100644
index 5ed1ea1..0000000
--- a/Bindings/i2c/renesas,iic-emev2.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Device tree configuration for Renesas EMEV2 IIC controller
-
-Required properties:
-- compatible : "renesas,iic-emev2"
-- reg : address start and address range size of device
-- interrupts : specifier for the IIC controller interrupt
-- clocks : phandle to the IP core SCLK
-- clock-names : must be "sclk"
-- #address-cells : should be <1>
-- #size-cells : should be <0>
-
-Example:
-
- iic0: i2c@e0070000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "renesas,iic-emev2";
- reg = <0xe0070000 0x28>;
- interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
- clocks = <&iic0_sclk>;
- clock-names = "sclk";
- };
diff --git a/Bindings/i2c/renesas,iic-emev2.yaml b/Bindings/i2c/renesas,iic-emev2.yaml
new file mode 100644
index 0000000..17c1102
--- /dev/null
+++ b/Bindings/i2c/renesas,iic-emev2.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/renesas,iic-emev2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile EV2 IIC Interface
+
+maintainers:
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ const: renesas,iic-emev2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: sclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - '#address-cells'
+ - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ iic0: i2c@e0070000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-emev2";
+ reg = <0xe0070000 0x28>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&iic0_sclk>;
+ clock-names = "sclk";
+ };
diff --git a/Bindings/i2c/renesas,iic.txt b/Bindings/i2c/renesas,iic.txt
deleted file mode 100644
index 93d4128..0000000
--- a/Bindings/i2c/renesas,iic.txt
+++ /dev/null
@@ -1,72 +0,0 @@
-Device tree configuration for Renesas IIC (sh_mobile) driver
-
-Required properties:
-- compatible :
- - "renesas,iic-r8a73a4" (R-Mobile APE6)
- - "renesas,iic-r8a7740" (R-Mobile A1)
- - "renesas,iic-r8a7742" (RZ/G1H)
- - "renesas,iic-r8a7743" (RZ/G1M)
- - "renesas,iic-r8a7744" (RZ/G1N)
- - "renesas,iic-r8a7745" (RZ/G1E)
- - "renesas,iic-r8a774a1" (RZ/G2M)
- - "renesas,iic-r8a774b1" (RZ/G2N)
- - "renesas,iic-r8a774c0" (RZ/G2E)
- - "renesas,iic-r8a774e1" (RZ/G2H)
- - "renesas,iic-r8a7790" (R-Car H2)
- - "renesas,iic-r8a7791" (R-Car M2-W)
- - "renesas,iic-r8a7792" (R-Car V2H)
- - "renesas,iic-r8a7793" (R-Car M2-N)
- - "renesas,iic-r8a7794" (R-Car E2)
- - "renesas,iic-r8a7795" (R-Car H3)
- - "renesas,iic-r8a7796" (R-Car M3-W)
- - "renesas,iic-r8a77961" (R-Car M3-W+)
- - "renesas,iic-r8a77965" (R-Car M3-N)
- - "renesas,iic-r8a77990" (R-Car E3)
- - "renesas,iic-sh73a0" (SH-Mobile AG5)
- - "renesas,rcar-gen2-iic" (generic R-Car Gen2 or RZ/G1
- compatible device)
- - "renesas,rcar-gen3-iic" (generic R-Car Gen3 or RZ/G2
- compatible device)
- - "renesas,rmobile-iic" (generic device)
-
- When compatible with a generic R-Car version, nodes
- must list the SoC-specific version corresponding to
- the platform first followed by the generic R-Car
- version.
-
- When compatible with "renesas,rmobile-iic" it should
- be the last compatibility string listed.
-
- The r8a77990 (R-Car E3) and r8a774c0 (RZ/G2E)
- controllers are not considered compatible with
- "renesas,rcar-gen3-iic" or "renesas,rmobile-iic"
- due to the absence of automatic transmission registers.
-
-- reg : address start and address range size of device
-- interrupts : interrupt of device
-- clocks : clock for device
-- #address-cells : should be <1>
-- #size-cells : should be <0>
-
-Optional properties:
-- clock-frequency : frequency of bus clock in Hz. Default 100kHz if unset.
-- dmas : Must contain a list of two references to DMA
- specifiers, one for transmission, and one for
- reception.
-- dma-names : Must contain a list of two DMA names, "tx" and "rx".
-
-
-Pinctrl properties might be needed, too. See there.
-
-Example:
-
- iic0: i2c@e6500000 {
- compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
- "renesas,rmobile-iic";
- reg = <0 0xe6500000 0 0x425>;
- interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
- clock-frequency = <400000>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
diff --git a/Bindings/i2c/renesas,rcar-i2c.yaml b/Bindings/i2c/renesas,rcar-i2c.yaml
new file mode 100644
index 0000000..052aad4
--- /dev/null
+++ b/Bindings/i2c/renesas,rcar-i2c.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car I2C Controller
+
+maintainers:
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,i2c-r8a7778 # R-Car M1A
+ - renesas,i2c-r8a7779 # R-Car H1
+ - const: renesas,rcar-gen1-i2c # R-Car Gen1
+
+ - items:
+ - enum:
+ - renesas,i2c-r8a7742 # RZ/G1H
+ - renesas,i2c-r8a7743 # RZ/G1M
+ - renesas,i2c-r8a7744 # RZ/G1N
+ - renesas,i2c-r8a7745 # RZ/G1E
+ - renesas,i2c-r8a77470 # RZ/G1C
+ - renesas,i2c-r8a7790 # R-Car H2
+ - renesas,i2c-r8a7791 # R-Car M2-W
+ - renesas,i2c-r8a7792 # R-Car V2H
+ - renesas,i2c-r8a7793 # R-Car M2-N
+ - renesas,i2c-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1
+
+ - items:
+ - enum:
+ - renesas,i2c-r8a774a1 # RZ/G2M
+ - renesas,i2c-r8a774b1 # RZ/G2N
+ - renesas,i2c-r8a774c0 # RZ/G2E
+ - renesas,i2c-r8a774e1 # RZ/G2H
+ - renesas,i2c-r8a7795 # R-Car H3
+ - renesas,i2c-r8a7796 # R-Car M3-W
+ - renesas,i2c-r8a77961 # R-Car M3-W+
+ - renesas,i2c-r8a77965 # R-Car M3-N
+ - renesas,i2c-r8a77970 # R-Car V3M
+ - renesas,i2c-r8a77980 # R-Car V3H
+ - renesas,i2c-r8a77990 # R-Car E3
+ - renesas,i2c-r8a77995 # R-Car D3
+ - renesas,i2c-r8a779a0 # R-Car V3U
+ - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-frequency:
+ description:
+ Desired I2C bus clock frequency in Hz. The absence of this property
+ indicates the default frequency 100 kHz.
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ minItems: 2
+ maxItems: 4
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+ i2c-scl-falling-time-ns:
+ default: 35
+ description:
+ Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
+ specification.
+
+ i2c-scl-internal-delay-ns:
+ default: 50
+ description:
+ Number of nanoseconds the IP core additionally needs to setup SCL.
+
+ i2c-scl-rising-time-ns:
+ default: 200
+ description:
+ Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
+ specification.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen1-i2c
+ - renesas,rcar-gen2-i2c
+ then:
+ properties:
+ dmas: false
+ dma-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-i2c
+ - renesas,rcar-gen3-i2c
+ then:
+ required:
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ i2c0: i2c@e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
+ reg = <0xe6508000 0x40>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <400000>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ i2c-scl-internal-delay-ns = <6>;
+ };
diff --git a/Bindings/i2c/renesas,riic.txt b/Bindings/i2c/renesas,riic.txt
deleted file mode 100644
index e26fe3a..0000000
--- a/Bindings/i2c/renesas,riic.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Device tree configuration for Renesas RIIC driver
-
-Required properties:
-- compatible :
- "renesas,riic-r7s72100" if the device is a part of a R7S72100 SoC.
- "renesas,riic-r7s9210" if the device is a part of a R7S9210 SoC.
- "renesas,riic-rz" for a generic RZ/A compatible device.
-- reg : address start and address range size of device
-- interrupts : 8 interrupts (TEI, RI, TI, SPI, STI, NAKI, ALI, TMOI)
-- clock-frequency : frequency of bus clock in Hz
-- #address-cells : should be <1>
-- #size-cells : should be <0>
-
-Pinctrl properties might be needed, too. See there.
-
-Example:
-
- i2c0: i2c@fcfee000 {
- compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
- reg = <0xfcfee000 0x44>;
- interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>,
- <0 158 IRQ_TYPE_EDGE_RISING>,
- <0 159 IRQ_TYPE_EDGE_RISING>,
- <0 160 IRQ_TYPE_LEVEL_HIGH>,
- <0 161 IRQ_TYPE_LEVEL_HIGH>,
- <0 162 IRQ_TYPE_LEVEL_HIGH>,
- <0 163 IRQ_TYPE_LEVEL_HIGH>,
- <0 164 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <100000>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
diff --git a/Bindings/i2c/renesas,riic.yaml b/Bindings/i2c/renesas,riic.yaml
new file mode 100644
index 0000000..52d92ec
--- /dev/null
+++ b/Bindings/i2c/renesas,riic.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/renesas,riic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC)
+
+maintainers:
+ - Chris Brandt <chris.brandt@renesas.com>
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,riic-r7s72100 # RZ/A1H
+ - renesas,riic-r7s9210 # RZ/A2M
+ - renesas,riic-r9a07g044 # RZ/G2{L,LC}
+ - const: renesas,riic-rz # RZ/A or RZ/G2L
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Transmit End Interrupt (TEI)
+ - description: Receive Data Full Interrupt (RI)
+ - description: Transmit Data Empty Interrupt (TI)
+ - description: Stop Condition Detection Interrupt (SPI)
+ - description: Start Condition Detection Interrupt (STI)
+ - description: NACK Reception Interrupt (NAKI)
+ - description: Arbitration-Lost Interrupt (ALI)
+ - description: Timeout Interrupt (TMOI)
+
+ clock-frequency:
+ description:
+ Desired I2C bus clock frequency in Hz. The absence of this property
+ indicates the default frequency 100 kHz.
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-frequency
+ - power-domains
+ - '#address-cells'
+ - '#size-cells'
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,riic-r9a07g044
+then:
+ required:
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r7s72100-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ i2c0: i2c@fcfee000 {
+ compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
+ reg = <0xfcfee000 0x44>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
+ clock-frequency = <100000>;
+ power-domains = <&cpg_clocks>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/Bindings/i2c/renesas,rmobile-iic.yaml b/Bindings/i2c/renesas,rmobile-iic.yaml
new file mode 100644
index 0000000..04e4ffd
--- /dev/null
+++ b/Bindings/i2c/renesas,rmobile-iic.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/renesas,rmobile-iic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Mobile I2C Bus Interface (IIC)
+
+maintainers:
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,iic-r8a73a4 # R-Mobile APE6
+ - renesas,iic-r8a7740 # R-Mobile A1
+ - renesas,iic-sh73a0 # SH-Mobile AG5
+ - const: renesas,rmobile-iic # Generic
+
+ - items:
+ - enum:
+ - renesas,iic-r8a7742 # RZ/G1H
+ - renesas,iic-r8a7743 # RZ/G1M
+ - renesas,iic-r8a7744 # RZ/G1N
+ - renesas,iic-r8a7745 # RZ/G1E
+ - renesas,iic-r8a7790 # R-Car H2
+ - renesas,iic-r8a7791 # R-Car M2-W
+ - renesas,iic-r8a7792 # R-Car V2H
+ - renesas,iic-r8a7793 # R-Car M2-N
+ - renesas,iic-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-iic # R-Car Gen2 and RZ/G1
+ - const: renesas,rmobile-iic # Generic
+
+ - items:
+ - enum:
+ - renesas,iic-r8a774a1 # RZ/G2M
+ - renesas,iic-r8a774b1 # RZ/G2N
+ - renesas,iic-r8a774c0 # RZ/G2E
+ - renesas,iic-r8a774e1 # RZ/G2H
+ - renesas,iic-r8a7795 # R-Car H3
+ - renesas,iic-r8a7796 # R-Car M3-W
+ - renesas,iic-r8a77961 # R-Car M3-W+
+ - renesas,iic-r8a77965 # R-Car M3-N
+ - renesas,iic-r8a77990 # R-Car E3
+ - const: renesas,rcar-gen3-iic # R-Car Gen3 and RZ/G2
+ - const: renesas,rmobile-iic # Generic
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+
+ clock-frequency:
+ description:
+ Desired I2C bus clock frequency in Hz. The absence of this property
+ indicates the default frequency 100 kHz.
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ minItems: 2
+ maxItems: 4
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - '#address-cells'
+ - '#size-cells'
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,iic-r8a7740
+ - renesas,iic-sh73a0
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: Arbitration Lost Interrupt (ALI)
+ - description: Non-acknowledge Detection Interrupt (TACKI)
+ - description: Wait Interrupt (WAITI)
+ - description: Data Transmit Enable interrupt (DTEI)
+ else:
+ properties:
+ interrupts:
+ items:
+ - description: Single combined interrupt
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,rcar-gen2-iic
+ - renesas,rcar-gen3-iic
+ then:
+ required:
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+
+ iic0: i2c@e6500000 {
+ compatible = "renesas,iic-r8a7790", "renesas,rcar-gen2-iic",
+ "renesas,rmobile-iic";
+ reg = <0xe6500000 0x425>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>;
+ clock-frequency = <400000>;
+ dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/Bindings/i2c/ti,omap4-i2c.yaml b/Bindings/i2c/ti,omap4-i2c.yaml
new file mode 100644
index 0000000..ff165ad
--- /dev/null
+++ b/Bindings/i2c/ti,omap4-i2c.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/ti,omap4-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for I2C controllers on TI's OMAP and K3 SoCs
+
+maintainers:
+ - Vignesh Raghavendra <vigneshr@ti.com>
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ti,omap2420-i2c
+ - ti,omap2430-i2c
+ - ti,omap3-i2c
+ - ti,omap4-i2c
+ - items:
+ - enum:
+ - ti,am4372-i2c
+ - ti,am64-i2c
+ - ti,am654-i2c
+ - ti,j721e-i2c
+ - const: ti,omap4-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+ clock-frequency: true
+
+ power-domains: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ ti,hwmods:
+ description:
+ Must be "i2c<n>", n being the instance number (1-based).
+ This property is applicable only on legacy platforms mainly omap2/3
+ and ti81xx and should not be used on other platforms.
+ $ref: /schemas/types.yaml#/definitions/string
+ deprecated: true
+
+# subnode's properties
+patternProperties:
+ "@[0-9a-f]+$":
+ type: object
+ description:
+ Flash device uses the below defined properties in the subnode.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+if:
+ properties:
+ compatible:
+ oneOf:
+ - const: ti,omap2420-i2c
+ - const: ti,omap2430-i2c
+ - const: ti,omap3-i2c
+ - const: ti,omap4-i2c
+
+then:
+ properties:
+ ti,hwmods:
+ items:
+ - pattern: "^i2c([1-9])$"
+
+else:
+ properties:
+ ti,hwmods: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ main_i2c0: i2c@2000000 {
+ compatible = "ti,j721e-i2c", "ti,omap4-i2c";
+ reg = <0x2000000 0x100>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/Bindings/iio/accel/adi,adis16201.yaml b/Bindings/iio/accel/adi,adis16201.yaml
new file mode 100644
index 0000000..6f8f8a6
--- /dev/null
+++ b/Bindings/iio/accel/adi,adis16201.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/adi,adis16201.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ADIS16201 Dual Axis Inclinometer and similar
+
+maintainers:
+ - Jonathan Cameron <Jonathan.Cameron@huawei.com>
+
+description: |
+ Two similar parts from external interface point of view.
+ SPI interface.
+ https://www.analog.com/en/products/adis16201.html
+ https://www.analog.com/en/products/adis16209.html
+
+properties:
+ compatible:
+ enum:
+ - adi,adis16201
+ - adi,adis16209
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@0 {
+ compatible = "adi,adis16201";
+ reg = <0>;
+ spi-max-frequency = <2500000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+...
diff --git a/Bindings/iio/accel/bosch,bma180.yaml b/Bindings/iio/accel/bosch,bma180.yaml
index 45b3abd..a7e8408 100644
--- a/Bindings/iio/accel/bosch,bma180.yaml
+++ b/Bindings/iio/accel/bosch,bma180.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/iio/accel/bosch,bma180.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Bosch BMA023 / BMA150/ BMA180 / BMA25x / SMB380 triaxial accelerometers
+title: Bosch BMA023 / BMA150/ BMA180 / BMA250 / SMB380 triaxial accelerometers
maintainers:
- Jonathan Cameron <jic23@kernel.org>
@@ -21,7 +21,6 @@
- bosch,bma150
- bosch,bma180
- bosch,bma250
- - bosch,bma254
- bosch,smb380
reg:
diff --git a/Bindings/iio/accel/bosch,bma220.yaml b/Bindings/iio/accel/bosch,bma220.yaml
new file mode 100644
index 0000000..942b23a
--- /dev/null
+++ b/Bindings/iio/accel/bosch,bma220.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/bosch,bma220.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMA220 Trixial Acceleration Sensor
+
+maintainers:
+ - Jonathan Cameron <Jonathan.Cameron@huawei.com>
+
+properties:
+ compatible:
+ enum:
+ - bosch,bma220
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ vdda-supply: true
+ vddd-supply: true
+ vddio-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@0 {
+ compatible = "bosch,bma220";
+ reg = <0>;
+ spi-max-frequency = <2500000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+...
diff --git a/Bindings/iio/accel/bosch,bma255.yaml b/Bindings/iio/accel/bosch,bma255.yaml
index c2efbb8..e830d52 100644
--- a/Bindings/iio/accel/bosch,bma255.yaml
+++ b/Bindings/iio/accel/bosch,bma255.yaml
@@ -18,6 +18,8 @@
enum:
- bosch,bmc150_accel
- bosch,bmi055_accel
+ - bosch,bma253
+ - bosch,bma254
- bosch,bma255
- bosch,bma250e
- bosch,bma222
@@ -31,7 +33,12 @@
vddio-supply: true
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
+ description: |
+ The first interrupt listed must be the one connected to the INT1 pin,
+ the second (optional) interrupt listed must be the one connected to the
+ INT2 pin (if available).
mount-matrix:
description: an optional 3x3 mounting rotation matrix.
diff --git a/Bindings/iio/accel/fsl,mma7455.yaml b/Bindings/iio/accel/fsl,mma7455.yaml
new file mode 100644
index 0000000..7c8f8bd
--- /dev/null
+++ b/Bindings/iio/accel/fsl,mma7455.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/fsl,mma7455.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MMA7455 and MMA7456 three axis accelerometers
+
+maintainers:
+ - Joachim Eastwood <manabian@gmail.com>
+ - Jonathan Cameron <jic23@kernel.org>
+
+description:
+ Devices support both SPI and I2C interfaces.
+
+properties:
+ compatible:
+ enum:
+ - fsl,mma7455
+ - fsl,mma7456
+ reg:
+ maxItems: 1
+
+ avdd-supply: true
+ vddio-supply: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ description:
+ Data ready is only available on INT1, but events can use either or
+ both pins. If not specified, first element assumed to correspond
+ to INT1 and second (where present) to INT2.
+ minItems: 1
+ maxItems: 2
+ items:
+ enum:
+ - "INT1"
+ - "INT2"
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ # include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@18 {
+ compatible = "fsl,mma7455";
+ reg = <0x18>;
+ vddio-supply = <&iovdd>;
+ avdd-supply = <&avdd>;
+ interrupts = <57 IRQ_TYPE_EDGE_FALLING>, <58 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "INT2", "INT1";
+ };
+ };
+ - |
+ # include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ accelerometer@0 {
+ compatible = "fsl,mma7456";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ vddio-supply = <&iovdd>;
+ avdd-supply = <&avdd>;
+ interrupts = <57 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "INT1";
+ };
+ };
+...
diff --git a/Bindings/iio/accel/kionix,kxcjk1013.yaml b/Bindings/iio/accel/kionix,kxcjk1013.yaml
index fbb7144..52fa0f7 100644
--- a/Bindings/iio/accel/kionix,kxcjk1013.yaml
+++ b/Bindings/iio/accel/kionix,kxcjk1013.yaml
@@ -16,6 +16,7 @@
- kionix,kxcj91008
- kionix,kxtj21009
- kionix,kxtf9
+ - kionix,kx023-1025
reg:
maxItems: 1
diff --git a/Bindings/iio/accel/murata,sca3300.yaml b/Bindings/iio/accel/murata,sca3300.yaml
new file mode 100644
index 0000000..55fd354
--- /dev/null
+++ b/Bindings/iio/accel/murata,sca3300.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/murata,sca3300.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Murata SCA3300 Accelerometer
+
+description: |
+ 3-axis industrial accelerometer with digital SPI interface
+ https://www.murata.com/en-global/products/sensor/accel/sca3300
+
+maintainers:
+ - Tomas Melin <tomas.melin@vaisala.com>
+
+properties:
+ compatible:
+ enum:
+ - murata,sca3300
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency:
+ maximum: 8000000
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ accelerometer@0 {
+ compatible = "murata,sca3300";
+ reg = <0x0>;
+ spi-max-frequency = <4000000>;
+ };
+ };
+...
diff --git a/Bindings/iio/accel/nxp,fxls8962af.yaml b/Bindings/iio/accel/nxp,fxls8962af.yaml
new file mode 100644
index 0000000..ad529ab
--- /dev/null
+++ b/Bindings/iio/accel/nxp,fxls8962af.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/accel/nxp,fxls8962af.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP FXLS8962AF/FXLS8964AF Accelerometer driver
+
+maintainers:
+ - Sean Nyekjaer <sean@geanix.com>
+
+description: |
+ NXP FXLS8962AF/FXLS8964AF Accelerometer driver that supports
+ SPI and I2C interface.
+ https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf
+ https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf
+
+properties:
+ compatible:
+ enum:
+ - nxp,fxls8962af
+ - nxp,fxls8964af
+
+ reg:
+ maxItems: 1
+
+ vdd-supply:
+ description: phandle to the regulator that provides power to the accelerometer
+
+ spi-max-frequency: true
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ enum:
+ - INT1
+ - INT2
+
+ drive-open-drain:
+ type: boolean
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Example for a I2C device node */
+ accelerometer@62 {
+ compatible = "nxp,fxls8962af";
+ reg = <0x62>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "INT1";
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Example for a SPI device node */
+ accelerometer@0 {
+ compatible = "nxp,fxls8962af";
+ reg = <0>;
+ spi-max-frequency = <4000000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "INT1";
+ };
+ };
diff --git a/Bindings/iio/adc/adc.yaml b/Bindings/iio/adc/adc.yaml
index 912a763..db348fc 100644
--- a/Bindings/iio/adc/adc.yaml
+++ b/Bindings/iio/adc/adc.yaml
@@ -39,4 +39,16 @@
The first value specifies the positive input pin, the second
specifies the negative input pin.
+ settling-time-us:
+ description:
+ Time between enabling the channel and first stable readings.
+
+ oversampling-ratio:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Oversampling is used as replacement of or addition to the low-pass filter.
+ In some cases, the desired filtering characteristics are a function the
+ device design and can interact with other characteristics such as
+ settling time.
+
additionalProperties: true
diff --git a/Bindings/iio/adc/adi,ad7298.yaml b/Bindings/iio/adc/adi,ad7298.yaml
new file mode 100644
index 0000000..ca414bb
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7298.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7298.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD7298 ADC
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ Bindings for the Analog Devices AD7298 ADC device. Datasheet can be
+ found here:
+ https://www.analog.com/en/products/ad7298.html
+
+properties:
+ compatible:
+ const: adi,ad7298
+
+ reg:
+ maxItems: 1
+
+ vref-supply: true
+ vdd-supply: true
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7298";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ vref-supply = <&adc_vref>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/adi,ad7476.yaml b/Bindings/iio/adc/adi,ad7476.yaml
new file mode 100644
index 0000000..cf71108
--- /dev/null
+++ b/Bindings/iio/adc/adi,ad7476.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 Analog Devices Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/adi,ad7476.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AD7476 and similar simple SPI ADCs from multiple manufacturers.
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ A lot of simple SPI ADCs have very straight forward interfaces.
+ They typically don't provide a MOSI pin, simply reading out data
+ on MISO when the clock toggles.
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7091
+ - adi,ad7091r
+ - adi,ad7273
+ - adi,ad7274
+ - adi,ad7276
+ - adi,ad7277
+ - adi,ad7278
+ - adi,ad7466
+ - adi,ad7467
+ - adi,ad7468
+ - adi,ad7475
+ - adi,ad7476
+ - adi,ad7476a
+ - adi,ad7477
+ - adi,ad7477a
+ - adi,ad7478
+ - adi,ad7478a
+ - adi,ad7495
+ - adi,ad7910
+ - adi,ad7920
+ - adi,ad7940
+ - ti,adc081s
+ - ti,adc101s
+ - ti,adc121s
+ - ti,ads7866
+ - ti,ads7867
+ - ti,ads7868
+ - lltc,ltc2314-14
+
+ reg:
+ maxItems: 1
+
+ vcc-supply:
+ description:
+ Main powersupply voltage for the chips, sometimes referred to as VDD on
+ datasheets. If there is no separate vref-supply, then this is needed
+ to establish channel scaling.
+
+ vdrive-supply:
+ description:
+ Some devices have separate supply for their digital control side.
+
+ vref-supply:
+ description:
+ Some devices have a specific reference voltage supplied on a different pin
+ to the other supplies. Needed to be able to establish channel scaling
+ unless there is also an internal reference available (e.g. ad7091r)
+
+ spi-max-frequency: true
+
+ adi,conversion-start-gpios:
+ description: A GPIO used to trigger the start of a conversion
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+allOf:
+ # Devices where reference is vcc
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091
+ - adi,ad7276
+ - adi,ad7277
+ - adi,ad7278
+ - adi,ad7466
+ - adi,ad7467
+ - adi,ad7468
+ - adi,ad7940
+ - ti,adc081s
+ - ti,adc101s
+ - ti,adc121s
+ - ti,ads7866
+ - ti,ads7868
+ required:
+ - vcc-supply
+ # Devices with a vref
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091r
+ - adi,ad7273
+ - adi,ad7274
+ - adi,ad7475
+ - lltc,ltc2314-14
+ then:
+ properties:
+ vref-supply: true
+ else:
+ properties:
+ vref-supply: false
+ # Devices with a vref where it is not optional
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7273
+ - adi,ad7274
+ - adi,ad7475
+ - lltc,ltc2314-14
+ then:
+ required:
+ - vref-supply
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7475
+ - adi,ad7495
+ then:
+ properties:
+ vdrive-supply: true
+ else:
+ properties:
+ vdrive-supply: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - adi,ad7091
+ - adi,ad7091r
+ then:
+ properties:
+ adi,conversion-start-gpios: true
+ else:
+ properties:
+ adi,conversion-start-gpios: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "adi,ad7091r";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ vcc-supply = <&adc_vcc>;
+ vref-supply = <&adc_vref>;
+ };
+ };
+...
diff --git a/Bindings/iio/adc/amlogic,meson-saradc.yaml b/Bindings/iio/adc/amlogic,meson-saradc.yaml
index 3be8955..7e8328e 100644
--- a/Bindings/iio/adc/amlogic,meson-saradc.yaml
+++ b/Bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -41,7 +41,6 @@
clock-names:
minItems: 2
- maxItems: 4
items:
- const: clkin
- const: core
diff --git a/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index 1e7894e..733351d 100644
--- a/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -38,14 +38,12 @@
dfsdm clock can also feed CLKOUT, when CLKOUT is used.
- description: audio clock can be used as an alternate to feed CLKOUT.
minItems: 1
- maxItems: 2
clock-names:
items:
- const: dfsdm
- const: audio
minItems: 1
- maxItems: 2
"#address-cells":
const: 1
diff --git a/Bindings/iio/adc/ti,tsc2046.yaml b/Bindings/iio/adc/ti,tsc2046.yaml
new file mode 100644
index 0000000..601d699
--- /dev/null
+++ b/Bindings/iio/adc/ti,tsc2046.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,tsc2046.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments TSC2046 touch screen controller.
+
+maintainers:
+ - Oleksij Rempel <o.rempel@pengutronix.de>
+
+description: |
+ TSC2046 is a touch screen controller with 8 channels ADC.
+
+properties:
+ compatible:
+ enum:
+ - ti,tsc2046e-adc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+ "#io-channel-cells":
+ const: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+patternProperties:
+ "^channel@[0-7]$":
+ $ref: "adc.yaml"
+ type: object
+
+ properties:
+ reg:
+ description: |
+ The channel number. It can have up to 8 channels
+ items:
+ minimum: 0
+ maximum: 7
+
+ settling-time-us: true
+ oversampling-ratio: true
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@0 {
+ compatible = "ti,tsc2046e-adc";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@2 {
+ reg = <2>;
+ };
+ channel@3 {
+ reg = <3>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@4 {
+ reg = <4>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@5 {
+ reg = <5>;
+ settling-time-us = <700>;
+ oversampling-ratio = <5>;
+ };
+ channel@6 {
+ reg = <6>;
+ };
+ channel@7 {
+ reg = <7>;
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/afe/current-sense-shunt.yaml b/Bindings/iio/afe/current-sense-shunt.yaml
index 90439a8..f8a112c 100644
--- a/Bindings/iio/afe/current-sense-shunt.yaml
+++ b/Bindings/iio/afe/current-sense-shunt.yaml
@@ -24,6 +24,9 @@
description: |
Channel node of a voltage io-channel.
+ "#io-channel-cells":
+ const: 0
+
shunt-resistor-micro-ohms:
description: The shunt resistance.
@@ -57,6 +60,7 @@
sysi {
compatible = "current-sense-shunt";
io-channels = <&tiadc 0>;
+ #io-channel-cells = <0>;
/* Divide the voltage by 3300000/1000000 (or 3.3) for the current. */
shunt-resistor-micro-ohms = <3300000>;
diff --git a/Bindings/iio/cdc/adi,ad7746.yaml b/Bindings/iio/cdc/adi,ad7746.yaml
new file mode 100644
index 0000000..a02036e
--- /dev/null
+++ b/Bindings/iio/cdc/adi,ad7746.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/cdc/adi,ad7746.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AD7746 24-Bit Capacitance-to-Digital Converter with Temperature Sensor
+
+maintainers:
+ - Michael Hennerich <michael.hennerich@analog.com>
+
+description: |
+ AD7746 24-Bit Capacitance-to-Digital Converter with Temperature Sensor
+
+ Specifications about the part can be found at:
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ad7291.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,ad7745
+ - adi,ad7746
+ - adi,ad7747
+
+ reg:
+ maxItems: 1
+
+ adi,excitation-vdd-permille:
+ description: |
+ Set VDD per mille to be used as the excitation voltage.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [125, 250, 375, 500]
+
+ adi,exca-output-en:
+ description: Enables the EXCA pin as the excitation output.
+ type: boolean
+
+ adi,exca-output-invert:
+ description: |
+ Inverts the excitation output in the EXCA pin.
+ Normally only one of the EXCX pins would be inverted, check the following
+ application notes for more details
+ https://www.analog.com/media/en/technical-documentation/application-notes/AN-1585.pdf
+ type: boolean
+
+ adi,excb-output-en:
+ description: Enables the EXCB pin as the excitation output.
+ type: boolean
+
+ adi,excb-output-invert:
+ description: Inverts the excitation output in the EXCB pin.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ad7746: cdc@48 {
+ compatible = "adi,ad7746";
+ reg = <0x48>;
+ adi,excitation-vdd-permille = <125>;
+
+ adi,exca-output-en;
+ adi,exca-output-invert;
+ adi,excb-output-en;
+ adi,excb-output-invert;
+ };
+ };
+...
diff --git a/Bindings/iio/chemical/sensirion,sps30.yaml b/Bindings/iio/chemical/sensirion,sps30.yaml
index a93d197..967500b 100644
--- a/Bindings/iio/chemical/sensirion,sps30.yaml
+++ b/Bindings/iio/chemical/sensirion,sps30.yaml
@@ -22,7 +22,6 @@
required:
- compatible
- - reg
additionalProperties: false
@@ -37,5 +36,11 @@
reg = <0x69>;
};
};
+ - |
+ serial {
+ air-pollution-sensor {
+ compatible = "sensirion,sps30";
+ };
+ };
...
diff --git a/Bindings/iio/dac/ad5755.txt b/Bindings/iio/dac/ad5755.txt
deleted file mode 100644
index 502e1e5..0000000
--- a/Bindings/iio/dac/ad5755.txt
+++ /dev/null
@@ -1,124 +0,0 @@
-* Analog Devices AD5755 IIO Multi-Channel DAC Linux Driver
-
-Required properties:
- - compatible: Has to contain one of the following:
- adi,ad5755
- adi,ad5755-1
- adi,ad5757
- adi,ad5735
- adi,ad5737
-
- - reg: spi chip select number for the device
- - spi-cpha or spi-cpol: is the only modes that is supported
-
-Recommended properties:
- - spi-max-frequency: Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Optional properties:
-See include/dt-bindings/iio/ad5755.h
- - adi,ext-dc-dc-compenstation-resistor: boolean set if the hardware have an
- external resistor and thereby bypasses
- the internal compensation resistor.
- - adi,dc-dc-phase:
- Valid values for DC DC Phase control is:
- 0: All dc-to-dc converters clock on the same edge.
- 1: Channel A and Channel B clock on the same edge,
- Channel C and Channel D clock on opposite edges.
- 2: Channel A and Channel C clock on the same edge,
- Channel B and Channel D clock on opposite edges.
- 3: Channel A, Channel B, Channel C, and Channel D
- clock 90 degrees out of phase from each other.
- - adi,dc-dc-freq-hz:
- Valid values for DC DC frequency is [Hz]:
- 250000
- 410000
- 650000
- - adi,dc-dc-max-microvolt:
- Valid values for the maximum allowed Vboost voltage supplied by
- the dc-to-dc converter is:
- 23000000
- 24500000
- 27000000
- 29500000
-
-Optional for every channel:
- - adi,mode:
- Valid values for DAC modes is:
- 0: 0 V to 5 V voltage range.
- 1: 0 V to 10 V voltage range.
- 2: Plus minus 5 V voltage range.
- 3: Plus minus 10 V voltage range.
- 4: 4 mA to 20 mA current range.
- 5: 0 mA to 20 mA current range.
- 6: 0 mA to 24 mA current range.
- - adi,ext-current-sense-resistor: boolean set if the hardware a external
- current sense resistor.
- - adi,enable-voltage-overrange: boolean enable voltage overrange
- - adi,slew: Array of slewrate settings should contain 3 fields:
- 1: Should be either 0 or 1 in order to enable or disable slewrate.
- 2: Slew rate settings:
- Valid values for the slew rate update frequency:
- 64000
- 32000
- 16000
- 8000
- 4000
- 2000
- 1000
- 500
- 250
- 125
- 64
- 32
- 16
- 8
- 4
- 0
- 3: Slew step size:
- Valid values for the step size LSBs:
- 1
- 2
- 4
- 16
- 32
- 64
- 128
- 256
-
-Example:
-dac@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "adi,ad5755";
- reg = <0>;
- spi-max-frequency = <1000000>;
- spi-cpha;
- adi,dc-dc-phase = <0>;
- adi,dc-dc-freq-hz = <410000>;
- adi,dc-dc-max-microvolt = <23000000>;
- channel@0 {
- reg = <0>;
- adi,mode = <4>;
- adi,ext-current-sense-resistor;
- adi,slew = <0 64000 1>;
- };
- channel@1 {
- reg = <1>;
- adi,mode = <4>;
- adi,ext-current-sense-resistor;
- adi,slew = <0 64000 1>;
- };
- channel@2 {
- reg = <2>;
- adi,mode = <4>;
- adi,ext-current-sense-resistor;
- adi,slew = <0 64000 1>;
- };
- channel@3 {
- reg = <3>;
- adi,mode = <4>;
- adi,ext-current-sense-resistor;
- adi,slew = <0 64000 1>;
- };
-};
diff --git a/Bindings/iio/dac/adi,ad5755.yaml b/Bindings/iio/dac/adi,ad5755.yaml
new file mode 100644
index 0000000..be419ac
--- /dev/null
+++ b/Bindings/iio/dac/adi,ad5755.yaml
@@ -0,0 +1,169 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/adi,ad5755.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD5755 Multi-Channel DAC
+
+maintainers:
+ - Sean Nyekjaer <sean.nyekjaer@prevas.dk>
+
+properties:
+ compatible:
+ enum:
+ - adi,ad5755
+ - adi,ad5755-1
+ - adi,ad5757
+ - adi,ad5735
+ - adi,ad5737
+
+ reg:
+ maxItems: 1
+
+ spi-cpha:
+ description: Either this or spi-cpol but not both.
+ spi-cpol: true
+
+ spi-max-frequency: true
+
+ adi,ext-dc-dc-compenstation-resistor:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Set if the hardware have an external resistor and thereby bypasses
+ the internal compensation resistor.
+
+ adi,dc-dc-phase:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3]
+ description: |
+ Valid values for DC DC Phase control is:
+ 0: All dc-to-dc converters clock on the same edge.
+ 1: Channel A and Channel B clock on the same edge,
+ Channel C and Channel D clock on opposite edges.
+ 2: Channel A and Channel C clock on the same edge,
+ Channel B and Channel D clock on opposite edges.
+ 3: Channel A, Channel B, Channel C, and Channel D
+ clock 90 degrees out of phase from each other.
+
+ adi,dc-dc-freq-hz:
+ enum: [250000, 410000, 650000]
+
+ adi,dc-dc-max-microvolt:
+ description:
+ Maximum allowed Vboost voltage supplied by the dc-to-dc converter.
+ enum: [23000000, 24500000, 27000000, 29500000]
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+patternProperties:
+ "^channel@[0-7]$":
+ type: object
+ description: Child node to describe a channel
+ properties:
+ reg:
+ maxItems: 1
+
+ adi,mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 6
+ description: |
+ Valid values for DAC modes is:
+ 0: 0 V to 5 V voltage range.
+ 1: 0 V to 10 V voltage range.
+ 2: Plus minus 5 V voltage range.
+ 3: Plus minus 10 V voltage range.
+ 4: 4 mA to 20 mA current range.
+ 5: 0 mA to 20 mA current range.
+ 6: 0 mA to 24 mA current range.
+
+ adi,ext-current-sense-resistor:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Set if the hardware has an external current sense resistor
+
+ adi,enable-voltage-overrange:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable voltage overrange
+
+ adi,slew:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Array of slewrate settings should contain 3 fields:
+ 1: Should be either 0 or 1 in order to enable or disable slewrate.
+ 2: Slew rate update frequency
+ 3: Slew step size
+ items:
+ - enum: [0, 1]
+ - enum: [64000, 32000, 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 64, 32, 16, 8, 4, 0]
+ - enum: [1, 2, 4, 16, 32, 64, 128, 256]
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+oneOf:
+ - required:
+ - spi-cpha
+ - required:
+ - spi-cpol
+
+examples:
+ - |
+ #include <dt-bindings/iio/adi,ad5592r.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "adi,ad5755";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ spi-cpha;
+ adi,dc-dc-phase = <0>;
+ adi,dc-dc-freq-hz = <410000>;
+ adi,dc-dc-max-microvolt = <23000000>;
+ channel@0 {
+ reg = <0>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+ channel@1 {
+ reg = <1>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+ channel@2 {
+ reg = <2>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+ channel@3 {
+ reg = <3>;
+ adi,mode = <4>;
+ adi,ext-current-sense-resistor;
+ adi,slew = <0 64000 1>;
+ };
+ };
+ };
+...
diff --git a/Bindings/iio/dac/ti,dac082s085.yaml b/Bindings/iio/dac/ti,dac082s085.yaml
new file mode 100644
index 0000000..b015705
--- /dev/null
+++ b/Bindings/iio/dac/ti,dac082s085.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/dac/ti,dac082s085.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments DAC082s085 and similar DACs
+
+description:
+ A family of Texas Instruments 8/10/12-bit 2/4-channel DACs
+
+maintainers:
+ - Lukas Wunner <lukas@wunner.de>
+
+properties:
+ compatible:
+ enum:
+ - ti,dac082s085
+ - ti,dac102s085
+ - ti,dac122s085
+ - ti,dac084s085
+ - ti,dac104s085
+ - ti,dac124s085
+
+ reg:
+ maxItems: 1
+
+ spi-cpha: true
+ spi-cpol:
+ description:
+ Must be either spi-cpha, or spi-cpol but not both.
+
+ vref-supply:
+ description: Needed to provide output scaling.
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+ - vref-supply
+
+additionalProperties: false
+
+oneOf:
+ - required:
+ - spi-cpha
+ - required:
+ - spi-cpol
+
+examples:
+ - |
+ vref_2v5_reg: regulator-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dac@0 {
+ compatible = "ti,dac082s085";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ spi-cpol;
+ vref-supply = <&vref_2v5_reg>;
+ };
+ };
+...
diff --git a/Bindings/iio/dac/ti-dac082s085.txt b/Bindings/iio/dac/ti-dac082s085.txt
deleted file mode 100644
index 9cb0e10..0000000
--- a/Bindings/iio/dac/ti-dac082s085.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Texas Instruments 8/10/12-bit 2/4-channel DAC driver
-
-Required properties:
- - compatible: Must be one of:
- "ti,dac082s085"
- "ti,dac102s085"
- "ti,dac122s085"
- "ti,dac084s085"
- "ti,dac104s085"
- "ti,dac124s085"
- - reg: Chip select number.
- - spi-cpha, spi-cpol: SPI mode (0,1) or (1,0) must be used, so specify
- either spi-cpha or spi-cpol (but not both).
- - vref-supply: Phandle to the external reference voltage supply.
-
-For other required and optional properties of SPI slave nodes please refer to
-../../spi/spi-bus.txt.
-
-Example:
- vref_2v5_reg: regulator-vref {
- compatible = "regulator-fixed";
- regulator-name = "2v5";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-always-on;
- };
-
- dac@0 {
- compatible = "ti,dac082s085";
- reg = <0>;
- spi-max-frequency = <40000000>;
- spi-cpol;
- vref-supply = <&vref_2v5_reg>;
- };
diff --git a/Bindings/iio/light/amstaos,tsl2591.yaml b/Bindings/iio/light/amstaos,tsl2591.yaml
new file mode 100644
index 0000000..83b88c6
--- /dev/null
+++ b/Bindings/iio/light/amstaos,tsl2591.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/amstaos,tsl2591.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMS/TAOS TSL2591 Ambient Light Sensor (ALS)
+
+maintainers:
+ - Joe Sandom <joe.g.sandom@gmail.com>
+
+description: |
+ AMS/TAOS TSL2591 is a very-high sensitivity
+ light-to-digital converter that transforms light intensity into a digital
+ signal.
+
+properties:
+ compatible:
+ const: amstaos,tsl2591
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+ description:
+ Interrupt (INT:Pin 2) Active low. Should be set to IRQ_TYPE_EDGE_FALLING.
+ interrupt is used to detect if the light intensity has fallen below
+ or reached above the configured threshold values.
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tsl2591@29 {
+ compatible = "amstaos,tsl2591";
+ reg = <0x29>;
+ interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+...
diff --git a/Bindings/iio/multiplexer/io-channel-mux.txt b/Bindings/iio/multiplexer/io-channel-mux.txt
deleted file mode 100644
index 89647d7..0000000
--- a/Bindings/iio/multiplexer/io-channel-mux.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-I/O channel multiplexer bindings
-
-If a multiplexer is used to select which hardware signal is fed to
-e.g. an ADC channel, these bindings describe that situation.
-
-Required properties:
-- compatible : "io-channel-mux"
-- io-channels : Channel node of the parent channel that has multiplexed
- input.
-- io-channel-names : Should be "parent".
-- #address-cells = <1>;
-- #size-cells = <0>;
-- mux-controls : Mux controller node to use for operating the mux
-- channels : List of strings, labeling the mux controller states.
-
-For each non-empty string in the channels property, an io-channel will
-be created. The number of this io-channel is the same as the index into
-the list of strings in the channels property, and also matches the mux
-controller state. The mux controller state is described in
-../mux/mux-controller.txt
-
-Example:
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
-
- channels = "sync", "in", "system-regulator";
- };
diff --git a/Bindings/iio/multiplexer/io-channel-mux.yaml b/Bindings/iio/multiplexer/io-channel-mux.yaml
new file mode 100644
index 0000000..870b043
--- /dev/null
+++ b/Bindings/iio/multiplexer/io-channel-mux.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I/O channel multiplexer bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ If a multiplexer is used to select which hardware signal is fed to
+ e.g. an ADC channel, these bindings describe that situation.
+
+ For each non-empty string in the channels property, an io-channel will be
+ created. The number of this io-channel is the same as the index into the list
+ of strings in the channels property, and also matches the mux controller
+ state. The mux controller state is described in
+ Documentation/devicetree/bindings/mux/mux-controller.yaml
+
+properties:
+
+ compatible:
+ const: io-channel-mux
+
+ io-channels:
+ maxItems: 1
+ description: Channel node of the parent channel that has multiplexed input.
+
+ io-channel-names:
+ const: parent
+
+ mux-controls: true
+ mux-control-names: true
+
+ channels:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description:
+ List of strings, labeling the mux controller states.
+
+required:
+ - compatible
+ - io-channels
+ - io-channel-names
+ - mux-controls
+ - channels
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+ channels = "sync", "in", "system-regulator";
+ };
+...
diff --git a/Bindings/iio/st,st-sensors.yaml b/Bindings/iio/st,st-sensors.yaml
index 7e98f47..b2a1e42 100644
--- a/Bindings/iio/st,st-sensors.yaml
+++ b/Bindings/iio/st,st-sensors.yaml
@@ -6,7 +6,9 @@
title: STMicroelectronics MEMS sensors
-description: |
+description: The STMicroelectronics sensor devices are pretty straight-forward
+ I2C or SPI devices, all sharing the same device tree descriptions no matter
+ what type of sensor it is.
Note that whilst this covers many STMicro MEMs sensors, some more complex
IMUs need their own bindings.
The STMicroelectronics sensor devices are pretty straight-forward I2C or
@@ -15,90 +17,181 @@
maintainers:
- Denis Ciocca <denis.ciocca@st.com>
+ - Linus Walleij <linus.walleij@linaro.org>
properties:
compatible:
- description: |
- Some values are deprecated.
- st,lis3lv02d (deprecated, use st,lis3lv02dl-accel)
- st,lis302dl-spi (deprecated, use st,lis3lv02dl-accel)
- enum:
- # Accelerometers
- - st,lis3lv02d
- - st,lis302dl-spi
- - st,lis3lv02dl-accel
- - st,lsm303dlh-accel
- - st,lsm303dlhc-accel
- - st,lis3dh-accel
- - st,lsm330d-accel
- - st,lsm330dl-accel
- - st,lsm330dlc-accel
- - st,lis331dl-accel
- - st,lis331dlh-accel
- - st,lsm303dl-accel
- - st,lsm303dlm-accel
- - st,lsm330-accel
- - st,lsm303agr-accel
- - st,lis2dh12-accel
- - st,h3lis331dl-accel
- - st,lng2dm-accel
- - st,lis3l02dq
- - st,lis2dw12
- - st,lis3dhh
- - st,lis3de
- - st,lis2de12
- - st,lis2hh12
- # Gyroscopes
- - st,l3g4200d-gyro
- - st,lsm330d-gyro
- - st,lsm330dl-gyro
- - st,lsm330dlc-gyro
- - st,l3gd20-gyro
- - st,l3gd20h-gyro
- - st,l3g4is-gyro
- - st,lsm330-gyro
- - st,lsm9ds0-gyro
- # Magnetometers
- - st,lsm303agr-magn
- - st,lsm303dlh-magn
- - st,lsm303dlhc-magn
- - st,lsm303dlm-magn
- - st,lis3mdl-magn
- - st,lis2mdl
- - st,lsm9ds1-magn
- - st,iis2mdc
- # Pressure sensors
- - st,lps001wp-press
- - st,lps25h-press
- - st,lps331ap-press
- - st,lps22hb-press
- - st,lps33hw
- - st,lps35hw
- - st,lps22hh
+ oneOf:
+ - description: STMicroelectronics Accelerometers
+ enum:
+ - st,h3lis331dl-accel
+ - st,lis2de12
+ - st,lis2dw12
+ - st,lis2hh12
+ - st,lis2dh12-accel
+ - st,lis331dl-accel
+ - st,lis331dlh-accel
+ - st,lis3de
+ - st,lis3dh-accel
+ - st,lis3dhh
+ - st,lis3l02dq
+ - st,lis3lv02dl-accel
+ - st,lng2dm-accel
+ - st,lsm303agr-accel
+ - st,lsm303dl-accel
+ - st,lsm303dlh-accel
+ - st,lsm303dlhc-accel
+ - st,lsm303dlm-accel
+ - st,lsm330-accel
+ - st,lsm330d-accel
+ - st,lsm330dl-accel
+ - st,lsm330dlc-accel
+ - description: STMicroelectronics Gyroscopes
+ enum:
+ - st,l3g4200d-gyro
+ - st,l3g4is-gyro
+ - st,l3gd20-gyro
+ - st,l3gd20h-gyro
+ - st,lsm330-gyro
+ - st,lsm330d-gyro
+ - st,lsm330dl-gyro
+ - st,lsm330dlc-gyro
+ - st,lsm9ds0-gyro
+ - description: STMicroelectronics Magnetometers
+ enum:
+ - st,lis2mdl
+ - st,lis3mdl-magn
+ - st,lsm303agr-magn
+ - st,lsm303dlh-magn
+ - st,lsm303dlhc-magn
+ - st,lsm303dlm-magn
+ - st,lsm9ds1-magn
+ - description: STMicroelectronics Pressure Sensors
+ enum:
+ - st,lps001wp-press
+ - st,lps22hb-press
+ - st,lps22hh
+ - st,lps25h-press
+ - st,lps331ap-press
+ - st,lps33hw
+ - st,lps35hw
+ - description: IMUs
+ enum:
+ - st,lsm9ds0-imu
+ - description: Deprecated bindings
+ enum:
+ - st,lis302dl-spi
+ - st,lis3lv02d
+ deprecated: true
reg:
maxItems: 1
interrupts:
+ description: interrupt line(s) connected to the DRDY line(s) and/or the
+ Intertial interrupt lines INT1 and INT2 if these exist. This means up to
+ three interrupts, and the DRDY must be the first one if it exists on
+ the package. The trigger edge of the interrupts is sometimes software
+ configurable in the hardware so the operating system should parse this
+ flag and set up the trigger edge as indicated in the device tree.
minItems: 1
+ maxItems: 2
vdd-supply: true
vddio-supply: true
st,drdy-int-pin:
+ description: the pin on the package that will be used to signal
+ "data ready" (valid values 1 or 2). This property is not configurable
+ on all sensors.
$ref: /schemas/types.yaml#/definitions/uint32
- description:
- Some sensors have multiple possible pins via which they can provide
- a data ready interrupt. This selects which one.
- enum:
- - 1
- - 2
+ enum: [1, 2]
drive-open-drain:
$ref: /schemas/types.yaml#/definitions/flag
- description: |
- The interrupt/data ready line will be configured as open drain, which
- is useful if several sensors share the same interrupt line.
+ description: the interrupt/data ready line will be configured
+ as open drain, which is useful if several sensors share the same
+ interrupt line. (This binding is taken from pinctrl.)
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix.
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ # These have no interrupts
+ - st,lps001wp
+ then:
+ properties:
+ interrupts: false
+ st,drdy-int-pin: false
+ drive-open-drain: false
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ # These have only DRDY
+ - st,lis2mdl
+ - st,lis3l02dq
+ - st,lis3lv02dl-accel
+ - st,lps22hb-press
+ - st,lps22hh
+ - st,lps25h-press
+ - st,lps33hw
+ - st,lps35hw
+ - st,lsm303agr-magn
+ - st,lsm303dlh-magn
+ - st,lsm303dlhc-magn
+ - st,lsm303dlm-magn
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ st,drdy-int-pin: false
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ # Two intertial interrupts i.e. accelerometer/gyro interrupts
+ - st,h3lis331dl-accel
+ - st,l3g4200d-gyro
+ - st,l3g4is-gyro
+ - st,l3gd20-gyro
+ - st,l3gd20h-gyro
+ - st,lis2de12
+ - st,lis2dw12
+ - st,lis2hh12
+ - st,lis2dh12-accel
+ - st,lis331dl-accel
+ - st,lis331dlh-accel
+ - st,lis3de
+ - st,lis3dh-accel
+ - st,lis3dhh
+ - st,lis3mdl-magn
+ - st,lng2dm-accel
+ - st,lps331ap-press
+ - st,lsm303agr-accel
+ - st,lsm303dlh-accel
+ - st,lsm303dlhc-accel
+ - st,lsm303dlm-accel
+ - st,lsm330-accel
+ - st,lsm330-gyro
+ - st,lsm330d-accel
+ - st,lsm330d-gyro
+ - st,lsm330dl-accel
+ - st,lsm330dl-gyro
+ - st,lsm330dlc-accel
+ - st,lsm330dlc-gyro
+ - st,lsm9ds0-gyro
+ - st,lsm9ds1-magn
+ then:
+ properties:
+ interrupts:
+ maxItems: 2
required:
- compatible
@@ -110,15 +203,30 @@
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
- #address-cells = <1>;
- #size-cells = <0>;
- accelerometer@1d {
- compatible = "st,lis3lv02dl-accel";
- reg = <0x1d>;
- interrupt-parent = <&gpio2>;
- interrupts = <18 IRQ_TYPE_EDGE_RISING>;
- pinctrl-0 = <&lis3lv02dl_nhk_mode>;
- pinctrl-names = "default";
- };
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ accelerometer@1c {
+ compatible = "st,lis331dl-accel";
+ reg = <0x1c>;
+ st,drdy-int-pin = <1>;
+ vdd-supply = <&ldo1>;
+ vddio-supply = <&ldo2>;
+ interrupt-parent = <&gpio>;
+ interrupts = <18 IRQ_TYPE_EDGE_RISING>, <19 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+
+ l3g4200d: gyroscope@0 {
+ compatible = "st,l3g4200d-gyro";
+ st,drdy-int-pin = <2>;
+ reg = <0>;
+ vdd-supply = <&vcc_io>;
+ vddio-supply = <&vcc_io>;
+ };
};
...
diff --git a/Bindings/iio/temperature/ti,tmp117.yaml b/Bindings/iio/temperature/ti,tmp117.yaml
new file mode 100644
index 0000000..347bc16
--- /dev/null
+++ b/Bindings/iio/temperature/ti,tmp117.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/iio/temperature/ti,tmp117.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: "TI TMP117 - Digital temperature sensor with integrated NV memory"
+
+description: |
+ TI TMP117 - Digital temperature sensor with integrated NV memory that supports
+ I2C interface.
+ https://www.ti.com/lit/gpn/tmp1
+
+maintainers:
+ - Puranjay Mohan <puranjay12@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - ti,tmp117
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tmp117@48 {
+ compatible = "ti,tmp117";
+ reg = <0x48>;
+ };
+ };
diff --git a/Bindings/input/fsl-mma8450.txt b/Bindings/input/fsl-mma8450.txt
deleted file mode 100644
index 0b96e57..0000000
--- a/Bindings/input/fsl-mma8450.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-* Freescale MMA8450 3-Axis Accelerometer
-
-Required properties:
-- compatible : "fsl,mma8450".
-- reg: the I2C address of MMA8450
-
-Example:
-
-accelerometer: mma8450@1c {
- compatible = "fsl,mma8450";
- reg = <0x1c>;
-};
diff --git a/Bindings/input/qcom,pm8941-pwrkey.txt b/Bindings/input/qcom,pm8941-pwrkey.txt
index 34ab576..6cd08bc 100644
--- a/Bindings/input/qcom,pm8941-pwrkey.txt
+++ b/Bindings/input/qcom,pm8941-pwrkey.txt
@@ -8,6 +8,8 @@
Definition: must be one of:
"qcom,pm8941-pwrkey"
"qcom,pm8941-resin"
+ "qcom,pmk8350-pwrkey"
+ "qcom,pmk8350-resin"
- reg:
Usage: required
diff --git a/Bindings/input/touchscreen/cypress,cy8ctma340.yaml b/Bindings/input/touchscreen/cypress,cy8ctma340.yaml
new file mode 100644
index 0000000..762e56e
--- /dev/null
+++ b/Bindings/input/touchscreen/cypress,cy8ctma340.yaml
@@ -0,0 +1,148 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/cypress,cy8ctma340.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cypress CY8CTMA340 series touchscreen controller bindings
+
+description: The Cypress CY8CTMA340 series (also known as "CYTTSP" after
+ the marketing name Cypress TrueTouch Standard Product) touchscreens can
+ be connected to either I2C or SPI buses.
+
+maintainers:
+ - Javier Martinez Canillas <javier@dowhile0.org>
+ - Linus Walleij <linus.walleij@linaro.org>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ $nodename:
+ pattern: "^touchscreen(@.*)?$"
+
+ compatible:
+ oneOf:
+ - const: cypress,cy8ctma340
+ - const: cypress,cy8ctst341
+ - const: cypress,cyttsp-spi
+ description: Legacy compatible for SPI connected CY8CTMA340
+ deprecated: true
+ - const: cypress,cyttsp-i2c
+ description: Legacy compatible for I2C connected CY8CTMA340
+ deprecated: true
+
+ reg:
+ description: I2C address when used on the I2C bus, or the SPI chip
+ select index when used on the SPI bus
+
+ clock-frequency:
+ description: I2C client clock frequency, defined for host when using
+ the device on the I2C bus
+ minimum: 0
+ maximum: 400000
+
+ spi-max-frequency:
+ description: SPI clock frequency, defined for host, defined when using
+ the device on the SPI bus. The throughput is maximum 2 Mbps so the
+ typical value is 2000000, if higher rates are used the total throughput
+ needs to be restricted to 2 Mbps.
+ minimum: 0
+ maximum: 6000000
+
+ interrupts:
+ description: Interrupt to host
+ maxItems: 1
+
+ vcpin-supply:
+ description: Analog power supply regulator on VCPIN pin
+
+ vdd-supply:
+ description: Digital power supply regulator on VDD pin
+
+ reset-gpios:
+ description: Reset line for the touchscreen, should be tagged
+ as GPIO_ACTIVE_LOW
+
+ bootloader-key:
+ description: the 8-byte bootloader key that is required to switch
+ the chip from bootloader mode (default mode) to application mode
+ $ref: /schemas/types.yaml#/definitions/uint8-array
+ minItems: 8
+ maxItems: 8
+
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-fuzz-x: true
+ touchscreen-fuzz-y: true
+
+ active-distance:
+ description: the distance in pixels beyond which a touch must move
+ before movement is detected and reported by the device
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 15
+
+ active-interval-ms:
+ description: the minimum period in ms between consecutive
+ scanning/processing cycles when the chip is in active mode
+ minimum: 0
+ maximum: 255
+
+ lowpower-interval-ms:
+ description: the minimum period in ms between consecutive
+ scanning/processing cycles when the chip is in low-power mode
+ minimum: 0
+ maximum: 2550
+
+ touch-timeout-ms:
+ description: minimum time in ms spent in the active power state while no
+ touches are detected before entering low-power mode
+ minimum: 0
+ maximum: 2550
+
+ use-handshake:
+ description: enable register-based handshake (boolean). This should only
+ be used if the chip is configured to use 'blocking communication with
+ timeout' (in this case the device generates an interrupt at the end of
+ every scanning/processing cycle)
+ $ref: /schemas/types.yaml#/definitions/flag
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - bootloader-key
+ - touchscreen-size-x
+ - touchscreen-size-y
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ num-cs = <1>;
+ cs-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+
+ touchscreen@0 {
+ compatible = "cypress,cy8ctma340";
+ reg = <0>;
+ interrupt-parent = <&gpio>;
+ interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&ldo_aux1_reg>;
+ vcpin-supply = <&ldo_aux2_reg>;
+ bootloader-key = /bits/ 8 <0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <800>;
+ active-interval-ms = <0>;
+ touch-timeout-ms = <255>;
+ lowpower-interval-ms = <10>;
+ };
+ };
+
+...
diff --git a/Bindings/input/touchscreen/cyttsp.txt b/Bindings/input/touchscreen/cyttsp.txt
deleted file mode 100644
index 6ee274a..0000000
--- a/Bindings/input/touchscreen/cyttsp.txt
+++ /dev/null
@@ -1,93 +0,0 @@
-* Cypress cyttsp touchscreen controller
-
-Required properties:
- - compatible : must be "cypress,cyttsp-i2c" or "cypress,cyttsp-spi"
- - reg : Device I2C address or SPI chip select number
- - spi-max-frequency : Maximum SPI clocking speed of the device (for cyttsp-spi)
- - interrupts : (gpio) interrupt to which the chip is connected
- (see interrupt binding[0]).
- - bootloader-key : the 8-byte bootloader key that is required to switch
- the chip from bootloader mode (default mode) to
- application mode.
- This property has to be specified as an array of 8
- '/bits/ 8' values.
-
-Optional properties:
- - reset-gpios : the reset gpio the chip is connected to
- (see GPIO binding[1] for more details).
- - touchscreen-size-x : horizontal resolution of touchscreen (in pixels)
- - touchscreen-size-y : vertical resolution of touchscreen (in pixels)
- - touchscreen-fuzz-x : horizontal noise value of the absolute input device
- (in pixels)
- - touchscreen-fuzz-y : vertical noise value of the absolute input device
- (in pixels)
- - active-distance : the distance in pixels beyond which a touch must move
- before movement is detected and reported by the device.
- Valid values: 0-15.
- - active-interval-ms : the minimum period in ms between consecutive
- scanning/processing cycles when the chip is in active mode.
- Valid values: 0-255.
- - lowpower-interval-ms : the minimum period in ms between consecutive
- scanning/processing cycles when the chip is in low-power mode.
- Valid values: 0-2550
- - touch-timeout-ms : minimum time in ms spent in the active power state while no
- touches are detected before entering low-power mode.
- Valid values: 0-2550
- - use-handshake : enable register-based handshake (boolean). This should
- only be used if the chip is configured to use 'blocking
- communication with timeout' (in this case the device
- generates an interrupt at the end of every
- scanning/processing cycle).
-
-[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-[1]: Documentation/devicetree/bindings/gpio/gpio.txt
-
-Example:
- &i2c1 {
- /* ... */
- cyttsp@a {
- compatible = "cypress,cyttsp-i2c";
- reg = <0xa>;
- interrupt-parent = <&gpio0>;
- interrupts = <28 0>;
- reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
-
- touchscreen-size-x = <800>;
- touchscreen-size-y = <480>;
- touchscreen-fuzz-x = <4>;
- touchscreen-fuzz-y = <7>;
-
- bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
- active-distance = <8>;
- active-interval-ms = <0>;
- lowpower-interval-ms = <200>;
- touch-timeout-ms = <100>;
- };
-
- /* ... */
- };
-
- &mcspi1 {
- /* ... */
- cyttsp@0 {
- compatible = "cypress,cyttsp-spi";
- spi-max-frequency = <6000000>;
- reg = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <28 0>;
- reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
-
- touchscreen-size-x = <800>;
- touchscreen-size-y = <480>;
- touchscreen-fuzz-x = <4>;
- touchscreen-fuzz-y = <7>;
-
- bootloader-key = /bits/ 8 <0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
- active-distance = <8>;
- active-interval-ms = <0>;
- lowpower-interval-ms = <200>;
- touch-timeout-ms = <100>;
- };
-
- /* ... */
- };
diff --git a/Bindings/input/touchscreen/edt-ft5x06.yaml b/Bindings/input/touchscreen/edt-ft5x06.yaml
index bfc3a8b..2e8da74 100644
--- a/Bindings/input/touchscreen/edt-ft5x06.yaml
+++ b/Bindings/input/touchscreen/edt-ft5x06.yaml
@@ -56,6 +56,7 @@
wakeup-source: true
vcc-supply: true
+ iovcc-supply: true
gain:
description: Allows setting the sensitivity in the range from 0 to 31.
diff --git a/Bindings/input/touchscreen/resistive-adc-touch.txt b/Bindings/input/touchscreen/resistive-adc-touch.txt
deleted file mode 100644
index af5223b..0000000
--- a/Bindings/input/touchscreen/resistive-adc-touch.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-Generic resistive touchscreen ADC
-
-Required properties:
-
- - compatible: must be "resistive-adc-touch"
-The device must be connected to an ADC device that provides channels for
-position measurement and optional pressure.
-Refer to
-https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml
-for details
-
- - iio-channels: must have at least two channels connected to an ADC device.
-These should correspond to the channels exposed by the ADC device and should
-have the right index as the ADC device registers them. These channels
-represent the relative position on the "x" and "y" axes.
- - iio-channel-names: must have all the channels' names. Mandatory channels
-are "x" and "y".
-
-Optional properties:
- - iio-channels: The third channel named "pressure" is optional and can be
-used if the ADC device also measures pressure besides position.
-If this channel is missing, pressure will be ignored and the touchscreen
-will only report position.
- - iio-channel-names: optional channel named "pressure".
-
-Example:
-
- resistive_touch: resistive_touch {
- compatible = "resistive-adc-touch";
- touchscreen-min-pressure = <50000>;
- io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
- io-channel-names = "x", "y", "pressure";
- };
diff --git a/Bindings/input/touchscreen/resistive-adc-touch.yaml b/Bindings/input/touchscreen/resistive-adc-touch.yaml
new file mode 100644
index 0000000..7fc22a4
--- /dev/null
+++ b/Bindings/input/touchscreen/resistive-adc-touch.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/resistive-adc-touch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic resistive touchscreen ADC
+
+maintainers:
+ - Oleksij Rempel <o.rempel@pengutronix.de>
+
+description: |
+ Generic ADC based resistive touchscreen controller
+ The device must be connected to an ADC device that provides channels for
+ position measurement and optional pressure.
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ const: resistive-adc-touch
+
+ io-channels:
+ minItems: 2
+ items:
+ - description: x
+ - description: y
+ - description: pressure (optional)
+ - description: z1 (optional)
+ - description: z2 (optional)
+
+ io-channel-names:
+ oneOf:
+ - items:
+ - enum: [x, y]
+ - enum: [x, y]
+ - items:
+ - enum: [x, y, pressure]
+ - enum: [x, y, pressure]
+ - enum: [x, y, pressure]
+ - items:
+ - enum: [x, y, z1, z2]
+ - enum: [x, y, z1, z2]
+ - enum: [x, y, z1, z2]
+ - enum: [x, y, z1, z2]
+
+ touchscreen-size-x: true
+ touchscreen-size-y: true
+ touchscreen-fuzz-x: true
+ touchscreen-fuzz-y: true
+ touchscreen-inverted-x: true
+ touchscreen-inverted-y: true
+ touchscreen-swapped-x-y: true
+ touchscreen-min-pressure: true
+ touchscreen-x-plate-ohms: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - io-channels
+ - io-channel-names
+
+examples:
+ - |
+ touchscreen {
+ compatible = "resistive-adc-touch";
+ io-channels = <&adc 24>, <&adc 25>;
+ io-channel-names = "y", "x";
+ };
+ - |
+ touchscreen {
+ compatible = "resistive-adc-touch";
+ touchscreen-min-pressure = <50000>;
+ io-channels = <&adc 24>, <&adc 25>, <&adc 26>;
+ io-channel-names = "y", "pressure", "x";
+ };
+ - |
+ touchscreen {
+ compatible = "resistive-adc-touch";
+ touchscreen-min-pressure = <50000>;
+ io-channels = <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
+ io-channel-names = "x", "z1", "z2", "y";
+ touchscreen-x-plate-ohms = <800>;
+ };
diff --git a/Bindings/input/touchscreen/sitronix,st1232.yaml b/Bindings/input/touchscreen/sitronix,st1232.yaml
new file mode 100644
index 0000000..1d8ca19
--- /dev/null
+++ b/Bindings/input/touchscreen/sitronix,st1232.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/touchscreen/sitronix,st1232.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sitronix st1232 or st1633 touchscreen controller
+
+maintainers:
+ - Bastian Hecht <hechtb@gmail.com>
+
+allOf:
+ - $ref: touchscreen.yaml#
+
+properties:
+ compatible:
+ enum:
+ - sitronix,st1232
+ - sitronix,st1633
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ gpios:
+ description: A phandle to the reset GPIO
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchscreen@55 {
+ compatible = "sitronix,st1232";
+ reg = <0x55>;
+ interrupts = <2 0>;
+ gpios = <&gpio1 166 0>;
+ };
+ };
diff --git a/Bindings/input/touchscreen/sitronix-st1232.txt b/Bindings/input/touchscreen/sitronix-st1232.txt
deleted file mode 100644
index 0193732..0000000
--- a/Bindings/input/touchscreen/sitronix-st1232.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Sitronix st1232 or st1633 touchscreen controller
-
-Required properties:
-- compatible: must contain one of
- * "sitronix,st1232"
- * "sitronix,st1633"
-- reg: I2C address of the chip
-- interrupts: interrupt to which the chip is connected
-
-Optional properties:
-- gpios: a phandle to the reset GPIO
-
-For additional optional properties see: touchscreen.txt
-
-Example:
-
- i2c@00000000 {
- /* ... */
-
- touchscreen@55 {
- compatible = "sitronix,st1232";
- reg = <0x55>;
- interrupts = <2 0>;
- gpios = <&gpio1 166 0>;
- };
-
- /* ... */
- };
diff --git a/Bindings/input/touchscreen/touchscreen.yaml b/Bindings/input/touchscreen/touchscreen.yaml
index 046ace4..4b5b212 100644
--- a/Bindings/input/touchscreen/touchscreen.yaml
+++ b/Bindings/input/touchscreen/touchscreen.yaml
@@ -74,6 +74,12 @@
touchscreen-y-mm:
description: vertical length in mm of the touchscreen
+ touchscreen-x-plate-ohms:
+ description: Resistance of the X-plate in Ohms
+
+ touchscreen-y-plate-ohms:
+ description: Resistance of the Y-plate in Ohms
+
dependencies:
touchscreen-size-x: [ touchscreen-size-y ]
touchscreen-size-y: [ touchscreen-size-x ]
diff --git a/Bindings/interconnect/qcom,rpmh.yaml b/Bindings/interconnect/qcom,rpmh.yaml
index 36c9559..5accc0d 100644
--- a/Bindings/interconnect/qcom,rpmh.yaml
+++ b/Bindings/interconnect/qcom,rpmh.yaml
@@ -37,6 +37,18 @@
- qcom,sc7180-npu-noc
- qcom,sc7180-qup-virt
- qcom,sc7180-system-noc
+ - qcom,sc7280-aggre1-noc
+ - qcom,sc7280-aggre2-noc
+ - qcom,sc7280-clk-virt
+ - qcom,sc7280-cnoc2
+ - qcom,sc7280-cnoc3
+ - qcom,sc7280-dc-noc
+ - qcom,sc7280-gem-noc
+ - qcom,sc7280-lpass-ag-noc
+ - qcom,sc7280-mc-virt
+ - qcom,sc7280-mmss-noc
+ - qcom,sc7280-nsp-noc
+ - qcom,sc7280-system-noc
- qcom,sdm845-aggre1-noc
- qcom,sdm845-aggre2-noc
- qcom,sdm845-config-noc
diff --git a/Bindings/interrupt-controller/arm,gic-v3.yaml b/Bindings/interrupt-controller/arm,gic-v3.yaml
index 1ecd183..c84f9fe 100644
--- a/Bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Bindings/interrupt-controller/arm,gic-v3.yaml
@@ -145,6 +145,19 @@
required:
- affinity
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: aclk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
dependencies:
mbi-ranges: [ msi-controller ]
msi-controller: [ mbi-ranges ]
diff --git a/Bindings/interrupt-controller/arm,vic.txt b/Bindings/interrupt-controller/arm,vic.txt
deleted file mode 100644
index dd52721..0000000
--- a/Bindings/interrupt-controller/arm,vic.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* ARM Vectored Interrupt Controller
-
-One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
-system for interrupt routing. For multiple controllers they can either be
-nested or have the outputs wire-OR'd together.
-
-Required properties:
-
-- compatible : should be one of
- "arm,pl190-vic"
- "arm,pl192-vic"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
- the VIC has no configuration options for interrupt sources. The cell is a u32
- and defines the interrupt number.
-- reg : The register bank for the VIC.
-
-Optional properties:
-
-- interrupts : Interrupt source for parent controllers if the VIC is nested.
-- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
- represents single interrupt source, starting from source 0 at LSb and ending
- at source 31 at MSb. A bit that is set means that the source is wired and
- clear means otherwise. If unspecified, defaults to all valid.
-- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be
- configured as wake up source for the system. Order of bits is the same as for
- valid-mask property. A set bit means that this interrupt source can be
- configured as a wake up source for the system. If unspecied, defaults to all
- interrupt sources configurable as wake up sources.
-
-Example:
-
- vic0: interrupt-controller@60000 {
- compatible = "arm,pl192-vic";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x60000 0x1000>;
-
- valid-mask = <0xffffff7f>;
- valid-wakeup-mask = <0x0000ff7f>;
- };
diff --git a/Bindings/interrupt-controller/arm,vic.yaml b/Bindings/interrupt-controller/arm,vic.yaml
new file mode 100644
index 0000000..0075e72
--- /dev/null
+++ b/Bindings/interrupt-controller/arm,vic.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Vectored Interrupt Controller
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |+
+ One or more Vectored Interrupt Controllers (VIC's) can be connected in an
+ ARM system for interrupt routing. For multiple controllers they can either
+ be nested or have the outputs wire-OR'd together.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - arm,pl190-vic
+ - arm,pl192-vic
+ - arm,versatile-vic
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+ description:
+ The number of cells to define the interrupts. It must be 1 as the
+ VIC has no configuration options for interrupt sources. The single
+ cell defines the interrupt number.
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ valid-mask:
+ description:
+ A one cell big bit mask of valid interrupt sources. Each bit
+ represents single interrupt source, starting from source 0 at
+ LSb and ending at source 31 at MSb. A bit that is set means
+ that the source is wired and clear means otherwise. If unspecified,
+ defaults to all valid.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ valid-wakeup-mask:
+ description:
+ A one cell big bit mask of interrupt sources that can be configured
+ as wake up source for the system. Order of bits is the same as for
+ valid-mask property. A set bit means that this interrupt source
+ can be configured as a wake up source for the system. If unspecied,
+ defaults to all interrupt sources configurable as wake up sources.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ // PL192 VIC
+ vic0: interrupt-controller@60000 {
+ compatible = "arm,pl192-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x60000 0x1000>;
+
+ valid-mask = <0xffffff7f>;
+ valid-wakeup-mask = <0x0000ff7f>;
+ };
+
+...
diff --git a/Bindings/interrupt-controller/fsl,irqsteer.yaml b/Bindings/interrupt-controller/fsl,irqsteer.yaml
index 3b11a1a..bcb5e20 100644
--- a/Bindings/interrupt-controller/fsl,irqsteer.yaml
+++ b/Bindings/interrupt-controller/fsl,irqsteer.yaml
@@ -35,7 +35,6 @@
- description: output interrupt 6
- description: output interrupt 7
minItems: 1
- maxItems: 8
clocks:
maxItems: 1
diff --git a/Bindings/interrupt-controller/loongson,liointc.yaml b/Bindings/interrupt-controller/loongson,liointc.yaml
index 067165c..edf2645 100644
--- a/Bindings/interrupt-controller/loongson,liointc.yaml
+++ b/Bindings/interrupt-controller/loongson,liointc.yaml
@@ -50,7 +50,6 @@
- const: int2
- const: int3
minItems: 1
- maxItems: 4
'#interrupt-cells':
const: 2
diff --git a/Bindings/interrupt-controller/renesas,irqc.yaml b/Bindings/interrupt-controller/renesas,irqc.yaml
index b67b8cb..abb22db 100644
--- a/Bindings/interrupt-controller/renesas,irqc.yaml
+++ b/Bindings/interrupt-controller/renesas,irqc.yaml
@@ -29,6 +29,7 @@
- renesas,intc-ex-r8a774c0 # RZ/G2E
- renesas,intc-ex-r8a7795 # R-Car H3
- renesas,intc-ex-r8a7796 # R-Car M3-W
+ - renesas,intc-ex-r8a77961 # R-Car M3-W+
- renesas,intc-ex-r8a77965 # R-Car M3-N
- renesas,intc-ex-r8a77970 # R-Car V3M
- renesas,intc-ex-r8a77980 # R-Car V3H
diff --git a/Bindings/interrupt-controller/ti,pruss-intc.yaml b/Bindings/interrupt-controller/ti,pruss-intc.yaml
index 9731dd4..051beb4 100644
--- a/Bindings/interrupt-controller/ti,pruss-intc.yaml
+++ b/Bindings/interrupt-controller/ti,pruss-intc.yaml
@@ -134,7 +134,7 @@
/* AM4376 PRU-ICSS */
#include <dt-bindings/interrupt-controller/arm-gic.h>
pruss@0 {
- compatible = "ti,am4376-pruss";
+ compatible = "ti,am4376-pruss1";
reg = <0x0 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/Bindings/iommu/arm,smmu-v3.yaml b/Bindings/iommu/arm,smmu-v3.yaml
index 5951c6f..e87bfbc 100644
--- a/Bindings/iommu/arm,smmu-v3.yaml
+++ b/Bindings/iommu/arm,smmu-v3.yaml
@@ -38,7 +38,6 @@
If provided, then the combined interrupt will be used in preference to
any others.
- minItems: 2
- maxItems: 4
items:
- const: eventq # Event Queue not empty
- const: gerror # Global Error activated
diff --git a/Bindings/iommu/arm,smmu.yaml b/Bindings/iommu/arm,smmu.yaml
index 9d27aa5..1181b59 100644
--- a/Bindings/iommu/arm,smmu.yaml
+++ b/Bindings/iommu/arm,smmu.yaml
@@ -54,8 +54,14 @@
- const: arm,mmu-500
- description: NVIDIA SoCs that program two ARM MMU-500s identically
items:
+ - description: NVIDIA SoCs that require memory controller interaction
+ and may program multiple ARM MMU-500s identically with the memory
+ controller interleaving translations between multiple instances
+ for improved performance.
+ items:
- enum:
- - nvidia,tegra194-smmu
+ - const: nvidia,tegra194-smmu
+ - const: nvidia,tegra186-smmu
- const: nvidia,smmu-500
- items:
- const: arm,mmu-500
@@ -165,10 +171,11 @@
contains:
enum:
- nvidia,tegra194-smmu
+ - nvidia,tegra186-smmu
then:
properties:
reg:
- minItems: 2
+ minItems: 1
maxItems: 2
else:
properties:
diff --git a/Bindings/iommu/iommu.txt b/Bindings/iommu/iommu.txt
index 3c36334..26ba9e5 100644
--- a/Bindings/iommu/iommu.txt
+++ b/Bindings/iommu/iommu.txt
@@ -92,6 +92,24 @@
tagging DMA transactions with an address space identifier. By default,
this is 0, which means that the device only has one address space.
+- dma-can-stall: When present, the master can wait for a transaction to
+ complete for an indefinite amount of time. Upon translation fault some
+ IOMMUs, instead of aborting the translation immediately, may first
+ notify the driver and keep the transaction in flight. This allows the OS
+ to inspect the fault and, for example, make physical pages resident
+ before updating the mappings and completing the transaction. Such IOMMU
+ accepts a limited number of simultaneous stalled transactions before
+ having to either put back-pressure on the master, or abort new faulting
+ transactions.
+
+ Firmware has to opt-in stalling, because most buses and masters don't
+ support it. In particular it isn't compatible with PCI, where
+ transactions have to complete before a time limit. More generally it
+ won't work in systems and masters that haven't been designed for
+ stalling. For example the OS, in order to handle a stalled transaction,
+ may attempt to retrieve pages from secondary storage in a stalled
+ domain, leading to a deadlock.
+
Notes:
======
diff --git a/Bindings/iommu/renesas,ipmmu-vmsa.yaml b/Bindings/iommu/renesas,ipmmu-vmsa.yaml
index dda4497..02c69a9 100644
--- a/Bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -49,7 +49,6 @@
interrupts:
minItems: 1
- maxItems: 2
description:
Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
items:
diff --git a/Bindings/iommu/rockchip,iommu.txt b/Bindings/iommu/rockchip,iommu.txt
deleted file mode 100644
index 6ecefea..0000000
--- a/Bindings/iommu/rockchip,iommu.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Rockchip IOMMU
-==============
-
-A Rockchip DRM iommu translates io virtual addresses to physical addresses for
-its master device. Each slave device is bound to a single master device, and
-shares its clocks, power domain and irq.
-
-Required properties:
-- compatible : Should be "rockchip,iommu"
-- reg : Address space for the configuration registers
-- interrupts : Interrupt specifier for the IOMMU instance
-- interrupt-names : Interrupt name for the IOMMU instance
-- #iommu-cells : Should be <0>. This indicates the iommu is a
- "single-master" device, and needs no additional information
- to associate with its master device. See:
- Documentation/devicetree/bindings/iommu/iommu.txt
-- clocks : A list of clocks required for the IOMMU to be accessible by
- the host CPU.
-- clock-names : Should contain the following:
- "iface" - Main peripheral bus clock (PCLK/HCL) (required)
- "aclk" - AXI bus clock (required)
-
-Optional properties:
-- rockchip,disable-mmu-reset : Don't use the mmu reset operation.
- Some mmu instances may produce unexpected results
- when the reset operation is used.
-
-Example:
-
- vopl_mmu: iommu@ff940300 {
- compatible = "rockchip,iommu";
- reg = <0xff940300 0x100>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
- clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
- clock-names = "aclk", "iface";
- #iommu-cells = <0>;
- };
diff --git a/Bindings/iommu/rockchip,iommu.yaml b/Bindings/iommu/rockchip,iommu.yaml
new file mode 100644
index 0000000..d2e28a9
--- /dev/null
+++ b/Bindings/iommu/rockchip,iommu.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip IOMMU
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |+
+ A Rockchip DRM iommu translates io virtual addresses to physical addresses for
+ its master device. Each slave device is bound to a single master device and
+ shares its clocks, power domain and irq.
+
+ For information on assigning IOMMU controller to its peripheral devices,
+ see generic IOMMU bindings.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,iommu
+ - rockchip,rk3568-iommu
+
+ reg:
+ items:
+ - description: configuration registers for MMU instance 0
+ - description: configuration registers for MMU instance 1
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ items:
+ - description: interruption for MMU instance 0
+ - description: interruption for MMU instance 1
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: Core clock
+ - description: Interface clock
+
+ clock-names:
+ items:
+ - const: aclk
+ - const: iface
+
+ "#iommu-cells":
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+ rockchip,disable-mmu-reset:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Do not use the mmu reset operation.
+ Some mmu instances may produce unexpected results
+ when the reset operation is used.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - "#iommu-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ vopl_mmu: iommu@ff940300 {
+ compatible = "rockchip,iommu";
+ reg = <0xff940300 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ };
diff --git a/Bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml b/Bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml
new file mode 100644
index 0000000..4ff6fab
--- /dev/null
+++ b/Bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED BMC KCS Devices
+
+maintainers:
+ - Andrew Jeffery <andrew@aj.id.au>
+
+description: |
+ The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)
+ interfaces on the LPC bus for in-band IPMI communication with their host.
+
+properties:
+ compatible:
+ oneOf:
+ - description: Channel ID derived from reg
+ items:
+ enum:
+ - aspeed,ast2400-kcs-bmc-v2
+ - aspeed,ast2500-kcs-bmc-v2
+ - aspeed,ast2600-kcs-bmc
+
+ - description: Old-style with explicit channel ID, no reg
+ deprecated: true
+ items:
+ enum:
+ - aspeed,ast2400-kcs-bmc
+ - aspeed,ast2500-kcs-bmc
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ # maxItems: 3
+ items:
+ - description: IDR register
+ - description: ODR register
+ - description: STR register
+
+ aspeed,lpc-io-reg:
+ $ref: '/schemas/types.yaml#/definitions/uint32-array'
+ minItems: 1
+ maxItems: 2
+ description: |
+ The host CPU LPC IO data and status addresses for the device. For most
+ channels the status address is derived from the data address, but the
+ status address may be optionally provided.
+
+ aspeed,lpc-interrupts:
+ $ref: "/schemas/types.yaml#/definitions/uint32-array"
+ minItems: 2
+ maxItems: 2
+ description: |
+ A 2-cell property expressing the LPC SerIRQ number and the interrupt
+ level/sense encoding (specified in the standard fashion).
+
+ Note that the generated interrupt is issued from the BMC to the host, and
+ thus the target interrupt controller is not captured by the BMC's
+ devicetree.
+
+ kcs_chan:
+ deprecated: true
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: The LPC channel number in the controller
+
+ kcs_addr:
+ deprecated: true
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: The host CPU IO map address
+
+required:
+ - compatible
+ - interrupts
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - aspeed,ast2400-kcs-bmc
+ - aspeed,ast2500-kcs-bmc
+ then:
+ required:
+ - kcs_chan
+ - kcs_addr
+ else:
+ required:
+ - reg
+ - aspeed,lpc-io-reg
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ kcs3: kcs@24 {
+ compatible = "aspeed,ast2600-kcs-bmc";
+ reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
+ aspeed,lpc-io-reg = <0xca2>;
+ aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupts = <8>;
+ };
diff --git a/Bindings/ipmi/aspeed-kcs-bmc.txt b/Bindings/ipmi/aspeed-kcs-bmc.txt
deleted file mode 100644
index 193e71c..0000000
--- a/Bindings/ipmi/aspeed-kcs-bmc.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-# Aspeed KCS (Keyboard Controller Style) IPMI interface
-
-The Aspeed SOCs (AST2400 and AST2500) are commonly used as BMCs
-(Baseboard Management Controllers) and the KCS interface can be
-used to perform in-band IPMI communication with their host.
-
-## v1
-Required properties:
-- compatible : should be one of
- "aspeed,ast2400-kcs-bmc"
- "aspeed,ast2500-kcs-bmc"
-- interrupts : interrupt generated by the controller
-- kcs_chan : The LPC channel number in the controller
-- kcs_addr : The host CPU IO map address
-
-## v2
-Required properties:
-- compatible : should be one of
- "aspeed,ast2400-kcs-bmc-v2"
- "aspeed,ast2500-kcs-bmc-v2"
-- reg : The address and size of the IDR, ODR and STR registers
-- interrupts : interrupt generated by the controller
-- aspeed,lpc-io-reg : The host CPU LPC IO address for the device
-
-Example:
-
- kcs3: kcs@24 {
- compatible = "aspeed,ast2500-kcs-bmc-v2";
- reg = <0x24 0x1>, <0x30 0x1>, <0x3c 0x1>;
- aspeed,lpc-reg = <0xca2>;
- interrupts = <8>;
- status = "okay";
- };
diff --git a/Bindings/leds/backlight/richtek,rt4831-backlight.yaml b/Bindings/leds/backlight/richtek,rt4831-backlight.yaml
new file mode 100644
index 0000000..e0ac686
--- /dev/null
+++ b/Bindings/leds/backlight/richtek,rt4831-backlight.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Richtek RT4831 Backlight
+
+maintainers:
+ - ChiYuan Huang <cy_huang@richtek.com>
+
+description: |
+ RT4831 is a mutifunctional device that can provide power to the LCD display
+ and LCD backlight.
+
+ For the LCD backlight, it can provide four channel WLED driving capability.
+ Each channel driving current is up to 30mA
+
+ Datasheet is available at
+ https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
+
+allOf:
+ - $ref: common.yaml#
+
+properties:
+ compatible:
+ const: richtek,rt4831-backlight
+
+ default-brightness:
+ minimum: 0
+ maximum: 2048
+
+ max-brightness:
+ minimum: 0
+ maximum: 2048
+
+ richtek,pwm-enable:
+ description: |
+ Specify the backlight dimming following by PWM duty or by SW control.
+ type: boolean
+
+ richtek,bled-ovp-sel:
+ description: |
+ Backlight OVP level selection, currently support 17V/21V/25V/29V.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ default: 1
+ minimum: 0
+ maximum: 3
+
+ richtek,channel-use:
+ description: |
+ Backlight LED channel to be used.
+ BIT 0/1/2/3 is used to indicate led channel 1/2/3/4 enable or disable.
+ $ref: /schemas/types.yaml#/definitions/uint8
+ minimum: 1
+ maximum: 15
+
+required:
+ - compatible
+ - richtek,channel-use
+
+additionalProperties: false
diff --git a/Bindings/mailbox/arm,mhu.yaml b/Bindings/mailbox/arm,mhu.yaml
index d07eb00..bd49c20 100644
--- a/Bindings/mailbox/arm,mhu.yaml
+++ b/Bindings/mailbox/arm,mhu.yaml
@@ -101,11 +101,19 @@
clocks = <&clock 0 2 1>;
clock-names = "apb_pclk";
};
+ };
- mhu_client_scb: scb@2e000000 {
- compatible = "fujitsu,mb86s70-scb-1.0";
- reg = <0 0x2e000000 0 0x4000>;
+ firmware {
+ scpi {
+ compatible = "arm,scpi";
mboxes = <&mhuA 1>; /* HP-NonSecure */
+ shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
+
+ scpi_devpd: power-controller {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
};
};
@@ -125,10 +133,36 @@
clocks = <&clock 0 2 1>;
clock-names = "apb_pclk";
};
+ };
- mhu_client_scpi: scpi@2f000000 {
- compatible = "arm,scpi";
- reg = <0 0x2f000000 0 0x200>;
- mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */
+ <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri0>,
+ <&cpu_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+
+ mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */
+ <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_hpri0>,
+ <&cpu_scp_hpri1>;
+ };
};
};
+
+...
diff --git a/Bindings/mailbox/arm,mhuv2.yaml b/Bindings/mailbox/arm,mhuv2.yaml
index 6608545..a4f1fe6 100644
--- a/Bindings/mailbox/arm,mhuv2.yaml
+++ b/Bindings/mailbox/arm,mhuv2.yaml
@@ -192,18 +192,17 @@
arm,mhuv2-protocols = <1 1>, <1 7>, <0 2>;
};
- mhu_client: scb@2e000000 {
- compatible = "fujitsu,mb86s70-scb-1.0";
- reg = <0 0x2e000000 0 0x4000>;
-
- mboxes =
- //data-transfer protocol with 5 windows, mhu-tx
- <&mhu_tx 2 0>,
- //data-transfer protocol with 7 windows, mhu-tx
- <&mhu_tx 3 0>,
- //doorbell protocol channel 4, doorbell 27, mhu-tx
- <&mhu_tx 4 27>,
- //data-transfer protocol with 1 window, mhu-rx
- <&mhu_rx 0 0>;
+ mhu_client: dsp@596e8000 {
+ compatible = "fsl,imx8qxp-dsp";
+ reg = <0 0x596e8000 0 0x88000>;
+ clocks = <&adma_lpcg 0>, <&adma_lpcg 1>, <&adma_lpcg 2>;
+ clock-names = "ipg", "ocram", "core";
+ power-domains = <&pd 0>, <&pd 1>, <&pd 2>, <&pd 3>;
+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
+ mboxes = <&mhu_tx 2 0>, //data-transfer protocol with 5 windows, mhu-tx
+ <&mhu_tx 3 0>, //data-transfer protocol with 7 windows, mhu-tx
+ <&mhu_rx 2 27>, //doorbell protocol channel 2, doorbell 27, mhu-rx
+ <&mhu_rx 0 0>; //data-transfer protocol with 1 window, mhu-rx
+ memory-region = <&dsp_reserved>;
};
};
diff --git a/Bindings/mailbox/fsl,mu.yaml b/Bindings/mailbox/fsl,mu.yaml
index 1a3dff2..675ad9d 100644
--- a/Bindings/mailbox/fsl,mu.yaml
+++ b/Bindings/mailbox/fsl,mu.yaml
@@ -26,6 +26,7 @@
oneOf:
- const: fsl,imx6sx-mu
- const: fsl,imx7ulp-mu
+ - const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- items:
- enum:
diff --git a/Bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
new file mode 100644
index 0000000..bbb173e
--- /dev/null
+++ b/Bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+ compatible:
+ const: microchip,polarfire-soc-mailbox
+
+ reg:
+ items:
+ - description: mailbox data registers
+ - description: mailbox interrupt registers
+
+ interrupts:
+ maxItems: 1
+
+ "#mbox-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ mbox: mailbox@37020000 {
+ compatible = "microchip,polarfire-soc-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
+ interrupt-parent = <&L1>;
+ interrupts = <96>;
+ #mbox-cells = <1>;
+ };
+ };
diff --git a/Bindings/mailbox/omap-mailbox.txt b/Bindings/mailbox/omap-mailbox.txt
deleted file mode 100644
index 12371f5..0000000
--- a/Bindings/mailbox/omap-mailbox.txt
+++ /dev/null
@@ -1,184 +0,0 @@
-OMAP2+ and K3 Mailbox
-=====================
-
-The OMAP mailbox hardware facilitates communication between different processors
-using a queued mailbox interrupt mechanism. The IP block is external to the
-various processor subsystems and is connected on an interconnect bus. The
-communication is achieved through a set of registers for message storage and
-interrupt configuration registers.
-
-Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
-interrupt lines. An output interrupt line is routed to an interrupt controller
-within a processor subsystem, and there can be more than one line going to a
-specific processor's interrupt controller. The interrupt line connections are
-fixed for an instance and are dictated by the IP integration into the SoC
-(excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
-programmable through a set of interrupt configuration registers, and have a rx
-and tx interrupt source per h/w fifo. Communication between different processors
-is achieved through the appropriate programming of the rx and tx interrupt
-sources on the appropriate interrupt lines.
-
-The number of h/w fifo queues and interrupt lines dictate the usable registers.
-All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
-instance. DRA7xx has multiple instances with different number of h/w fifo queues
-and interrupt lines between different instances. The interrupt lines can also be
-routed to different processor sub-systems on DRA7xx as they are routed through
-the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
-SoCs has each of these instances form a cluster and combine multiple clusters
-into a single IP block present within the Main NavSS. The interrupt lines from
-all these clusters are multiplexed and routed to different processor subsystems
-over a limited number of common interrupt output lines of an Interrupt Router.
-The AM64x SoCS also uses a single IP block comprising of multiple clusters,
-but the number of clusters are smaller, and the interrupt output lines are
-connected directly to various processors.
-
-Mailbox Device Node:
-====================
-A Mailbox device node is used to represent a Mailbox IP instance/cluster within
-a SoC. The sub-mailboxes are represented as child nodes of this parent node.
-
-Required properties:
---------------------
-- compatible: Should be one of the following,
- "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
- "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
- "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
- AM43xx and DRA7xx SoCs
- "ti,am654-mailbox" for K3 AM65x and J721E SoCs
- "ti,am64-mailbox" for K3 AM64x SoCs
-- reg: Contains the mailbox register address range (base
- address and length)
-- interrupts: Contains the interrupt information for the mailbox
- device. The format is dependent on which interrupt
- controller the Mailbox device uses
-- #mbox-cells: Common mailbox binding property to identify the number
- of cells required for the mailbox specifier. Should be
- 1
-- ti,mbox-num-users: Number of targets (processor devices) that the mailbox
- device can interrupt
-- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
-
-SoC-specific Required properties:
----------------------------------
-The following are mandatory properties for the OMAP architecture based SoCs
-only:
-- ti,hwmods: Name of the hwmod associated with the mailbox. This
- should be defined in the mailbox node only if the node
- is not defined as a child node of a corresponding sysc
- interconnect node.
-
-The following are mandatory properties for the K3 AM65x and J721E SoCs only:
-- interrupt-parent: Should contain a phandle to the TI-SCI interrupt
- controller node that is used to dynamically program
- the interrupt routes between the IP and the main GIC
- controllers. See the following binding for additional
- details,
- Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
-
-Child Nodes:
-============
-A child node is used for representing the actual sub-mailbox device that is
-used for the communication between the host processor and a remote processor.
-Each child node should have a unique node name across all the different
-mailbox device nodes.
-
-Required properties:
---------------------
-- ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
-- ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
-
-Sub-mailbox Descriptor Data
----------------------------
-Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
-data that represent the following:
- Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
- (ti,mbox-tx) or for receiving (ti,mbox-rx)
- Cell #2 (irq_id) - irq identifier index number to use from the parent's
- interrupts data. Should be 0 for most of the cases, a
- positive index value is seen only on mailboxes that have
- multiple interrupt lines connected to the MPU processor.
- Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
- associated with generating a tx/rx fifo interrupt.
-
-Optional Properties:
---------------------
-- ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
- to send messages without triggering a Tx ready interrupt,
- and to control the Tx ticker. Should be used only on
- sub-mailboxes used to communicate with WkupM3 remote
- processor on AM33xx/AM43xx SoCs.
-
-Mailbox Users:
-==============
-A device needing to communicate with a target processor device should specify
-them using the common mailbox binding properties, "mboxes" and the optional
-"mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
-for details). Each value of the mboxes property should contain a phandle to the
-mailbox controller device node and an args specifier that will be the phandle to
-the intended sub-mailbox child node to be used for communication. The equivalent
-"mbox-names" property value can be used to give a name to the communication channel
-to be used by the client user.
-
-
-Example:
---------
-
-1. /* OMAP4 */
-mailbox: mailbox@4a0f4000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x4a0f4000 0x200>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <3>;
- ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- mbox_dsp: mbox_dsp {
- ti,mbox-tx = <3 0 0>;
- ti,mbox-rx = <2 0 0>;
- };
-};
-
-dsp {
- ...
- mboxes = <&mailbox &mbox_dsp>;
- ...
-};
-
-2. /* AM33xx */
-mailbox: mailbox@480c8000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x480C8000 0x200>;
- interrupts = <77>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <0 0 3>;
- };
-};
-
-3. /* AM65x */
-&cbass_main {
- cbass_main_navss: interconnect0 {
- mailbox0_cluster0: mailbox@31f80000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f80000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- interrupts = <164 0>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
- };
- };
-};
diff --git a/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/Bindings/mailbox/qcom,apcs-kpss-global.yaml
index 5dc1173..8878ec0 100644
--- a/Bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -19,6 +19,7 @@
- qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8916-apcs-kpss-global
+ - qcom,msm8939-apcs-kpss-global
- qcom,msm8994-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
@@ -27,6 +28,7 @@
- qcom,sc8180x-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
+ - qcom,sm6125-apcs-hmss-global
- qcom,sm8150-apss-shared
reg:
@@ -75,6 +77,7 @@
- qcom,sc7180-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
+ - qcom,sm6125-apcs-hmss-global
- qcom,sm8150-apss-shared
then:
properties:
diff --git a/Bindings/mailbox/st,stm32-ipcc.yaml b/Bindings/mailbox/st,stm32-ipcc.yaml
index 3b7ab61..b15da9b 100644
--- a/Bindings/mailbox/st,stm32-ipcc.yaml
+++ b/Bindings/mailbox/st,stm32-ipcc.yaml
@@ -32,7 +32,6 @@
- description: tx channel free
- description: wakeup source
minItems: 2
- maxItems: 3
interrupt-names:
items:
@@ -40,7 +39,6 @@
- const: tx
- const: wakeup
minItems: 2
- maxItems: 3
wakeup-source: true
diff --git a/Bindings/mailbox/ti,omap-mailbox.yaml b/Bindings/mailbox/ti,omap-mailbox.yaml
new file mode 100644
index 0000000..e864d79
--- /dev/null
+++ b/Bindings/mailbox/ti,omap-mailbox.yaml
@@ -0,0 +1,308 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI OMAP2+ and K3 Mailbox devices
+
+maintainers:
+ - Suman Anna <s-anna@ti.com>
+
+description: |
+ The OMAP Mailbox hardware facilitates communication between different
+ processors using a queued mailbox interrupt mechanism. The IP block is
+ external to the various processor subsystems and is connected on an
+ interconnect bus. The communication is achieved through a set of registers
+ for message storage and interrupt configuration registers.
+
+ Each mailbox IP block/cluster has a certain number of h/w fifo queues and
+ output interrupt lines. An output interrupt line is routed to an interrupt
+ controller within a processor subsystem, and there can be more than one line
+ going to a specific processor's interrupt controller. The interrupt line
+ connections are fixed for an instance and are dictated by the IP integration
+ into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
+ Interrupt Router IP). Each interrupt line is programmable through a set of
+ interrupt configuration registers, and have a rx and tx interrupt source per
+ h/w fifo. Communication between different processors is achieved through the
+ appropriate programming of the rx and tx interrupt sources on the appropriate
+ interrupt lines.
+
+ The number of h/w fifo queues and interrupt lines dictate the usable
+ registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a
+ single IP instance. DRA7xx has multiple instances with different number of
+ h/w fifo queues and interrupt lines between different instances. The interrupt
+ lines can also be routed to different processor sub-systems on DRA7xx as they
+ are routed through the Crossbar, a kind of interrupt router/multiplexer. The
+ K3 AM65x, J721E and J7200 SoCs has each of these instances form a cluster and
+ combine multiple clusters into a single IP block present within the Main
+ NavSS. The interrupt lines from all these clusters are multiplexed and routed
+ to different processor subsystems over a limited number of common interrupt
+ output lines of an Interrupt Router. The AM64x SoCS also uses a single IP
+ block comprising of multiple clusters, but the number of clusters are
+ smaller, and the interrupt output lines are connected directly to various
+ processors.
+
+ Mailbox Controller Nodes
+ =========================
+ A Mailbox device node is used to represent a Mailbox IP instance/cluster
+ within a SoC. The sub-mailboxes (actual communication channels) are
+ represented as child nodes of this parent node.
+
+ Mailbox Users
+ ==============
+ A device needing to communicate with a target processor device should specify
+ them using the common mailbox binding properties, "mboxes" and the optional
+ "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
+ for details). Each value of the mboxes property should contain a phandle to
+ the mailbox controller device node and an args specifier that will be the
+ phandle to the intended sub-mailbox child node to be used for communication.
+ The equivalent "mbox-names" property value can be used to give a name to the
+ communication channel to be used by the client user.
+
+$defs:
+ omap-mbox-descriptor:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ The omap-mbox-descriptor is made of up of 3 cells and represents a single
+ uni-directional communication channel. A typical sub-mailbox device uses
+ two such channels - one for transmitting (Tx) and one for receiving (Rx).
+ items:
+ - description:
+ mailbox fifo id used either for transmitting on ti,mbox-tx channel or
+ for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
+ fifo number within a mailbox cluster.
+ - description:
+ irq identifier index number to use from the parent's interrupts data.
+ Should be 0 for most of the cases, a positive index value is seen only
+ on mailboxes that have multiple interrupt lines connected to the MPU
+ processor (irq_id). This is an index number in the listed interrupts
+ property in the DT nodes.
+ - description:
+ mailbox user id for identifying the interrupt line associated with
+ generating a tx/rx fifo interrupt (usr_id). This is the hardware
+ user id number within a mailbox cluster.
+
+ omap-sub-mailbox:
+ type: object
+ description:
+ The omap-sub-mailbox is a child node within a Mailbox controller device
+ node and represents the actual communication channel used to send and
+ receive messages between the host processor and a remote processor. Each
+ child node should have a unique node name across all the different mailbox
+ device nodes.
+
+ properties:
+ ti,mbox-tx:
+ $ref: "#/$defs/omap-mbox-descriptor"
+ description: sub-mailbox descriptor property defining a Tx fifo.
+
+ ti,mbox-rx:
+ $ref: "#/$defs/omap-mbox-descriptor"
+ description: sub-mailbox descriptor property defining a Rx fifo.
+
+ ti,mbox-send-noirq:
+ type: boolean
+ description:
+ Quirk flag to allow the client user of this sub-mailbox to send
+ messages without triggering a Tx ready interrupt, and to control
+ the Tx ticker. Should be used only on sub-mailboxes used to
+ communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs.
+
+ required:
+ - ti,mbox-tx
+ - ti,mbox-rx
+
+properties:
+ compatible:
+ enum:
+ - ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs
+ - ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs
+ - ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs
+ - ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs
+ - ti,am64-mailbox # for K3 AM64x SoCs
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Contains the interrupt information for the mailbox device. The format is
+ dependent on which interrupt controller the Mailbox device uses. The
+ number of interrupts listed will at most be the value specified in
+ ti,mbox-num-users property, but is usually limited by the number of
+ interrupts reaching the main processor. An interrupt-parent property
+ is required on SoCs where the interrupt lines are connected through a
+ Interrupt Router before reaching the main processor's GIC.
+
+ "#mbox-cells":
+ const: 1
+ description:
+ The specifier is a phandle to an omap-sub-mailbox device.
+
+ ti,mbox-num-users:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of targets (processor devices) that the mailbox device can
+ interrupt.
+
+ ti,mbox-num-fifos:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of h/w fifo queues within the mailbox IP block.
+
+ ti,hwmods:
+ $ref: /schemas/types.yaml#/definitions/string
+ deprecated: true
+ description:
+ Name of the hwmod associated with the mailbox. This should be defined
+ in the mailbox node only if the node is not defined as a child node of
+ a corresponding sysc interconnect node.
+
+ This property is only needed on some legacy OMAP SoCs which have not
+ yet been converted to the ti,sysc interconnect hierarachy, but is
+ otherwise considered obsolete.
+
+patternProperties:
+ "^mbox-[a-z0-9-]+$":
+ $ref: "#/$defs/omap-sub-mailbox"
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+ - ti,mbox-num-users
+ - ti,mbox-num-fifos
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-mailbox
+ then:
+ required:
+ - interrupt-parent
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-mailbox
+ - ti,am64-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ const: 4
+ ti,mbox-num-fifos:
+ const: 16
+ interrupts:
+ minItems: 1
+ maxItems: 4
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,omap4-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ enum: [3, 4]
+ ti,mbox-num-fifos:
+ enum: [8, 12]
+ interrupts:
+ minItems: 1
+ maxItems: 4
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,omap3-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ const: 2
+ ti,mbox-num-fifos:
+ const: 2
+ interrupts:
+ minItems: 1
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,omap2-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ const: 4
+ ti,mbox-num-fifos:
+ const: 6
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ /* OMAP4 */
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ mailbox: mailbox@4a0f4000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4a0f4000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+
+ mbox_ipu: mbox-ipu {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ mbox_dsp: mbox-dsp {
+ ti,mbox-tx = <3 0 0>;
+ ti,mbox-rx = <2 0 0>;
+ };
+ };
+
+ dsp {
+ mboxes = <&mailbox &mbox_dsp>;
+ };
+
+ - |
+ /* AM33xx */
+ mailbox1: mailbox@480c8000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x480c8000 0x200>;
+ interrupts = <77>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <8>;
+
+ mbox_wkupm3: mbox-wkup-m3 {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ ti,mbox-send-noirq;
+ };
+ };
+
+ - |
+ /* AM65x */
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x31f80000 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
+ };
diff --git a/Bindings/media/amlogic,gx-vdec.yaml b/Bindings/media/amlogic,gx-vdec.yaml
index b902495..5044c4b 100644
--- a/Bindings/media/amlogic,gx-vdec.yaml
+++ b/Bindings/media/amlogic,gx-vdec.yaml
@@ -67,7 +67,6 @@
clock-names:
minItems: 4
- maxItems: 5
items:
- const: dos_parser
- const: dos
diff --git a/Bindings/media/atmel,isc.yaml b/Bindings/media/atmel,isc.yaml
new file mode 100644
index 0000000..3e4bb88
--- /dev/null
+++ b/Bindings/media/atmel,isc.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Copyright (C) 2016-2021 Microchip Technology, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/atmel,isc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel Image Sensor Controller (ISC)
+
+maintainers:
+ - Eugen Hristev <eugen.hristev@microchip.com>
+
+description: |
+ The Image Sensor Controller (ISC) device provides the video input capabilities for the
+ Atmel/Microchip AT91 SAMA family of devices.
+
+ The ISC has a single parallel input that supports RAW Bayer, RGB or YUV video,
+ with both external synchronization and BT.656 synchronization for the latter.
+
+properties:
+ compatible:
+ const: atmel,sama5d2-isc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: hclock
+ - const: iscck
+ - const: gck
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ const: isc-mck
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port node, single endpoint describing the input pad.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+
+ properties:
+ remote-endpoint: true
+
+ bus-width:
+ enum: [8, 9, 10, 11, 12]
+ default: 12
+
+ hsync-active:
+ enum: [0, 1]
+ default: 1
+
+ vsync-active:
+ enum: [0, 1]
+ default: 1
+
+ pclk-sample:
+ enum: [0, 1]
+ default: 1
+
+ required:
+ - remote-endpoint
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - clock-output-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ isc: isc@f0008000 {
+ compatible = "atmel,sama5d2-isc";
+ reg = <0xf0008000 0x4000>;
+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
+ clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
+ clock-names = "hclock", "iscck", "gck";
+ #clock-cells = <0>;
+ clock-output-names = "isc-mck";
+
+ port {
+ isc_0: endpoint {
+ remote-endpoint = <&ov7740_0>;
+ hsync-active = <1>;
+ vsync-active = <0>;
+ pclk-sample = <1>;
+ bus-width = <8>;
+ };
+ };
+ };
diff --git a/Bindings/media/atmel-isc.txt b/Bindings/media/atmel-isc.txt
deleted file mode 100644
index bbe0e87..0000000
--- a/Bindings/media/atmel-isc.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Atmel Image Sensor Controller (ISC)
-----------------------------------------------
-
-Required properties for ISC:
-- compatible
- Must be "atmel,sama5d2-isc".
-- reg
- Physical base address and length of the registers set for the device.
-- interrupts
- Should contain IRQ line for the ISC.
-- clocks
- List of clock specifiers, corresponding to entries in
- the clock-names property;
- Please refer to clock-bindings.txt.
-- clock-names
- Required elements: "hclock", "iscck", "gck".
-- #clock-cells
- Should be 0.
-- clock-output-names
- Should be "isc-mck".
-- pinctrl-names, pinctrl-0
- Please refer to pinctrl-bindings.txt.
-
-ISC supports a single port node with parallel bus. It should contain one
-'port' child node with child 'endpoint' node. Please refer to the bindings
-defined in Documentation/devicetree/bindings/media/video-interfaces.txt.
-
-Example:
-isc: isc@f0008000 {
- compatible = "atmel,sama5d2-isc";
- reg = <0xf0008000 0x4000>;
- interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
- clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
- clock-names = "hclock", "iscck", "gck";
- #clock-cells = <0>;
- clock-output-names = "isc-mck";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
-
- port {
- isc_0: endpoint {
- remote-endpoint = <&ov7740_0>;
- hsync-active = <1>;
- vsync-active = <0>;
- pclk-sample = <1>;
- };
- };
-};
-
-i2c1: i2c@fc028000 {
- ov7740: camera@21 {
- compatible = "ovti,ov7740";
- reg = <0x21>;
- clocks = <&isc>;
- clock-names = "xvclk";
- assigned-clocks = <&isc>;
- assigned-clock-rates = <24000000>;
-
- port {
- ov7740_0: endpoint {
- remote-endpoint = <&isc_0>;
- };
- };
- };
-};
diff --git a/Bindings/media/i2c/adv7180.yaml b/Bindings/media/i2c/adv7180.yaml
index bcfd937..3ce4af1 100644
--- a/Bindings/media/i2c/adv7180.yaml
+++ b/Bindings/media/i2c/adv7180.yaml
@@ -36,7 +36,13 @@
maxItems: 1
port:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
ports: true
diff --git a/Bindings/media/i2c/adv7604.yaml b/Bindings/media/i2c/adv7604.yaml
index df634b0..de15ceb 100644
--- a/Bindings/media/i2c/adv7604.yaml
+++ b/Bindings/media/i2c/adv7604.yaml
@@ -30,7 +30,6 @@
reg-names:
minItems: 1
- maxItems: 13
items:
- const: main
- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
diff --git a/Bindings/media/i2c/imx258.yaml b/Bindings/media/i2c/imx258.yaml
index 515317e..cde0f73 100644
--- a/Bindings/media/i2c/imx258.yaml
+++ b/Bindings/media/i2c/imx258.yaml
@@ -49,7 +49,7 @@
# See ../video-interfaces.txt for more details
port:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
diff --git a/Bindings/media/i2c/maxim,max9286.yaml b/Bindings/media/i2c/maxim,max9286.yaml
index ee16102..02f656e 100644
--- a/Bindings/media/i2c/maxim,max9286.yaml
+++ b/Bindings/media/i2c/maxim,max9286.yaml
@@ -111,17 +111,10 @@
i2c-mux:
type: object
+ $ref: /schemas/i2c/i2c-mux.yaml#
+ unevaluatedProperties: false
description: |
- Each GMSL link is modelled as a child bus of an i2c bus
- multiplexer/switch, in accordance with bindings described in
- Documentation/devicetree/bindings/i2c/i2c-mux.txt.
-
- properties:
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
+ Each GMSL link is modelled as a child bus of an i2c bus multiplexer/switch.
patternProperties:
"^i2c@[0-3]$":
@@ -133,12 +126,6 @@
channels.
properties:
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
reg:
description: The index of the GMSL channel.
maxItems: 1
@@ -173,10 +160,6 @@
additionalProperties: false
- additionalProperties: false
-
- additionalProperties: false
-
required:
- compatible
- reg
diff --git a/Bindings/media/i2c/ovti,ov5648.yaml b/Bindings/media/i2c/ovti,ov5648.yaml
index 9149f56..246dc5f 100644
--- a/Bindings/media/i2c/ovti,ov5648.yaml
+++ b/Bindings/media/i2c/ovti,ov5648.yaml
@@ -45,7 +45,7 @@
port:
description: MIPI CSI-2 transmitter port
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
diff --git a/Bindings/media/i2c/ovti,ov8865.yaml b/Bindings/media/i2c/ovti,ov8865.yaml
index 0699c7e..b962863 100644
--- a/Bindings/media/i2c/ovti,ov8865.yaml
+++ b/Bindings/media/i2c/ovti,ov8865.yaml
@@ -45,7 +45,7 @@
port:
description: MIPI CSI-2 transmitter port
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
diff --git a/Bindings/media/i2c/rda,rda5807.yaml b/Bindings/media/i2c/rda,rda5807.yaml
new file mode 100644
index 0000000..f50e54a
--- /dev/null
+++ b/Bindings/media/i2c/rda,rda5807.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/rda,rda5807.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc Communications RDA5807 FM radio receiver
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ compatible:
+ enum:
+ - rda,rda5807
+
+ reg:
+ description: I2C address.
+ maxItems: 1
+
+ power-supply: true
+
+ rda,lnan:
+ description: Use LNAN input port.
+ type: boolean
+
+ rda,lnap:
+ description: Use LNAP input port.
+ type: boolean
+
+ rda,analog-out:
+ description: Enable analog audio output.
+ type: boolean
+
+ rda,i2s-out:
+ description: Enable I2S digital audio output.
+ type: boolean
+
+ rda,lna-microamp:
+ description: LNA working current, in micro-amperes.
+ default: 2500
+ enum: [1800, 2100, 2500, 3000]
+
+required:
+ - compatible
+ - reg
+ - power-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ radio@11 {
+ compatible = "rda,rda5807";
+ reg = <0x11>;
+
+ power-supply = <&ldo6>;
+
+ rda,lnan;
+ rda,lnap;
+ rda,analog-out;
+ };
+ };
diff --git a/Bindings/media/i2c/sony,imx334.yaml b/Bindings/media/i2c/sony,imx334.yaml
index 27cc5b7..f5055b9 100644
--- a/Bindings/media/i2c/sony,imx334.yaml
+++ b/Bindings/media/i2c/sony,imx334.yaml
@@ -37,7 +37,7 @@
port:
additionalProperties: false
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
properties:
endpoint:
diff --git a/Bindings/media/marvell,mmp2-ccic.yaml b/Bindings/media/marvell,mmp2-ccic.yaml
index c14c7d8..b39b84c 100644
--- a/Bindings/media/marvell,mmp2-ccic.yaml
+++ b/Bindings/media/marvell,mmp2-ccic.yaml
@@ -43,7 +43,6 @@
clocks:
minItems: 1
- maxItems: 3
items:
- description: AXI bus interface clock
- description: Peripheral clock
diff --git a/Bindings/media/mediatek-vcodec.txt b/Bindings/media/mediatek-vcodec.txt
index 06db683..ad1321e 100644
--- a/Bindings/media/mediatek-vcodec.txt
+++ b/Bindings/media/mediatek-vcodec.txt
@@ -9,6 +9,7 @@
"mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
"mediatek,mt8183-vcodec-enc" for MT8183 encoder.
"mediatek,mt8173-vcodec-dec" for MT8173 decoder.
+ "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
- reg : Physical base address of the video codec registers and length of
memory mapped region.
- interrupts : interrupt number to the cpu.
@@ -22,6 +23,7 @@
- iommus : should point to the respective IOMMU block with master port as
argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
for details.
+- dma-ranges : describes the dma address range space that the codec hw access.
One of the two following nodes:
- mediatek,vpu : the node of the video processor unit, if using VPU.
- mediatek,scp : the node of the SCP unit, if using SCP.
diff --git a/Bindings/media/microchip,sama5d4-vdec.yaml b/Bindings/media/microchip,sama5d4-vdec.yaml
new file mode 100644
index 0000000..4b77103
--- /dev/null
+++ b/Bindings/media/microchip,sama5d4-vdec.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/microchip,sama5d4-vdec.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Hantro G1 VPU codec implemented on Microchip SAMA5D4 SoCs
+
+maintainers:
+ - Emil Velikov <emil.velikov@collabora.com>
+
+description:
+ Hantro G1 video decode accelerator present on Microchip SAMA5D4 SoCs.
+
+properties:
+ compatible:
+ const: microchip,sama5d4-vdec
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ vdec0: vdec@300000 {
+ compatible = "microchip,sama5d4-vdec";
+ reg = <0x00300000 0x100000>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ };
diff --git a/Bindings/media/microchip,xisc.yaml b/Bindings/media/microchip,xisc.yaml
new file mode 100644
index 0000000..41afe2e
--- /dev/null
+++ b/Bindings/media/microchip,xisc.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Microchip Technology, Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/microchip,xisc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip eXtended Image Sensor Controller (XISC)
+
+maintainers:
+ - Eugen Hristev <eugen.hristev@microchip.com>
+
+description: |
+ The eXtended Image Sensor Controller (XISC) device provides the video input capabilities for the
+ Microchip AT91 SAM family of devices.
+
+ The XISC has a single internal parallel input that supports RAW Bayer, RGB or YUV video.
+ The source can be either a demuxer from a CSI2 type of bus, or a simple direct bridge to a
+ parallel sensor.
+
+ The XISC provides one clock output that is used to clock the demuxer/bridge.
+
+properties:
+ compatible:
+ const: microchip,sama7g5-isc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: hclock
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ const: isc-mck
+
+ microchip,mipi-mode:
+ type: boolean
+ description:
+ As the XISC is usually connected to a demux/bridge, the XISC receives
+ the same type of input, however, it should be aware of the type of
+ signals received. The mipi-mode enables different internal handling
+ of the data and clock lines.
+
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port node, single endpoint describing the input pad.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+
+ properties:
+ bus-type:
+ enum: [5, 6]
+
+ remote-endpoint: true
+
+ bus-width:
+ enum: [8, 9, 10, 11, 12]
+ default: 12
+
+ hsync-active:
+ enum: [0, 1]
+ default: 1
+
+ vsync-active:
+ enum: [0, 1]
+ default: 1
+
+ pclk-sample:
+ enum: [0, 1]
+ default: 1
+
+ required:
+ - remote-endpoint
+ - bus-type
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - clock-output-names
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/at91.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ xisc: xisc@e1408000 {
+ compatible = "microchip,sama7g5-isc";
+ reg = <0xe1408000 0x2000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 56>;
+ clock-names = "hclock";
+ #clock-cells = <0>;
+ clock-output-names = "isc-mck";
+
+ port {
+ xisc_in: endpoint {
+ bus-type = <5>; /* Parallel */
+ remote-endpoint = <&csi2dc_out>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ bus-width = <12>;
+ };
+ };
+ };
+
diff --git a/Bindings/media/nxp,imx7-mipi-csi2.yaml b/Bindings/media/nxp,imx7-mipi-csi2.yaml
index d8ed480..7c09eec 100644
--- a/Bindings/media/nxp,imx7-mipi-csi2.yaml
+++ b/Bindings/media/nxp,imx7-mipi-csi2.yaml
@@ -4,15 +4,17 @@
$id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: NXP i.MX7 MIPI CSI-2 receiver
+title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
maintainers:
- Rui Miguel Silva <rmfrfs@gmail.com>
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
description: |-
- The NXP i.MX7 SoC family includes a MIPI CSI-2 receiver IP core, documented
- as "CSIS V3.3". The IP core seems to originate from Samsung, and may be
- compatible with some of the Exynos4 ad S5P SoCs.
+ The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
+ receiver IP core named CSIS. The IP core originates from Samsung, and may be
+ compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
+ 3.3, and i.MX8 SoCs use CSIS version 3.6.3.
While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
completely wrapped by the CSIS and doesn't expose a control interface of its
@@ -20,7 +22,9 @@
properties:
compatible:
- const: fsl,imx7-mipi-csi2
+ enum:
+ - fsl,imx7-mipi-csi2
+ - fsl,imx8mm-mipi-csi2
reg:
maxItems: 1
@@ -29,16 +33,20 @@
maxItems: 1
clocks:
+ minItems: 3
items:
- description: The peripheral clock (a.k.a. APB clock)
- description: The external clock (optionally used as the pixel clock)
- description: The MIPI D-PHY clock
+ - description: The AXI clock
clock-names:
+ minItems: 3
items:
- const: pclk
- const: wrap
- const: phy
+ - const: axi
power-domains:
maxItems: 1
@@ -71,16 +79,30 @@
properties:
data-lanes:
- oneOf:
- - items:
- - const: 1
- - items:
- - const: 1
- - const: 2
+ items:
+ minItems: 1
+ maxItems: 4
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
required:
- data-lanes
+ allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx7-mipi-csi2
+ then:
+ properties:
+ data-lanes:
+ items:
+ maxItems: 2
+
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
@@ -93,12 +115,29 @@
- clocks
- clock-names
- power-domains
- - phy-supply
- - resets
- ports
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx7-mipi-csi2
+ then:
+ required:
+ - phy-supply
+ - resets
+ else:
+ properties:
+ clocks:
+ minItems: 4
+ clock-names:
+ minItems: 4
+ phy-supply: false
+ resets: false
+
examples:
- |
#include <dt-bindings/clock/imx7d-clock.h>
@@ -106,7 +145,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset/imx7-reset.h>
- mipi_csi: mipi-csi@30750000 {
+ mipi-csi@30750000 {
compatible = "fsl,imx7-mipi-csi2";
reg = <0x30750000 0x10000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -144,4 +183,46 @@
};
};
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ mipi-csi@32e30000 {
+ compatible = "fsl,imx8mm-mipi-csi2";
+ reg = <0x32e30000 0x1000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <333000000>;
+ clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MM_CLK_CSI1_ROOT>,
+ <&clk IMX8MM_CLK_CSI1_PHY_REF>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+ clock-names = "pclk", "wrap", "phy", "axi";
+ power-domains = <&mipi_pd>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ imx8mm_mipi_csi_in: endpoint {
+ remote-endpoint = <&imx477_out>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ imx8mm_mipi_csi_out: endpoint {
+ remote-endpoint = <&csi_in>;
+ };
+ };
+ };
+ };
+
...
diff --git a/Bindings/media/qcom,sc7180-venus.yaml b/Bindings/media/qcom,sc7180-venus.yaml
index 04013e5..90b4af2 100644
--- a/Bindings/media/qcom,sc7180-venus.yaml
+++ b/Bindings/media/qcom,sc7180-venus.yaml
@@ -30,7 +30,6 @@
power-domain-names:
minItems: 2
- maxItems: 3
items:
- const: venus
- const: vcodec0
diff --git a/Bindings/media/qcom,sdm845-venus-v2.yaml b/Bindings/media/qcom,sdm845-venus-v2.yaml
index 04b9af4..177bf81 100644
--- a/Bindings/media/qcom,sdm845-venus-v2.yaml
+++ b/Bindings/media/qcom,sdm845-venus-v2.yaml
@@ -30,7 +30,6 @@
power-domain-names:
minItems: 3
- maxItems: 4
items:
- const: venus
- const: vcodec0
diff --git a/Bindings/media/qcom,sm8250-venus.yaml b/Bindings/media/qcom,sm8250-venus.yaml
index 7b81bd7..ebf8f3d 100644
--- a/Bindings/media/qcom,sm8250-venus.yaml
+++ b/Bindings/media/qcom,sm8250-venus.yaml
@@ -30,7 +30,6 @@
power-domain-names:
minItems: 2
- maxItems: 3
items:
- const: venus
- const: vcodec0
diff --git a/Bindings/media/rc.yaml b/Bindings/media/rc.yaml
index af9e7e5..d4c541c 100644
--- a/Bindings/media/rc.yaml
+++ b/Bindings/media/rc.yaml
@@ -45,6 +45,7 @@
- rc-cec
- rc-cinergy
- rc-cinergy-1400
+ - rc-ct-90405
- rc-d680-dmb
- rc-delock-61959
- rc-dib0700-nec
@@ -125,7 +126,6 @@
- rc-snapstream-firefly
- rc-streamzap
- rc-su3000
- - rc-tango
- rc-tanix-tx3mini
- rc-tanix-tx5max
- rc-tbs-nec
diff --git a/Bindings/media/renesas,csi2.yaml b/Bindings/media/renesas,csi2.yaml
index 20396f1..23703b7 100644
--- a/Bindings/media/renesas,csi2.yaml
+++ b/Bindings/media/renesas,csi2.yaml
@@ -25,6 +25,7 @@
- renesas,r8a774e1-csi2 # RZ/G2H
- renesas,r8a7795-csi2 # R-Car H3
- renesas,r8a7796-csi2 # R-Car M3-W
+ - renesas,r8a77961-csi2 # R-Car M3-W+
- renesas,r8a77965-csi2 # R-Car M3-N
- renesas,r8a77970-csi2 # R-Car V3M
- renesas,r8a77980-csi2 # R-Car V3H
diff --git a/Bindings/media/renesas,drif.yaml b/Bindings/media/renesas,drif.yaml
index 9cd56ff..817a6d5 100644
--- a/Bindings/media/renesas,drif.yaml
+++ b/Bindings/media/renesas,drif.yaml
@@ -78,7 +78,6 @@
dma-names:
minItems: 1
- maxItems: 2
items:
- const: rx
- const: rx
diff --git a/Bindings/media/renesas,isp.yaml b/Bindings/media/renesas,isp.yaml
new file mode 100644
index 0000000..514857d
--- /dev/null
+++ b/Bindings/media/renesas,isp.yaml
@@ -0,0 +1,196 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+# Copyright (C) 2021 Renesas Electronics Corp.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/renesas,isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car ISP Channel Selector
+
+maintainers:
+ - Niklas Söderlund <niklas.soderlund@ragnatech.se>
+
+description:
+ The R-Car ISP Channel Selector provides MIPI CSI-2 VC and DT filtering
+ capabilities for the Renesas R-Car family of devices. It is used in
+ conjunction with the R-Car VIN and CSI-2 modules, which provides the video
+ capture capabilities.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,r8a779a0-isp # V3U
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port node, multiple endpoints describing the connected R-Car
+ CSI-2 receivers.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 0.
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 1.
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 2.
+
+ port@4:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 3.
+
+ port@5:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 4.
+
+ port@6:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 5.
+
+ port@7:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 6.
+
+ port@8:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Single endpoint describing the R-Car VIN connected to output port 7.
+
+ required:
+ - port@0
+ - port@1
+ - port@2
+ - port@3
+ - port@4
+ - port@5
+ - port@6
+ - port@7
+ - port@8
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - resets
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a779a0-sysc.h>
+
+ isp1: isp@fed20000 {
+ compatible = "renesas,r8a779a0-isp";
+ reg = <0xfed20000 0x10000>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 613>;
+ power-domains = <&sysc R8A779A0_PD_A3ISP01>;
+ resets = <&cpg 613>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0>;
+ isp1csi41: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&csi41isp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ isp1vin08: endpoint {
+ remote-endpoint = <&vin08isp1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ isp1vin09: endpoint {
+ remote-endpoint = <&vin09isp1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ isp1vin10: endpoint {
+ remote-endpoint = <&vin10isp1>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ isp1vin11: endpoint {
+ remote-endpoint = <&vin11isp1>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ isp1vin12: endpoint {
+ remote-endpoint = <&vin12isp1>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ isp1vin13: endpoint {
+ remote-endpoint = <&vin13isp1>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ isp1vin14: endpoint {
+ remote-endpoint = <&vin14isp1>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ isp1vin15: endpoint {
+ remote-endpoint = <&vin15isp1>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/media/renesas,vin.yaml b/Bindings/media/renesas,vin.yaml
index dd1a5ce..c0442e7 100644
--- a/Bindings/media/renesas,vin.yaml
+++ b/Bindings/media/renesas,vin.yaml
@@ -46,11 +46,13 @@
- renesas,vin-r8a7779 # R-Car H1
- renesas,vin-r8a7795 # R-Car H3
- renesas,vin-r8a7796 # R-Car M3-W
+ - renesas,vin-r8a77961 # R-Car M3-W+
- renesas,vin-r8a77965 # R-Car M3-N
- renesas,vin-r8a77970 # R-Car V3M
- renesas,vin-r8a77980 # R-Car V3H
- renesas,vin-r8a77990 # R-Car E3
- renesas,vin-r8a77995 # R-Car D3
+ - renesas,vin-r8a779a0 # R-Car V3U
reg:
maxItems: 1
@@ -111,14 +113,15 @@
description: VIN channel number
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
- maximum: 15
+ maximum: 31
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
description:
Input port node, single endpoint describing a parallel input source.
@@ -187,6 +190,29 @@
- required:
- endpoint@3
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port node, multiple endpoints describing all the R-Car ISP
+ modules connected the VIN.
+
+ properties:
+ endpoint@0:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Endpoint connected to ISP0.
+
+ endpoint@1:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Endpoint connected to ISP1.
+
+ endpoint@2:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Endpoint connected to ISP2.
+
+ endpoint@3:
+ $ref: /schemas/graph.yaml#/properties/endpoint
+ description: Endpoint connected to ISP3.
+
required:
- compatible
- reg
diff --git a/Bindings/media/rockchip,vdec.yaml b/Bindings/media/rockchip,vdec.yaml
index 8d35c32..089f11d 100644
--- a/Bindings/media/rockchip,vdec.yaml
+++ b/Bindings/media/rockchip,vdec.yaml
@@ -15,7 +15,11 @@
properties:
compatible:
- const: rockchip,rk3399-vdec
+ oneOf:
+ - const: rockchip,rk3399-vdec
+ - items:
+ - const: rockchip,rk3228-vdec
+ - const: rockchip,rk3399-vdec
reg:
maxItems: 1
@@ -37,6 +41,10 @@
- const: cabac
- const: core
+ assigned-clocks: true
+
+ assigned-clock-rates: true
+
power-domains:
maxItems: 1
diff --git a/Bindings/media/rockchip-vpu.yaml b/Bindings/media/rockchip-vpu.yaml
index c81dbc3..b88172a 100644
--- a/Bindings/media/rockchip-vpu.yaml
+++ b/Bindings/media/rockchip-vpu.yaml
@@ -15,10 +15,19 @@
properties:
compatible:
- enum:
- - rockchip,rk3288-vpu
- - rockchip,rk3328-vpu
- - rockchip,rk3399-vpu
+ oneOf:
+ - enum:
+ - rockchip,rk3036-vpu
+ - rockchip,rk3066-vpu
+ - rockchip,rk3288-vpu
+ - rockchip,rk3328-vpu
+ - rockchip,rk3399-vpu
+ - items:
+ - const: rockchip,rk3188-vpu
+ - const: rockchip,rk3066-vpu
+ - items:
+ - const: rockchip,rk3228-vpu
+ - const: rockchip,rk3399-vpu
reg:
maxItems: 1
@@ -35,12 +44,20 @@
- const: vdpu
clocks:
- maxItems: 2
+ oneOf:
+ - maxItems: 2
+ - maxItems: 4
clock-names:
- items:
- - const: aclk
- - const: hclk
+ oneOf:
+ - items:
+ - const: aclk
+ - const: hclk
+ - items:
+ - const: aclk_vdpu
+ - const: hclk_vdpu
+ - const: aclk_vepu
+ - const: hclk_vepu
power-domains:
maxItems: 1
diff --git a/Bindings/media/tango-ir.txt b/Bindings/media/tango-ir.txt
deleted file mode 100644
index a9f00c2..0000000
--- a/Bindings/media/tango-ir.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Sigma Designs Tango IR NEC/RC-5/RC-6 decoder (SMP86xx and SMP87xx)
-
-Required properties:
-
-- compatible: "sigma,smp8642-ir"
-- reg: address/size of NEC+RC5 area, address/size of RC6 area
-- interrupts: spec for IR IRQ
-- clocks: spec for IR clock (typically the crystal oscillator)
-
-Optional properties:
-
-- linux,rc-map-name: see Documentation/devicetree/bindings/media/rc.txt
-
-Example:
-
- ir@10518 {
- compatible = "sigma,smp8642-ir";
- reg = <0x10518 0x18>, <0x105e0 0x1c>;
- interrupts = <21 IRQ_TYPE_EDGE_RISING>;
- clocks = <&xtal>;
- };
diff --git a/Bindings/memory-controllers/arm,pl353-smc.yaml b/Bindings/memory-controllers/arm,pl353-smc.yaml
new file mode 100644
index 0000000..7a63c85
--- /dev/null
+++ b/Bindings/memory-controllers/arm,pl353-smc.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+ - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
+
+description:
+ The PL353 Static Memory Controller is a bus where you can connect two kinds
+ of memory interfaces, which are NAND and memory mapped interfaces (such as
+ SRAM or NOR).
+
+# We need a select here so we don't match all nodes with 'arm,primecell'
+select:
+ properties:
+ compatible:
+ contains:
+ const: arm,pl353-smc-r2p1
+ required:
+ - compatible
+
+properties:
+ $nodename:
+ pattern: "^memory-controller@[0-9a-f]+$"
+
+ compatible:
+ items:
+ - const: arm,pl353-smc-r2p1
+ - const: arm,primecell
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ reg:
+ items:
+ - description:
+ Configuration registers for the host and sub-controllers.
+ The three chip select regions are defined in 'ranges'.
+
+ clocks:
+ items:
+ - description: clock for the memory device bus
+ - description: main clock of the SMC
+
+ clock-names:
+ items:
+ - const: memclk
+ - const: apb_pclk
+
+ ranges:
+ minItems: 1
+ maxItems: 3
+ description: |
+ Memory bus areas for interacting with the devices. Reflects
+ the memory layout with four integer values following:
+ <cs-number> 0 <offset> <size>
+ items:
+ - description: NAND bank 0
+ - description: NOR/SRAM bank 0
+ - description: NOR/SRAM bank 1
+
+ interrupts: true
+
+patternProperties:
+ "@[0-3],[a-f0-9]+$":
+ type: object
+ description: |
+ The child device node represents the controller connected to the SMC
+ bus. The controller can be a NAND controller or a pair of any memory
+ mapped controllers such as NOR and SRAM controllers.
+
+ properties:
+ compatible:
+ description:
+ Compatible of memory controller.
+
+ reg:
+ items:
+ - items:
+ - description: |
+ Chip-select ID, as in the parent range property.
+ minimum: 0
+ maximum: 2
+ - description: |
+ Offset of the memory region requested by the device.
+ - description: |
+ Length of the memory region requested by the device.
+
+ required:
+ - compatible
+ - reg
+
+required:
+ - compatible
+ - reg
+ - clock-names
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ smcc: memory-controller@e000e000 {
+ compatible = "arm,pl353-smc-r2p1", "arm,primecell";
+ reg = <0xe000e000 0x0001000>;
+ clock-names = "memclk", "apb_pclk";
+ clocks = <&clkc 11>, <&clkc 44>;
+ ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
+ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
+ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ nfc0: nand-controller@0,0 {
+ compatible = "arm,pl353-nand-r2p1";
+ reg = <0 0 0x1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
diff --git a/Bindings/memory-controllers/mediatek,smi-common.yaml b/Bindings/memory-controllers/mediatek,smi-common.yaml
index a08a323..e87e438 100644
--- a/Bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Bindings/memory-controllers/mediatek,smi-common.yaml
@@ -53,14 +53,12 @@
apb and smi are mandatory. the async is only for generation 1 smi HW.
gals(global async local sync) also is optional, see below.
minItems: 2
- maxItems: 4
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
- description: smi is the clock for transfer data and command.
- - description: async is asynchronous clock, it help transform the smi
- clock into the emi clock domain.
- - description: gals0 is the path0 clock of gals.
+ - description: Either asynchronous clock to help transform the smi clock
+ into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
- description: gals1 is the path1 clock of gals.
clock-names:
diff --git a/Bindings/memory-controllers/mediatek,smi-larb.yaml b/Bindings/memory-controllers/mediatek,smi-larb.yaml
index 7ed7839..2353f6c 100644
--- a/Bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -37,7 +37,6 @@
description: |
apb and smi are mandatory. gals(global async local sync) is optional.
minItems: 2
- maxItems: 3
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
diff --git a/Bindings/memory-controllers/nvidia,tegra20-emc.txt b/Bindings/memory-controllers/nvidia,tegra20-emc.txt
deleted file mode 100644
index d225049..0000000
--- a/Bindings/memory-controllers/nvidia,tegra20-emc.txt
+++ /dev/null
@@ -1,130 +0,0 @@
-Embedded Memory Controller
-
-Properties:
-- name : Should be emc
-- #address-cells : Should be 1
-- #size-cells : Should be 0
-- compatible : Should contain "nvidia,tegra20-emc".
-- reg : Offset and length of the register set for the device
-- nvidia,use-ram-code : If present, the sub-nodes will be addressed
- and chosen using the ramcode board selector. If omitted, only one
- set of tables can be present and said tables will be used
- irrespective of ram-code configuration.
-- interrupts : Should contain EMC General interrupt.
-- clocks : Should contain EMC clock.
-- nvidia,memory-controller : Phandle of the Memory Controller node.
-- #interconnect-cells : Should be 0.
-- operating-points-v2: See ../bindings/opp/opp.txt for details.
-
-For each opp entry in 'operating-points-v2' table:
-- opp-supported-hw: One bitfield indicating SoC process ID mask
-
- A bitwise AND is performed against this value and if any bit
- matches, the OPP gets enabled.
-
-Optional properties:
-- power-domains: Phandle of the SoC "core" power domain.
-
-Child device nodes describe the memory settings for different configurations and clock rates.
-
-Example:
-
- opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp@36000000 {
- opp-microvolt = <950000 950000 1300000>;
- opp-hz = /bits/ 64 <36000000>;
- };
- ...
- };
-
- memory-controller@7000f400 {
- #address-cells = < 1 >;
- #size-cells = < 0 >;
- #interconnect-cells = <0>;
- compatible = "nvidia,tegra20-emc";
- reg = <0x7000f400 0x400>;
- interrupts = <0 78 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_EMC>;
- nvidia,memory-controller = <&mc>;
- power-domains = <&domain>;
- operating-points-v2 = <&opp_table>;
- }
-
-
-Embedded Memory Controller ram-code table
-
-If the emc node has the nvidia,use-ram-code property present, then the
-next level of nodes below the emc table are used to specify which settings
-apply for which ram-code settings.
-
-If the emc node lacks the nvidia,use-ram-code property, this level is omitted
-and the tables are stored directly under the emc node (see below).
-
-Properties:
-
-- name : Should be emc-tables
-- nvidia,ram-code : the binary representation of the ram-code board strappings
- for which this node (and children) are valid.
-
-
-
-Embedded Memory Controller configuration table
-
-This is a table containing the EMC register settings for the various
-operating speeds of the memory controller. They are always located as
-subnodes of the emc controller node.
-
-There are two ways of specifying which tables to use:
-
-* The simplest is if there is just one set of tables in the device tree,
- and they will always be used (based on which frequency is used).
- This is the preferred method, especially when firmware can fill in
- this information based on the specific system information and just
- pass it on to the kernel.
-
-* The slightly more complex one is when more than one memory configuration
- might exist on the system. The Tegra20 platform handles this during
- early boot by selecting one out of possible 4 memory settings based
- on a 2-pin "ram code" bootstrap setting on the board. The values of
- these strappings can be read through a register in the SoC, and thus
- used to select which tables to use.
-
-Properties:
-- name : Should be emc-table
-- compatible : Should contain "nvidia,tegra20-emc-table".
-- reg : either an opaque enumerator to tell different tables apart, or
- the valid frequency for which the table should be used (in kHz).
-- clock-frequency : the clock frequency for the EMC at which this
- table should be used (in kHz).
-- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
- for operation at the 'clock-frequency' setting.
- The order and contents of the registers are:
- RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
- WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
- PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
- TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
- ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
- ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
- CFG_CLKTRIM_1, CFG_CLKTRIM_2
-
- emc-table@166000 {
- reg = <166000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = < 166000 >;
- nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 >;
- };
-
- emc-table@333000 {
- reg = <333000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = < 333000 >;
- nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 >;
- };
diff --git a/Bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Bindings/memory-controllers/nvidia,tegra20-emc.yaml
new file mode 100644
index 0000000..cac6842
--- /dev/null
+++ b/Bindings/memory-controllers/nvidia,tegra20-emc.yaml
@@ -0,0 +1,230 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra20 SoC External Memory Controller
+
+maintainers:
+ - Dmitry Osipenko <digetx@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
+ service the request stream sent from Memory Controller. The EMC also has
+ various performance-affecting settings beyond the obvious SDRAM configuration
+ parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
+ standard protocols: DDR1, LPDDR2 and DDR2.
+
+properties:
+ compatible:
+ const: nvidia,tegra20-emc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#interconnect-cells":
+ const: 0
+
+ nvidia,memory-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of the Memory Controller node.
+
+ power-domains:
+ maxItems: 1
+ description:
+ Phandle of the SoC "core" power domain.
+
+ operating-points-v2:
+ description:
+ Should contain freqs and voltages and opp-supported-hw property, which
+ is a bitfield indicating SoC process ID mask.
+
+ nvidia,use-ram-code:
+ type: boolean
+ description:
+ If present, the emc-tables@ sub-nodes will be addressed.
+
+$defs:
+ emc-table:
+ type: object
+ properties:
+ compatible:
+ const: nvidia,tegra20-emc-table
+
+ clock-frequency:
+ description:
+ Memory clock rate in kHz.
+ minimum: 1000
+ maximum: 900000
+
+ reg:
+ maxItems: 1
+ description:
+ Either an opaque enumerator to tell different tables apart, or
+ the valid frequency for which the table should be used (in kHz).
+
+ nvidia,emc-registers:
+ description:
+ EMC timing characterization data. These are the registers
+ (see section "15.4.1 EMC Registers" in the TRM) whose values
+ need to be specified, according to the board documentation.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: EMC_RC
+ - description: EMC_RFC
+ - description: EMC_RAS
+ - description: EMC_RP
+ - description: EMC_R2W
+ - description: EMC_W2R
+ - description: EMC_R2P
+ - description: EMC_W2P
+ - description: EMC_RD_RCD
+ - description: EMC_WR_RCD
+ - description: EMC_RRD
+ - description: EMC_REXT
+ - description: EMC_WDV
+ - description: EMC_QUSE
+ - description: EMC_QRST
+ - description: EMC_QSAFE
+ - description: EMC_RDV
+ - description: EMC_REFRESH
+ - description: EMC_BURST_REFRESH_NUM
+ - description: EMC_PDEX2WR
+ - description: EMC_PDEX2RD
+ - description: EMC_PCHG2PDEN
+ - description: EMC_ACT2PDEN
+ - description: EMC_AR2PDEN
+ - description: EMC_RW2PDEN
+ - description: EMC_TXSR
+ - description: EMC_TCKE
+ - description: EMC_TFAW
+ - description: EMC_TRPAB
+ - description: EMC_TCLKSTABLE
+ - description: EMC_TCLKSTOP
+ - description: EMC_TREFBW
+ - description: EMC_QUSE_EXTRA
+ - description: EMC_FBIO_CFG6
+ - description: EMC_ODT_WRITE
+ - description: EMC_ODT_READ
+ - description: EMC_FBIO_CFG5
+ - description: EMC_CFG_DIG_DLL
+ - description: EMC_DLL_XFORM_DQS
+ - description: EMC_DLL_XFORM_QUSE
+ - description: EMC_ZCAL_REF_CNT
+ - description: EMC_ZCAL_WAIT_CNT
+ - description: EMC_AUTO_CAL_INTERVAL
+ - description: EMC_CFG_CLKTRIM_0
+ - description: EMC_CFG_CLKTRIM_1
+ - description: EMC_CFG_CLKTRIM_2
+
+ required:
+ - clock-frequency
+ - compatible
+ - reg
+ - nvidia,emc-registers
+
+ additionalProperties: false
+
+patternProperties:
+ "^emc-table@[0-9]+$":
+ $ref: "#/$defs/emc-table"
+
+ "^emc-tables@[a-z0-9-]+$":
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+ description:
+ An opaque enumerator to tell different tables apart.
+
+ nvidia,ram-code:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Value of RAM_CODE this timing set is used for.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^emc-table@[0-9]+$":
+ $ref: "#/$defs/emc-table"
+
+ required:
+ - nvidia,ram-code
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - nvidia,memory-controller
+ - "#interconnect-cells"
+ - operating-points-v2
+
+additionalProperties: false
+
+examples:
+ - |
+ external-memory-controller@7000f400 {
+ compatible = "nvidia,tegra20-emc";
+ reg = <0x7000f400 0x400>;
+ interrupts = <0 78 4>;
+ clocks = <&clock_controller 57>;
+
+ nvidia,memory-controller = <&mc>;
+ operating-points-v2 = <&dvfs_opp_table>;
+ power-domains = <&domain>;
+
+ #interconnect-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nvidia,use-ram-code;
+
+ emc-tables@0 {
+ nvidia,ram-code = <0>;
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000018 0x00000033
+ 0x00000012 0x00000004 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000bff
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xf0440303
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+ };
diff --git a/Bindings/memory-controllers/pl353-smc.txt b/Bindings/memory-controllers/pl353-smc.txt
deleted file mode 100644
index d56615f..0000000
--- a/Bindings/memory-controllers/pl353-smc.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Device tree bindings for ARM PL353 static memory controller
-
-PL353 static memory controller supports two kinds of memory
-interfaces.i.e NAND and SRAM/NOR interfaces.
-The actual devices are instantiated from the child nodes of pl353 smc node.
-
-Required properties:
-- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
-- reg : Controller registers map and length.
-- clock-names : List of input clock names - "memclk", "apb_pclk"
- (See clock bindings for details).
-- clocks : Clock phandles (see clock bindings for details).
-- address-cells : Must be 2.
-- size-cells : Must be 1.
-
-Child nodes:
- For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
-supported as child nodes.
-
-for NAND partition information please refer the below file
-Documentation/devicetree/bindings/mtd/partition.txt
-
-Example:
- smcc: memory-controller@e000e000
- compatible = "arm,pl353-smc-r2p1", "arm,primecell";
- clock-names = "memclk", "apb_pclk";
- clocks = <&clkc 11>, <&clkc 44>;
- reg = <0xe000e000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
- 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
- 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
- nand_0: flash@e1000000 {
- compatible = "arm,pl353-nand-r2p1"
- reg = <0 0 0x1000000>;
- (...)
- };
- nor0: flash@e2000000 {
- compatible = "cfi-flash";
- reg = <1 0 0x2000000>;
- };
- nor1: flash@e4000000 {
- compatible = "cfi-flash";
- reg = <2 0 0x2000000>;
- };
- };
diff --git a/Bindings/mfd/google,cros-ec.yaml b/Bindings/mfd/google,cros-ec.yaml
index 4dfa70a..d793dd0 100644
--- a/Bindings/mfd/google,cros-ec.yaml
+++ b/Bindings/mfd/google,cros-ec.yaml
@@ -117,6 +117,22 @@
- "#address-cells"
- "#size-cells"
+ cbas:
+ type: object
+
+ description:
+ This device is used to signal when a detachable base is attached
+ to a Chrome OS tablet. This device cannot be detected at runtime.
+
+ properties:
+ compatible:
+ const: google,cros-cbas
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
patternProperties:
"^i2c-tunnel[0-9]*$":
type: object
@@ -187,6 +203,10 @@
proximity {
compatible = "google,cros-ec-mkbp-proximity";
};
+
+ cbas {
+ compatible = "google,cros-cbas";
+ };
};
};
diff --git a/Bindings/mfd/motorola-cpcap.txt b/Bindings/mfd/motorola-cpcap.txt
index b52e7a3..1902302 100644
--- a/Bindings/mfd/motorola-cpcap.txt
+++ b/Bindings/mfd/motorola-cpcap.txt
@@ -16,8 +16,8 @@
The sub-functions of CPCAP get their own node with their own compatible values,
which are described in the following files:
-- Documentation/devicetree/bindings/power/supply/cpcap-battery.txt
-- Documentation/devicetree/bindings/power/supply/cpcap-charger.txt
+- Documentation/devicetree/bindings/power/supply/cpcap-battery.yaml
+- Documentation/devicetree/bindings/power/supply/cpcap-charger.yaml
- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt
- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
diff --git a/Bindings/mfd/mt6397.txt b/Bindings/mfd/mt6397.txt
index 2661775..99a84b6 100644
--- a/Bindings/mfd/mt6397.txt
+++ b/Bindings/mfd/mt6397.txt
@@ -21,6 +21,7 @@
compatible:
"mediatek,mt6323" for PMIC MT6323
"mediatek,mt6358" for PMIC MT6358
+ "mediatek,mt6359" for PMIC MT6359
"mediatek,mt6397" for PMIC MT6397
Optional subnodes:
diff --git a/Bindings/mfd/qcom,pm8008.yaml b/Bindings/mfd/qcom,pm8008.yaml
new file mode 100644
index 0000000..7799368
--- /dev/null
+++ b/Bindings/mfd/qcom,pm8008.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/qcom,pm8008.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. PM8008 PMIC bindings
+
+maintainers:
+ - Guru Das Srinagesh <gurus@codeaurora.org>
+
+description: |
+ Qualcomm Technologies, Inc. PM8008 is a dedicated camera PMIC that integrates
+ all the necessary power management, housekeeping, and interface support
+ functions into a single IC.
+
+properties:
+ compatible:
+ const: qcom,pm8008
+
+ reg:
+ description:
+ I2C slave address.
+
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ description: Parent interrupt.
+
+ "#interrupt-cells":
+ const: 2
+
+ description: |
+ The first cell is the IRQ number, the second cell is the IRQ trigger
+ flag. All interrupts are listed in include/dt-bindings/mfd/qcom-pm8008.h.
+
+ interrupt-controller: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^gpio@[0-9a-f]+$":
+ type: object
+
+ description: |
+ The GPIO peripheral. This node may be specified twice, one for each GPIO.
+
+ properties:
+ compatible:
+ const: qcom,pm8008-gpio
+
+ reg:
+ description: Peripheral address of one of the two GPIO peripherals.
+ maxItems: 1
+
+ gpio-controller: true
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ "#gpio-cells":
+ const: 2
+
+ required:
+ - compatible
+ - reg
+ - gpio-controller
+ - interrupt-controller
+ - "#gpio-cells"
+ - "#interrupt-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/mfd/qcom-pm8008.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pm8008i@8 {
+ compatible = "qcom,pm8008";
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <32 IRQ_TYPE_EDGE_RISING>;
+
+ gpio@c000 {
+ compatible = "qcom,pm8008-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/mfd/qcom,spmi-pmic.txt b/Bindings/mfd/qcom,spmi-pmic.txt
index 79367a4..5ef79bf 100644
--- a/Bindings/mfd/qcom,spmi-pmic.txt
+++ b/Bindings/mfd/qcom,spmi-pmic.txt
@@ -34,6 +34,10 @@
"qcom,pm8998",
"qcom,pmi8998",
"qcom,pm8005",
+ "qcom,pm8350c",
+ "qcom,pmk8350",
+ "qcom,pm7325",
+ "qcom,pmr735a",
or generalized "qcom,spmi-pmic".
- reg: Specifies the SPMI USID slave address for this device.
For more information see:
diff --git a/Bindings/mfd/richtek,rt4831.yaml b/Bindings/mfd/richtek,rt4831.yaml
new file mode 100644
index 0000000..4762eb1
--- /dev/null
+++ b/Bindings/mfd/richtek,rt4831.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/richtek,rt4831.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Richtek RT4831 DSV and Backlight Integrated IC
+
+maintainers:
+ - ChiYuan Huang <cy_huang@richtek.com>
+
+description: |
+ RT4831 is a multifunctional device that can provide power to the LCD display
+ and LCD backlight.
+
+ For Display Bias Voltage DSVP and DSVN, the output range is about 4V to 6.5V.
+ It's sufficient to meet the current LCD power requirement.
+
+ For the LCD backlight, it can provide four channel WLED driving capability.
+ Each channel driving current is up to 30mA
+
+ Datasheet is available at
+ https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
+
+properties:
+ compatible:
+ const: richtek,rt4831
+
+ reg:
+ description: I2C device address.
+ maxItems: 1
+
+ enable-gpios:
+ description: |
+ GPIO to enable/disable the chip. It is optional.
+ Some usage directly tied this pin to follow VIO 1.8V power on sequence.
+ maxItems: 1
+
+ regulators:
+ $ref: ../regulator/richtek,rt4831-regulator.yaml
+
+ backlight:
+ $ref: ../leds/backlight/richtek,rt4831-backlight.yaml
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/rt4831-backlight.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rt4831@11 {
+ compatible = "richtek,rt4831";
+ reg = <0x11>;
+
+ regulators {
+ DSVLCM {
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <7150000>;
+ regulator-allow-bypass;
+ };
+ DSVP {
+ regulator-name = "rt4831-dsvp";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6500000>;
+ regulator-boot-on;
+ };
+ DSVN {
+ regulator-name = "rt4831-dsvn";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6500000>;
+ regulator-boot-on;
+ };
+ };
+
+ backlight {
+ compatible = "richtek,rt4831-backlight";
+ default-brightness = <1024>;
+ max-brightness = <2048>;
+ richtek,bled-ovp-sel = /bits/ 8 <RT4831_BLOVPLVL_21V>;
+ richtek,channel-use = /bits/ 8 <RT4831_BLED_ALLCHEN>;
+ };
+ };
+ };
diff --git a/Bindings/mfd/rk808.txt b/Bindings/mfd/rk808.txt
index 04df07f..23a17a6 100644
--- a/Bindings/mfd/rk808.txt
+++ b/Bindings/mfd/rk808.txt
@@ -23,6 +23,7 @@
default output clock name
- rockchip,system-power-controller: Telling whether or not this pmic is controlling
the system power.
+- wakeup-source: Device can be used as a wakeup source.
Optional RK805 properties:
- vcc1-supply: The input supply for DCDC_REG1
@@ -63,8 +64,18 @@
- vcc9-supply: The input supply for DCDC_REG5, SWITCH_REG2
Optional RK817 properties:
+- clocks: The input clock for the audio codec
+- clock-names: The clock name for the codec clock. Should be "mclk".
+- #sound-dai-cells: Needed for the interpretation of sound dais. Should be 0.
+
- vcc8-supply: The input supply for BOOST
- vcc9-supply: The input supply for OTG_SWITCH
+- codec: The child node for the codec to hold additional properties.
+ If no additional properties are required for the codec, this
+ node can be omitted.
+
+- rockchip,mic-in-differential: Telling if the microphone uses differential
+ mode. Should be under the codec child node.
Optional RK818 properties:
- vcc1-supply: The input supply for DCDC_REG1
@@ -275,3 +286,180 @@
};
};
};
+
+ rk817: pmic@20 {
+ compatible = "rockchip,rk817";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S1_OUT>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
+ wakeup-source;
+ #clock-cells = <1>;
+ #sound-dai-cells = <0>;
+
+ vcc1-supply = <&vccsys>;
+ vcc2-supply = <&vccsys>;
+ vcc3-supply = <&vccsys>;
+ vcc4-supply = <&vccsys>;
+ vcc5-supply = <&vccsys>;
+ vcc6-supply = <&vccsys>;
+ vcc7-supply = <&vccsys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <950000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc_3v3: DCDC_REG4 {
+ regulator-name = "vcc_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG2 {
+ regulator-name = "vcc_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd_1v0: LDO_REG3 {
+ regulator-name = "vdd_1v0";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG4 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_sd: LDO_REG6 {
+ regulator-name = "vcc_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_bl: LDO_REG7 {
+ regulator-name = "vcc_bl";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_lcd: LDO_REG8 {
+ regulator-name = "vcc_lcd";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <2800000>;
+ };
+ };
+
+ vcc_cam: LDO_REG9 {
+ regulator-name = "vcc_cam";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <3000000>;
+ };
+ };
+ };
+
+ rk817_codec: codec {
+ rockchip,mic-in-differential;
+ };
+ };
diff --git a/Bindings/mfd/st,stm32-timers.yaml b/Bindings/mfd/st,stm32-timers.yaml
index 0f16c88..dace353 100644
--- a/Bindings/mfd/st,stm32-timers.yaml
+++ b/Bindings/mfd/st,stm32-timers.yaml
@@ -119,8 +119,6 @@
- compatible
required:
- - "#address-cells"
- - "#size-cells"
- compatible
- reg
- clocks
diff --git a/Bindings/mfd/stericsson,db8500-prcmu.yaml b/Bindings/mfd/stericsson,db8500-prcmu.yaml
new file mode 100644
index 0000000..a0d4bad
--- /dev/null
+++ b/Bindings/mfd/stericsson,db8500-prcmu.yaml
@@ -0,0 +1,278 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/stericsson,db8500-prcmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ST-Ericsson DB8500 PRCMU - Power Reset and Control Management Unit
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description:
+ The DB8500 Power Reset and Control Management Unit is an XP70 8-bit
+ microprocessor that is embedded in the always-on power domain of the
+ DB8500 SoCs to manage the low power states, powering up and down parts
+ of the silicon, and controlling reset of different IP blocks.
+
+properties:
+ $nodename:
+ pattern: '^prcmu@[0-9a-f]+$'
+
+ compatible:
+ description: The device is compatible both to the device-specific
+ compatible "stericsson,db8500-prcmu" and "syscon". The latter
+ compatible is needed for the device to be exposed as a system
+ controller so that arbitrary registers can be access by
+ different operating system components.
+ items:
+ - const: stericsson,db8500-prcmu
+ - const: syscon
+
+ reg:
+ items:
+ - description: Main PRCMU register area
+ - description: PRCMU TCPM register area
+ - description: PRCMU TCDM register area
+
+ reg-names:
+ items:
+ - const: prcmu
+ - const: prcmu-tcpm
+ - const: prcmu-tcdm
+
+ interrupts:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ ranges: true
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+ db8500-prcmu-regulators:
+ description: Node describing the DB8500 regulators. These are mainly
+ power rails inside the silicon but some of those are also routed
+ out to external pins.
+ type: object
+
+ properties:
+ compatible:
+ const: stericsson,db8500-prcmu-regulator
+
+ db8500_vape:
+ description: The voltage for the application processor, the
+ main voltage domain for the chip.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_varm:
+ description: The voltage for the ARM Cortex A-9 CPU.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_vmodem:
+ description: The voltage for the modem subsystem.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_vpll:
+ description: The voltage for the phase locked loop clocks.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_vsmps1:
+ description: Also known as VIO12, is a step-down voltage regulator
+ for 1.2V I/O. SMPS means System Management Power Source.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_vsmps2:
+ description: Also known as VIO18, is a step-down voltage regulator
+ for 1.8V I/O. SMPS means System Management Power Source.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_vsmps3:
+ description: This is a step-down voltage regulator
+ for 0.87 thru 1.875V I/O. SMPS means System Management Power Source.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_vrf1:
+ description: RF transciever voltage regulator.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_sva_mmdsp:
+ description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
+ voltage regulator. This is the voltage for the accelerator DSP
+ for video encoding and decoding.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_sva_mmdsp_ret:
+ description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
+ voltage regulator for retention mode.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_sva_pipe:
+ description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
+ voltage regulator for the data pipe.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_sia_mmdsp:
+ description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
+ voltage regulator. This is the voltage for the accelerator DSP
+ for image encoding and decoding.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_sia_mmdsp_ret:
+ description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
+ voltage regulator for retention mode.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_sia_pipe:
+ description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
+ voltage regulator for the data pipe.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_sga:
+ description: Smart Graphics Accelerator (SGA) voltage regulator.
+ This is in effect controlling the power to the MALI400 3D
+ accelerator block.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_b2r2_mcde:
+ description: Blit Blend Rotate and Rescale (B2R2), and Multi-Channel
+ Display Engine (MCDE) voltage regulator. These are two graphics
+ blocks.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_esram12:
+ description: Embedded Static RAM (ESRAM) 1 and 2 voltage regulator.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_esram12_ret:
+ description: Embedded Static RAM (ESRAM) 1 and 2 voltage regulator for
+ retention mode.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_esram34:
+ description: Embedded Static RAM (ESRAM) 3 and 4 voltage regulator.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ db8500_esram34_ret:
+ description: Embedded Static RAM (ESRAM) 3 and 4 voltage regulator for
+ retention mode.
+ type: object
+ $ref: ../regulator/regulator.yaml#
+
+ required:
+ - compatible
+ - db8500_vape
+ - db8500_varm
+ - db8500_vmodem
+ - db8500_vpll
+ - db8500_vsmps1
+ - db8500_vsmps2
+ - db8500_vsmps3
+ - db8500_vrf1
+ - db8500_sva_mmdsp
+ - db8500_sva_mmdsp_ret
+ - db8500_sva_pipe
+ - db8500_sia_mmdsp
+ - db8500_sia_mmdsp_ret
+ - db8500_sia_pipe
+ - db8500_sga
+ - db8500_b2r2_mcde
+ - db8500_esram12
+ - db8500_esram12_ret
+ - db8500_esram34
+ - db8500_esram34_ret
+
+ additionalProperties: false
+
+patternProperties:
+ "^thermal@[0-9a-f]+$":
+ description: Node describing the DB8500 thermal control functions.
+ This binds to an operating system driver that monitors the
+ temperature of the SoC.
+ type: object
+
+ properties:
+ compatible:
+ const: stericsson,db8500-thermal
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Hotmon low interrupt (falling temperature)
+ - description: Hotmon high interrupt (rising temperature)
+
+ interrupt-names:
+ items:
+ - const: IRQ_HOTMON_LOW
+ - const: IRQ_HOTMON_HIGH
+
+ '#thermal-sensor-cells':
+ const: 0
+
+ additionalProperties: false
+
+ "^prcmu-timer-4@[0-9a-f]+$":
+ description: Node describing the externally visible timer 4 in the
+ PRCMU block. This timer is interesting to the operating system
+ since even thought it has a very low resolution (32768 Hz) it is
+ always on, and thus provides a consistent monotonic timeline for
+ the system.
+ type: object
+
+ properties:
+ compatible:
+ const: stericsson,db8500-prcmu-timer-4
+
+ reg:
+ maxItems: 1
+
+ additionalProperties: false
+
+ "^ab850[05]$":
+ description: Node describing the Analog Baseband 8500 mixed-signals
+ ASIC AB8500 and subcomponents. The AB8500 is accessed through the
+ PRCMU and hence it appears here. This component has a separate
+ set of devicetree bindings. The AB8505 is a newer version of the
+ same ASIC.
+ type: object
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+ - ranges
+ - interrupts
+ - interrupt-controller
+ - '#interrupt-cells'
+ - db8500-prcmu-regulators
+
+additionalProperties: false
diff --git a/Bindings/mfd/ti,j721e-system-controller.yaml b/Bindings/mfd/ti,j721e-system-controller.yaml
index 19fcf59..272832e 100644
--- a/Bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Bindings/mfd/ti,j721e-system-controller.yaml
@@ -43,12 +43,10 @@
patternProperties:
# Optional children
- "^serdes-ln-ctrl@[0-9a-f]+$":
+ "^mux-controller@[0-9a-f]+$":
type: object
- description: |
- This is the SERDES lane control mux. It should follow the bindings
- specified in
- Documentation/devicetree/bindings/mux/reg-mux.txt
+ description:
+ This is the SERDES lane control mux.
required:
- compatible
@@ -68,9 +66,18 @@
#size-cells = <1>;
ranges;
- serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+ serdes_ln_ctrl: mux-controller@4080 {
compatible = "mmio-mux";
reg = <0x00004080 0x50>;
+
+ #mux-control-cells = <1>;
+ mux-reg-masks =
+ <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+ <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+ /* SERDES4 lane0/1/2/3 select */
};
};
...
diff --git a/Bindings/misc/eeprom-93xx46.txt b/Bindings/misc/eeprom-93xx46.txt
index 7b636b7..72ea0af 100644
--- a/Bindings/misc/eeprom-93xx46.txt
+++ b/Bindings/misc/eeprom-93xx46.txt
@@ -2,7 +2,10 @@
Required properties:
- compatible : shall be one of:
+ "atmel,at93c46"
"atmel,at93c46d"
+ "atmel,at93c56"
+ "atmel,at93c66"
"eeprom-93xx46"
"microchip,93lc46b"
- data-size : number of data bits per word (either 8 or 16)
diff --git a/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml
index e75b3a8..4f62ad6 100644
--- a/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml
+++ b/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml
@@ -64,7 +64,6 @@
clocks:
minItems: 2
- maxItems: 4
items:
- description: Bus Clock
- description: Module Clock
@@ -73,7 +72,6 @@
clock-names:
minItems: 2
- maxItems: 4
items:
- const: ahb
- const: mmc
diff --git a/Bindings/mmc/brcm,iproc-sdhci.yaml b/Bindings/mmc/brcm,iproc-sdhci.yaml
index 6f569fb..2f63f2c 100644
--- a/Bindings/mmc/brcm,iproc-sdhci.yaml
+++ b/Bindings/mmc/brcm,iproc-sdhci.yaml
@@ -21,6 +21,7 @@
- brcm,bcm2711-emmc2
- brcm,sdhci-iproc-cygnus
- brcm,sdhci-iproc
+ - brcm,bcm7211a0-sdhci
reg:
minItems: 1
diff --git a/Bindings/mmc/fsl-imx-esdhc.yaml b/Bindings/mmc/fsl-imx-esdhc.yaml
index 3694718..b5baf43 100644
--- a/Bindings/mmc/fsl-imx-esdhc.yaml
+++ b/Bindings/mmc/fsl-imx-esdhc.yaml
@@ -116,7 +116,6 @@
pinctrl-names:
minItems: 1
- maxItems: 4
items:
- const: default
- const: state_100mhz
diff --git a/Bindings/mmc/ingenic,mmc.yaml b/Bindings/mmc/ingenic,mmc.yaml
index 04ba8b7..546480f 100644
--- a/Bindings/mmc/ingenic,mmc.yaml
+++ b/Bindings/mmc/ingenic,mmc.yaml
@@ -19,6 +19,7 @@
- ingenic,jz4740-mmc
- ingenic,jz4725b-mmc
- ingenic,jz4760-mmc
+ - ingenic,jz4775-mmc
- ingenic,jz4780-mmc
- ingenic,x1000-mmc
- items:
diff --git a/Bindings/mmc/mmc-controller.yaml b/Bindings/mmc/mmc-controller.yaml
index e141330..25ac8e2 100644
--- a/Bindings/mmc/mmc-controller.yaml
+++ b/Bindings/mmc/mmc-controller.yaml
@@ -220,6 +220,11 @@
description:
eMMC HS400 enhanced strobe mode is supported
+ no-mmc-hs400:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ All eMMC HS400 modes are not supported.
+
dsr:
description:
Value the card Driver Stage Register (DSR) should be programmed
@@ -358,22 +363,6 @@
examples:
- |
- mmc@ab000000 {
- compatible = "sdhci";
- reg = <0xab000000 0x200>;
- interrupts = <23>;
- bus-width = <4>;
- cd-gpios = <&gpio 69 0>;
- cd-inverted;
- wp-gpios = <&gpio 70 0>;
- max-frequency = <50000000>;
- keep-power-in-suspend;
- wakeup-source;
- mmc-pwrseq = <&sdhci0_pwrseq>;
- clk-phase-sd-hs = <63>, <72>;
- };
-
- - |
mmc3: mmc@1c12000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -385,9 +374,9 @@
non-removable;
mmc-pwrseq = <&sdhci0_pwrseq>;
- brcmf: bcrmf@1 {
+ brcmf: wifi@1 {
reg = <1>;
- compatible = "brcm,bcm43xx-fmac";
+ compatible = "brcm,bcm4329-fmac";
interrupt-parent = <&pio>;
interrupts = <10 8>;
interrupt-names = "host-wake";
diff --git a/Bindings/mmc/mtk-sd.yaml b/Bindings/mmc/mtk-sd.yaml
index 8648d48..e866e98 100644
--- a/Bindings/mmc/mtk-sd.yaml
+++ b/Bindings/mmc/mtk-sd.yaml
@@ -31,6 +31,8 @@
- const: mediatek,mt2701-mmc
- items:
- const: mediatek,mt8192-mmc
+ - const: mediatek,mt8183-mmc
+ - items:
- const: mediatek,mt8195-mmc
- const: mediatek,mt8183-mmc
@@ -38,7 +40,6 @@
description:
Should contain phandle for the clock feeding the MMC controller.
minItems: 2
- maxItems: 8
items:
- description: source clock (required).
- description: HCLK which used for host (required).
@@ -51,7 +52,6 @@
clock-names:
minItems: 2
- maxItems: 8
items:
- const: source
- const: hclk
diff --git a/Bindings/mmc/renesas,mmcif.txt b/Bindings/mmc/renesas,mmcif.txt
deleted file mode 100644
index 291532a..0000000
--- a/Bindings/mmc/renesas,mmcif.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* Renesas Multi Media Card Interface (MMCIF) Controller
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the MMCIF device.
-
-
-Required properties:
-
-- compatible: should be "renesas,mmcif-<soctype>", "renesas,sh-mmcif" as a
- fallback. Examples with <soctype> are:
- - "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
- - "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
- - "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
- - "renesas,mmcif-r8a7742" for the MMCIF found in r8a7742 SoCs
- - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
- - "renesas,mmcif-r8a7744" for the MMCIF found in r8a7744 SoCs
- - "renesas,mmcif-r8a7745" for the MMCIF found in r8a7745 SoCs
- - "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
- - "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- - "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
- - "renesas,mmcif-r8a7793" for the MMCIF found in r8a7793 SoCs
- - "renesas,mmcif-r8a7794" for the MMCIF found in r8a7794 SoCs
- - "renesas,mmcif-sh73a0" for the MMCIF found in sh73a0 SoCs
-
-- interrupts: Some SoCs have only 1 shared interrupt, while others have either
- 2 or 3 individual interrupts (error, int, card detect). Below is the number
- of interrupts for each SoC:
- 1: r8a73a4, r8a7742, r8a7743, r8a7744, r8a7745, r8a7778, r8a7790, r8a7791,
- r8a7793, r8a7794
- 2: r8a7740, sh73a0
- 3: r7s72100
-
-- clocks: reference to the functional clock
-
-- dmas: reference to the DMA channels, one per channel name listed in the
- dma-names property.
-- dma-names: must contain "tx" for the transmit DMA channel and "rx" for the
- receive DMA channel.
-- max-frequency: Maximum operating clock frequency, driver uses default clock
- frequency if it is not set.
-
-
-Example: R8A7790 (R-Car H2) MMCIF0
-
- mmcif0: mmc@ee200000 {
- compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
- reg = <0 0xee200000 0 0x80>;
- interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
- dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
- dma-names = "tx", "rx";
- max-frequency = <97500000>;
- };
diff --git a/Bindings/mmc/renesas,mmcif.yaml b/Bindings/mmc/renesas,mmcif.yaml
new file mode 100644
index 0000000..c36ba56
--- /dev/null
+++ b/Bindings/mmc/renesas,mmcif.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/renesas,mmcif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas Multi Media Card Interface (MMCIF) Controller
+
+maintainers:
+ - Wolfram Sang <wsa+renesas@sang-engineering.com>
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,mmcif-r7s72100 # RZ/A1H
+ - renesas,mmcif-r8a73a4 # R-Mobile APE6
+ - renesas,mmcif-r8a7740 # R-Mobile A1
+ - renesas,mmcif-r8a7742 # RZ/G1H
+ - renesas,mmcif-r8a7743 # RZ/G1M
+ - renesas,mmcif-r8a7744 # RZ/G1N
+ - renesas,mmcif-r8a7745 # RZ/G1E
+ - renesas,mmcif-r8a7778 # R-Car M1A
+ - renesas,mmcif-r8a7790 # R-Car H2
+ - renesas,mmcif-r8a7791 # R-Car M2-W
+ - renesas,mmcif-r8a7793 # R-Car M2-N
+ - renesas,mmcif-r8a7794 # R-Car E2
+ - renesas,mmcif-sh73a0 # SH-Mobile AG5
+ - const: renesas,sh-mmcif
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dmas:
+ minItems: 2
+ maxItems: 4
+ description:
+ Must contain a list of pairs of references to DMA specifiers, one for
+ transmission, and one for reception.
+
+ dma-names:
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - tx
+ - rx
+
+ max-frequency: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,mmcif-r7s72100
+then:
+ properties:
+ interrupts:
+ items:
+ - description: Error interrupt
+ - description: Normal operation interrupt
+ - description: Card detection interrupt
+else:
+ if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,mmcif-r8a7740
+ - renesas,mmcif-sh73a0
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: Error interrupt
+ - description: Normal operation interrupt
+ else:
+ if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,mmcif-r8a73a4
+ - renesas,mmcif-r8a7778
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ required:
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7790-sysc.h>
+
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
+ reg = <0xee200000 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ };
diff --git a/Bindings/mmc/renesas,sdhi.yaml b/Bindings/mmc/renesas,sdhi.yaml
index 1118b6f..677989b 100644
--- a/Bindings/mmc/renesas,sdhi.yaml
+++ b/Bindings/mmc/renesas,sdhi.yaml
@@ -75,7 +75,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: core
- const: cd
@@ -107,7 +106,6 @@
pinctrl-names:
minItems: 1
- maxItems: 2
items:
- const: default
- const: state_uhs
diff --git a/Bindings/mmc/rockchip-dw-mshc.yaml b/Bindings/mmc/rockchip-dw-mshc.yaml
index 3762f1c..54fb598 100644
--- a/Bindings/mmc/rockchip-dw-mshc.yaml
+++ b/Bindings/mmc/rockchip-dw-mshc.yaml
@@ -29,21 +29,15 @@
- const: rockchip,rk3288-dw-mshc
- items:
- enum:
- # for Rockchip PX30
- rockchip,px30-dw-mshc
- # for Rockchip RK3036
+ - rockchip,rk1808-dw-mshc
- rockchip,rk3036-dw-mshc
- # for Rockchip RK322x
- rockchip,rk3228-dw-mshc
- # for Rockchip RK3308
- rockchip,rk3308-dw-mshc
- # for Rockchip RK3328
- rockchip,rk3328-dw-mshc
- # for Rockchip RK3368
- rockchip,rk3368-dw-mshc
- # for Rockchip RK3399
- rockchip,rk3399-dw-mshc
- # for Rockchip RV1108
+ - rockchip,rk3568-dw-mshc
- rockchip,rv1108-dw-mshc
- const: rockchip,rk3288-dw-mshc
diff --git a/Bindings/mmc/sdhci-am654.yaml b/Bindings/mmc/sdhci-am654.yaml
index 3a79e39..224303f 100644
--- a/Bindings/mmc/sdhci-am654.yaml
+++ b/Bindings/mmc/sdhci-am654.yaml
@@ -19,7 +19,6 @@
- const: ti,am654-sdhci-5.1
- const: ti,j721e-sdhci-8bit
- const: ti,j721e-sdhci-4bit
- - const: ti,j721e-sdhci-4bit
- const: ti,am64-sdhci-8bit
- const: ti,am64-sdhci-4bit
- items:
@@ -45,7 +44,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: clk_ahb
- const: clk_xin
diff --git a/Bindings/mmc/sdhci-pxa.yaml b/Bindings/mmc/sdhci-pxa.yaml
index aa12480..1c87f42 100644
--- a/Bindings/mmc/sdhci-pxa.yaml
+++ b/Bindings/mmc/sdhci-pxa.yaml
@@ -57,7 +57,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: io
- const: core
diff --git a/Bindings/mmc/ti-omap-hsmmc.txt b/Bindings/mmc/ti-omap-hsmmc.txt
index 4a9145e..57d077c 100644
--- a/Bindings/mmc/ti-omap-hsmmc.txt
+++ b/Bindings/mmc/ti-omap-hsmmc.txt
@@ -25,10 +25,10 @@
- power-domains:Should contain a phandle to a PM domain provider node
and an args specifier containing the MMC device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
- clocks: Must contain an entry for each entry in clock-names. Should
be defined as per the he appropriate clock bindings consumer
- usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ usage in Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
- clock-names: Shall be "fck" for the functional clock,
and "mmchsdb_fck" for the debounce clock.
diff --git a/Bindings/mtd/arm,pl353-nand-r2p1.yaml b/Bindings/mtd/arm,pl353-nand-r2p1.yaml
new file mode 100644
index 0000000..5f126bb
--- /dev/null
+++ b/Bindings/mtd/arm,pl353-nand-r2p1.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/arm,pl353-nand-r2p1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PL353 NAND Controller device tree bindings
+
+allOf:
+ - $ref: "nand-controller.yaml"
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+ - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
+
+properties:
+ compatible:
+ items:
+ - const: arm,pl353-nand-r2p1
+
+ reg:
+ items:
+ - items:
+ - description: CS with regard to the parent ranges property
+ - description: Offset of the memory region requested by the device
+ - description: Length of the memory region requested by the device
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ smcc: memory-controller@e000e000 {
+ compatible = "arm,pl353-smc-r2p1", "arm,primecell";
+ reg = <0xe000e000 0x0001000>;
+ clock-names = "memclk", "apb_pclk";
+ clocks = <&clkc 11>, <&clkc 44>;
+ ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */
+ 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */
+ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ nfc0: nand-controller@0,0 {
+ compatible = "arm,pl353-nand-r2p1";
+ reg = <0 0 0x1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
diff --git a/Bindings/mtd/arm-versatile.txt b/Bindings/mtd/arm-versatile.txt
deleted file mode 100644
index 4ec2879..0000000
--- a/Bindings/mtd/arm-versatile.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Flash device on ARM Versatile board
-
-These flash chips are found in the ARM reference designs like Integrator,
-Versatile, RealView, Versatile Express etc.
-
-They are regular CFI compatible (Intel or AMD extended) flash chips with
-some special write protect/VPP bits that can be controlled by the machine's
-system controller.
-
-Required properties:
-- compatible : must be "arm,versatile-flash", "cfi-flash";
-- reg : memory address for the flash chip
-- bank-width : width in bytes of flash interface.
-
-For the rest of the properties, see mtd-physmap.txt.
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
-flash@34000000 {
- compatible = "arm,versatile-flash", "cfi-flash";
- reg = <0x34000000 0x4000000>;
- bank-width = <4>;
-};
diff --git a/Bindings/mtd/brcm,brcmnand.txt b/Bindings/mtd/brcm,brcmnand.txt
deleted file mode 100644
index 44335a4..0000000
--- a/Bindings/mtd/brcm,brcmnand.txt
+++ /dev/null
@@ -1,186 +0,0 @@
-* Broadcom STB NAND Controller
-
-The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
-flash chips. It has a memory-mapped register interface for both control
-registers and for its data input/output buffer. On some SoCs, this controller is
-paired with a custom DMA engine (inventively named "Flash DMA") which supports
-basic PROGRAM and READ functions, among other features.
-
-This controller was originally designed for STB SoCs (BCM7xxx) but is now
-available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
-iProc/Cygnus. Its history includes several similar (but not fully register
-compatible) versions.
-
-Required properties:
-- compatible : May contain an SoC-specific compatibility string (see below)
- to account for any SoC-specific hardware bits that may be
- added on top of the base core controller.
- In addition, must contain compatibility information about
- the core NAND controller, of the following form:
- "brcm,brcmnand" and an appropriate version compatibility
- string, like "brcm,brcmnand-v7.0"
- Possible values:
- brcm,brcmnand-v2.1
- brcm,brcmnand-v2.2
- brcm,brcmnand-v4.0
- brcm,brcmnand-v5.0
- brcm,brcmnand-v6.0
- brcm,brcmnand-v6.1
- brcm,brcmnand-v6.2
- brcm,brcmnand-v7.0
- brcm,brcmnand-v7.1
- brcm,brcmnand-v7.2
- brcm,brcmnand-v7.3
- brcm,brcmnand
-- reg : the register start and length for NAND register region.
- (optional) Flash DMA register range (if present)
- (optional) NAND flash cache range (if at non-standard offset)
-- reg-names : a list of the names corresponding to the previous register
- ranges. Should contain "nand" and (optionally)
- "flash-dma" or "flash-edu" and/or "nand-cache".
-- interrupts : The NAND CTLRDY interrupt, (if Flash DMA is available)
- FLASH_DMA_DONE and if EDU is avaialble and used FLASH_EDU_DONE
-- interrupt-names : May be "nand_ctlrdy" or "flash_dma_done" or "flash_edu_done",
- if broken out as individual interrupts.
- May be "nand", if the SoC has the individual NAND
- interrupts multiplexed behind another custom piece of
- hardware
-- #address-cells : <1> - subnodes give the chip-select number
-- #size-cells : <0>
-
-Optional properties:
-- clock : reference to the clock for the NAND controller
-- clock-names : "nand" (required for the above clock)
-- brcm,nand-has-wp : Some versions of this IP include a write-protect
- (WP) control bit. It is always available on >=
- v7.0. Use this property to describe the rare
- earlier versions of this core that include WP
-
- -- Additional SoC-specific NAND controller properties --
-
-The NAND controller is integrated differently on the variety of SoCs on which it
-is found. Part of this integration involves providing status and enable bits
-with which to control the 8 exposed NAND interrupts, as well as hardware for
-configuring the endianness of the data bus. On some SoCs, these features are
-handled via standard, modular components (e.g., their interrupts look like a
-normal IRQ chip), but on others, they are controlled in unique and interesting
-ways, sometimes with registers that lump multiple NAND-related functions
-together. The former case can be described simply by the standard interrupts
-properties in the main controller node. But for the latter exceptional cases,
-we define additional 'compatible' properties and associated register resources within the NAND controller node above.
-
- - compatible: Can be one of several SoC-specific strings. Each SoC may have
- different requirements for its additional properties, as described below each
- bullet point below.
-
- * "brcm,nand-bcm63138"
- - reg: (required) the 'NAND_INT_BASE' register range, with separate status
- and enable registers
- - reg-names: (required) "nand-int-base"
-
- * "brcm,nand-bcm6368"
- - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
- - reg: (required) the 'NAND_INTR_BASE' register range, with combined status
- and enable registers, and boot address registers
- - reg-names: (required) "nand-int-base"
-
- * "brcm,nand-iproc"
- - reg: (required) the "IDM" register range, for interrupt enable and APB
- bus access endianness configuration, and the "EXT" register range,
- for interrupt status/ack.
- - reg-names: (required) a list of the names corresponding to the previous
- register ranges. Should contain "iproc-idm" and "iproc-ext".
-
-
-* NAND chip-select
-
-Each controller (compatible: "brcm,brcmnand") may contain one or more subnodes
-to represent enabled chip-selects which (may) contain NAND flash chips. Their
-properties are as follows.
-
-Required properties:
-- compatible : should contain "brcm,nandcs"
-- reg : a single integer representing the chip-select
- number (e.g., 0, 1, 2, etc.)
-- #address-cells : see partition.txt
-- #size-cells : see partition.txt
-
-Optional properties:
-- nand-ecc-strength : see nand-controller.yaml
-- nand-ecc-step-size : must be 512 or 1024. See nand-controller.yaml
-- nand-on-flash-bbt : boolean, to enable the on-flash BBT for this
- chip-select. See nand-controller.yaml
-- brcm,nand-oob-sector-size : integer, to denote the spare area sector size
- expected for the ECC layout in use. This size, in
- addition to the strength and step-size,
- determines how the hardware BCH engine will lay
- out the parity bytes it stores on the flash.
- This property can be automatically determined by
- the flash geometry (particularly the NAND page
- and OOB size) in many cases, but when booting
- from NAND, the boot controller has only a limited
- number of available options for its default ECC
- layout.
-
-Each nandcs device node may optionally contain sub-nodes describing the flash
-partition mapping. See partition.txt for more detail.
-
-
-Example:
-
-nand@f0442800 {
- compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
- reg = <0xF0442800 0x600>,
- <0xF0443000 0x100>;
- reg-names = "nand", "flash-dma";
- interrupt-parent = <&hif_intr2_intc>;
- interrupts = <24>, <4>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nandcs@1 {
- compatible = "brcm,nandcs";
- reg = <1>; // Chip select 1
- nand-on-flash-bbt;
- nand-ecc-strength = <12>;
- nand-ecc-step-size = <512>;
-
- // Partitions
- #address-cells = <1>; // <2>, for 64-bit offset
- #size-cells = <1>; // <2>, for 64-bit length
- flash0.rootfs@0 {
- reg = <0 0x10000000>;
- };
- flash0@0 {
- reg = <0 0>; // MTDPART_SIZ_FULL
- };
- flash0.kernel@10000000 {
- reg = <0x10000000 0x400000>;
- };
- };
-};
-
-nand@10000200 {
- compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
- "brcm,brcmnand-v4.0", "brcm,brcmnand";
- reg = <0x10000200 0x180>,
- <0x10000600 0x200>,
- <0x100000b0 0x10>;
- reg-names = "nand", "nand-cache", "nand-int-base";
- interrupt-parent = <&periph_intc>;
- interrupts = <50>;
- clocks = <&periph_clk 20>;
- clock-names = "nand";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- nand0: nandcs@0 {
- compatible = "brcm,nandcs";
- reg = <0>;
- nand-on-flash-bbt;
- nand-ecc-strength = <1>;
- nand-ecc-step-size = <512>;
- };
-};
diff --git a/Bindings/mtd/brcm,brcmnand.yaml b/Bindings/mtd/brcm,brcmnand.yaml
new file mode 100644
index 0000000..e5f1a33
--- /dev/null
+++ b/Bindings/mtd/brcm,brcmnand.yaml
@@ -0,0 +1,242 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/brcm,brcmnand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB NAND Controller
+
+maintainers:
+ - Brian Norris <computersforpeace@gmail.com>
+ - Kamal Dasu <kdasu.kdev@gmail.com>
+
+description: |
+ The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
+ flash chips. It has a memory-mapped register interface for both control
+ registers and for its data input/output buffer. On some SoCs, this controller
+ is paired with a custom DMA engine (inventively named "Flash DMA") which
+ supports basic PROGRAM and READ functions, among other features.
+
+ This controller was originally designed for STB SoCs (BCM7xxx) but is now
+ available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
+ iProc/Cygnus. Its history includes several similar (but not fully register
+ compatible) versions.
+
+ -- Additional SoC-specific NAND controller properties --
+
+ The NAND controller is integrated differently on the variety of SoCs on which
+ it is found. Part of this integration involves providing status and enable
+ bits with which to control the 8 exposed NAND interrupts, as well as hardware
+ for configuring the endianness of the data bus. On some SoCs, these features
+ are handled via standard, modular components (e.g., their interrupts look like
+ a normal IRQ chip), but on others, they are controlled in unique and
+ interesting ways, sometimes with registers that lump multiple NAND-related
+ functions together. The former case can be described simply by the standard
+ interrupts properties in the main controller node. But for the latter
+ exceptional cases, we define additional 'compatible' properties and associated
+ register resources within the NAND controller node above.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,brcmnand-v2.1
+ - brcm,brcmnand-v2.2
+ - brcm,brcmnand-v4.0
+ - brcm,brcmnand-v5.0
+ - brcm,brcmnand-v6.0
+ - brcm,brcmnand-v6.1
+ - brcm,brcmnand-v6.2
+ - brcm,brcmnand-v7.0
+ - brcm,brcmnand-v7.1
+ - brcm,brcmnand-v7.2
+ - brcm,brcmnand-v7.3
+ - const: brcm,brcmnand
+ - description: BCM63138 SoC-specific NAND controller
+ items:
+ - const: brcm,nand-bcm63138
+ - enum:
+ - brcm,brcmnand-v7.0
+ - brcm,brcmnand-v7.1
+ - const: brcm,brcmnand
+ - description: iProc SoC-specific NAND controller
+ items:
+ - const: brcm,nand-iproc
+ - const: brcm,brcmnand-v6.1
+ - const: brcm,brcmnand
+ - description: BCM63168 SoC-specific NAND controller
+ items:
+ - const: brcm,nand-bcm63168
+ - const: brcm,nand-bcm6368
+ - const: brcm,brcmnand-v4.0
+ - const: brcm,brcmnand
+
+ reg:
+ minItems: 1
+ maxItems: 6
+
+ reg-names:
+ minItems: 1
+ maxItems: 6
+ items:
+ enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
+
+ interrupts:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: NAND CTLRDY interrupt
+ - description: FLASH_DMA_DONE if flash DMA is available
+ - description: FLASH_EDU_DONE if EDU is available
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ - const: nand_ctlrdy
+ - const: flash_dma_done
+ - const: flash_edu_done
+
+ clocks:
+ maxItems: 1
+ description: reference to the clock for the NAND controller
+
+ clock-names:
+ const: nand
+
+ brcm,nand-has-wp:
+ description: >
+ Some versions of this IP include a write-protect
+ (WP) control bit. It is always available on >=
+ v7.0. Use this property to describe the rare
+ earlier versions of this core that include WP
+ type: boolean
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ compatible:
+ const: brcm,nandcs
+
+ nand-ecc-step-size:
+ enum: [ 512, 1024 ]
+
+ brcm,nand-oob-sector-size:
+ description: |
+ integer, to denote the spare area sector size
+ expected for the ECC layout in use. This size, in
+ addition to the strength and step-size,
+ determines how the hardware BCH engine will lay
+ out the parity bytes it stores on the flash.
+ This property can be automatically determined by
+ the flash geometry (particularly the NAND page
+ and OOB size) in many cases, but when booting
+ from NAND, the boot controller has only a limited
+ number of available options for its default ECC
+ layout.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+allOf:
+ - $ref: nand-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,nand-bcm63138
+ then:
+ properties:
+ reg-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ - const: nand
+ - const: nand-int-base
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,nand-bcm6368
+ then:
+ properties:
+ reg-names:
+ minItems: 3
+ maxItems: 3
+ items:
+ - const: nand
+ - const: nand-int-base
+ - const: nand-cache
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,nand-iproc
+ then:
+ properties:
+ reg-names:
+ minItems: 3
+ maxItems: 3
+ items:
+ - const: nand
+ - const: iproc-idm
+ - const: iproc-ext
+
+unevaluatedProperties: false
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+
+examples:
+ - |
+ nand-controller@f0442800 {
+ compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
+ reg = <0xf0442800 0x600>,
+ <0xf0443000 0x100>;
+ reg-names = "nand", "flash-dma";
+ interrupt-parent = <&hif_intr2_intc>;
+ interrupts = <24>, <4>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@1 {
+ compatible = "brcm,nandcs";
+ reg = <1>; // Chip select 1
+ nand-on-flash-bbt;
+ nand-ecc-strength = <12>;
+ nand-ecc-step-size = <512>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+ - |
+ nand-controller@10000200 {
+ compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
+ "brcm,brcmnand-v4.0", "brcm,brcmnand";
+ reg = <0x10000200 0x180>,
+ <0x100000b0 0x10>,
+ <0x10000600 0x200>;
+ reg-names = "nand", "nand-int-base", "nand-cache";
+ interrupt-parent = <&periph_intc>;
+ interrupts = <50>;
+ clocks = <&periph_clk 20>;
+ clock-names = "nand";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <1>;
+ nand-ecc-step-size = <512>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
diff --git a/Bindings/mtd/common.txt b/Bindings/mtd/common.txt
index fc068b9..ae16f9e 100644
--- a/Bindings/mtd/common.txt
+++ b/Bindings/mtd/common.txt
@@ -1,15 +1 @@
-* Common properties of all MTD devices
-
-Optional properties:
-- label: user-defined MTD device name. Can be used to assign user
- friendly names to MTD devices (instead of the flash model or flash
- controller based name) in order to ease flash device identification
- and/or describe what they are used for.
-
-Example:
-
- flash@0 {
- label = "System-firmware";
-
- /* flash type specific properties */
- };
+This file has been moved to mtd.yaml.
diff --git a/Bindings/mtd/cortina,gemini-flash.txt b/Bindings/mtd/cortina,gemini-flash.txt
index 3fa1b34..efa5b2a 100644
--- a/Bindings/mtd/cortina,gemini-flash.txt
+++ b/Bindings/mtd/cortina,gemini-flash.txt
@@ -9,7 +9,7 @@
- syscon : must be a phandle to the system controller
- bank-width : width in bytes of flash interface, should be <2>
-For the rest of the properties, see mtd-physmap.txt.
+For the rest of the properties, see mtd-physmap.yaml.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
diff --git a/Bindings/mtd/cypress,hyperflash.txt b/Bindings/mtd/cypress,hyperflash.txt
deleted file mode 100644
index ad42f4d..0000000
--- a/Bindings/mtd/cypress,hyperflash.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus
-specification and supports Cypress CFI specification 1.5 command set.
-
-Required properties:
-- compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips
-- reg : Address of flash's memory map
-
-Example:
-
- flash@0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x4000000>;
- };
diff --git a/Bindings/mtd/intel,ixp4xx-flash.txt b/Bindings/mtd/intel,ixp4xx-flash.txt
deleted file mode 100644
index 4bdcb92..0000000
--- a/Bindings/mtd/intel,ixp4xx-flash.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Flash device on Intel IXP4xx SoC
-
-This flash is regular CFI compatible (Intel or AMD extended) flash chips with
-specific big-endian or mixed-endian memory access pattern.
-
-Required properties:
-- compatible : must be "intel,ixp4xx-flash", "cfi-flash";
-- reg : memory address for the flash chip
-- bank-width : width in bytes of flash interface, should be <2>
-
-For the rest of the properties, see mtd-physmap.txt.
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
-flash@50000000 {
- compatible = "intel,ixp4xx-flash", "cfi-flash";
- reg = <0x50000000 0x01000000>;
- bank-width = <2>;
-};
diff --git a/Bindings/mtd/jedec,spi-nor.yaml b/Bindings/mtd/jedec,spi-nor.yaml
index 5e7e534..ed590d7 100644
--- a/Bindings/mtd/jedec,spi-nor.yaml
+++ b/Bindings/mtd/jedec,spi-nor.yaml
@@ -9,6 +9,9 @@
maintainers:
- Rob Herring <robh@kernel.org>
+allOf:
+ - $ref: "mtd.yaml#"
+
properties:
compatible:
oneOf:
@@ -82,6 +85,9 @@
'^partition@':
type: object
+ "^otp(-[0-9]+)?$":
+ type: object
+
additionalProperties: false
examples:
diff --git a/Bindings/mtd/microchip,mchp48l640.yaml b/Bindings/mtd/microchip,mchp48l640.yaml
new file mode 100644
index 0000000..2cdf6bf
--- /dev/null
+++ b/Bindings/mtd/microchip,mchp48l640.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mtd/microchip,mchp48l640.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip 48l640 (and similar) serial EERAM bindings
+
+maintainers:
+ - Heiko Schocher <hs@denx.de>
+
+description: |
+ The Microchip 48l640 is a 8KByte EERAM connected via SPI.
+
+ datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/20006055B.pdf
+
+properties:
+ compatible:
+ items:
+ - const: microchip,48l640
+
+ reg:
+ maxItems: 1
+
+ spi-max-frequency: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eeram@0 {
+ compatible = "microchip,48l640";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ };
+ };
+...
diff --git a/Bindings/mtd/mtd-physmap.txt b/Bindings/mtd/mtd-physmap.txt
deleted file mode 100644
index c69f4f0..0000000
--- a/Bindings/mtd/mtd-physmap.txt
+++ /dev/null
@@ -1,114 +0,0 @@
-CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
-
-Flash chips (Memory Technology Devices) are often used for solid state
-file systems on embedded devices.
-
- - compatible : should contain the specific model of mtd chip(s)
- used, if known, followed by either "cfi-flash", "jedec-flash",
- "mtd-ram" or "mtd-rom".
- - reg : Address range(s) of the mtd chip(s)
- It's possible to (optionally) define multiple "reg" tuples so that
- non-identical chips can be described in one node.
- - bank-width : Width (in bytes) of the bank. Equal to the
- device width times the number of interleaved chips.
- - device-width : (optional) Width of a single mtd chip. If
- omitted, assumed to be equal to 'bank-width'.
- - #address-cells, #size-cells : Must be present if the device has
- sub-nodes representing partitions (see below). In this case
- both #address-cells and #size-cells must be equal to 1.
- - no-unaligned-direct-access: boolean to disable the default direct
- mapping of the flash.
- On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
- problems with JFFS2 usage, as the local bus (LPB) doesn't support
- unaligned accesses as implemented in the JFFS2 code via memcpy().
- By defining "no-unaligned-direct-access", the flash will not be
- exposed directly to the MTD users (e.g. JFFS2) any more.
- - linux,mtd-name: allow to specify the mtd name for retro capability with
- physmap-flash drivers as boot loader pass the mtd partition via the old
- device name physmap-flash.
- - use-advanced-sector-protection: boolean to enable support for the
- advanced sector protection (Spansion: PPB - Persistent Protection
- Bits) locking.
- - addr-gpios : (optional) List of GPIO descriptors that will be used to
- address the MSBs address lines. The order goes from LSB to MSB.
-
-For JEDEC compatible devices, the following additional properties
-are defined:
-
- - vendor-id : Contains the flash chip's vendor id (1 byte).
- - device-id : Contains the flash chip's device id (1 byte).
-
-For ROM compatible devices (and ROM fallback from cfi-flash), the following
-additional (optional) property is defined:
-
- - erase-size : The chip's physical erase block size in bytes.
-
- The device tree may optionally contain endianness property.
- little-endian or big-endian : It Represents the endianness that should be used
- by the controller to properly read/write data
- from/to the flash. If this property is missing,
- the endianness is chosen by the system
- (potentially based on extra configuration options).
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
- flash@ff000000 {
- compatible = "amd,am29lv128ml", "cfi-flash";
- reg = <ff000000 01000000>;
- bank-width = <4>;
- device-width = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- fs@0 {
- label = "fs";
- reg = <0 f80000>;
- };
- firmware@f80000 {
- label ="firmware";
- reg = <f80000 80000>;
- read-only;
- };
- };
-
-Here an example with multiple "reg" tuples:
-
- flash@f0000000,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "intel,PC48F4400P0VB", "cfi-flash";
- reg = <0 0x00000000 0x02000000
- 0 0x02000000 0x02000000>;
- bank-width = <2>;
- partition@0 {
- label = "test-part1";
- reg = <0 0x04000000>;
- };
- };
-
-An example using SRAM:
-
- sram@2,0 {
- compatible = "samsung,k6f1616u6a", "mtd-ram";
- reg = <2 0 0x00200000>;
- bank-width = <2>;
- };
-
-An example using gpio-addrs
-
- flash@20000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash", "jedec-flash";
- reg = <0x20000000 0x02000000>;
- ranges = <0 0x00000000 0x02000000
- 1 0x02000000 0x02000000>;
- bank-width = <2>;
- addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- partition@0 {
- label = "test-part1";
- reg = <0 0x04000000>;
- };
- };
diff --git a/Bindings/mtd/mtd-physmap.yaml b/Bindings/mtd/mtd-physmap.yaml
new file mode 100644
index 0000000..13c29cc
--- /dev/null
+++ b/Bindings/mtd/mtd-physmap.yaml
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |
+ Flash chips (Memory Technology Devices) are often used for solid state
+ file systems on embedded devices.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - amd,s29gl01gp
+ - amd,s29gl032a
+ - amd,s29gl256n
+ - amd,s29gl512n
+ - arm,versatile-flash
+ - cortina,gemini-flash
+ - cypress,hyperflash
+ - ge,imp3a-firmware-mirror
+ - ge,imp3a-paged-flash
+ - gef,ppc9a-firmware-mirror
+ - gef,ppc9a-paged-flash
+ - gef,sbc310-firmware-mirror
+ - gef,sbc310-paged-flash
+ - gef,sbc610-firmware-mirror
+ - gef,sbc610-paged-flash
+ - intel,28f128j3
+ - intel,dt28f160
+ - intel,ixp4xx-flash
+ - intel,JS28F128
+ - intel,JS28F640
+ - intel,PC28F640P30T85
+ - numonyx,js28f00a
+ - numonyx,js28f128
+ - sst,sst39vf320
+ - xlnx,xps-mch-emc-2.00.a
+ - const: cfi-flash
+ - items:
+ - enum:
+ - cypress,cy7c1019dv33-10zsxi
+ - arm,vexpress-psram
+ - const: mtd-ram
+ - enum:
+ - cfi-flash
+ - jedec-flash
+ - mtd-ram
+ - mtd-rom
+
+ reg:
+ description: |
+ It's possible to (optionally) define multiple "reg" tuples so that
+ non-identical chips can be described in one node.
+ minItems: 1
+ maxItems: 8
+
+ bank-width:
+ description: Width (in bytes) of the bank. Equal to the device width times
+ the number of interleaved chips.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 4 ]
+
+ device-width:
+ description:
+ Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2 ]
+
+ no-unaligned-direct-access:
+ type: boolean
+ description: |
+ Disables the default direct mapping of the flash.
+
+ On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems
+ with JFFS2 usage, as the local bus (LPB) doesn't support unaligned
+ accesses as implemented in the JFFS2 code via memcpy(). By defining
+ "no-unaligned-direct-access", the flash will not be exposed directly to
+ the MTD users (e.g. JFFS2) any more.
+
+ linux,mtd-name:
+ description:
+ Allows specifying the mtd name for retro capability with physmap-flash
+ drivers as boot loader pass the mtd partition via the old device name
+ physmap-flash.
+ $ref: /schemas/types.yaml#/definitions/string
+
+ use-advanced-sector-protection:
+ type: boolean
+ description: |
+ Enables support for the advanced sector protection (Spansion: PPB -
+ Persistent Protection Bits) locking.
+
+ erase-size:
+ description: The chip's physical erase block size in bytes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ addr-gpios:
+ description:
+ List of GPIO descriptors that will be used to address the MSBs address
+ lines. The order goes from LSB to MSB.
+ minItems: 1
+ maxItems: 8
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ big-endian: true
+ little-endian: true
+
+patternProperties:
+ '@[0-9a-f]+$':
+ $ref: partitions/partition.yaml
+
+required:
+ - compatible
+ - reg
+
+# FIXME: A parent bus may define timing properties
+additionalProperties: true
+
+examples:
+ - |
+
+ flash@ff000000 {
+ compatible = "cfi-flash";
+ reg = <0xff000000 0x01000000>;
+ bank-width = <4>;
+ device-width = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff000000 0x01000000>;
+
+ fs@0 {
+ label = "fs";
+ reg = <0 0xf80000>;
+ };
+ firmware@f80000 {
+ label ="firmware";
+ reg = <0xf80000 0x80000>;
+ read-only;
+ };
+ };
+
+ - |
+ /* An example with multiple "reg" tuples */
+
+ flash@0 {
+ compatible = "intel,PC28F640P30T85", "cfi-flash";
+ reg = <0x00000000 0x02000000>,
+ <0x02000000 0x02000000>;
+ bank-width = <2>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x04000000>;
+
+ partition@0 {
+ label = "test-part1";
+ reg = <0 0x04000000>;
+ };
+ };
+
+ - |
+ /* An example using SRAM */
+ bus {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ sram@2,0 {
+ compatible = "mtd-ram";
+ reg = <2 0 0x00200000>;
+ bank-width = <2>;
+ };
+ };
+
+ - |
+ /* An example using addr-gpios */
+ #include <dt-bindings/gpio/gpio.h>
+
+ flash@20000000 {
+ compatible = "cfi-flash";
+ reg = <0x20000000 0x02000000>;
+ bank-width = <2>;
+ addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00000000 0x02000000>,
+ <1 0x02000000 0x02000000>;
+
+ partition@0 {
+ label = "test-part1";
+ reg = <0 0x04000000>;
+ };
+ };
+...
diff --git a/Bindings/mtd/mtd.yaml b/Bindings/mtd/mtd.yaml
new file mode 100644
index 0000000..376b679
--- /dev/null
+++ b/Bindings/mtd/mtd.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/mtd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MTD (Memory Technology Device) Device Tree Bindings
+
+maintainers:
+ - Miquel Raynal <miquel.raynal@bootlin.com>
+ - Richard Weinberger <richard@nod.at>
+
+properties:
+ $nodename:
+ pattern: "^flash(@.*)?$"
+
+ label:
+ description:
+ User-defined MTD device name. Can be used to assign user friendly
+ names to MTD devices (instead of the flash model or flash controller
+ based name) in order to ease flash device identification and/or
+ describe what they are used for.
+
+patternProperties:
+ "^otp(-[0-9]+)?$":
+ type: object
+ $ref: ../nvmem/nvmem.yaml#
+
+ description: |
+ An OTP memory region. Some flashes provide a one-time-programmable
+ memory whose content can either be programmed by a user or is already
+ pre-programmed by the factory. Some flashes might provide both.
+
+ properties:
+ compatible:
+ enum:
+ - user-otp
+ - factory-otp
+
+ required:
+ - compatible
+
+additionalProperties: true
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ label = "System-firmware";
+ };
+ };
+
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+
+ otp-1 {
+ compatible = "factory-otp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ electronic-serial-number@0 {
+ reg = <0 8>;
+ };
+ };
+
+ otp-2 {
+ compatible = "user-otp";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mac-address@0 {
+ reg = <0 6>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/mtd/nand-controller.yaml b/Bindings/mtd/nand-controller.yaml
index 678b399..bd217e6 100644
--- a/Bindings/mtd/nand-controller.yaml
+++ b/Bindings/mtd/nand-controller.yaml
@@ -38,6 +38,17 @@
ranges: true
+ cs-gpios:
+ minItems: 1
+ maxItems: 8
+ description:
+ Array of chip-select available to the controller. The first
+ entries are a 1:1 mapping of the available chip-select on the
+ NAND controller (even if they are not used). As many additional
+ chip-select as needed may follow and should be phandles of GPIO
+ lines. 'reg' entries of the NAND chip subnodes become indexes of
+ this array when this property is present.
+
patternProperties:
"^nand@[a-f0-9]$":
type: object
@@ -164,14 +175,19 @@
nand-controller {
#address-cells = <1>;
#size-cells = <0>;
+ cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
/* controller specific properties */
nand@0 {
- reg = <0>;
+ reg = <0>; /* Native CS */
nand-use-soft-ecc-engine;
nand-ecc-algo = "bch";
/* controller specific properties */
};
+
+ nand@1 {
+ reg = <1>; /* GPIO CS */
+ };
};
diff --git a/Bindings/mtd/partitions/brcm,trx.txt b/Bindings/mtd/partitions/brcm,trx.txt
index b677147..c2175d3 100644
--- a/Bindings/mtd/partitions/brcm,trx.txt
+++ b/Bindings/mtd/partitions/brcm,trx.txt
@@ -28,6 +28,11 @@
Required properties:
- compatible : (required) must be "brcm,trx"
+Optional properties:
+
+- brcm,trx-magic: TRX magic, if it is different from the default magic
+ 0x30524448 as a u32.
+
Example:
flash@0 {
diff --git a/Bindings/mtd/ti,am654-hbmc.txt b/Bindings/mtd/ti,am654-hbmc.txt
deleted file mode 100644
index faa81c2..0000000
--- a/Bindings/mtd/ti,am654-hbmc.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-Bindings for HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs
-
-Required properties:
-- compatible : "ti,am654-hbmc" for AM654 SoC
-- reg : Two entries:
- First entry pointed to the register space of HBMC controller
- Second entry pointing to the memory map region dedicated for
- MMIO access to attached flash devices
-- ranges : Address translation from offset within CS to allocated MMIO
- space in SoC
-
-Optional properties:
-- mux-controls : phandle to the multiplexer that controls selection of
- HBMC vs OSPI inside Flash SubSystem (FSS). Default is OSPI,
- if property is absent.
- See Documentation/devicetree/bindings/mux/reg-mux.txt
- for mmio-mux binding details
-
-Example:
-
- system-controller@47000000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x0 0x47000000 0x0 0x100>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- hbmc_mux: multiplexer {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */
- };
- };
-
- hbmc: hyperbus@47034000 {
- compatible = "ti,am654-hbmc";
- reg = <0x0 0x47034000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
- power-domains = <&k3_pds 55>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
- <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
- mux-controls = <&hbmc_mux 0>;
-
- /* Slave flash node */
- flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x0 0x4000000>;
- };
- };
diff --git a/Bindings/mtd/ti,am654-hbmc.yaml b/Bindings/mtd/ti,am654-hbmc.yaml
new file mode 100644
index 0000000..30b458c
--- /dev/null
+++ b/Bindings/mtd/ti,am654-hbmc.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ti,am654-hbmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HyperBus Memory Controller (HBMC) on TI's K3 family of SoCs
+
+maintainers:
+ - Vignesh Raghavendra <vigneshr@ti.com>
+
+properties:
+ compatible:
+ const: ti,am654-hbmc
+
+ reg:
+ maxItems: 2
+
+ power-domains: true
+ '#address-cells': true
+ '#size-cells': true
+ ranges: true
+
+ mux-controls:
+ description: MMIO mux controller node to select b/w OSPI and HBMC.
+
+ clocks:
+ maxItems: 1
+
+patternProperties:
+ "^flash@[0-1],[0-9a-f]+$":
+ type: object
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - clocks
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ hbmc: memory-controller@47034000 {
+ compatible = "ti,am654-hbmc";
+ reg = <0x0 0x47034000 0x0 0x100>,
+ <0x5 0x00000000 0x1 0x0000000>;
+ ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
+ <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
+ clocks = <&k3_clks 102 0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 55>;
+ mux-controls = <&hbmc_mux 0>;
+
+ flash@0,0 {
+ compatible = "cypress,hyperflash", "cfi-flash";
+ reg = <0x0 0x0 0x4000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+ };
diff --git a/Bindings/mux/adi,adg792a.txt b/Bindings/mux/adi,adg792a.txt
index 96b787a..b0e5bf6 100644
--- a/Bindings/mux/adi,adg792a.txt
+++ b/Bindings/mux/adi,adg792a.txt
@@ -5,7 +5,7 @@
- #mux-control-cells : <0> if parallel (the three muxes are bound together
with a single mux controller controlling all three muxes), or <1> if
not (one mux controller for each mux).
-* Standard mux-controller bindings as described in mux-controller.txt
+* Standard mux-controller bindings as described in mux-controller.yaml
Optional properties for ADG792G:
- gpio-controller : if present, #gpio-cells below is required.
diff --git a/Bindings/mux/adi,adgs1408.txt b/Bindings/mux/adi,adgs1408.txt
index be6947f..453a389 100644
--- a/Bindings/mux/adi,adgs1408.txt
+++ b/Bindings/mux/adi,adgs1408.txt
@@ -4,7 +4,7 @@
- compatible : Should be one of
* "adi,adgs1408"
* "adi,adgs1409"
-* Standard mux-controller bindings as described in mux-controller.txt
+* Standard mux-controller bindings as described in mux-controller.yaml
Optional properties for ADGS1408/1409:
- gpio-controller : if present, #gpio-cells is required.
diff --git a/Bindings/mux/gpio-mux.txt b/Bindings/mux/gpio-mux.txt
deleted file mode 100644
index b8f7463..0000000
--- a/Bindings/mux/gpio-mux.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-GPIO-based multiplexer controller bindings
-
-Define what GPIO pins are used to control a multiplexer. Or several
-multiplexers, if the same pins control more than one multiplexer.
-
-Required properties:
-- compatible : "gpio-mux"
-- mux-gpios : list of gpios used to control the multiplexer, least
- significant bit first.
-- #mux-control-cells : <0>
-* Standard mux-controller bindings as decribed in mux-controller.txt
-
-Optional properties:
-- idle-state : if present, the state the mux will have when idle. The
- special state MUX_IDLE_AS_IS is the default.
-
-The multiplexer state is defined as the number represented by the
-multiplexer GPIO pins, where the first pin is the least significant
-bit. An active pin is a binary 1, an inactive pin is a binary 0.
-
-Example:
-
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
-
- channels = "sync-1", "in", "out", "sync-2";
- };
-
- i2c-mux {
- compatible = "i2c-mux";
- i2c-parent = <&i2c1>;
-
- mux-controls = <&mux>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ssd1307: oled@3c {
- /* ... */
- };
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pca9555: pca9555@20 {
- /* ... */
- };
- };
- };
diff --git a/Bindings/mux/gpio-mux.yaml b/Bindings/mux/gpio-mux.yaml
new file mode 100644
index 0000000..0a7c8d6
--- /dev/null
+++ b/Bindings/mux/gpio-mux.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO-based multiplexer controller bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ Define what GPIO pins are used to control a multiplexer. Or several
+ multiplexers, if the same pins control more than one multiplexer.
+
+ The multiplexer state is defined as the number represented by the
+ multiplexer GPIO pins, where the first pin is the least significant
+ bit. An active pin is a binary 1, an inactive pin is a binary 0.
+
+properties:
+ compatible:
+ const: gpio-mux
+
+ mux-gpios:
+ description:
+ List of gpios used to control the multiplexer, least significant bit first.
+
+ '#mux-control-cells':
+ const: 0
+
+ idle-state:
+ default: -1
+
+required:
+ - compatible
+ - mux-gpios
+ - "#mux-control-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+
+ channels = "sync-1", "in", "out", "sync-2";
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307: oled@3c {
+ reg = <0x3c>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ reg = <0x20>;
+ };
+ };
+ };
+...
diff --git a/Bindings/mux/mux-consumer.yaml b/Bindings/mux/mux-consumer.yaml
new file mode 100644
index 0000000..7af9329
--- /dev/null
+++ b/Bindings/mux/mux-consumer.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common multiplexer controller consumer bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ Mux controller consumers should specify a list of mux controllers that they
+ want to use with a property containing a 'mux-ctrl-list':
+
+ mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
+ single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
+ mux-ctrl-phandle : phandle to mux controller node
+ mux-ctrl-specifier : array of #mux-control-cells specifying the
+ given mux controller (controller specific)
+
+ Mux controller properties should be named "mux-controls". The exact meaning of
+ each mux controller property must be documented in the device tree binding for
+ each consumer. An optional property "mux-control-names" may contain a list of
+ strings to label each of the mux controllers listed in the "mux-controls"
+ property.
+
+ mux-ctrl-specifier typically encodes the chip-relative mux controller number.
+ If the mux controller chip only provides a single mux controller, the
+ mux-ctrl-specifier can typically be left out.
+
+select: true
+
+properties:
+ mux-controls:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ mux-control-names:
+ description:
+ Devices that use more than a single mux controller can use the
+ "mux-control-names" property to map the name of the requested mux
+ controller to an index into the list given by the "mux-controls" property.
+
+additionalProperties: true
+
+...
diff --git a/Bindings/mux/mux-controller.txt b/Bindings/mux/mux-controller.txt
deleted file mode 100644
index 4f47e4b..0000000
--- a/Bindings/mux/mux-controller.txt
+++ /dev/null
@@ -1,157 +0,0 @@
-Common multiplexer controller bindings
-======================================
-
-A multiplexer (or mux) controller will have one, or several, consumer devices
-that uses the mux controller. Thus, a mux controller can possibly control
-several parallel multiplexers. Presumably there will be at least one
-multiplexer needed by each consumer, but a single mux controller can of course
-control several multiplexers for a single consumer.
-
-A mux controller provides a number of states to its consumers, and the state
-space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
-0-7 for an 8-way multiplexer, etc.
-
-
-Consumers
----------
-
-Mux controller consumers should specify a list of mux controllers that they
-want to use with a property containing a 'mux-ctrl-list':
-
- mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
- single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
- mux-ctrl-phandle : phandle to mux controller node
- mux-ctrl-specifier : array of #mux-control-cells specifying the
- given mux controller (controller specific)
-
-Mux controller properties should be named "mux-controls". The exact meaning of
-each mux controller property must be documented in the device tree binding for
-each consumer. An optional property "mux-control-names" may contain a list of
-strings to label each of the mux controllers listed in the "mux-controls"
-property.
-
-Drivers for devices that use more than a single mux controller can use the
-"mux-control-names" property to map the name of the requested mux controller
-to an index into the list given by the "mux-controls" property.
-
-mux-ctrl-specifier typically encodes the chip-relative mux controller number.
-If the mux controller chip only provides a single mux controller, the
-mux-ctrl-specifier can typically be left out.
-
-Example:
-
- /* One consumer of a 2-way mux controller (one GPIO-line) */
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
- mux-control-names = "adc";
-
- channels = "sync", "in";
- };
-
-Note that in the example above, specifying the "mux-control-names" is redundant
-because there is only one mux controller in the list. However, if the driver
-for the consumer node in fact asks for a named mux controller, that name is of
-course still required.
-
- /*
- * Two consumers (one for an ADC line and one for an i2c bus) of
- * parallel 4-way multiplexers controlled by the same two GPIO-lines.
- */
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
-
- channels = "sync-1", "in", "out", "sync-2";
- };
-
- i2c-mux {
- compatible = "i2c-mux";
- i2c-parent = <&i2c1>;
-
- mux-controls = <&mux>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ssd1307: oled@3c {
- /* ... */
- };
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pca9555: pca9555@20 {
- /* ... */
- };
- };
- };
-
-
-Mux controller nodes
---------------------
-
-Mux controller nodes must specify the number of cells used for the
-specifier using the '#mux-control-cells' property.
-
-Optionally, mux controller nodes can also specify the state the mux should
-have when it is idle. The idle-state property is used for this. If the
-idle-state is not present, the mux controller is typically left as is when
-it is idle. For multiplexer chips that expose several mux controllers, the
-idle-state property is an array with one idle state for each mux controller.
-
-The special value (-1) may be used to indicate that the mux should be left
-as is when it is idle. This is the default, but can still be useful for
-mux controller chips with more than one mux controller, particularly when
-there is a need to "step past" a mux controller and set some other idle
-state for a mux controller with a higher index.
-
-Some mux controllers have the ability to disconnect the input/output of the
-multiplexer. Using this disconnected high-impedance state as the idle state
-is indicated with idle state (-2).
-
-These constants are available in
-
- #include <dt-bindings/mux/mux.h>
-
-as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2).
-
-An example mux controller node look like this (the adg972a chip is a triple
-4-way multiplexer):
-
- mux: mux-controller@50 {
- compatible = "adi,adg792a";
- reg = <0x50>;
- #mux-control-cells = <1>;
-
- idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
- };
diff --git a/Bindings/mux/mux-controller.yaml b/Bindings/mux/mux-controller.yaml
new file mode 100644
index 0000000..736a84c
--- /dev/null
+++ b/Bindings/mux/mux-controller.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/mux-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common multiplexer controller provider bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ A multiplexer (or mux) controller will have one, or several, consumer devices
+ that uses the mux controller. Thus, a mux controller can possibly control
+ several parallel multiplexers. Presumably there will be at least one
+ multiplexer needed by each consumer, but a single mux controller can of course
+ control several multiplexers for a single consumer.
+
+ A mux controller provides a number of states to its consumers, and the state
+ space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
+ 0-7 for an 8-way multiplexer, etc.
+
+
+ Mux controller nodes
+ --------------------
+
+ Mux controller nodes must specify the number of cells used for the
+ specifier using the '#mux-control-cells' property.
+
+ Optionally, mux controller nodes can also specify the state the mux should
+ have when it is idle. The idle-state property is used for this. If the
+ idle-state is not present, the mux controller is typically left as is when
+ it is idle. For multiplexer chips that expose several mux controllers, the
+ idle-state property is an array with one idle state for each mux controller.
+
+ The special value (-1) may be used to indicate that the mux should be left
+ as is when it is idle. This is the default, but can still be useful for
+ mux controller chips with more than one mux controller, particularly when
+ there is a need to "step past" a mux controller and set some other idle
+ state for a mux controller with a higher index.
+
+ Some mux controllers have the ability to disconnect the input/output of the
+ multiplexer. Using this disconnected high-impedance state as the idle state
+ is indicated with idle state (-2).
+
+ These constants are available in
+
+ #include <dt-bindings/mux/mux.h>
+
+ as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2).
+
+ An example mux controller node look like this (the adg972a chip is a triple
+ 4-way multiplexer):
+
+ mux: mux-controller@50 {
+ compatible = "adi,adg792a";
+ reg = <0x50>;
+ #mux-control-cells = <1>;
+
+ idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
+ };
+
+select:
+ anyOf:
+ - properties:
+ $nodename:
+ pattern: '^mux-controller'
+ - required:
+ - '#mux-control-cells'
+
+properties:
+ $nodename:
+ pattern: '^mux-controller(@.*|-[0-9a-f]+)?$'
+
+ '#mux-control-cells':
+ enum: [ 0, 1 ]
+
+ idle-state:
+ $ref: /schemas/types.yaml#/definitions/int32
+ minimum: -2
+
+ idle-states:
+ description: |
+ Mux controller nodes can specify the state the mux should have when it is
+ idle. If the idle-state is not present, the mux controller is typically
+ left as is when it is idle. For multiplexer chips that expose several mux
+ controllers, the idle-state property is an array with one idle state for
+ each mux controller.
+
+ The special value (-1) may be used to indicate that the mux should be left
+ as is when it is idle. This is the default, but can still be useful for
+ mux controller chips with more than one mux controller, particularly when
+ there is a need to "step past" a mux controller and set some other idle
+ state for a mux controller with a higher index.
+
+ Some mux controllers have the ability to disconnect the input/output of the
+ multiplexer. Using this disconnected high-impedance state as the idle state
+ is indicated with idle state (-2).
+ $ref: /schemas/types.yaml#/definitions/int32-array
+ items:
+ minimum: -2
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ /* One consumer of a 2-way mux controller (one GPIO-line) */
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+ mux-control-names = "adc";
+
+ channels = "sync", "in";
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ /*
+ * Two consumers (one for an ADC line and one for an i2c bus) of
+ * parallel 4-way multiplexers controlled by the same two GPIO-lines.
+ */
+ mux2: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux2>;
+
+ channels = "sync-1", "in", "out", "sync-2";
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux2>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307: oled@3c {
+ reg = <0x3c>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ reg = <0x20>;
+ };
+ };
+ };
+...
diff --git a/Bindings/mux/reg-mux.txt b/Bindings/mux/reg-mux.txt
deleted file mode 100644
index 4afd7ba..0000000
--- a/Bindings/mux/reg-mux.txt
+++ /dev/null
@@ -1,129 +0,0 @@
-Generic register bitfield-based multiplexer controller bindings
-
-Define register bitfields to be used to control multiplexers. The parent
-device tree node must be a device node to provide register r/w access.
-
-Required properties:
-- compatible : should be one of
- "reg-mux" : if parent device of mux controller is not syscon device
- "mmio-mux" : if parent device of mux controller is syscon device
-- #mux-control-cells : <1>
-- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
- pairs, each describing a single mux control.
-* Standard mux-controller bindings as decribed in mux-controller.txt
-
-Optional properties:
-- idle-states : if present, the state the muxes will have when idle. The
- special state MUX_IDLE_AS_IS is the default.
-
-The multiplexer state of each multiplexer is defined as the value of the
-bitfield described by the corresponding register offset and bitfield mask
-pair in the mux-reg-masks array.
-
-Example 1:
-The parent device of mux controller is not a syscon device.
-
-&i2c0 {
- fpga@66 { // fpga connected to i2c
- compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
- "simple-mfd";
- reg = <0x66>;
-
- mux: mux-controller {
- compatible = "reg-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
- <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
- };
- };
-};
-
-mdio-mux-1 {
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 0>;
- mdio-parent-bus = <&emdio1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@8 {
- reg = <0x8>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
-
-mdio-mux-2 {
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 1>;
- mdio-parent-bus = <&emdio2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@1 {
- reg = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
-
-Example 2:
-The parent device of mux controller is syscon device.
-
-syscon {
- compatible = "syscon";
-
- mux: mux-controller {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
-
- mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
- <0x3 0x40>, /* 1: reg 0x3, bit 6 */
- idle-states = <MUX_IDLE_AS_IS>, <0>;
- };
-};
-
-video-mux {
- compatible = "video-mux";
- mux-controls = <&mux 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- /* inputs 0..3 */
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- reg = <2>;
- };
- port@3 {
- reg = <3>;
- };
-
- /* output */
- port@4 {
- reg = <4>;
- };
- };
-};
diff --git a/Bindings/mux/reg-mux.yaml b/Bindings/mux/reg-mux.yaml
new file mode 100644
index 0000000..60d5746
--- /dev/null
+++ b/Bindings/mux/reg-mux.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/reg-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic register bitfield-based multiplexer controller bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ Define register bitfields to be used to control multiplexers. The parent
+ device tree node must be a device node to provide register r/w access.
+
+properties:
+ compatible:
+ enum:
+ - reg-mux # parent device of mux controller is not syscon device
+ - mmio-mux # parent device of mux controller is syscon device
+
+ reg: true
+
+ '#mux-control-cells':
+ const: 1
+
+ mux-reg-masks:
+ description: an array of register offset and pre-shifted bitfield mask
+ pairs, each describing a single mux control.
+
+ idle-states: true
+
+required:
+ - compatible
+ - mux-reg-masks
+ - '#mux-control-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ /* The parent device of mux controller is not a syscon device. */
+
+ #include <dt-bindings/mux/mux.h>
+
+ mux-controller {
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks =
+ <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+ <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
+ };
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux1 0>;
+ mdio-parent-bus = <&emdio1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@8 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mux-2 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux1 1>;
+ mdio-parent-bus = <&emdio2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ - |
+ /* The parent device of mux controller is syscon device. */
+
+ #include <dt-bindings/mux/mux.h>
+ syscon@1000 {
+ compatible = "fsl,imx7d-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
+ reg = <0x1000 0x100>;
+
+ mux2: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+
+ mux-reg-masks =
+ <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
+ <0x3 0x40>; /* 1: reg 0x3, bit 6 */
+ idle-states = <MUX_IDLE_AS_IS>, <0>;
+ };
+ };
+
+ video-mux {
+ compatible = "video-mux";
+ mux-controls = <&mux2 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* inputs 0..3 */
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ port@2 {
+ reg = <2>;
+ };
+ port@3 {
+ reg = <3>;
+ };
+
+ /* output */
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
+...
diff --git a/Bindings/net/amlogic,meson-dwmac.yaml b/Bindings/net/amlogic,meson-dwmac.yaml
index 0467441..608e1d6 100644
--- a/Bindings/net/amlogic,meson-dwmac.yaml
+++ b/Bindings/net/amlogic,meson-dwmac.yaml
@@ -43,7 +43,6 @@
properties:
clocks:
minItems: 3
- maxItems: 4
items:
- description: GMAC main clock
- description: First parent clock of the internal mux
@@ -52,7 +51,6 @@
clock-names:
minItems: 3
- maxItems: 4
items:
- const: stmmaceth
- const: clkin0
diff --git a/Bindings/net/brcm,bcm4908-enet.yaml b/Bindings/net/brcm,bcm4908-enet.yaml
index 2f46e45..a93d2f1 100644
--- a/Bindings/net/brcm,bcm4908-enet.yaml
+++ b/Bindings/net/brcm,bcm4908-enet.yaml
@@ -23,14 +23,12 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: RX interrupt
- description: TX interrupt
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: rx
- const: tx
diff --git a/Bindings/net/brcm,iproc-mdio.txt b/Bindings/net/brcm,iproc-mdio.txt
deleted file mode 100644
index 8ba9ed1..0000000
--- a/Bindings/net/brcm,iproc-mdio.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Broadcom iProc MDIO bus controller
-
-Required properties:
-- compatible: should be "brcm,iproc-mdio"
-- reg: address and length of the register set for the MDIO interface
-- #size-cells: must be 1
-- #address-cells: must be 0
-
-Child nodes of this MDIO bus controller node are standard Ethernet PHY device
-nodes as described in Documentation/devicetree/bindings/net/phy.txt
-
-Example:
-
-mdio@18002000 {
- compatible = "brcm,iproc-mdio";
- reg = <0x18002000 0x8>;
- #size-cells = <1>;
- #address-cells = <0>;
-
- enet-gphy@0 {
- reg = <0>;
- };
-};
diff --git a/Bindings/net/brcm,iproc-mdio.yaml b/Bindings/net/brcm,iproc-mdio.yaml
new file mode 100644
index 0000000..3031395
--- /dev/null
+++ b/Bindings/net/brcm,iproc-mdio.yaml
@@ -0,0 +1,38 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/brcm,iproc-mdio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom iProc MDIO bus controller
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+allOf:
+ - $ref: mdio.yaml#
+
+properties:
+ compatible:
+ const: brcm,iproc-mdio
+
+ reg:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+required:
+ - reg
+
+examples:
+ - |
+ mdio@18002000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18002000 0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
diff --git a/Bindings/net/brcm,mdio-mux-iproc.txt b/Bindings/net/brcm,mdio-mux-iproc.txt
index b58843f..deb9e85 100644
--- a/Bindings/net/brcm,mdio-mux-iproc.txt
+++ b/Bindings/net/brcm,mdio-mux-iproc.txt
@@ -17,7 +17,7 @@
- clocks: phandle of the core clock which drives the mdio block.
Additional information regarding generic multiplexer properties can be found
-at- Documentation/devicetree/bindings/net/mdio-mux.txt
+at- Documentation/devicetree/bindings/net/mdio-mux.yaml
for example:
diff --git a/Bindings/net/can/bosch,m_can.yaml b/Bindings/net/can/bosch,m_can.yaml
index 798fa5f..f84e313 100644
--- a/Bindings/net/can/bosch,m_can.yaml
+++ b/Bindings/net/can/bosch,m_can.yaml
@@ -30,14 +30,12 @@
- description: interrupt line0
- description: interrupt line1
minItems: 1
- maxItems: 2
interrupt-names:
items:
- const: int0
- const: int1
minItems: 1
- maxItems: 2
clocks:
items:
diff --git a/Bindings/net/can/c_can.txt b/Bindings/net/can/c_can.txt
index 2d50425..3664798 100644
--- a/Bindings/net/can/c_can.txt
+++ b/Bindings/net/can/c_can.txt
@@ -19,10 +19,10 @@
- power-domains : Should contain a phandle to a PM domain provider node
and an args specifier containing the DCAN device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
- clocks : CAN functional clock phandle. This property is as per the
binding,
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
Optional properties:
- syscon-raminit : Handle to system control region that contains the
diff --git a/Bindings/net/can/rcar_can.txt b/Bindings/net/can/rcar_can.txt
deleted file mode 100644
index 90ac4fe..0000000
--- a/Bindings/net/can/rcar_can.txt
+++ /dev/null
@@ -1,80 +0,0 @@
-Renesas R-Car CAN controller Device Tree Bindings
--------------------------------------------------
-
-Required properties:
-- compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC.
- "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC.
- "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC.
- "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC.
- "renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC.
- "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC.
- "renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC.
- "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC.
- "renesas,can-r8a774e1" if CAN controller is a part of R8A774E1 SoC.
- "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
- "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
- "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
- "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
- "renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC.
- "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC.
- "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC.
- "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC.
- "renesas,can-r8a7796" if CAN controller is a part of R8A77960 SoC.
- "renesas,can-r8a77961" if CAN controller is a part of R8A77961 SoC.
- "renesas,can-r8a77965" if CAN controller is a part of R8A77965 SoC.
- "renesas,can-r8a77990" if CAN controller is a part of R8A77990 SoC.
- "renesas,can-r8a77995" if CAN controller is a part of R8A77995 SoC.
- "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device.
- "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1
- compatible device.
- "renesas,rcar-gen3-can" for a generic R-Car Gen3 or RZ/G2
- compatible device.
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first
- followed by the generic version.
-
-- reg: physical base address and size of the R-Car CAN register map.
-- interrupts: interrupt specifier for the sole interrupt.
-- clocks: phandles and clock specifiers for 3 CAN clock inputs.
-- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk".
-- pinctrl-0: pin control group to be used for this controller.
-- pinctrl-names: must be "default".
-
-Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795,
-R8A77960, R8A77961, R8A77965, R8A77990, and R8A77995:
-For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can
-be used by both CAN and CAN FD controller at the same time. It needs to be
-scaled to maximum frequency if any of these controllers use it. This is done
-using the below properties:
-
-- assigned-clocks: phandle of clkp2(CANFD) clock.
-- assigned-clock-rates: maximum frequency of this clock.
-
-Optional properties:
-- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
- <0x0> (default) : Peripheral clock (clkp1)
- <0x1> : Peripheral clock (clkp2)
- <0x3> : External input clock
-
-Example
--------
-
-SoC common .dtsi file:
-
- can0: can@e6e80000 {
- compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
- reg = <0 0xe6e80000 0 0x1000>;
- interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
- <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
- clock-names = "clkp1", "clkp2", "can_clk";
- status = "disabled";
- };
-
-Board specific .dts file:
-
-&can0 {
- pinctrl-0 = <&can0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
diff --git a/Bindings/net/can/rcar_canfd.txt b/Bindings/net/can/rcar_canfd.txt
deleted file mode 100644
index 248c4ed..0000000
--- a/Bindings/net/can/rcar_canfd.txt
+++ /dev/null
@@ -1,107 +0,0 @@
-Renesas R-Car CAN FD controller Device Tree Bindings
-----------------------------------------------------
-
-Required properties:
-- compatible: Must contain one or more of the following:
- - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers.
- - "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller.
- - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller.
- - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller.
- - "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller.
- - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller.
- - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller.
- - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller.
- - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller.
- - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller.
- - "renesas,r8a77990-canfd" for R8A77990 (R-Car E3) compatible controller.
- - "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller.
-
- When compatible with the generic version, nodes must list the
- SoC-specific version corresponding to the platform first, followed by the
- family-specific and/or generic versions.
-
-- reg: physical base address and size of the R-Car CAN FD register map.
-- interrupts: interrupt specifiers for the Channel & Global interrupts
-- clocks: phandles and clock specifiers for 3 clock inputs.
-- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk".
-- pinctrl-0: pin control group to be used for this controller.
-- pinctrl-names: must be "default".
-
-Required child nodes:
-The controller supports two channels and each is represented as a child node.
-The name of the child nodes are "channel0" and "channel1" respectively. Each
-child node supports the "status" property only, which is used to
-enable/disable the respective channel.
-
-Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795,
-R8A7796, R8A77965, R8A77990, and R8A77995:
-In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN
-and CAN FD controller at the same time. It needs to be scaled to maximum
-frequency if any of these controllers use it. This is done using the below
-properties:
-
-- assigned-clocks: phandle of canfd clock.
-- assigned-clock-rates: maximum frequency of this clock.
-
-Optional property:
-The controller can operate in either CAN FD only mode (default) or
-Classical CAN only mode. The mode is global to both the channels. In order to
-enable the later, define the following optional property.
- - renesas,no-can-fd: puts the controller in Classical CAN only mode.
-
-Example
--------
-
-SoC common .dtsi file:
-
- canfd: can@e66c0000 {
- compatible = "renesas,r8a7795-canfd",
- "renesas,rcar-gen3-canfd";
- reg = <0 0xe66c0000 0 0x8000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 914>,
- <&cpg CPG_CORE R8A7795_CLK_CANFD>,
- <&can_clk>;
- clock-names = "fck", "canfd", "can_clk";
- assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
- power-domains = <&cpg>;
- status = "disabled";
-
- channel0 {
- status = "disabled";
- };
-
- channel1 {
- status = "disabled";
- };
- };
-
-Board specific .dts file:
-
-E.g. below enables Channel 1 alone in the board in Classical CAN only mode.
-
-&canfd {
- pinctrl-0 = <&canfd1_pins>;
- pinctrl-names = "default";
- renesas,no-can-fd;
- status = "okay";
-
- channel1 {
- status = "okay";
- };
-};
-
-E.g. below enables Channel 0 alone in the board using External clock
-as fCAN clock.
-
-&canfd {
- pinctrl-0 = <&canfd0_pins>, <&can_clk_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- channel0 {
- status = "okay";
- };
-};
diff --git a/Bindings/net/can/renesas,rcar-can.yaml b/Bindings/net/can/renesas,rcar-can.yaml
new file mode 100644
index 0000000..fadc871
--- /dev/null
+++ b/Bindings/net/can/renesas,rcar-can.yaml
@@ -0,0 +1,139 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car CAN Controller
+
+maintainers:
+ - Sergei Shtylyov <sergei.shtylyov@gmail.com>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,can-r8a7778 # R-Car M1-A
+ - renesas,can-r8a7779 # R-Car H1
+ - const: renesas,rcar-gen1-can # R-Car Gen1
+
+ - items:
+ - enum:
+ - renesas,can-r8a7742 # RZ/G1H
+ - renesas,can-r8a7743 # RZ/G1M
+ - renesas,can-r8a7744 # RZ/G1N
+ - renesas,can-r8a7745 # RZ/G1E
+ - renesas,can-r8a77470 # RZ/G1C
+ - renesas,can-r8a7790 # R-Car H2
+ - renesas,can-r8a7791 # R-Car M2-W
+ - renesas,can-r8a7792 # R-Car V2H
+ - renesas,can-r8a7793 # R-Car M2-N
+ - renesas,can-r8a7794 # R-Car E2
+ - const: renesas,rcar-gen2-can # R-Car Gen2 and RZ/G1
+
+ - items:
+ - enum:
+ - renesas,can-r8a774a1 # RZ/G2M
+ - renesas,can-r8a774b1 # RZ/G2N
+ - renesas,can-r8a774c0 # RZ/G2E
+ - renesas,can-r8a774e1 # RZ/G2H
+ - renesas,can-r8a7795 # R-Car H3
+ - renesas,can-r8a7796 # R-Car M3-W
+ - renesas,can-r8a77961 # R-Car M3-W+
+ - renesas,can-r8a77965 # R-Car M3-N
+ - renesas,can-r8a77990 # R-Car E3
+ - renesas,can-r8a77995 # R-Car D3
+ - const: renesas,rcar-gen3-can # R-Car Gen3 and RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: clkp1
+ - const: clkp2
+ - const: can_clk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ renesas,can-clock-select:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 3 ]
+ default: 0
+ description: |
+ R-Car CAN Clock Source Select. Valid values are:
+ <0x0> (default) : Peripheral clock (clkp1)
+ <0x1> : Peripheral clock (clkp2)
+ <0x3> : External input clock
+
+ assigned-clocks:
+ description:
+ Reference to the clkp2 (CANFD) clock.
+ On R-Car Gen3 and RZ/G2 SoCs, "clkp2" is the CANFD clock. This is a div6
+ clock and can be used by both CAN and CAN FD controllers at the same
+ time. It needs to be scaled to maximum frequency if any of these
+ controllers use it.
+
+ assigned-clock-rates:
+ description: Maximum frequency of the CANFD clock.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+
+allOf:
+ - $ref: can-controller.yaml#
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rcar-gen1-can
+ then:
+ required:
+ - resets
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rcar-gen3-can
+ then:
+ required:
+ - assigned-clocks
+ - assigned-clock-rates
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7791-sysc.h>
+
+ can0: can@e6e80000 {
+ compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
+ reg = <0xe6e80000 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 916>,
+ <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>;
+ clock-names = "clkp1", "clkp2", "can_clk";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 916>;
+ };
diff --git a/Bindings/net/can/renesas,rcar-canfd.yaml b/Bindings/net/can/renesas,rcar-canfd.yaml
new file mode 100644
index 0000000..0b33ba9
--- /dev/null
+++ b/Bindings/net/can/renesas,rcar-canfd.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car CAN FD Controller
+
+maintainers:
+ - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
+
+allOf:
+ - $ref: can-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r8a774a1-canfd # RZ/G2M
+ - renesas,r8a774b1-canfd # RZ/G2N
+ - renesas,r8a774c0-canfd # RZ/G2E
+ - renesas,r8a774e1-canfd # RZ/G2H
+ - renesas,r8a7795-canfd # R-Car H3
+ - renesas,r8a7796-canfd # R-Car M3-W
+ - renesas,r8a77965-canfd # R-Car M3-N
+ - renesas,r8a77970-canfd # R-Car V3M
+ - renesas,r8a77980-canfd # R-Car V3H
+ - renesas,r8a77990-canfd # R-Car E3
+ - renesas,r8a77995-canfd # R-Car D3
+ - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Channel interrupt
+ - description: Global interrupt
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: fck
+ - const: canfd
+ - const: can_clk
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ renesas,no-can-fd:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ The controller can operate in either CAN FD only mode (default) or
+ Classical CAN only mode. The mode is global to both the channels.
+ Specify this property to put the controller in Classical CAN only mode.
+
+ assigned-clocks:
+ description:
+ Reference to the CANFD clock. The CANFD clock is a div6 clock and can be
+ used by both CAN (if present) and CAN FD controllers at the same time.
+ It needs to be scaled to maximum frequency if any of these controllers
+ use it.
+
+ assigned-clock-rates:
+ description: Maximum frequency of the CANFD clock.
+
+patternProperties:
+ "^channel[01]$":
+ type: object
+ description:
+ The controller supports two channels and each is represented as a child
+ node. Each child node supports the "status" property only, which
+ is used to enable/disable the respective channel.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - resets
+ - assigned-clocks
+ - assigned-clock-rates
+ - channel0
+ - channel1
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/r8a7795-sysc.h>
+
+ canfd: can@e66c0000 {
+ compatible = "renesas,r8a7795-canfd",
+ "renesas,rcar-gen3-canfd";
+ reg = <0xe66c0000 0x8000>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 914>,
+ <&cpg CPG_CORE R8A7795_CLK_CANFD>,
+ <&can_clk>;
+ clock-names = "fck", "canfd", "can_clk";
+ assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
+ assigned-clock-rates = <40000000>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
+
+ channel0 {
+ };
+
+ channel1 {
+ };
+ };
diff --git a/Bindings/net/dsa/brcm,sf2.yaml b/Bindings/net/dsa/brcm,sf2.yaml
index d730fe5..d159ac7 100644
--- a/Bindings/net/dsa/brcm,sf2.yaml
+++ b/Bindings/net/dsa/brcm,sf2.yaml
@@ -48,14 +48,12 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: switch's main clock
- description: dividing of the switch core clock
clock-names:
minItems: 1
- maxItems: 2
items:
- const: sw_switch
- const: sw_switch_mdiv
diff --git a/Bindings/net/dsa/mt7530.txt b/Bindings/net/dsa/mt7530.txt
index de04626..18247eb 100644
--- a/Bindings/net/dsa/mt7530.txt
+++ b/Bindings/net/dsa/mt7530.txt
@@ -81,6 +81,12 @@
- gpio-controller: Boolean; if defined, MT7530's LED controller will run on
GPIO mode.
- #gpio-cells: Must be 2 if gpio-controller is defined.
+- interrupt-controller: Boolean; Enables the internal interrupt controller.
+
+If interrupt-controller is defined, the following properties are required.
+
+- #interrupt-cells: Must be 1.
+- interrupts: Parent interrupt for the interrupt controller.
See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
required, optional properties and how the integrated switch subnodes must
diff --git a/Bindings/net/dsa/nxp,sja1105.yaml b/Bindings/net/dsa/nxp,sja1105.yaml
new file mode 100644
index 0000000..0b8a05d
--- /dev/null
+++ b/Bindings/net/dsa/nxp,sja1105.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings
+
+description:
+ The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
+ least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
+ cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
+ depends on the SPI bus master driver.
+
+allOf:
+ - $ref: "dsa.yaml#"
+
+maintainers:
+ - Vladimir Oltean <vladimir.oltean@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - nxp,sja1105e
+ - nxp,sja1105t
+ - nxp,sja1105p
+ - nxp,sja1105q
+ - nxp,sja1105r
+ - nxp,sja1105s
+ - nxp,sja1110a
+ - nxp,sja1110b
+ - nxp,sja1110c
+ - nxp,sja1110d
+
+ reg:
+ maxItems: 1
+
+ # Optional container node for the 2 internal MDIO buses of the SJA1110
+ # (one for the internal 100base-T1 PHYs and the other for the single
+ # 100base-TX PHY). The "reg" property does not have physical significance.
+ # The PHY addresses to port correspondence is as follows: for 100base-T1,
+ # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
+ # PHY 1.
+ mdios:
+ type: object
+
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^mdio@[0-1]$":
+ type: object
+
+ allOf:
+ - $ref: "http://devicetree.org/schemas/net/mdio.yaml#"
+
+ properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nxp,sja1110-base-t1-mdio
+ - nxp,sja1110-base-tx-mdio
+
+ reg:
+ oneOf:
+ - enum:
+ - 0
+ - 1
+
+ required:
+ - compatible
+ - reg
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@1 {
+ reg = <0x1>;
+ compatible = "nxp,sja1105t";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ phy-handle = <&rgmii_phy6>;
+ phy-mode = "rgmii-id";
+ reg = <0>;
+ };
+
+ port@1 {
+ phy-handle = <&rgmii_phy3>;
+ phy-mode = "rgmii-id";
+ reg = <1>;
+ };
+
+ port@2 {
+ phy-handle = <&rgmii_phy4>;
+ phy-mode = "rgmii-id";
+ reg = <2>;
+ };
+
+ port@3 {
+ phy-mode = "rgmii-id";
+ reg = <3>;
+ };
+
+ port@4 {
+ ethernet = <&enet2>;
+ phy-mode = "rgmii";
+ reg = <4>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/net/dsa/qca8k.txt b/Bindings/net/dsa/qca8k.txt
index ccbc6d8..8c73f67 100644
--- a/Bindings/net/dsa/qca8k.txt
+++ b/Bindings/net/dsa/qca8k.txt
@@ -3,6 +3,7 @@
Required properties:
- compatible: should be one of:
+ "qca,qca8327"
"qca,qca8334"
"qca,qca8337"
@@ -20,6 +21,10 @@
mdio-bus each subnode describing a port needs to have a valid phandle
referencing the internal PHY it is connected to. This is because there's no
N:N mapping of port and PHY id.
+To declare the internal mdio-bus configuration, declare a mdio node in the
+switch node and declare the phandle for the port referencing the internal
+PHY is connected to. In this config a internal mdio-bus is registered and
+the mdio MASTER is used as communication.
Don't use mixed external and internal mdio-bus configurations, as this is
not supported by the hardware.
@@ -149,26 +154,61 @@
port@1 {
reg = <1>;
label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
+ phy-mode = "internal";
+ phy-handle = <&phy_port5>;
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_port1: phy@0 {
+ reg = <0>;
+ };
+
+ phy_port2: phy@1 {
+ reg = <1>;
+ };
+
+ phy_port3: phy@2 {
+ reg = <2>;
+ };
+
+ phy_port4: phy@3 {
+ reg = <3>;
+ };
+
+ phy_port5: phy@4 {
+ reg = <4>;
};
};
};
diff --git a/Bindings/net/dsa/sja1105.txt b/Bindings/net/dsa/sja1105.txt
deleted file mode 100644
index 13fd210..0000000
--- a/Bindings/net/dsa/sja1105.txt
+++ /dev/null
@@ -1,156 +0,0 @@
-NXP SJA1105 switch driver
-=========================
-
-Required properties:
-
-- compatible:
- Must be one of:
- - "nxp,sja1105e"
- - "nxp,sja1105t"
- - "nxp,sja1105p"
- - "nxp,sja1105q"
- - "nxp,sja1105r"
- - "nxp,sja1105s"
-
- Although the device ID could be detected at runtime, explicit bindings
- are required in order to be able to statically check their validity.
- For example, SGMII can only be specified on port 4 of R and S devices,
- and the non-SGMII devices, while pin-compatible, are not equal in terms
- of support for RGMII internal delays (supported on P/Q/R/S, but not on
- E/T).
-
-Optional properties:
-
-- sja1105,role-mac:
-- sja1105,role-phy:
- Boolean properties that can be assigned under each port node. By
- default (unless otherwise specified) a port is configured as MAC if it
- is driving a PHY (phy-handle is present) or as PHY if it is PHY-less
- (fixed-link specified, presumably because it is connected to a MAC).
- The effect of this property (in either its implicit or explicit form)
- is:
- - In the case of MII or RMII it specifies whether the SJA1105 port is a
- clock source or sink for this interface (not applicable for RGMII
- where there is a Tx and an Rx clock).
- - In the case of RGMII it affects the behavior regarding internal
- delays:
- 1. If sja1105,role-mac is specified, and the phy-mode property is one
- of "rgmii-id", "rgmii-txid" or "rgmii-rxid", then the entity
- designated to apply the delay/clock skew necessary for RGMII
- is the PHY. The SJA1105 MAC does not apply any internal delays.
- 2. If sja1105,role-phy is specified, and the phy-mode property is one
- of the above, the designated entity to apply the internal delays
- is the SJA1105 MAC (if hardware-supported). This is only supported
- by the second-generation (P/Q/R/S) hardware. On a first-generation
- E or T device, it is an error to specify an RGMII phy-mode other
- than "rgmii" for a port that is in fixed-link mode. In that case,
- the clock skew must either be added by the MAC at the other end of
- the fixed-link, or by PCB serpentine traces on the board.
- These properties are required, for example, in the case where SJA1105
- ports are at both ends of a MII/RMII PHY-less setup. One end would need
- to have sja1105,role-mac, while the other sja1105,role-phy.
-
-See Documentation/devicetree/bindings/net/dsa/dsa.txt for the list of standard
-DSA required and optional properties.
-
-Other observations
-------------------
-
-The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944) of at least
-one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
-cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
-depends on the SPI bus master driver.
-
-Example
--------
-
-Ethernet switch connected via SPI to the host, CPU port wired to enet2:
-
-arch/arm/boot/dts/ls1021a-tsn.dts:
-
-/* SPI controller of the LS1021 */
-&dspi0 {
- sja1105@1 {
- reg = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nxp,sja1105t";
- spi-max-frequency = <4000000>;
- fsl,spi-cs-sck-delay = <1000>;
- fsl,spi-sck-cs-delay = <1000>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- /* ETH5 written on chassis */
- label = "swp5";
- phy-handle = <&rgmii_phy6>;
- phy-mode = "rgmii-id";
- reg = <0>;
- /* Implicit "sja1105,role-mac;" */
- };
- port@1 {
- /* ETH2 written on chassis */
- label = "swp2";
- phy-handle = <&rgmii_phy3>;
- phy-mode = "rgmii-id";
- reg = <1>;
- /* Implicit "sja1105,role-mac;" */
- };
- port@2 {
- /* ETH3 written on chassis */
- label = "swp3";
- phy-handle = <&rgmii_phy4>;
- phy-mode = "rgmii-id";
- reg = <2>;
- /* Implicit "sja1105,role-mac;" */
- };
- port@3 {
- /* ETH4 written on chassis */
- phy-handle = <&rgmii_phy5>;
- label = "swp4";
- phy-mode = "rgmii-id";
- reg = <3>;
- /* Implicit "sja1105,role-mac;" */
- };
- port@4 {
- /* Internal port connected to eth2 */
- ethernet = <&enet2>;
- phy-mode = "rgmii";
- reg = <4>;
- /* Implicit "sja1105,role-phy;" */
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
-};
-
-/* MDIO controller of the LS1021 */
-&mdio0 {
- /* BCM5464 */
- rgmii_phy3: ethernet-phy@3 {
- reg = <0x3>;
- };
- rgmii_phy4: ethernet-phy@4 {
- reg = <0x4>;
- };
- rgmii_phy5: ethernet-phy@5 {
- reg = <0x5>;
- };
- rgmii_phy6: ethernet-phy@6 {
- reg = <0x6>;
- };
-};
-
-/* Ethernet master port of the LS1021 */
-&enet2 {
- phy-connection-type = "rgmii";
- status = "ok";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
diff --git a/Bindings/net/ethernet-controller.yaml b/Bindings/net/ethernet-controller.yaml
index e8f0468..b0933a8 100644
--- a/Bindings/net/ethernet-controller.yaml
+++ b/Bindings/net/ethernet-controller.yaml
@@ -68,6 +68,7 @@
- tbi
- rev-mii
- rmii
+ - rev-rmii
# RX and TX delays are added by the MAC when required
- rgmii
@@ -97,6 +98,7 @@
- 10gbase-kr
- usxgmii
- 10gbase-r
+ - 25gbase-r
phy-mode:
$ref: "#/properties/phy-connection-type"
diff --git a/Bindings/net/ingenic,mac.yaml b/Bindings/net/ingenic,mac.yaml
new file mode 100644
index 0000000..d08a881
--- /dev/null
+++ b/Bindings/net/ingenic,mac.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for MAC in Ingenic SoCs
+
+maintainers:
+ - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
+
+description:
+ The Ethernet Media Access Controller in Ingenic SoCs.
+
+properties:
+ compatible:
+ enum:
+ - ingenic,jz4775-mac
+ - ingenic,x1000-mac
+ - ingenic,x1600-mac
+ - ingenic,x1830-mac
+ - ingenic,x2000-mac
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ const: macirq
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: stmmaceth
+
+ mode-reg:
+ description: An extra syscon register that control ethernet interface and timing delay
+
+ rx-clk-delay-ps:
+ description: RGMII receive clock delay defined in pico seconds
+
+ tx-clk-delay-ps:
+ description: RGMII transmit clock delay defined in pico seconds
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - mode-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/x1000-cgu.h>
+
+ mac: ethernet@134b0000 {
+ compatible = "ingenic,x1000-mac";
+ reg = <0x134b0000 0x2000>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <55>;
+ interrupt-names = "macirq";
+
+ clocks = <&cgu X1000_CLK_MAC>;
+ clock-names = "stmmaceth";
+
+ mode-reg = <&mac_phy_ctrl>;
+ };
+...
diff --git a/Bindings/net/mdio-gpio.txt b/Bindings/net/mdio-gpio.txt
deleted file mode 100644
index 4d91a36..0000000
--- a/Bindings/net/mdio-gpio.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-MDIO on GPIOs
-
-Currently defined compatibles:
-- virtual,gpio-mdio
-- microchip,mdio-smi0
-
-MDC and MDIO lines connected to GPIO controllers are listed in the
-gpios property as described in section VIII.1 in the following order:
-
-MDC, MDIO.
-
-Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
-node.
-
-Example:
-
-aliases {
- mdio-gpio0 = &mdio0;
-};
-
-mdio0: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- gpios = <&qe_pio_a 11
- &qe_pio_c 6>;
-};
diff --git a/Bindings/net/mdio-gpio.yaml b/Bindings/net/mdio-gpio.yaml
new file mode 100644
index 0000000..1d83b8d
--- /dev/null
+++ b/Bindings/net/mdio-gpio.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MDIO on GPIOs
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Heiner Kallweit <hkallweit1@gmail.com>
+ - Russell King <linux@armlinux.org.uk>
+
+allOf:
+ - $ref: "mdio.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - virtual,mdio-gpio
+ - microchip,mdio-smi0
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ gpios:
+ minItems: 2
+ items:
+ - description: MDC
+ - description: MDIO
+ - description: MDO
+
+#Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
+#node.
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ aliases {
+ mdio-gpio0 = &mdio0;
+ };
+
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&qe_pio_a 11>,
+ <&qe_pio_c 6>;
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+...
diff --git a/Bindings/net/mdio-mux-gpio.txt b/Bindings/net/mdio-mux-gpio.txt
deleted file mode 100644
index 694987d..0000000
--- a/Bindings/net/mdio-mux-gpio.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
-
-This is a special case of a MDIO bus multiplexer. One or more GPIO
-lines are used to control which child bus is connected.
-
-Required properties in addition to the generic multiplexer properties:
-
-- compatible : mdio-mux-gpio.
-- gpios : GPIO specifiers for each GPIO line. One or more must be specified.
-
-
-Example :
-
- /* The parent MDIO bus. */
- smi1: mdio@1180000001900 {
- compatible = "cavium,octeon-3860-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x11800 0x00001900 0x0 0x40>;
- };
-
- /*
- An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
- pair of GPIO lines. Child busses 2 and 3 populated with 4
- PHYs each.
- */
- mdio-mux {
- compatible = "mdio-mux-gpio";
- gpios = <&gpio1 3 0>, <&gpio1 4 0>;
- mdio-parent-bus = <&smi1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy11: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy12: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy13: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy14: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- };
-
- mdio@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy21: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy22: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy23: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy24: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- };
- };
diff --git a/Bindings/net/mdio-mux-gpio.yaml b/Bindings/net/mdio-mux-gpio.yaml
new file mode 100644
index 0000000..71c25c4
--- /dev/null
+++ b/Bindings/net/mdio-mux-gpio.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description:
+ This is a special case of a MDIO bus multiplexer. One or more GPIO
+ lines are used to control which child bus is connected.
+
+allOf:
+ - $ref: /schemas/net/mdio-mux.yaml#
+
+properties:
+ compatible:
+ const: mdio-mux-gpio
+
+ gpios:
+ description:
+ List of GPIOs used to control the multiplexer, least significant bit first.
+ minItems: 1
+ maxItems: 32
+
+required:
+ - compatible
+ - gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /*
+ An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
+ pair of GPIO lines. Child busses 2 and 3 populated with 4
+ PHYs each.
+ */
+ mdio-mux {
+ compatible = "mdio-mux-gpio";
+ gpios = <&gpio1 3 0>, <&gpio1 4 0>;
+ mdio-parent-bus = <&smi1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ reg = <1>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ ethernet-phy@2 {
+ reg = <2>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ ethernet-phy@3 {
+ reg = <3>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ ethernet-phy@4 {
+ reg = <4>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ };
+
+ mdio@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ reg = <1>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ ethernet-phy@2 {
+ reg = <2>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ ethernet-phy@3 {
+ reg = <3>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ ethernet-phy@4 {
+ reg = <4>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ };
+ };
+...
diff --git a/Bindings/net/mdio-mux-mmioreg.txt b/Bindings/net/mdio-mux-mmioreg.txt
deleted file mode 100644
index 065e8bd..0000000
--- a/Bindings/net/mdio-mux-mmioreg.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-Properties for an MDIO bus multiplexer controlled by a memory-mapped device
-
-This is a special case of a MDIO bus multiplexer. A memory-mapped device,
-like an FPGA, is used to control which child bus is connected. The mdio-mux
-node must be a child of the memory-mapped device. The driver currently only
-supports devices with 8, 16 or 32-bit registers.
-
-Required properties in addition to the generic multiplexer properties:
-
-- compatible : string, must contain "mdio-mux-mmioreg"
-
-- reg : integer, contains the offset of the register that controls the bus
- multiplexer. The size field in the 'reg' property is the size of
- register, and must therefore be 1, 2, or 4.
-
-- mux-mask : integer, contains an eight-bit mask that specifies which
- bits in the register control the actual bus multiplexer. The
- 'reg' property of each child mdio-mux node must be constrained by
- this mask.
-
-Example:
-
-The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
-For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.
-A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on
-BRDCFG1 that control the actual mux.
-
- /* The FPGA node */
- fpga: board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
- reg = <3 0 0x30>;
- ranges = <0 3 0 0x30>;
-
- mdio-mux-emi2 {
- compatible = "mdio-mux-mmioreg", "mdio-mux";
- mdio-parent-bus = <&xmdio0>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <9 1>; // BRDCFG1
- mux-mask = <0x6>; // EMI2
-
- emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2)
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_xgmii_slot1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <4>;
- };
- };
-
- emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1)
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_xgmii_slot2: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- };
- };
- };
-
- /* The parent MDIO bus. */
- xmdio0: mdio@f1000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,fman-xmdio";
- reg = <0xf1000 0x1000>;
- interrupts = <100 1 0 0>;
- };
diff --git a/Bindings/net/mdio-mux-mmioreg.yaml b/Bindings/net/mdio-mux-mmioreg.yaml
new file mode 100644
index 0000000..cf86bb0
--- /dev/null
+++ b/Bindings/net/mdio-mux-mmioreg.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description: |+
+ This is a special case of a MDIO bus multiplexer. A memory-mapped device,
+ like an FPGA, is used to control which child bus is connected. The mdio-mux
+ node must be a child of the memory-mapped device. The driver currently only
+ supports devices with 8, 16 or 32-bit registers.
+
+allOf:
+ - $ref: /schemas/net/mdio-mux.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: mdio-mux-mmioreg
+ - const: mdio-mux
+
+ reg:
+ description: Contains the offset of the register that controls the bus
+ multiplexer. The size field in the 'reg' property is the size of register,
+ and must therefore be 1, 2, or 4.
+ maxItems: 1
+
+ mux-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Contains an eight-bit mask that specifies which bits in the
+ register control the actual bus multiplexer. The 'reg' property of each
+ child mdio-mux node must be constrained by this mask.
+
+required:
+ - compatible
+ - reg
+ - mux-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio-mux@9 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&xmdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <9 1>; // BRDCFG1
+ mux-mask = <0x6>; // EMI2
+
+ mdio@0 { // Slot 1 XAUI (FM2)
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_xgmii_slot1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <4>;
+ };
+ };
+
+ mdio@2 { // Slot 2 XAUI (FM1)
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <4>;
+ };
+ };
+ };
+...
diff --git a/Bindings/net/mdio-mux-multiplexer.txt b/Bindings/net/mdio-mux-multiplexer.txt
deleted file mode 100644
index 534e380..0000000
--- a/Bindings/net/mdio-mux-multiplexer.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-Properties for an MDIO bus multiplexer consumer device
-
-This is a special case of MDIO mux when MDIO mux is defined as a consumer
-of a mux producer device. The mux producer can be of any type like mmio mux
-producer, gpio mux producer or generic register based mux producer.
-
-Required properties in addition to the MDIO Bus multiplexer properties:
-
-- compatible : should be "mmio-mux-multiplexer"
-- mux-controls : mux controller node to use for operating the mux
-- mdio-parent-bus : phandle to the parent MDIO bus.
-
-each child node of mdio bus multiplexer consumer device represent a mdio
-bus.
-
-for more information please refer
-Documentation/devicetree/bindings/mux/mux-controller.txt
-and Documentation/devicetree/bindings/net/mdio-mux.txt
-
-Example:
-In below example the Mux producer and consumer are separate nodes.
-
-&i2c0 {
- fpga@66 { // fpga connected to i2c
- compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
- "simple-mfd";
- reg = <0x66>;
-
- mux: mux-controller { // Mux Producer
- compatible = "reg-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
- <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
- };
- };
-};
-
-mdio-mux-1 { // Mux consumer
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 0>;
- mdio-parent-bus = <&emdio1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@8 {
- reg = <0x8>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
-
-mdio-mux-2 { // Mux consumer
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 1>;
- mdio-parent-bus = <&emdio2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@1 {
- reg = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
diff --git a/Bindings/net/mdio-mux-multiplexer.yaml b/Bindings/net/mdio-mux-multiplexer.yaml
new file mode 100644
index 0000000..2829870
--- /dev/null
+++ b/Bindings/net/mdio-mux-multiplexer.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Properties for an MDIO bus multiplexer consumer device
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description: |+
+ This is a special case of MDIO mux when MDIO mux is defined as a consumer
+ of a mux producer device. The mux producer can be of any type like mmio mux
+ producer, gpio mux producer or generic register based mux producer.
+
+
+allOf:
+ - $ref: /schemas/net/mdio-mux.yaml#
+
+properties:
+ compatible:
+ const: mdio-mux-multiplexer
+
+ mux-controls:
+ maxItems: 1
+
+required:
+ - compatible
+ - mux-controls
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mux: mux-controller { // Mux Producer
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+ <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
+ };
+
+ mdio-mux-1 { // Mux consumer
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 0>;
+ mdio-parent-bus = <&emdio1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@8 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mux-2 { // Mux consumer
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 1>;
+ mdio-parent-bus = <&emdio2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+...
diff --git a/Bindings/net/mdio-mux.txt b/Bindings/net/mdio-mux.txt
deleted file mode 100644
index f58571f..0000000
--- a/Bindings/net/mdio-mux.txt
+++ /dev/null
@@ -1,129 +0,0 @@
-Common MDIO bus multiplexer/switch properties.
-
-An MDIO bus multiplexer/switch will have several child busses that are
-numbered uniquely in a device dependent manner. The nodes for an MDIO
-bus multiplexer/switch will have one child node for each child bus.
-
-Required properties:
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Optional properties:
-- mdio-parent-bus : phandle to the parent MDIO bus.
-
-- Other properties specific to the multiplexer/switch hardware.
-
-Required properties for child nodes:
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg : The sub-bus number.
-
-
-Example :
-
- /* The parent MDIO bus. */
- smi1: mdio@1180000001900 {
- compatible = "cavium,octeon-3860-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x11800 0x00001900 0x0 0x40>;
- };
-
- /*
- An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
- pair of GPIO lines. Child busses 2 and 3 populated with 4
- PHYs each.
- */
- mdio-mux {
- compatible = "mdio-mux-gpio";
- gpios = <&gpio1 3 0>, <&gpio1 4 0>;
- mdio-parent-bus = <&smi1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy11: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy12: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy13: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy14: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- };
-
- mdio@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy21: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy22: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy23: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy24: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- };
- };
diff --git a/Bindings/net/mdio-mux.yaml b/Bindings/net/mdio-mux.yaml
new file mode 100644
index 0000000..d169adf
--- /dev/null
+++ b/Bindings/net/mdio-mux.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common MDIO bus multiplexer/switch properties.
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description: |+
+ An MDIO bus multiplexer/switch will have several child busses that are
+ numbered uniquely in a device dependent manner. The nodes for an MDIO
+ bus multiplexer/switch will have one child node for each child bus.
+
+properties:
+ $nodename:
+ pattern: '^mdio-mux[\-@]?'
+
+ mdio-parent-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle of the MDIO bus that this multiplexer's master-side port is
+ connected to.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^mdio@[0-9a-f]+$':
+ type: object
+
+ properties:
+ reg:
+ maxItems: 1
+ description: The sub-bus number.
+
+additionalProperties: true
+
+...
diff --git a/Bindings/net/microchip,sparx5-switch.yaml b/Bindings/net/microchip,sparx5-switch.yaml
new file mode 100644
index 0000000..347b912
--- /dev/null
+++ b/Bindings/net/microchip,sparx5-switch.yaml
@@ -0,0 +1,226 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Ethernet switch controller
+
+maintainers:
+ - Steen Hegelund <steen.hegelund@microchip.com>
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ The SparX-5 Enterprise Ethernet switch family provides a rich set of
+ Enterprise switching features such as advanced TCAM-based VLAN and
+ QoS processing enabling delivery of differentiated services, and
+ security through TCAM-based frame processing using versatile content
+ aware processor (VCAP).
+
+ IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
+ with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K
+ IPv6 (S,G) multicast groups.
+
+ L3 security features include source guard and reverse path
+ forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
+ IP tunnels (IP over GRE/IP).
+
+ The SparX-5 switch family targets managed Layer 2 and Layer 3
+ equipment in SMB, SME, and Enterprise where high port count
+ 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required.
+
+properties:
+ $nodename:
+ pattern: "^switch@[0-9a-f]+$"
+
+ compatible:
+ const: microchip,sparx5-switch
+
+ reg:
+ items:
+ - description: cpu target
+ - description: devices target
+ - description: general control block target
+
+ reg-names:
+ items:
+ - const: cpu
+ - const: devices
+ - const: gcb
+
+ interrupts:
+ minItems: 1
+ items:
+ - description: register based extraction
+ - description: frame dma based extraction
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: xtr
+ - const: fdma
+
+ resets:
+ items:
+ - description: Reset controller used for switch core reset (soft reset)
+
+ reset-names:
+ items:
+ - const: switch
+
+ mac-address: true
+
+ ethernet-ports:
+ type: object
+ patternProperties:
+ "^port@[0-9a-f]+$":
+ type: object
+
+ properties:
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+
+ reg:
+ description: Switch port number
+
+ phys:
+ maxItems: 1
+ description:
+ phandle of a Ethernet SerDes PHY. This defines which SerDes
+ instance will handle the Ethernet traffic.
+
+ phy-mode:
+ description:
+ This specifies the interface used by the Ethernet SerDes towards
+ the PHY or SFP.
+
+ microchip,bandwidth:
+ description: Specifies bandwidth in Mbit/s allocated to the port.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ maximum: 25000
+
+ phy-handle:
+ description:
+ phandle of a Ethernet PHY. This is optional and if provided it
+ points to the cuPHY used by the Ethernet SerDes.
+
+ sfp:
+ description:
+ phandle of an SFP. This is optional and used when not specifying
+ a cuPHY. It points to the SFP node that describes the SFP used by
+ the Ethernet SerDes.
+
+ managed: true
+
+ microchip,sd-sgpio:
+ description:
+ Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs
+ This is optional, and only needed if the default used index is
+ is not correct.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 0
+ maximum: 383
+
+ required:
+ - reg
+ - phys
+ - phy-mode
+ - microchip,bandwidth
+
+ oneOf:
+ - required:
+ - phy-handle
+ - required:
+ - sfp
+ - managed
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - interrupt-names
+ - resets
+ - reset-names
+ - ethernet-ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ switch: switch@600000000 {
+ compatible = "microchip,sparx5-switch";
+ reg = <0 0x401000>,
+ <0x10004000 0x7fc000>,
+ <0x11010000 0xaf0000>;
+ reg-names = "cpu", "devices", "gcb";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "xtr";
+ resets = <&reset 0>;
+ reset-names = "switch";
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy0>;
+ phy-mode = "qsgmii";
+ };
+ /* ... */
+ /* Then the 25G interfaces */
+ port60: port@60 {
+ reg = <60>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 29>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth60>;
+ managed = "in-band-status";
+ microchip,sd-sgpio = <365>;
+ };
+ port61: port@61 {
+ reg = <61>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 30>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth61>;
+ managed = "in-band-status";
+ microchip,sd-sgpio = <369>;
+ };
+ port62: port@62 {
+ reg = <62>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 31>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth62>;
+ managed = "in-band-status";
+ microchip,sd-sgpio = <373>;
+ };
+ port63: port@63 {
+ reg = <63>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 32>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth63>;
+ managed = "in-band-status";
+ microchip,sd-sgpio = <377>;
+ };
+ /* Finally the Management interface */
+ port64: port@64 {
+ reg = <64>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 0>;
+ phy-handle = <&phy64>;
+ phy-mode = "sgmii";
+ mac-address = [ 00 00 00 01 02 03 ];
+ };
+ };
+ };
+
+...
+# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :
diff --git a/Bindings/net/nfc/samsung,s3fwrn5.yaml b/Bindings/net/nfc/samsung,s3fwrn5.yaml
index 477066e..081742c 100644
--- a/Bindings/net/nfc/samsung,s3fwrn5.yaml
+++ b/Bindings/net/nfc/samsung,s3fwrn5.yaml
@@ -27,6 +27,9 @@
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+
wake-gpios:
maxItems: 1
description:
@@ -80,6 +83,8 @@
en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
+
+ clocks = <&rpmcc 20>;
};
};
# UART example on Raspberry Pi
diff --git a/Bindings/net/qcom,ipa.yaml b/Bindings/net/qcom,ipa.yaml
index 5fe6d3d..ed88ba4 100644
--- a/Bindings/net/qcom,ipa.yaml
+++ b/Bindings/net/qcom,ipa.yaml
@@ -44,6 +44,7 @@
properties:
compatible:
enum:
+ - qcom,msm8998-ipa
- qcom,sc7180-ipa
- qcom,sc7280-ipa
- qcom,sdm845-ipa
diff --git a/Bindings/net/qualcomm-bluetooth.txt b/Bindings/net/qualcomm-bluetooth.txt
deleted file mode 100644
index 709ca6d..0000000
--- a/Bindings/net/qualcomm-bluetooth.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-Qualcomm Bluetooth Chips
----------------------
-
-This documents the binding structure and common properties for serial
-attached Qualcomm devices.
-
-Serial attached Qualcomm devices shall be a child node of the host UART
-device the slave device is attached to.
-
-Required properties:
- - compatible: should contain one of the following:
- * "qcom,qca6174-bt"
- * "qcom,qca9377-bt"
- * "qcom,wcn3990-bt"
- * "qcom,wcn3991-bt"
- * "qcom,wcn3998-bt"
- * "qcom,qca6390-bt"
-
-Optional properties for compatible string qcom,qca6174-bt:
-
- - enable-gpios: gpio specifier used to enable chip
- - clocks: clock provided to the controller (SUSCLK_32KHZ)
- - firmware-name: specify the name of nvm firmware to load
-
-Optional properties for compatible string qcom,qca9377-bt:
-
- - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml
-
-Required properties for compatible string qcom,wcn399x-bt:
-
- - vddio-supply: VDD_IO supply regulator handle.
- - vddxo-supply: VDD_XO supply regulator handle.
- - vddrf-supply: VDD_RF supply regulator handle.
- - vddch0-supply: VDD_CH0 supply regulator handle.
-
-Optional properties for compatible string qcom,wcn399x-bt:
-
- - max-speed: see Documentation/devicetree/bindings/serial/serial.yaml
- - firmware-name: specify the name of nvm firmware to load
- - clocks: clock provided to the controller
-
-Examples:
-
-serial@7570000 {
- label = "BT-UART";
- status = "okay";
-
- bluetooth {
- compatible = "qcom,qca6174-bt";
-
- enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
- clocks = <&divclk4>;
- firmware-name = "nvm_00440302.bin";
- };
-};
-
-serial@898000 {
- bluetooth {
- compatible = "qcom,wcn3990-bt";
-
- vddio-supply = <&vreg_s4a_1p8>;
- vddxo-supply = <&vreg_l7a_1p8>;
- vddrf-supply = <&vreg_l17a_1p3>;
- vddch0-supply = <&vreg_l25a_3p3>;
- max-speed = <3200000>;
- firmware-name = "crnv21.bin";
- clocks = <&rpmhcc RPMH_RF_CLK2>;
- };
-};
diff --git a/Bindings/net/qualcomm-bluetooth.yaml b/Bindings/net/qualcomm-bluetooth.yaml
new file mode 100644
index 0000000..f93c6e7
--- /dev/null
+++ b/Bindings/net/qualcomm-bluetooth.yaml
@@ -0,0 +1,183 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/qualcomm-bluetooth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Bluetooth Chips
+
+maintainers:
+ - Balakrishna Godavarthi <bgodavar@codeaurora.org>
+ - Rocky Liao <rjliao@codeaurora.org>
+
+description:
+ This binding describes Qualcomm UART-attached bluetooth chips.
+
+properties:
+ compatible:
+ enum:
+ - qcom,qca6174-bt
+ - qcom,qca9377-bt
+ - qcom,wcn3990-bt
+ - qcom,wcn3991-bt
+ - qcom,wcn3998-bt
+ - qcom,qca6390-bt
+ - qcom,wcn6750-bt
+
+ enable-gpios:
+ maxItems: 1
+ description: gpio specifier used to enable chip
+
+ swctrl-gpios:
+ maxItems: 1
+ description: gpio specifier is used to find status
+ of clock supply to SoC
+
+ clocks:
+ maxItems: 1
+ description: clock provided to the controller (SUSCLK_32KHZ)
+
+ vddio-supply:
+ description: VDD_IO supply regulator handle
+
+ vddxo-supply:
+ description: VDD_XO supply regulator handle
+
+ vddrf-supply:
+ description: VDD_RF supply regulator handle
+
+ vddch0-supply:
+ description: VDD_CH0 supply regulator handle
+
+ vddaon-supply:
+ description: VDD_AON supply regulator handle
+
+ vddbtcxmx-supply:
+ description: VDD_BT_CXMX supply regulator handle
+
+ vddrfacmn-supply:
+ description: VDD_RFA_CMN supply regulator handle
+
+ vddrfa0p8-supply:
+ description: VDD_RFA_0P8 suppply regulator handle
+
+ vddrfa1p7-supply:
+ description: VDD_RFA_1P7 supply regulator handle
+
+ vddrfa1p2-supply:
+ description: VDD_RFA_1P2 supply regulator handle
+
+ vddrfa2p2-supply:
+ description: VDD_RFA_2P2 supply regulator handle
+
+ vddasd-supply:
+ description: VDD_ASD supply regulator handle
+
+ max-speed:
+ description: see Documentation/devicetree/bindings/serial/serial.yaml
+
+ firmware-name:
+ description: specify the name of nvm firmware to load
+
+ local-bd-address:
+ description: see Documentation/devicetree/bindings/net/bluetooth.txt
+
+
+required:
+ - compatible
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qca6174-bt
+ then:
+ required:
+ - enable-gpios
+ - clocks
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,wcn3990-bt
+ - qcom,wcn3991-bt
+ - qcom,wcn3998-bt
+ then:
+ required:
+ - vddio-supply
+ - vddxo-supply
+ - vddrf-supply
+ - vddch0-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,wcn6750-bt
+ then:
+ required:
+ - enable-gpios
+ - swctrl-gpios
+ - vddio-supply
+ - vddaon-supply
+ - vddbtcxmx-supply
+ - vddrfacmn-supply
+ - vddrfa0p8-supply
+ - vddrfa1p7-supply
+ - vddrfa1p2-supply
+ - vddasd-supply
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ serial {
+
+ bluetooth {
+ compatible = "qcom,qca6174-bt";
+ enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>;
+ clocks = <&divclk4>;
+ firmware-name = "nvm_00440302.bin";
+ };
+ };
+ - |
+ serial {
+
+ bluetooth {
+ compatible = "qcom,wcn3990-bt";
+ vddio-supply = <&vreg_s4a_1p8>;
+ vddxo-supply = <&vreg_l7a_1p8>;
+ vddrf-supply = <&vreg_l17a_1p3>;
+ vddch0-supply = <&vreg_l25a_3p3>;
+ max-speed = <3200000>;
+ firmware-name = "crnv21.bin";
+ };
+ };
+ - |
+ serial {
+
+ bluetooth {
+ compatible = "qcom,wcn6750-bt";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_default>;
+ enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
+ swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
+ vddio-supply = <&vreg_l19b_1p8>;
+ vddaon-supply = <&vreg_s7b_0p9>;
+ vddbtcxmx-supply = <&vreg_s7b_0p9>;
+ vddrfacmn-supply = <&vreg_s7b_0p9>;
+ vddrfa0p8-supply = <&vreg_s7b_0p9>;
+ vddrfa1p7-supply = <&vreg_s1b_1p8>;
+ vddrfa1p2-supply = <&vreg_s8b_1p2>;
+ vddrfa2p2-supply = <&vreg_s1c_2p2>;
+ vddasd-supply = <&vreg_l11c_2p8>;
+ max-speed = <3200000>;
+ firmware-name = "msnv11.bin";
+ };
+ };
diff --git a/Bindings/net/realtek,rtl82xx.yaml b/Bindings/net/realtek,rtl82xx.yaml
new file mode 100644
index 0000000..bb94a23
--- /dev/null
+++ b/Bindings/net/realtek,rtl82xx.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/realtek,rtl82xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek RTL82xx PHY
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Florian Fainelli <f.fainelli@gmail.com>
+ - Heiner Kallweit <hkallweit1@gmail.com>
+
+description:
+ Bindings for Realtek RTL82xx PHYs
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ realtek,clkout-disable:
+ type: boolean
+ description:
+ Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset.
+
+
+ realtek,aldps-enable:
+ type: boolean
+ description:
+ Enable ALDPS mode, ALDPS mode default is disabled after hardware reset.
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ realtek,clkout-disable;
+ realtek,aldps-enable;
+ };
+ };
diff --git a/Bindings/net/rockchip-dwmac.yaml b/Bindings/net/rockchip-dwmac.yaml
index 5acddb6..083623c 100644
--- a/Bindings/net/rockchip-dwmac.yaml
+++ b/Bindings/net/rockchip-dwmac.yaml
@@ -19,10 +19,12 @@
- rockchip,rk3128-gmac
- rockchip,rk3228-gmac
- rockchip,rk3288-gmac
+ - rockchip,rk3308-gmac
- rockchip,rk3328-gmac
- rockchip,rk3366-gmac
- rockchip,rk3368-gmac
- rockchip,rk3399-gmac
+ - rockchip,rk3568-gmac
- rockchip,rv1108-gmac
required:
- compatible
@@ -32,17 +34,23 @@
properties:
compatible:
- items:
- - enum:
- - rockchip,px30-gmac
- - rockchip,rk3128-gmac
- - rockchip,rk3228-gmac
- - rockchip,rk3288-gmac
- - rockchip,rk3328-gmac
- - rockchip,rk3366-gmac
- - rockchip,rk3368-gmac
- - rockchip,rk3399-gmac
- - rockchip,rv1108-gmac
+ oneOf:
+ - items:
+ - enum:
+ - rockchip,px30-gmac
+ - rockchip,rk3128-gmac
+ - rockchip,rk3228-gmac
+ - rockchip,rk3288-gmac
+ - rockchip,rk3308-gmac
+ - rockchip,rk3328-gmac
+ - rockchip,rk3366-gmac
+ - rockchip,rk3368-gmac
+ - rockchip,rk3399-gmac
+ - rockchip,rv1108-gmac
+ - items:
+ - enum:
+ - rockchip,rk3568-gmac
+ - const: snps,dwmac-4.20a
clocks:
minItems: 5
diff --git a/Bindings/net/snps,dwmac.yaml b/Bindings/net/snps,dwmac.yaml
index 2edd8be..d765259 100644
--- a/Bindings/net/snps,dwmac.yaml
+++ b/Bindings/net/snps,dwmac.yaml
@@ -51,11 +51,20 @@
- allwinner,sun8i-r40-emac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - loongson,ls2k-dwmac
+ - loongson,ls7a-dwmac
- amlogic,meson6-dwmac
- amlogic,meson8b-dwmac
- amlogic,meson8m2-dwmac
- amlogic,meson-gxbb-dwmac
- amlogic,meson-axg-dwmac
+ - loongson,ls2k-dwmac
+ - loongson,ls7a-dwmac
+ - ingenic,jz4775-mac
+ - ingenic,x1000-mac
+ - ingenic,x1600-mac
+ - ingenic,x1830-mac
+ - ingenic,x2000-mac
- rockchip,px30-gmac
- rockchip,rk3128-gmac
- rockchip,rk3228-gmac
@@ -82,7 +91,6 @@
interrupts:
minItems: 1
- maxItems: 3
items:
- description: Combined signal for various interrupt events
- description: The interrupt to manage the remote wake-up packet detection
@@ -90,7 +98,6 @@
interrupt-names:
minItems: 1
- maxItems: 3
items:
- const: macirq
- const: eth_wake_irq
@@ -310,6 +317,11 @@
- allwinner,sun8i-r40-emac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - ingenic,jz4775-mac
+ - ingenic,x1000-mac
+ - ingenic,x1600-mac
+ - ingenic,x1830-mac
+ - ingenic,x2000-mac
- snps,dwxgmac
- snps,dwxgmac-2.10
- st,spear600-gmac
@@ -353,6 +365,13 @@
- allwinner,sun8i-r40-emac
- allwinner,sun8i-v3s-emac
- allwinner,sun50i-a64-emac
+ - loongson,ls2k-dwmac
+ - loongson,ls7a-dwmac
+ - ingenic,jz4775-mac
+ - ingenic,x1000-mac
+ - ingenic,x1600-mac
+ - ingenic,x1830-mac
+ - ingenic,x2000-mac
- snps,dwmac-4.00
- snps,dwmac-4.10a
- snps,dwmac-4.20a
diff --git a/Bindings/net/stm32-dwmac.yaml b/Bindings/net/stm32-dwmac.yaml
index 27eb606..d3f05d5 100644
--- a/Bindings/net/stm32-dwmac.yaml
+++ b/Bindings/net/stm32-dwmac.yaml
@@ -46,17 +46,17 @@
clocks:
minItems: 3
- maxItems: 5
items:
- description: GMAC main clock
- description: MAC TX clock
- description: MAC RX clock
- description: For MPU family, used for power mode
- description: For MPU family, used for PHY without quartz
+ - description: PTP clock
clock-names:
minItems: 3
- maxItems: 5
+ maxItems: 6
contains:
enum:
- stmmaceth
@@ -64,6 +64,7 @@
- mac-clk-rx
- ethstp
- eth-ck
+ - ptp_ref
st,syscon:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
diff --git a/Bindings/pci/brcm,stb-pcie.yaml b/Bindings/pci/brcm,stb-pcie.yaml
index f90557f..b9589a0 100644
--- a/Bindings/pci/brcm,stb-pcie.yaml
+++ b/Bindings/pci/brcm,stb-pcie.yaml
@@ -25,14 +25,12 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: PCIe host controller
- description: builtin MSI controller
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: pcie
- const: msi
diff --git a/Bindings/pci/fsl,imx6q-pcie.txt b/Bindings/pci/fsl,imx6q-pcie.txt
index de4b2ba..d8971ab 100644
--- a/Bindings/pci/fsl,imx6q-pcie.txt
+++ b/Bindings/pci/fsl,imx6q-pcie.txt
@@ -38,6 +38,9 @@
The regulator will be enabled when initializing the PCIe host and
disabled either as part of the init process or when shutting down the
host.
+- vph-supply: Should specify the regulator in charge of VPH one of the three
+ PCIe PHY powers. This regulator can be supplied by both 1.8v and 3.3v voltage
+ supplies.
Additional required properties for imx6sx-pcie:
- clock names: Must include the following additional entries:
diff --git a/Bindings/pci/intel,ixp4xx-pci.yaml b/Bindings/pci/intel,ixp4xx-pci.yaml
new file mode 100644
index 0000000..debfb54
--- /dev/null
+++ b/Bindings/pci/intel,ixp4xx-pci.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/intel,ixp4xx-pci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel IXP4xx PCI controller
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: PCI host controller found in the Intel IXP4xx SoC series.
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - intel,ixp42x-pci
+ - intel,ixp43x-pci
+ description: The two supported variants are ixp42x and ixp43x,
+ though more variants may exist.
+
+ reg:
+ items:
+ - description: IXP4xx-specific registers
+
+ interrupts:
+ items:
+ - description: Main PCI interrupt
+ - description: PCI DMA interrupt 1
+ - description: PCI DMA interrupt 2
+
+ ranges:
+ maxItems: 2
+ description: Typically one memory range of 64MB and one IO
+ space range of 64KB.
+
+ dma-ranges:
+ maxItems: 1
+ description: The DMA range tells the PCI host which addresses
+ the RAM is at. It can map only 64MB so if the RAM is bigger
+ than 64MB the DMA access has to be restricted to these
+ addresses.
+
+ "#interrupt-cells": true
+
+ interrupt-map: true
+
+ interrupt-map-mask:
+ items:
+ - const: 0xf800
+ - const: 0
+ - const: 0
+ - const: 7
+
+required:
+ - compatible
+ - reg
+ - dma-ranges
+ - "#interrupt-cells"
+ - interrupt-map
+ - interrupt-map-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ pci@c0000000 {
+ compatible = "intel,ixp43x-pci";
+ reg = <0xc0000000 0x1000>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+
+ ranges =
+ <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
+ <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
+ dma-ranges =
+ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map =
+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
+ <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
+ <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
+ <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
+ <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
+ <0x1800 0 0 4 &gpio0 10 3>; /* INT D on slot 3 is irq 10 */
+ };
diff --git a/Bindings/pci/loongson.yaml b/Bindings/pci/loongson.yaml
index 81bae06..82bc6c4 100644
--- a/Bindings/pci/loongson.yaml
+++ b/Bindings/pci/loongson.yaml
@@ -24,7 +24,6 @@
reg:
minItems: 1
- maxItems: 2
items:
- description: CFG0 standard config space register
- description: CFG1 extended config space register
diff --git a/Bindings/pci/mediatek-pcie-gen3.yaml b/Bindings/pci/mediatek-pcie-gen3.yaml
index e7b1f98..742206d 100644
--- a/Bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Bindings/pci/mediatek-pcie-gen3.yaml
@@ -70,7 +70,6 @@
reset-names:
minItems: 1
- maxItems: 2
items:
- const: phy
- const: mac
diff --git a/Bindings/pci/microchip,pcie-host.yaml b/Bindings/pci/microchip,pcie-host.yaml
index 04251d7..fb95c27 100644
--- a/Bindings/pci/microchip,pcie-host.yaml
+++ b/Bindings/pci/microchip,pcie-host.yaml
@@ -26,14 +26,12 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: PCIe host controller
- description: builtin MSI controller
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: pcie
- const: msi
diff --git a/Bindings/pci/pci-keystone.txt b/Bindings/pci/pci-keystone.txt
deleted file mode 100644
index 47202a2..0000000
--- a/Bindings/pci/pci-keystone.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-TI Keystone PCIe interface
-
-Keystone PCI host Controller is based on the Synopsys DesignWare PCI
-hardware version 3.65. It shares common functions with the PCIe DesignWare
-core driver and inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt
-
-Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
-for the details of DesignWare DT bindings. Additional properties are
-described here as well as properties that are not applicable.
-
-Required Properties:-
-
-compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
- Should be "ti,am654-pcie-rc" for RC on AM654x SoC
-reg: Three register ranges as listed in the reg-names property
-reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
- TI specific application registers, "config" for the
- configuration space address
-
-pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
- interrupt-cells: should be set to 1
- interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
- (required if the compatible is "ti,keystone-pcie")
-msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
- (required if the compatible is "ti,am654-pcie-rc".
-
-ti,syscon-pcie-id : phandle to the device control module required to set device
- id and vendor id.
-ti,syscon-pcie-mode : phandle to the device control module required to configure
- PCI in either RC mode or EP mode.
-
- Example:
- pcie_msi_intc: msi-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
- };
-
-pcie_intc: Interrupt controller device node for Legacy IRQ chip
- interrupt-cells: should be set to 1
-
- Example:
- pcie_intc: legacy-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
- };
-
-Optional properties:-
- phys: phandle to generic Keystone SerDes PHY for PCI
- phy-names: name of the generic Keystone SerDes PHY for PCI
- - If boot loader already does PCI link establishment, then phys and
- phy-names shouldn't be present.
- interrupts: platform interrupt for error interrupts.
-
-DesignWare DT Properties not applicable for Keystone PCI
-
-1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
-
-AM654 PCIe Endpoint
-===================
-
-Required Properties:-
-
-compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
-reg: Four register ranges as listed in the reg-names property
-reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
- TI specific application registers, "atu" for the
- Address Translation Unit configuration registers and
- "addr_space" used to map remote RC address space
-num-ib-windows: As specified in
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-num-ob-windows: As specified in
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-num-lanes: As specified in
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-power-domains: As documented by the generic PM domain bindings in
- Documentation/devicetree/bindings/power/power_domain.txt.
-ti,syscon-pcie-mode: phandle to the device control module required to configure
- PCI in either RC mode or EP mode.
-
-Optional properties:-
-
-phys: list of PHY specifiers (used by generic PHY framework)
-phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
- number of lanes as specified in *num-lanes* property.
-("phys" and "phy-names" DT bindings are specified in
-Documentation/devicetree/bindings/phy/phy-bindings.txt)
-interrupts: platform interrupt for error interrupts.
-
-pcie-ep {
- compatible = "ti,am654-pcie-ep";
- reg = <0x5500000 0x1000>, <0x5501000 0x1000>,
- <0x10000000 0x8000000>, <0x5506000 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
- num-lanes = <1>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
-};
diff --git a/Bindings/pci/qcom,pcie.txt b/Bindings/pci/qcom,pcie.txt
index 0da458a..25f4def 100644
--- a/Bindings/pci/qcom,pcie.txt
+++ b/Bindings/pci/qcom,pcie.txt
@@ -14,6 +14,7 @@
- "qcom,pcie-qcs404" for qcs404
- "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8250" for sm8250
+ - "qcom,pcie-ipq6018" for ipq6018
- reg:
Usage: required
@@ -124,6 +125,16 @@
- "aux" Auxiliary clock
- clock-names:
+ Usage: required for ipq6018
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "iface" PCIe to SysNOC BIU clock
+ - "axi_m" AXI Master clock
+ - "axi_s" AXI Slave clock
+ - "axi_bridge" AXI bridge clock
+ - "rchng"
+
+- clock-names:
Usage: required for qcs404
Value type: <stringlist>
Definition: Should contain the following entries
@@ -210,6 +221,19 @@
- "axi_m_sticky" AXI Master Sticky reset
- reset-names:
+ Usage: required for ipq6018
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "pipe" PIPE reset
+ - "sleep" Sleep reset
+ - "sticky" Core Sticky reset
+ - "axi_m" AXI Master reset
+ - "axi_s" AXI Slave reset
+ - "ahb" AHB Reset
+ - "axi_m_sticky" AXI Master Sticky reset
+ - "axi_s_sticky" AXI Slave Sticky reset
+
+- reset-names:
Usage: required for qcs404
Value type: <stringlist>
Definition: Should contain the following entries
diff --git a/Bindings/pci/ti,am65-pci-ep.yaml b/Bindings/pci/ti,am65-pci-ep.yaml
new file mode 100644
index 0000000..78c217d
--- /dev/null
+++ b/Bindings/pci/ti,am65-pci-ep.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI AM65 PCI Endpoint
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+
+allOf:
+ - $ref: pci-ep.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,am654-pcie-ep
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: app
+ - const: dbics
+ - const: addr_space
+ - const: atu
+
+ power-domains:
+ maxItems: 1
+
+ ti,syscon-pcie-mode:
+ description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ interrupts:
+ minItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - max-link-speed
+ - power-domains
+ - ti,syscon-pcie-mode
+ - dma-coherent
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ pcie0_ep: pcie-ep@5500000 {
+ compatible = "ti,am654-pcie-ep";
+ reg = <0x5500000 0x1000>,
+ <0x5501000 0x1000>,
+ <0x10000000 0x8000000>,
+ <0x5506000 0x1000>;
+ reg-names = "app", "dbics", "addr_space", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ };
diff --git a/Bindings/pci/ti,am65-pci-host.yaml b/Bindings/pci/ti,am65-pci-host.yaml
new file mode 100644
index 0000000..834dc1c
--- /dev/null
+++ b/Bindings/pci/ti,am65-pci-host.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI AM65 PCI Host
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,am654-pcie-rc
+ - ti,keystone-pcie
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: app
+ - const: dbics
+ - const: config
+ - const: atu
+
+ power-domains:
+ maxItems: 1
+
+ ti,syscon-pcie-id:
+ description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ ti,syscon-pcie-mode:
+ description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ msi-map: true
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - max-link-speed
+ - ti,syscon-pcie-id
+ - ti,syscon-pcie-mode
+ - ranges
+
+if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-pcie-rc
+then:
+ required:
+ - dma-coherent
+ - power-domains
+ - msi-map
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ pcie0_rc: pcie@5500000 {
+ compatible = "ti,am654-pcie-rc";
+ reg = <0x5500000 0x1000>,
+ <0x5501000 0x1000>,
+ <0x10000000 0x2000>,
+ <0x5506000 0x1000>;
+ reg-names = "app", "dbics", "config", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
+ <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&pcie_devid>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ bus-range = <0x0 0xff>;
+ num-viewport = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ device_type = "pci";
+ };
diff --git a/Bindings/perf/arm,cmn.yaml b/Bindings/perf/arm,cmn.yaml
index e4fcc0d..42424cc 100644
--- a/Bindings/perf/arm,cmn.yaml
+++ b/Bindings/perf/arm,cmn.yaml
@@ -21,7 +21,6 @@
interrupts:
minItems: 1
- maxItems: 4
items:
- description: Overflow interrupt for DTC0
- description: Overflow interrupt for DTC1
diff --git a/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml b/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
index f804310..e288450 100644
--- a/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
+++ b/Bindings/phy/allwinner,sun8i-h3-usb-phy.yaml
@@ -15,7 +15,9 @@
const: 1
compatible:
- const: allwinner,sun8i-h3-usb-phy
+ enum:
+ - allwinner,sun8i-h3-usb-phy
+ - allwinner,sun50i-h616-usb-phy
reg:
items:
diff --git a/Bindings/phy/brcm,bcm63xx-usbh-phy.yaml b/Bindings/phy/brcm,bcm63xx-usbh-phy.yaml
index 9a2e779..0f0bcde 100644
--- a/Bindings/phy/brcm,bcm63xx-usbh-phy.yaml
+++ b/Bindings/phy/brcm,bcm63xx-usbh-phy.yaml
@@ -28,7 +28,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: usbh
- const: usb_ref
diff --git a/Bindings/phy/brcm,brcmstb-usb-phy.yaml b/Bindings/phy/brcm,brcmstb-usb-phy.yaml
index 5f9e91b..43a4b88 100644
--- a/Bindings/phy/brcm,brcmstb-usb-phy.yaml
+++ b/Bindings/phy/brcm,brcmstb-usb-phy.yaml
@@ -22,7 +22,6 @@
reg:
minItems: 1
- maxItems: 6
items:
- description: the base CTRL register
- description: XHCI EC register
@@ -33,7 +32,6 @@
reg-names:
minItems: 1
- maxItems: 6
items:
- const: ctrl
- const: xhci_ec
@@ -51,7 +49,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: sw_usb
- const: sw_usb3
diff --git a/Bindings/phy/brcm,sata-phy.yaml b/Bindings/phy/brcm,sata-phy.yaml
index 04edda5..cb1aa32 100644
--- a/Bindings/phy/brcm,sata-phy.yaml
+++ b/Bindings/phy/brcm,sata-phy.yaml
@@ -35,7 +35,6 @@
reg-names:
minItems: 1
- maxItems: 2
items:
- const: phy
- const: phy-ctrl
diff --git a/Bindings/phy/hisilicon,hi3670-usb3.yaml b/Bindings/phy/hisilicon,hi3670-usb3.yaml
new file mode 100644
index 0000000..ebd78ac
--- /dev/null
+++ b/Bindings/phy/hisilicon,hi3670-usb3.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/hisilicon,hi3670-usb3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Hisilicon Kirin970 USB PHY
+
+maintainers:
+ - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
+
+description: |+
+ Bindings for USB3 PHY on HiSilicon Kirin 970.
+
+properties:
+ compatible:
+ const: hisilicon,hi3670-usb-phy
+
+ "#phy-cells":
+ const: 0
+
+ hisilicon,pericrg-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle of syscon used to control iso refclk.
+
+ hisilicon,pctrl-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle of syscon used to control usb tcxo.
+
+ hisilicon,sctrl-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle of syscon used to control phy deep sleep.
+
+ hisilicon,eye-diagram-param:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Eye diagram for phy.
+
+ hisilicon,tx-vboost-lvl:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: TX level vboost for phy.
+
+required:
+ - compatible
+ - hisilicon,pericrg-syscon
+ - hisilicon,pctrl-syscon
+ - hisilicon,sctrl-syscon
+ - hisilicon,eye-diagram-param
+ - hisilicon,tx-vboost-lvl
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb3_otg_bc: usb3_otg_bc@ff200000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0xff200000 0x0 0x1000>;
+
+ usb_phy {
+ compatible = "hisilicon,hi3670-usb-phy";
+ #phy-cells = <0>;
+ hisilicon,pericrg-syscon = <&crg_ctrl>;
+ hisilicon,pctrl-syscon = <&pctrl>;
+ hisilicon,sctrl-syscon = <&sctrl>;
+ hisilicon,eye-diagram-param = <0xfdfee4>;
+ hisilicon,tx-vboost-lvl = <0x5>;
+ };
+ };
+ };
diff --git a/Bindings/phy/mediatek,mt7621-pci-phy.yaml b/Bindings/phy/mediatek,mt7621-pci-phy.yaml
index 0ccaded..29d4123 100644
--- a/Bindings/phy/mediatek,mt7621-pci-phy.yaml
+++ b/Bindings/phy/mediatek,mt7621-pci-phy.yaml
@@ -16,6 +16,9 @@
reg:
maxItems: 1
+ clocks:
+ maxItems: 1
+
"#phy-cells":
const: 1
description: selects if the phy is dual-ported
@@ -23,6 +26,7 @@
required:
- compatible
- reg
+ - clocks
- "#phy-cells"
additionalProperties: false
@@ -32,5 +36,6 @@
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
+ clocks = <&sysc 0>;
#phy-cells = <1>;
};
diff --git a/Bindings/phy/mediatek,tphy.yaml b/Bindings/phy/mediatek,tphy.yaml
index b8a7651..ef9d9d4 100644
--- a/Bindings/phy/mediatek,tphy.yaml
+++ b/Bindings/phy/mediatek,tphy.yaml
@@ -131,7 +131,6 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
- description: Reference clock of analog phy
@@ -141,7 +140,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: da_ref
diff --git a/Bindings/phy/phy-cadence-sierra.yaml b/Bindings/phy/phy-cadence-sierra.yaml
index 84383e2..e71b32c 100644
--- a/Bindings/phy/phy-cadence-sierra.yaml
+++ b/Bindings/phy/phy-cadence-sierra.yaml
@@ -31,14 +31,12 @@
resets:
minItems: 1
- maxItems: 2
items:
- description: Sierra PHY reset.
- description: Sierra APB reset. This is optional.
reset-names:
minItems: 1
- maxItems: 2
items:
- const: sierra_reset
- const: sierra_apb
diff --git a/Bindings/phy/phy-cadence-torrent.yaml b/Bindings/phy/phy-cadence-torrent.yaml
index 320a232..bd9ae11 100644
--- a/Bindings/phy/phy-cadence-torrent.yaml
+++ b/Bindings/phy/phy-cadence-torrent.yaml
@@ -52,28 +52,24 @@
reg:
minItems: 1
- maxItems: 2
items:
- description: Offset of the Torrent PHY configuration registers.
- description: Offset of the DPTX PHY configuration registers.
reg-names:
minItems: 1
- maxItems: 2
items:
- const: torrent_phy
- const: dptx_phy
resets:
minItems: 1
- maxItems: 2
items:
- description: Torrent PHY reset.
- description: Torrent APB reset. This is optional.
reset-names:
minItems: 1
- maxItems: 2
items:
- const: torrent_reset
- const: torrent_apb
diff --git a/Bindings/phy/phy-mvebu-comphy.txt b/Bindings/phy/phy-mvebu-comphy.txt
index 8c60e69..5ffd0f5 100644
--- a/Bindings/phy/phy-mvebu-comphy.txt
+++ b/Bindings/phy/phy-mvebu-comphy.txt
@@ -42,22 +42,22 @@
Examples:
- cpm_comphy: phy@120000 {
+ CP11X_LABEL(comphy): phy@120000 {
compatible = "marvell,comphy-cp110";
reg = <0x120000 0x6000>;
- marvell,system-controller = <&cpm_syscon0>;
- clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
- <&CP110_LABEL(clk) 1 18>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
+ <&CP11X_LABEL(clk) 1 18>;
clock-names = "mg_clk", "mg_core_clk", "axi_clk";
#address-cells = <1>;
#size-cells = <0>;
- cpm_comphy0: phy@0 {
+ CP11X_LABEL(comphy0): phy@0 {
reg = <0>;
#phy-cells = <1>;
};
- cpm_comphy1: phy@1 {
+ CP11X_LABEL(comphy1): phy@1 {
reg = <1>;
#phy-cells = <1>;
};
diff --git a/Bindings/phy/phy-rockchip-inno-usb2.yaml b/Bindings/phy/phy-rockchip-inno-usb2.yaml
index fb29ad8..5bebd86 100644
--- a/Bindings/phy/phy-rockchip-inno-usb2.yaml
+++ b/Bindings/phy/phy-rockchip-inno-usb2.yaml
@@ -14,6 +14,7 @@
enum:
- rockchip,px30-usb2phy
- rockchip,rk3228-usb2phy
+ - rockchip,rk3308-usb2phy
- rockchip,rk3328-usb2phy
- rockchip,rk3366-usb2phy
- rockchip,rk3399-usb2phy
@@ -29,9 +30,6 @@
"#clock-cells":
const: 0
- "#phy-cells":
- const: 0
-
clocks:
maxItems: 1
@@ -119,7 +117,6 @@
- reg
- clock-output-names
- "#clock-cells"
- - "#phy-cells"
- host-port
- otg-port
@@ -130,26 +127,25 @@
#include <dt-bindings/clock/rk3399-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
- u2phy0: usb2-phy@e450 {
+ u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
clocks = <&cru SCLK_USB2PHY0_REF>;
clock-names = "phyclk";
clock-output-names = "clk_usbphy0_480m";
#clock-cells = <0>;
- #phy-cells = <0>;
u2phy0_host: host-port {
- #phy-cells = <0>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "linestate";
+ #phy-cells = <0>;
};
u2phy0_otg: otg-port {
- #phy-cells = <0>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "otg-bvalid", "otg-id", "linestate";
+ #phy-cells = <0>;
};
};
diff --git a/Bindings/phy/phy-stm32-usbphyc.yaml b/Bindings/phy/phy-stm32-usbphyc.yaml
index 018cc12..3329f1d 100644
--- a/Bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Bindings/phy/phy-stm32-usbphyc.yaml
@@ -74,6 +74,13 @@
"#phy-cells":
enum: [ 0x0, 0x1 ]
+ connector:
+ type: object
+ allOf:
+ - $ref: ../connector/usb-connector.yaml
+ properties:
+ vbus-supply: true
+
allOf:
- if:
properties:
@@ -130,6 +137,10 @@
reg = <0>;
phy-supply = <&vdd_usb>;
#phy-cells = <0>;
+ connector {
+ compatible = "usb-a-connector";
+ vbus-supply = <&vbus_sw>;
+ };
};
usbphyc_port1: usb-phy@1 {
diff --git a/Bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
index 17f132c..35296c5 100644
--- a/Bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
+++ b/Bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
@@ -30,7 +30,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: xo
diff --git a/Bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
index 17fd7f6..6cf5c6c 100644
--- a/Bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
+++ b/Bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
@@ -30,7 +30,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: xo
diff --git a/Bindings/phy/qcom,qmp-phy.yaml b/Bindings/phy/qcom,qmp-phy.yaml
index 7808ec8..f0497b8 100644
--- a/Bindings/phy/qcom,qmp-phy.yaml
+++ b/Bindings/phy/qcom,qmp-phy.yaml
@@ -17,6 +17,7 @@
properties:
compatible:
enum:
+ - qcom,ipq6018-qmp-pcie-phy
- qcom,ipq8074-qmp-pcie-phy
- qcom,ipq8074-qmp-usb3-phy
- qcom,msm8996-qmp-pcie-phy
@@ -45,11 +46,11 @@
- qcom,sm8350-qmp-ufs-phy
- qcom,sm8350-qmp-usb3-phy
- qcom,sm8350-qmp-usb3-uni-phy
+ - qcom,sdx55-qmp-pcie-phy
- qcom,sdx55-qmp-usb3-uni-phy
reg:
minItems: 1
- maxItems: 2
items:
- description: Address and length of PHY's common serdes block.
- description: Address and length of PHY's DP_COM control block.
@@ -301,8 +302,33 @@
compatible:
contains:
enum:
+ - qcom,ipq6018-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
+ - qcom,sdx55-qmp-pcie-phy
- qcom,sm8250-qmp-gen3x1-pcie-phy
- qcom,sm8250-qmp-gen3x2-pcie-phy
- qcom,sm8250-qmp-modem-pcie-phy
diff --git a/Bindings/phy/qcom,qusb2-phy.yaml b/Bindings/phy/qcom,qusb2-phy.yaml
index 9f9cf07..ec9ccaa 100644
--- a/Bindings/phy/qcom,qusb2-phy.yaml
+++ b/Bindings/phy/qcom,qusb2-phy.yaml
@@ -23,6 +23,8 @@
- qcom,msm8998-qusb2-phy
- qcom,sdm660-qusb2-phy
- qcom,ipq6018-qusb2-phy
+ - qcom,sm4250-qusb2-phy
+ - qcom,sm6115-qusb2-phy
- items:
- enum:
- qcom,sc7180-qusb2-phy
@@ -36,7 +38,6 @@
clocks:
minItems: 2
- maxItems: 3
items:
- description: phy config clock
- description: 19.2 MHz ref clk
@@ -44,7 +45,6 @@
clock-names:
minItems: 2
- maxItems: 3
items:
- const: cfg_ahb
- const: ref
diff --git a/Bindings/phy/rcar-gen3-phy-pcie.txt b/Bindings/phy/rcar-gen3-phy-pcie.txt
deleted file mode 100644
index 63853b3..0000000
--- a/Bindings/phy/rcar-gen3-phy-pcie.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* Renesas R-Car generation 3 PCIe PHY
-
-This file provides information on what the device node for the R-Car
-generation 3 PCIe PHY contains.
-
-Required properties:
-- compatible: "renesas,r8a77980-pcie-phy" if the device is a part of the
- R8A77980 SoC.
-- reg: offset and length of the register block.
-- clocks: clock phandle and specifier pair.
-- power-domains: power domain phandle and specifier pair.
-- resets: reset phandle and specifier pair.
-- #phy-cells: see phy-bindings.txt in the same directory, must be <0>.
-
-Example (R-Car V3H):
-
- pcie-phy@e65d0000 {
- compatible = "renesas,r8a77980-pcie-phy";
- reg = <0 0xe65d0000 0 0x8000>;
- #phy-cells = <0>;
- clocks = <&cpg CPG_MOD 319>;
- power-domains = <&sysc 32>;
- resets = <&cpg 319>;
- };
diff --git a/Bindings/phy/renesas,rcar-gen3-pcie-phy.yaml b/Bindings/phy/renesas,rcar-gen3-pcie-phy.yaml
new file mode 100644
index 0000000..247ef7c
--- /dev/null
+++ b/Bindings/phy/renesas,rcar-gen3-pcie-phy.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/renesas,rcar-gen3-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car Generation 3 PCIe PHY
+
+maintainers:
+ - Sergei Shtylyov <sergei.shtylyov@gmail.com>
+
+properties:
+ compatible:
+ const: renesas,r8a77980-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ '#phy-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - power-domains
+ - resets
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
+ #include <dt-bindings/power/r8a77980-sysc.h>
+
+ pcie-phy@e65d0000 {
+ compatible = "renesas,r8a77980-pcie-phy";
+ reg = <0xe65d0000 0x8000>;
+ #phy-cells = <0>;
+ clocks = <&cpg CPG_MOD 319>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ };
diff --git a/Bindings/phy/renesas,usb2-phy.yaml b/Bindings/phy/renesas,usb2-phy.yaml
index 0f358d5..d5dc5a3 100644
--- a/Bindings/phy/renesas,usb2-phy.yaml
+++ b/Bindings/phy/renesas,usb2-phy.yaml
@@ -39,7 +39,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: fck
- const: usb_x1
@@ -61,7 +60,6 @@
resets:
minItems: 1
- maxItems: 2
items:
- description: reset of USB 2.0 host side
- description: reset of USB 2.0 peripheral side
diff --git a/Bindings/phy/renesas,usb3-phy.yaml b/Bindings/phy/renesas,usb3-phy.yaml
index f3ef738..b8483f9 100644
--- a/Bindings/phy/renesas,usb3-phy.yaml
+++ b/Bindings/phy/renesas,usb3-phy.yaml
@@ -33,7 +33,6 @@
# If you want to use the ssc, the clock-frequency of usb_extal
# must not be 0.
minItems: 2
- maxItems: 3
items:
- const: usb3-if # The funcional clock
- const: usb3s_clk # The usb3's external clock
diff --git a/Bindings/phy/rockchip-inno-csi-dphy.yaml b/Bindings/phy/rockchip-inno-csi-dphy.yaml
new file mode 100644
index 0000000..bb4a2e4
--- /dev/null
+++ b/Bindings/phy/rockchip-inno-csi-dphy.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
+ connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-csi-dphy
+ - rockchip,rk1808-csi-dphy
+ - rockchip,rk3326-csi-dphy
+ - rockchip,rk3368-csi-dphy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: pclk
+
+ '#phy-cells':
+ const: 0
+
+ power-domains:
+ description: Video in/out power domain.
+ maxItems: 1
+
+ resets:
+ items:
+ - description: exclusive PHY reset line
+
+ reset-names:
+ items:
+ - const: apb
+
+ rockchip,grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Some additional phy settings are access through GRF regs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#phy-cells'
+ - power-domains
+ - resets
+ - reset-names
+ - rockchip,grf
+
+additionalProperties: false
+
+examples:
+ - |
+
+ csi_dphy: phy@ff2f0000 {
+ compatible = "rockchip,px30-csi-dphy";
+ reg = <0xff2f0000 0x4000>;
+ clocks = <&cru 1>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ power-domains = <&power 1>;
+ resets = <&cru 1>;
+ reset-names = "apb";
+ rockchip,grf = <&grf>;
+ };
diff --git a/Bindings/phy/rockchip-usb-phy.txt b/Bindings/phy/rockchip-usb-phy.txt
deleted file mode 100644
index 4ed5690..0000000
--- a/Bindings/phy/rockchip-usb-phy.txt
+++ /dev/null
@@ -1,52 +0,0 @@
-ROCKCHIP USB2 PHY
-
-Required properties:
- - compatible: matching the soc type, one of
- "rockchip,rk3066a-usb-phy"
- "rockchip,rk3188-usb-phy"
- "rockchip,rk3288-usb-phy"
- - #address-cells: should be 1
- - #size-cells: should be 0
-
-Deprecated properties:
- - rockchip,grf : phandle to the syscon managing the "general
- register files" - phy should be a child of the GRF instead
-
-Sub-nodes:
-Each PHY should be represented as a sub-node.
-
-Sub-nodes
-required properties:
-- #phy-cells: should be 0
-- reg: PHY configure reg address offset in GRF
- "0x320" - for PHY attach to OTG controller
- "0x334" - for PHY attach to HOST0 controller
- "0x348" - for PHY attach to HOST1 controller
-
-Optional Properties:
-- clocks : phandle + clock specifier for the phy clocks
-- clock-names: string, clock name, must be "phyclk"
-- #clock-cells: for users of the phy-pll, should be 0
-- reset-names: Only allow the following entries:
- - phy-reset
-- resets: Must contain an entry for each entry in reset-names.
-- vbus-supply: power-supply phandle for vbus power source
-
-Example:
-
-grf: syscon@ff770000 {
- compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
-
-...
-
- usbphy: phy {
- compatible = "rockchip,rk3288-usb-phy";
- #address-cells = <1>;
- #size-cells = <0>;
-
- usbphy0: usb-phy0 {
- #phy-cells = <0>;
- reg = <0x320>;
- };
- };
-};
diff --git a/Bindings/phy/rockchip-usb-phy.yaml b/Bindings/phy/rockchip-usb-phy.yaml
new file mode 100644
index 0000000..f0fc827
--- /dev/null
+++ b/Bindings/phy/rockchip-usb-phy.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip USB2.0 phy
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: rockchip,rk3288-usb-phy
+ - items:
+ - enum:
+ - rockchip,rk3066a-usb-phy
+ - rockchip,rk3188-usb-phy
+ - const: rockchip,rk3288-usb-phy
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "usb-phy@[0-9a-f]+$":
+ type: object
+
+ properties:
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: phyclk
+
+ "#clock-cells":
+ const: 0
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: phy-reset
+
+ vbus-supply:
+ description: phandle for vbus power source
+
+ required:
+ - reg
+ - "#phy-cells"
+
+ additionalProperties: false
+
+examples:
+ - |
+ usbphy: usbphy {
+ compatible = "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usbphy0: usb-phy@320 {
+ reg = <0x320>;
+ #phy-cells = <0>;
+ };
+ };
diff --git a/Bindings/phy/ti,tcan104x-can.yaml b/Bindings/phy/ti,tcan104x-can.yaml
new file mode 100644
index 0000000..6107880
--- /dev/null
+++ b/Bindings/phy/ti,tcan104x-can.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/ti,tcan104x-can.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: TCAN104x CAN TRANSCEIVER PHY
+
+maintainers:
+ - Aswath Govindraju <a-govindraju@ti.com>
+
+properties:
+ $nodename:
+ pattern: "^can-phy"
+
+ compatible:
+ enum:
+ - ti,tcan1042
+ - ti,tcan1043
+
+ '#phy-cells':
+ const: 0
+
+ standby-gpios:
+ description:
+ gpio node to toggle standby signal on transceiver
+ maxItems: 1
+
+ enable-gpios:
+ description:
+ gpio node to toggle enable signal on transceiver
+ maxItems: 1
+
+ max-bitrate:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ max bit rate supported in bps
+ minimum: 1
+
+required:
+ - compatible
+ - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ transceiver1: can-phy {
+ compatible = "ti,tcan1043";
+ #phy-cells = <0>;
+ max-bitrate = <5000000>;
+ standby-gpios = <&wakeup_gpio1 16 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&main_gpio1 67 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/Bindings/pinctrl/actions,s500-pinctrl.yaml b/Bindings/pinctrl/actions,s500-pinctrl.yaml
index ccdd9e3..3f94f69 100644
--- a/Bindings/pinctrl/actions,s500-pinctrl.yaml
+++ b/Bindings/pinctrl/actions,s500-pinctrl.yaml
@@ -26,7 +26,6 @@
- description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
- description: PAD Drive Capacity Select
minItems: 1
- maxItems: 4
clocks:
maxItems: 1
diff --git a/Bindings/pinctrl/apple,pinctrl.yaml b/Bindings/pinctrl/apple,pinctrl.yaml
new file mode 100644
index 0000000..d50571a
--- /dev/null
+++ b/Bindings/pinctrl/apple,pinctrl.yaml
@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple GPIO controller
+
+maintainers:
+ - Mark Kettenis <kettenis@openbsd.org>
+
+description: |
+ The Apple GPIO controller is a simple combined pin and GPIO
+ controller present on Apple ARM SoC platforms, including various
+ iPhone and iPad devices and the "Apple Silicon" Macs.
+
+properties:
+ compatible:
+ items:
+ - const: apple,t8103-pinctrl
+ - const: apple,pinctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupts:
+ description: One interrupt for each of the (up to 7) interrupt
+ groups supported by the controller sorted by interrupt group
+ number in ascending order.
+ minItems: 1
+ maxItems: 7
+
+ interrupt-controller: true
+
+patternProperties:
+ '-pins$':
+ type: object
+ $ref: pinmux-node.yaml#
+
+ properties:
+ pinmux:
+ description:
+ Values are constructed from pin number and alternate function
+ configuration number using the APPLE_PINMUX() helper macro
+ defined in include/dt-bindings/pinctrl/apple.h.
+
+ required:
+ - pinmux
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/apple-aic.h>
+ #include <dt-bindings/pinctrl/apple.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pinctrl: pinctrl@23c100000 {
+ compatible = "apple,t8103-pinctrl", "apple,pinctrl";
+ reg = <0x2 0x3c100000 0x0 0x100000>;
+ clocks = <&gpio_clk>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 212>;
+
+ interrupt-controller;
+ interrupt-parent = <&aic>;
+ interrupts = <AIC_IRQ 16 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 17 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 18 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 19 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 20 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 21 IRQ_TYPE_LEVEL_HIGH>,
+ <AIC_IRQ 22 IRQ_TYPE_LEVEL_HIGH>;
+
+ pcie_pins: pcie-pins {
+ pinmux = <APPLE_PINMUX(150, 1)>,
+ <APPLE_PINMUX(151, 1)>,
+ <APPLE_PINMUX(32, 1)>;
+ };
+ };
+ };
diff --git a/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
index ad91c0b..ad2866c 100644
--- a/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
+++ b/Bindings/pinctrl/aspeed,ast2600-pinctrl.yaml
@@ -46,8 +46,8 @@
PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4,
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14,
SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8,
- SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ,
- SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
+ SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO,
+ SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2,
SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14,
TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0,
THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12,
@@ -74,9 +74,9 @@
RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1,
SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0,
SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6,
- SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL,
- SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR,
- SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
+ SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2,
+ SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1,
+ SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11,
TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6,
TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3,
TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6,
diff --git a/Bindings/pinctrl/brcm,bcm4708-pinmux.txt b/Bindings/pinctrl/brcm,bcm4708-pinmux.txt
deleted file mode 100644
index 8ab2d46..0000000
--- a/Bindings/pinctrl/brcm,bcm4708-pinmux.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Broadcom Northstar pins mux controller
-
-Some of Northstar SoCs's pins can be used for various purposes thanks to the mux
-controller. This binding allows describing mux controller and listing available
-functions. They can be referenced later by other bindings to let system
-configure controller correctly.
-
-A list of pins varies across chipsets so few bindings are available.
-
-Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
-noce.
-
-Required properties:
-- compatible: must be one of:
- "brcm,bcm4708-pinmux"
- "brcm,bcm4709-pinmux"
- "brcm,bcm53012-pinmux"
-- offset: offset of pin registers in the CRU block
-
-Functions and their groups available for all chipsets:
-- "spi": "spi_grp"
-- "i2c": "i2c_grp"
-- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
-- "uart1": "uart1_grp"
-
-Additionally available on BCM4709 and BCM53012:
-- "mdio": "mdio_grp"
-- "uart2": "uart2_grp"
-- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
-
-For documentation of subnodes see:
-Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
-
-Example:
- dmu@1800c000 {
- compatible = "simple-bus";
- ranges = <0 0x1800c000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- cru@100 {
- compatible = "syscon", "simple-mfd";
- reg = <0x100 0x1a4>;
-
- pinctrl {
- compatible = "brcm,bcm4708-pinmux";
- offset = <0xc0>;
-
- spi-pins {
- function = "spi";
- groups = "spi_grp";
- };
- };
- };
- };
diff --git a/Bindings/pinctrl/brcm,ns-pinmux.yaml b/Bindings/pinctrl/brcm,ns-pinmux.yaml
new file mode 100644
index 0000000..470aff5
--- /dev/null
+++ b/Bindings/pinctrl/brcm,ns-pinmux.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Northstar pins mux controller
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+description:
+ Some of Northstar SoCs's pins can be used for various purposes thanks to the
+ mux controller. This binding allows describing mux controller and listing
+ available functions. They can be referenced later by other bindings to let
+ system configure controller correctly.
+
+ A list of pins varies across chipsets so few bindings are available.
+
+ Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
+ node.
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm4708-pinmux
+ - brcm,bcm4709-pinmux
+ - brcm,bcm53012-pinmux
+
+ offset:
+ description: offset of pin registers in the CRU block
+ maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+patternProperties:
+ '-pins$':
+ type: object
+ description: pin node
+ $ref: pinmux-node.yaml#
+
+ properties:
+ function:
+ enum: [ spi, i2c, pwm, uart1, mdio, uart2, sdio ]
+ groups:
+ minItems: 1
+ maxItems: 4
+ items:
+ enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp,
+ uart1_grp, mdio_grp, uart2_grp, sdio_pwr_grp, sdio_1p8v_grp ]
+
+ required:
+ - function
+ - groups
+
+ additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: brcm,bcm4708-pinmux
+ then:
+ patternProperties:
+ '-pins$':
+ properties:
+ function:
+ enum: [ spi, i2c, pwm, uart1 ]
+ groups:
+ items:
+ enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp,
+ uart1_grp ]
+
+required:
+ - offset
+
+additionalProperties: false
+
+examples:
+ - |
+ cru@1800c100 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1800c100 0x1a4>;
+
+ pinctrl {
+ compatible = "brcm,bcm4708-pinmux";
+ offset = <0xc0>;
+
+ spi-pins {
+ function = "spi";
+ groups = "spi_grp";
+ };
+ };
+ };
diff --git a/Bindings/pinctrl/pinctrl-mcp23s08.txt b/Bindings/pinctrl/pinctrl-mcp23s08.txt
index 6ec3c8d..2fa5eda 100644
--- a/Bindings/pinctrl/pinctrl-mcp23s08.txt
+++ b/Bindings/pinctrl/pinctrl-mcp23s08.txt
@@ -49,6 +49,7 @@
- interrupt-controller: Marks the device node as a interrupt controller.
- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
the IRQ output as open drain active low.
+- reset-gpios: Corresponds to the active-low RESET# pin for the chip
Optional device specific properties:
- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
@@ -135,6 +136,7 @@
microchip,irq-mirror;
pinctrl-names = "default";
pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>;
+ reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
gpio21pullups: pinmux {
pins = "gpio0", "gpio1", "gpio2", "gpio3",
diff --git a/Bindings/pinctrl/pinctrl-mt65xx.txt b/Bindings/pinctrl/pinctrl-mt65xx.txt
index 360e59c..5fe2c26 100644
--- a/Bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Bindings/pinctrl/pinctrl-mt65xx.txt
@@ -12,6 +12,7 @@
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
+ "mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl.
"mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
- pins-are-numbered: Specify the subnodes are using numbered pinmux to
specify pins.
diff --git a/Bindings/pinctrl/qcom,pmic-gpio.txt b/Bindings/pinctrl/qcom,pmic-gpio.txt
index f6a9760..161216d 100644
--- a/Bindings/pinctrl/qcom,pmic-gpio.txt
+++ b/Bindings/pinctrl/qcom,pmic-gpio.txt
@@ -31,6 +31,7 @@
"qcom,pm8350b-gpio"
"qcom,pm8350c-gpio"
"qcom,pmk8350-gpio"
+ "qcom,pm7325-gpio"
"qcom,pmr735a-gpio"
"qcom,pmr735b-gpio"
"qcom,pm6150-gpio"
@@ -120,6 +121,7 @@
gpio1-gpio8 for pm8350b
gpio1-gpio9 for pm8350c
gpio1-gpio4 for pmk8350
+ gpio1-gpio10 for pm7325
gpio1-gpio4 for pmr735a
gpio1-gpio4 for pmr735b
gpio1-gpio10 for pm6150
diff --git a/Bindings/pinctrl/qcom,pmic-mpp.txt b/Bindings/pinctrl/qcom,pmic-mpp.txt
index 0ba07bc..5363d44 100644
--- a/Bindings/pinctrl/qcom,pmic-mpp.txt
+++ b/Bindings/pinctrl/qcom,pmic-mpp.txt
@@ -21,6 +21,7 @@
"qcom,pmi8950-mpp",
"qcom,pm8994-mpp",
"qcom,pma8084-mpp",
+ "qcom,pmi8994-mpp",
And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp"
if the device is on an spmi bus or an ssbi bus respectively.
diff --git a/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml b/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml
new file mode 100644
index 0000000..5f7adaa
--- /dev/null
+++ b/Bindings/pinctrl/qcom,sm6125-pinctrl.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+title: Qualcomm Technologies, Inc. SM6125 TLMM block
+
+maintainers:
+ - Martin Botka <martin.botka@somainline.org>
+
+description: |
+ This binding describes the Top Level Mode Multiplexer (TLMM) block found
+ in the SM6125 platform.
+
+allOf:
+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+ compatible:
+ const: qcom,sm6125-tlmm
+
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: "west"
+ - const: "south"
+ - const: "east"
+
+ interrupts: true
+ interrupt-controller: true
+ '#interrupt-cells': true
+ gpio-controller: true
+ gpio-reserved-ranges: true
+ '#gpio-cells': true
+ gpio-ranges: true
+ wakeup-parent: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+additionalProperties: false
+
+patternProperties:
+ '-state$':
+ oneOf:
+ - $ref: "#/$defs/qcom-sm6125-tlmm-state"
+ - patternProperties:
+ ".*":
+ $ref: "#/$defs/qcom-sm6125-tlmm-state"
+
+$defs:
+ qcom-sm6125-tlmm-state:
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for desired pin configuration.
+ Client device subnodes use below standard properties.
+ $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
+
+ properties:
+ pins:
+ description:
+ List of gpio pins affected by the properties specified in this
+ subnode.
+ items:
+ oneOf:
+ - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$"
+ - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
+ minItems: 1
+ maxItems: 36
+
+ function:
+ description:
+ Specify the alternative function to be configured for the specified
+ pins.
+
+ enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1,
+ atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1,
+ atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2,
+ atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb,
+ audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1,
+ cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng,
+ cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
+ ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk,
+ dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
+ gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en,
+ ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1,
+ mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte,
+ nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset,
+ pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable,
+ qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04,
+ qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx,
+ swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm,
+ uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
+ uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger,
+ wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ]
+
+
+ bias-disable: true
+ bias-pull-down: true
+ bias-pull-up: true
+ drive-strength: true
+ input-enable: true
+ output-high: true
+ output-low: true
+
+ required:
+ - pins
+ - function
+
+ additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ pinctrl@500000 {
+ compatible = "qcom,sm6125-tlmm";
+ reg = <0x00500000 0x400000>,
+ <0x00900000 0x400000>,
+ <0x00d00000 0x400000>;
+ reg-names = "west", "south", "east";
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ gpio-ranges = <&tlmm 0 0 134>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
diff --git a/Bindings/power/amlogic,meson-ee-pwrc.yaml b/Bindings/power/amlogic,meson-ee-pwrc.yaml
index d30f85c..f005aba 100644
--- a/Bindings/power/amlogic,meson-ee-pwrc.yaml
+++ b/Bindings/power/amlogic,meson-ee-pwrc.yaml
@@ -37,7 +37,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: vpu
- const: vapb
diff --git a/Bindings/power/fsl,imx-gpcv2.yaml b/Bindings/power/fsl,imx-gpcv2.yaml
index a96e6db..01bdda1 100644
--- a/Bindings/power/fsl,imx-gpcv2.yaml
+++ b/Bindings/power/fsl,imx-gpcv2.yaml
@@ -25,7 +25,9 @@
compatible:
enum:
- fsl,imx7d-gpc
+ - fsl,imx8mn-gpc
- fsl,imx8mq-gpc
+ - fsl,imx8mm-gpc
reg:
maxItems: 1
@@ -54,6 +56,7 @@
Power domain index. Valid values are defined in
include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
+ include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
maxItems: 1
clocks:
@@ -66,6 +69,16 @@
power-supply: true
+ resets:
+ description: |
+ A number of phandles to resets that need to be asserted during
+ power-up sequencing of the domain. The resets belong to devices
+ located inside the power domain, which need to be held in reset
+ across the power-up sequence. So no means to specify what each
+ reset is in a generic power-domain binding.
+ minItems: 1
+ maxItems: 4
+
required:
- '#power-domain-cells'
- reg
diff --git a/Bindings/power/qcom,rpmpd.yaml b/Bindings/power/qcom,rpmpd.yaml
index ff21bfe..4807b56 100644
--- a/Bindings/power/qcom,rpmpd.yaml
+++ b/Bindings/power/qcom,rpmpd.yaml
@@ -16,6 +16,7 @@
properties:
compatible:
enum:
+ - qcom,mdm9607-rpmpd
- qcom,msm8916-rpmpd
- qcom,msm8939-rpmpd
- qcom,msm8976-rpmpd
@@ -26,6 +27,7 @@
- qcom,sdm660-rpmpd
- qcom,sc7180-rpmhpd
- qcom,sc7280-rpmhpd
+ - qcom,sc8180x-rpmhpd
- qcom,sdm845-rpmhpd
- qcom,sdx55-rpmhpd
- qcom,sm8150-rpmhpd
diff --git a/Bindings/power/renesas,rzg2l-sysc.yaml b/Bindings/power/renesas,rzg2l-sysc.yaml
new file mode 100644
index 0000000..84ddc77
--- /dev/null
+++ b/Bindings/power/renesas,rzg2l-sysc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas RZ/G2L System Controller (SYSC)
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The RZ/G2L System Controller (SYSC) performs system control of the LSI and
+ supports following functions,
+ - External terminal state capture function
+ - 34-bit address space access function
+ - Low power consumption control
+ - WDT stop control
+
+properties:
+ compatible:
+ enum:
+ - renesas,r9a07g044-sysc # RZ/G2{L,LC}
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: CA55/CM33 Sleep/Software Standby Mode request interrupt
+ - description: CA55 Software Standby Mode release request interrupt
+ - description: CM33 Software Standby Mode release request interrupt
+ - description: CA55 ACE Asynchronous Bridge Master/Slave interface deny request interrupt
+
+ interrupt-names:
+ items:
+ - const: lpm_int
+ - const: ca55stbydone_int
+ - const: cm33stbyr_int
+ - const: ca55_deny
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0x11020000 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int",
+ "ca55_deny";
+ };
diff --git a/Bindings/power/renesas,sysc-rmobile.txt b/Bindings/power/renesas,sysc-rmobile.txt
deleted file mode 100644
index 49aba15..0000000
--- a/Bindings/power/renesas,sysc-rmobile.txt
+++ /dev/null
@@ -1,100 +0,0 @@
-DT bindings for the Renesas R-Mobile System Controller
-
-== System Controller Node ==
-
-The R-Mobile System Controller provides the following functions:
- - Boot mode management,
- - Reset generation,
- - Power management.
-
-Required properties:
-- compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as
- fallback.
- Examples with soctypes are:
- - "renesas,sysc-r8a73a4" (R-Mobile APE6)
- - "renesas,sysc-r8a7740" (R-Mobile A1)
- - "renesas,sysc-sh73a0" (SH-Mobile AG5)
-- reg: Two address start and address range blocks for the device:
- - The first block refers to the normally accessible registers,
- - the second block refers to the registers protected by the HPB
- semaphore.
-
-Optional nodes:
-- pm-domains: This node contains a hierarchy of PM domain nodes, which should
- match the Power Area Hierarchy in the Power Domain Specifications section of
- the device's datasheet.
-
-
-== PM Domain Nodes ==
-
-Each of the PM domain nodes represents a PM domain, as documented by the
-generic PM domain bindings in
-Documentation/devicetree/bindings/power/power-domain.yaml.
-
-The nodes should be named by the real power area names, and thus their names
-should be unique.
-
-Required properties:
- - #power-domain-cells: Must be 0.
-
-Optional properties:
-- reg: If the PM domain is not always-on, this property must contain the bit
- index number for the corresponding power area in the various Power
- Control and Status Registers. The parent's node must contain the
- following two properties:
- - #address-cells: Must be 1,
- - #size-cells: Must be 0.
- If the PM domain is always-on, this property must be omitted.
-
-
-Example:
-
-This shows a subset of the r8a7740 PM domain hierarchy, containing the
-C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain,
-which is a subdomain of A4S.
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
- reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
-
- pm-domains {
- pd_c5: c5 {
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- pd_a4s: a4s@10 {
- reg = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- pd_a3sp: a3sp@11 {
- reg = <11>;
- #power-domain-cells = <0>;
- };
- };
-
- pd_a4su: a4su@20 {
- reg = <20>;
- #power-domain-cells = <0>;
- };
- };
- };
- };
-
-
-== PM Domain Consumers ==
-
-Hardware blocks belonging to a PM domain should contain a "power-domains"
-property that is a phandle pointing to the corresponding PM domain node.
-
-Example:
-
- tpu: pwm@e6600000 {
- compatible = "renesas,tpu-r8a7740", "renesas,tpu";
- reg = <0xe6600000 0x100>;
- clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
- power-domains = <&pd_a3sp>;
- #pwm-cells = <3>;
- };
diff --git a/Bindings/power/renesas,sysc-rmobile.yaml b/Bindings/power/renesas,sysc-rmobile.yaml
new file mode 100644
index 0000000..5597189
--- /dev/null
+++ b/Bindings/power/renesas,sysc-rmobile.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/renesas,sysc-rmobile.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Mobile System Controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ The R-Mobile System Controller provides the following functions:
+ - Boot mode management,
+ - Reset generation,
+ - Power management.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,sysc-r8a73a4 # R-Mobile APE6
+ - renesas,sysc-r8a7740 # R-Mobile A1
+ - renesas,sysc-sh73a0 # SH-Mobile AG5
+ - const: renesas,sysc-rmobile # Generic SH/R-Mobile
+
+ reg:
+ items:
+ - description: Normally accessible register block
+ - description: Register block protected by the HPB semaphore
+
+ pm-domains:
+ type: object
+ description: |
+ This node contains a hierarchy of PM domain nodes, which should match the
+ Power Area Hierarchy in the Power Domain Specifications section of the
+ device's datasheet.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ additionalProperties:
+ $ref: "#/$defs/pd-node"
+
+required:
+ - compatible
+ - reg
+ - pm-domains
+
+additionalProperties: false
+
+$defs:
+ pd-node:
+ type: object
+ description:
+ PM domain node representing a PM domain. This node hould be named by
+ the real power area name, and thus its name should be unique.
+
+ properties:
+ reg:
+ maxItems: 1
+ description:
+ If the PM domain is not always-on, this property must contain the
+ bit index number for the corresponding power area in the various
+ Power Control and Status Registers.
+ If the PM domain is always-on, this property must be omitted.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#power-domain-cells':
+ const: 0
+
+ required:
+ - '#power-domain-cells'
+
+ additionalProperties:
+ $ref: "#/$defs/pd-node"
+
+examples:
+ - |
+ // This shows a subset of the r8a7740 PM domain hierarchy, containing the
+ // C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP
+ // domain, which is a subdomain of A4S.
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
+ reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
+
+ pm-domains {
+ pd_c5: c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_a4s: a4s@10 {
+ reg = <10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_a3sp: a3sp@11 {
+ reg = <11>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ pd_a4su: a4su@20 {
+ reg = <20>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/power/rockchip,power-controller.yaml b/Bindings/power/rockchip,power-controller.yaml
new file mode 100644
index 0000000..9b9d710
--- /dev/null
+++ b/Bindings/power/rockchip,power-controller.yaml
@@ -0,0 +1,248 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip Power Domains
+
+maintainers:
+ - Elaine Zhang <zhangqing@rock-chips.com>
+ - Heiko Stuebner <heiko@sntech.de>
+
+description: |
+ Rockchip processors include support for multiple power domains
+ which can be powered up/down by software based on different
+ application scenarios to save power.
+
+ Power domains contained within power-controller node are
+ generic power domain providers documented in
+ Documentation/devicetree/bindings/power/power-domain.yaml.
+
+ IP cores belonging to a power domain should contain a
+ "power-domains" property that is a phandle for the
+ power domain node representing the domain.
+
+properties:
+ $nodename:
+ const: power-controller
+
+ compatible:
+ enum:
+ - rockchip,px30-power-controller
+ - rockchip,rk3036-power-controller
+ - rockchip,rk3066-power-controller
+ - rockchip,rk3128-power-controller
+ - rockchip,rk3188-power-controller
+ - rockchip,rk3228-power-controller
+ - rockchip,rk3288-power-controller
+ - rockchip,rk3328-power-controller
+ - rockchip,rk3366-power-controller
+ - rockchip,rk3368-power-controller
+ - rockchip,rk3399-power-controller
+ - rockchip,rk3568-power-controller
+
+ "#power-domain-cells":
+ const: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - "#power-domain-cells"
+
+additionalProperties: false
+
+patternProperties:
+ "^power-domain@[0-9a-f]+$":
+
+ $ref: "#/$defs/pd-node"
+
+ unevaluatedProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+
+ $ref: "#/$defs/pd-node"
+
+ unevaluatedProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+
+ $ref: "#/$defs/pd-node"
+
+ unevaluatedProperties: false
+
+ properties:
+ "#power-domain-cells":
+ const: 0
+
+$defs:
+ pd-node:
+ type: object
+ description: |
+ Represents the power domains within the power controller node.
+
+ properties:
+ reg:
+ maxItems: 1
+ description: |
+ Power domain index. Valid values are defined in
+ "include/dt-bindings/power/px30-power.h"
+ "include/dt-bindings/power/rk3036-power.h"
+ "include/dt-bindings/power/rk3066-power.h"
+ "include/dt-bindings/power/rk3128-power.h"
+ "include/dt-bindings/power/rk3188-power.h"
+ "include/dt-bindings/power/rk3228-power.h"
+ "include/dt-bindings/power/rk3288-power.h"
+ "include/dt-bindings/power/rk3328-power.h"
+ "include/dt-bindings/power/rk3366-power.h"
+ "include/dt-bindings/power/rk3368-power.h"
+ "include/dt-bindings/power/rk3399-power.h"
+ "include/dt-bindings/power/rk3568-power.h"
+
+ clocks:
+ minItems: 1
+ maxItems: 30
+ description: |
+ A number of phandles to clocks that need to be enabled
+ while power domain switches state.
+
+ pm_qos:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ A number of phandles to qos blocks which need to be saved and restored
+ while power domain switches state.
+
+ "#power-domain-cells":
+ enum: [0, 1]
+ description:
+ Must be 0 for nodes representing a single PM domain and 1 for nodes
+ providing multiple PM domains.
+
+ required:
+ - reg
+ - "#power-domain-cells"
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/power/rk3399-power.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ qos_hdcp: qos@ffa90000 {
+ compatible = "rockchip,rk3399-qos", "syscon";
+ reg = <0x0 0xffa90000 0x0 0x20>;
+ };
+
+ qos_iep: qos@ffa98000 {
+ compatible = "rockchip,rk3399-qos", "syscon";
+ reg = <0x0 0xffa98000 0x0 0x20>;
+ };
+
+ qos_rga_r: qos@ffab0000 {
+ compatible = "rockchip,rk3399-qos", "syscon";
+ reg = <0x0 0xffab0000 0x0 0x20>;
+ };
+
+ qos_rga_w: qos@ffab0080 {
+ compatible = "rockchip,rk3399-qos", "syscon";
+ reg = <0x0 0xffab0080 0x0 0x20>;
+ };
+
+ qos_video_m0: qos@ffab8000 {
+ compatible = "rockchip,rk3399-qos", "syscon";
+ reg = <0x0 0xffab8000 0x0 0x20>;
+ };
+
+ qos_video_m1_r: qos@ffac0000 {
+ compatible = "rockchip,rk3399-qos", "syscon";
+ reg = <0x0 0xffac0000 0x0 0x20>;
+ };
+
+ qos_video_m1_w: qos@ffac0080 {
+ compatible = "rockchip,rk3399-qos", "syscon";
+ reg = <0x0 0xffac0080 0x0 0x20>;
+ };
+
+ power-management@ff310000 {
+ compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff310000 0x0 0x1000>;
+
+ power-controller {
+ compatible = "rockchip,rk3399-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* These power domains are grouped by VD_CENTER */
+ power-domain@RK3399_PD_IEP {
+ reg = <RK3399_PD_IEP>;
+ clocks = <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>;
+ pm_qos = <&qos_iep>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3399_PD_RGA {
+ reg = <RK3399_PD_RGA>;
+ clocks = <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>;
+ pm_qos = <&qos_rga_r>,
+ <&qos_rga_w>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3399_PD_VCODEC {
+ reg = <RK3399_PD_VCODEC>;
+ clocks = <&cru ACLK_VCODEC>,
+ <&cru HCLK_VCODEC>;
+ pm_qos = <&qos_video_m0>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3399_PD_VDU {
+ reg = <RK3399_PD_VDU>;
+ clocks = <&cru ACLK_VDU>,
+ <&cru HCLK_VDU>;
+ pm_qos = <&qos_video_m1_r>,
+ <&qos_video_m1_w>;
+ #power-domain-cells = <0>;
+ };
+ power-domain@RK3399_PD_VIO {
+ reg = <RK3399_PD_VIO>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3399_PD_HDCP {
+ reg = <RK3399_PD_HDCP>;
+ clocks = <&cru ACLK_HDCP>,
+ <&cru HCLK_HDCP>,
+ <&cru PCLK_HDCP>;
+ pm_qos = <&qos_hdcp>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/power/supply/charger-manager.txt b/Bindings/power/supply/charger-manager.txt
deleted file mode 100644
index b5ae906..0000000
--- a/Bindings/power/supply/charger-manager.txt
+++ /dev/null
@@ -1,91 +0,0 @@
-charger-manager bindings
-~~~~~~~~~~~~~~~~~~~~~~~~
-
-Required properties :
- - compatible : "charger-manager"
- - <>-supply : for regulator consumer, named according to cm-regulator-name
- - cm-chargers : name of chargers
- - cm-fuel-gauge : name of battery fuel gauge
- - subnode <regulator> :
- - cm-regulator-name : name of charger regulator
- - subnode <cable> :
- - cm-cable-name : name of charger cable - one of USB, USB-HOST,
- SDP, DCP, CDP, ACA, FAST-CHARGER, SLOW-CHARGER, WPT,
- PD, DOCK, JIG, or MECHANICAL
- - cm-cable-extcon : name of extcon dev
-(optional) - cm-cable-min : minimum current of cable
-(optional) - cm-cable-max : maximum current of cable
-
-Optional properties :
- - cm-name : charger manager's name (default : "battery")
- - cm-poll-mode : polling mode - 0 for disabled, 1 for always, 2 for when
- external power is connected, or 3 for when charging. If not present,
- then polling is disabled
- - cm-poll-interval : polling interval (in ms)
- - cm-battery-stat : battery status - 0 for battery always present, 1 for no
- battery, 2 to check presence via fuel gauge, or 3 to check presence
- via charger
- - cm-fullbatt-vchkdrop-volt : voltage drop (in uV) before restarting charging
- - cm-fullbatt-voltage : voltage (in uV) of full battery
- - cm-fullbatt-soc : state of charge to consider as full battery
- - cm-fullbatt-capacity : capcity (in uAh) to consider as full battery
- - cm-thermal-zone : name of external thermometer's thermal zone
- - cm-battery-* : threshold battery temperature for charging
- -cold : critical cold temperature of battery for charging
- -cold-in-minus : flag that cold temperature is in minus degrees
- -hot : critical hot temperature of battery for charging
- -temp-diff : temperature difference to allow recharging
- - cm-dis/charging-max = limits of charging duration
-
-Deprecated properties:
- - cm-num-chargers
- - cm-fullbatt-vchkdrop-ms
-
-Example :
- charger-manager@0 {
- compatible = "charger-manager";
- chg-reg-supply = <&charger_regulator>;
-
- cm-name = "battery";
- /* Always polling ON : 30s */
- cm-poll-mode = <1>;
- cm-poll-interval = <30000>;
-
- cm-fullbatt-vchkdrop-volt = <150000>;
- cm-fullbatt-soc = <100>;
-
- cm-battery-stat = <3>;
-
- cm-chargers = "charger0", "charger1", "charger2";
-
- cm-fuel-gauge = "fuelgauge0";
-
- cm-thermal-zone = "thermal_zone.1"
- /* in deci centigrade */
- cm-battery-cold = <50>;
- cm-battery-cold-in-minus;
- cm-battery-hot = <800>;
- cm-battery-temp-diff = <100>;
-
- /* Allow charging for 5hr */
- cm-charging-max = <18000000>;
- /* Allow discharging for 2hr */
- cm-discharging-max = <7200000>;
-
- regulator@0 {
- cm-regulator-name = "chg-reg";
- cable@0 {
- cm-cable-name = "USB";
- cm-cable-extcon = "extcon-dev.0";
- cm-cable-min = <475000>;
- cm-cable-max = <500000>;
- };
- cable@1 {
- cm-cable-name = "SDP";
- cm-cable-extcon = "extcon-dev.0";
- cm-cable-min = <650000>;
- cm-cable-max = <675000>;
- };
- };
-
- };
diff --git a/Bindings/power/supply/charger-manager.yaml b/Bindings/power/supply/charger-manager.yaml
new file mode 100644
index 0000000..c863cfa
--- /dev/null
+++ b/Bindings/power/supply/charger-manager.yaml
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/supply/charger-manager.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Charger Manager
+
+maintainers:
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |
+ Binding for the legacy charger manager driver.
+ Please do not use for new products.
+
+properties:
+ compatible:
+ const: charger-manager
+
+ cm-chargers:
+ description: name of chargers
+ $ref: /schemas/types.yaml#/definitions/string-array
+
+ cm-num-chargers:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
+
+ cm-fuel-gauge:
+ description: name of battery fuel gauge
+ $ref: /schemas/types.yaml#/definitions/string
+
+ cm-name:
+ description: name of the charger manager
+ default: battery
+ $ref: /schemas/types.yaml#/definitions/string
+
+ cm-poll-mode:
+ description: polling mode
+ default: 0
+ enum:
+ - 0 # disabled
+ - 1 # always
+ - 2 # when external power is connected
+ - 3 # when charging
+
+ cm-poll-interval:
+ description: polling interval (in ms)
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-battery-stat:
+ description: battery status
+ enum:
+ - 0 # battery always present
+ - 1 # no battery
+ - 2 # check presence via fuel gauge
+ - 3 # check presence via charger
+
+ cm-fullbatt-vchkdrop-volt:
+ description: voltage drop before restarting charging in uV
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-fullbatt-vchkdrop-ms:
+ deprecated: true
+
+ cm-fullbatt-voltage:
+ description: voltage of full battery in uV
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-fullbatt-soc:
+ description: state of charge to consider as full battery in %
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-fullbatt-capacity:
+ description: capcity to consider as full battery in uAh
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-thermal-zone:
+ description: name of external thermometer's thermal zone
+ $ref: /schemas/types.yaml#/definitions/string
+
+ cm-discharging-max:
+ description: limits of discharging duration in ms
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-charging-max:
+ description: limits of charging duration in ms
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-battery-cold:
+ description: critical cold temperature of battery for charging in deci-degree celsius
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-battery-cold-in-minus:
+ description: if set cm-battery-cold temperature is in minus degrees
+ type: boolean
+
+ cm-battery-hot:
+ description: critical hot temperature of battery for charging in deci-degree celsius
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-battery-temp-diff:
+ description: temperature difference to allow recharging in deci-degree celsius
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+patternProperties:
+ "-supply$":
+ description: regulator consumer, named according to cm-regulator-name
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ "^regulator[@-][0-9]$":
+ type: object
+ properties:
+ cm-regulator-name:
+ description: name of charger regulator
+ $ref: /schemas/types.yaml#/definitions/string
+
+ required:
+ - cm-regulator-name
+
+ additionalProperties: false
+
+ patternProperties:
+ "^cable[@-][0-9]$":
+ type: object
+ properties:
+ cm-cable-name:
+ description: name of charger cable
+ enum:
+ - USB
+ - USB-HOST
+ - SDP
+ - DCP
+ - CDP
+ - ACA
+ - FAST-CHARGER
+ - SLOW-CHARGER
+ - WPT
+ - PD
+ - DOCK
+ - JIG
+ - MECHANICAL
+
+ cm-cable-extcon:
+ description: name of extcon dev
+ $ref: /schemas/types.yaml#/definitions/string
+
+ cm-cable-min:
+ description: minimum current of cable in uA
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cm-cable-max:
+ description: maximum current of cable in uA
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - cm-cable-name
+ - cm-cable-extcon
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - cm-chargers
+ - cm-fuel-gauge
+
+additionalProperties: false
+
+examples:
+ - |
+ charger-manager {
+ compatible = "charger-manager";
+ chg-reg-supply = <&charger_regulator>;
+
+ cm-name = "battery";
+ /* Always polling ON : 30s */
+ cm-poll-mode = <1>;
+ cm-poll-interval = <30000>;
+
+ cm-fullbatt-vchkdrop-volt = <150000>;
+ cm-fullbatt-soc = <100>;
+
+ cm-battery-stat = <3>;
+
+ cm-chargers = "charger0", "charger1", "charger2";
+
+ cm-fuel-gauge = "fuelgauge0";
+
+ cm-thermal-zone = "thermal_zone.1";
+ /* in deci centigrade */
+ cm-battery-cold = <50>;
+ cm-battery-cold-in-minus;
+ cm-battery-hot = <800>;
+ cm-battery-temp-diff = <100>;
+
+ /* Allow charging for 5hr */
+ cm-charging-max = <18000000>;
+ /* Allow discharging for 2hr */
+ cm-discharging-max = <7200000>;
+
+ regulator-0 {
+ cm-regulator-name = "chg-reg";
+ cable-0 {
+ cm-cable-name = "USB";
+ cm-cable-extcon = "extcon-dev.0";
+ cm-cable-min = <475000>;
+ cm-cable-max = <500000>;
+ };
+ cable-1 {
+ cm-cable-name = "SDP";
+ cm-cable-extcon = "extcon-dev.0";
+ cm-cable-min = <650000>;
+ cm-cable-max = <675000>;
+ };
+ };
+ };
diff --git a/Bindings/power/supply/maxim,max17040.yaml b/Bindings/power/supply/maxim,max17040.yaml
index de91cf3..f792d06 100644
--- a/Bindings/power/supply/maxim,max17040.yaml
+++ b/Bindings/power/supply/maxim,max17040.yaml
@@ -89,7 +89,7 @@
reg = <0x36>;
maxim,alert-low-soc-level = <10>;
interrupt-parent = <&gpio7>;
- interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
wakeup-source;
};
};
diff --git a/Bindings/power/supply/richtek,rt5033-battery.yaml b/Bindings/power/supply/richtek,rt5033-battery.yaml
new file mode 100644
index 0000000..ae647d3
--- /dev/null
+++ b/Bindings/power/supply/richtek,rt5033-battery.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/supply/richtek,rt5033-battery.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Richtek RT5033 PMIC Fuel Gauge
+
+maintainers:
+ - Stephan Gerhold <stephan@gerhold.net>
+
+allOf:
+ - $ref: power-supply.yaml#
+
+properties:
+ compatible:
+ const: richtek,rt5033-battery
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ battery@35 {
+ compatible = "richtek,rt5033-battery";
+ reg = <0x35>;
+ };
+ };
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ battery@35 {
+ compatible = "richtek,rt5033-battery";
+ reg = <0x35>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <121 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
diff --git a/Bindings/property-units.txt b/Bindings/property-units.txt
deleted file mode 100644
index 218f99f..0000000
--- a/Bindings/property-units.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Standard Unit Suffixes for Property names
-
-Properties which have a unit of measure are recommended to have a unit
-suffix appended to the property name. The list below contains the
-recommended suffixes. Other variations exist in bindings, but should not
-be used in new bindings or added here. The inconsistency in the unit
-prefixes is due to selecting the most commonly used variants.
-
-It is also recommended to use the units listed here and not add additional
-unit prefixes.
-
-Time/Frequency
-----------------------------------------
--mhz : megahertz
--hz : hertz (preferred)
--sec : second
--ms : millisecond
--us : microsecond
--ns : nanosecond
--ps : picosecond
-
-Distance
-----------------------------------------
--mm : millimeter
-
-Electricity
-----------------------------------------
--microamp : microampere
--microamp-hours : microampere hour
--ohms : ohm
--micro-ohms : microohm
--microwatt-hours: microwatt hour
--microvolt : microvolt
--picofarads : picofarad
--femtofarads : femtofarad
-
-Temperature
-----------------------------------------
--celsius : degree Celsius
--millicelsius : millidegree Celsius
-
-Pressure
-----------------------------------------
--kpascal : kilopascal
-
-Throughput
-----------------------------------------
--kBps : kilobytes per second
diff --git a/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 7dcab2b..800d511 100644
--- a/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -25,6 +25,9 @@
- const: allwinner,sun8i-a83t-pwm
- const: allwinner,sun8i-h3-pwm
- items:
+ - const: allwinner,sun8i-v3s-pwm
+ - const: allwinner,sun7i-a20-pwm
+ - items:
- const: allwinner,sun50i-a64-pwm
- const: allwinner,sun5i-a13-pwm
- items:
@@ -37,7 +40,6 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: Module Clock
- description: Bus Clock
diff --git a/Bindings/pwm/brcm,iproc-pwm.txt b/Bindings/pwm/brcm,iproc-pwm.txt
deleted file mode 100644
index 655f6cd..0000000
--- a/Bindings/pwm/brcm,iproc-pwm.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Broadcom iProc PWM controller device tree bindings
-
-This controller has 4 channels.
-
-Required Properties :
-- compatible: must be "brcm,iproc-pwm"
-- reg: physical base address and length of the controller's registers
-- clocks: phandle + clock specifier pair for the external clock
-- #pwm-cells: Should be 3. See pwm.yaml in this directory for a
- description of the cells format.
-
-Refer to clocks/clock-bindings.txt for generic clock consumer properties.
-
-Example:
-
-pwm: pwm@18031000 {
- compatible = "brcm,iproc-pwm";
- reg = <0x18031000 0x28>;
- clocks = <&osc>;
- #pwm-cells = <3>;
-};
diff --git a/Bindings/pwm/brcm,iproc-pwm.yaml b/Bindings/pwm/brcm,iproc-pwm.yaml
new file mode 100644
index 0000000..218ab06
--- /dev/null
+++ b/Bindings/pwm/brcm,iproc-pwm.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/brcm,iproc-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom iProc PWM controller
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+description:
+ This controller has 4 channels.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: brcm,iproc-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: external clock
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+unevaluatedProperties: false
+
+required:
+ - reg
+ - clocks
+
+examples:
+ - |
+ pwm@18031000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x18031000 0x28>;
+ clocks = <&osc>;
+ #pwm-cells = <3>;
+ };
diff --git a/Bindings/pwm/pwm-tiecap.txt b/Bindings/pwm/pwm-tiecap.txt
deleted file mode 100644
index c7c4347..0000000
--- a/Bindings/pwm/pwm-tiecap.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-TI SOC ECAP based APWM controller
-
-Required properties:
-- compatible: Must be "ti,<soc>-ecap".
- for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
- for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
- for da850 - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
- for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
- for 66ak2g - compatible = "ti,k2g-ecap", "ti,am3352-ecap";
- for am654 - compatible = "ti,am654-ecap", "ti,am3352-ecap";
-- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
- the cells format. The PWM channel index ranges from 0 to 4. The only third
- cell flag supported by this binding is PWM_POLARITY_INVERTED.
-- reg: physical base address and size of the registers map.
-
-Optional properties:
-- clocks: Handle to the ECAP's functional clock.
-- clock-names: Must be set to "fck".
-
-Example:
-
-ecap0: ecap@48300100 { /* ECAP on am33xx */
- compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48300100 0x80>;
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
-};
-
-ecap0: ecap@48300100 { /* ECAP on am4372 */
- compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x48300100 0x80>;
- ti,hwmods = "ecap0";
- clocks = <&l4ls_gclk>;
- clock-names = "fck";
-};
-
-ecap0: ecap@1f06000 { /* ECAP on da850 */
- compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
- #pwm-cells = <3>;
- reg = <0x1f06000 0x80>;
-};
-
-ecap0: ecap@4843e100 {
- compatible = "ti,dra746-ecap", "ti,am3352-ecap";
- #pwm-cells = <3>;
- reg = <0x4843e100 0x80>;
- clocks = <&l4_root_clk_div>;
- clock-names = "fck";
-};
diff --git a/Bindings/pwm/pwm-tiecap.yaml b/Bindings/pwm/pwm-tiecap.yaml
new file mode 100644
index 0000000..ed35b6c
--- /dev/null
+++ b/Bindings/pwm/pwm-tiecap.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/pwm-tiecap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SOC ECAP based APWM controller
+
+maintainers:
+ - Vignesh R <vigneshr@ti.com>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: ti,am3352-ecap
+ - items:
+ - enum:
+ - ti,da850-ecap
+ - ti,am4372-ecap
+ - ti,dra746-ecap
+ - ti,k2g-ecap
+ - ti,am654-ecap
+ - ti,am64-ecap
+ - const: ti,am3352-ecap
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+ description: |
+ See pwm.yaml in this directory for a description of the cells format.
+ The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.
+
+ clock-names:
+ const: fck
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ ecap0: pwm@48300100 { /* ECAP on am33xx */
+ compatible = "ti,am3352-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48300100 0x80>;
+ clocks = <&l4ls_gclk>;
+ clock-names = "fck";
+ };
diff --git a/Bindings/pwm/pwm-tiehrpwm.txt b/Bindings/pwm/pwm-tiehrpwm.txt
deleted file mode 100644
index c7e28f6..0000000
--- a/Bindings/pwm/pwm-tiehrpwm.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-TI SOC EHRPWM based PWM controller
-
-Required properties:
-- compatible: Must be "ti,<soc>-ehrpwm".
- for am33xx - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
- for am4372 - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
- for am654 - compatible = "ti,am654-ehrpwm", "ti-am3352-ehrpwm";
- for da850 - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
- for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
-- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
- the cells format. The only third cell flag supported by this binding is
- PWM_POLARITY_INVERTED.
-- reg: physical base address and size of the registers map.
-
-Optional properties:
-- clocks: Handle to the PWM's time-base and functional clock.
-- clock-names: Must be set to "tbclk" and "fck".
-
-Example:
-
-ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
- compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48300200 0x100>;
- clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
-};
-
-ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */
- compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x48300200 0x80>;
- clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
- clock-names = "tbclk", "fck";
- ti,hwmods = "ehrpwm0";
-};
-
-ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */
- compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x1f00000 0x2000>;
-};
-
-ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */
- compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
- #pwm-cells = <3>;
- reg = <0x4843e200 0x80>;
- clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
- clock-names = "tbclk", "fck";
-};
diff --git a/Bindings/pwm/pwm-tiehrpwm.yaml b/Bindings/pwm/pwm-tiehrpwm.yaml
new file mode 100644
index 0000000..ee312cb
--- /dev/null
+++ b/Bindings/pwm/pwm-tiehrpwm.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/pwm-tiehrpwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI SOC EHRPWM based PWM controller
+
+maintainers:
+ - Vignesh R <vigneshr@ti.com>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: ti,am3352-ehrpwm
+ - items:
+ - enum:
+ - ti,da850-ehrpwm
+ - ti,am4372-ehrpwm
+ - ti,dra746-ehrpwm
+ - ti,am654-ehrpwm
+ - ti,am64-epwm
+ - const: ti,am3352-ehrpwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+ description: |
+ See pwm.yaml in this directory for a description of the cells format.
+ The only third cell flag supported by this binding is PWM_POLARITY_INVERTED.
+
+ clock-names:
+ items:
+ - const: tbclk
+ - const: fck
+
+ clocks:
+ maxItems: 2
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
+ compatible = "ti,am3352-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48300200 0x100>;
+ clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+ clock-names = "tbclk", "fck";
+ };
diff --git a/Bindings/pwm/pwm.yaml b/Bindings/pwm/pwm.yaml
index 7d1f687..2effe6c 100644
--- a/Bindings/pwm/pwm.yaml
+++ b/Bindings/pwm/pwm.yaml
@@ -24,8 +24,9 @@
examples:
- |
- pwm: pwm@7000a000 {
- compatible = "nvidia,tegra20-pwm";
- reg = <0x7000a000 0x100>;
- #pwm-cells = <2>;
+ pwm: pwm@1c20e00 {
+ compatible = "allwinner,sun7i-a20-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
};
diff --git a/Bindings/pwm/renesas,pwm-rcar.yaml b/Bindings/pwm/renesas,pwm-rcar.yaml
index 3c2fa2e..7ea1070 100644
--- a/Bindings/pwm/renesas,pwm-rcar.yaml
+++ b/Bindings/pwm/renesas,pwm-rcar.yaml
@@ -61,6 +61,19 @@
- reg
- '#pwm-cells'
- clocks
+ - power-domains
+
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,pwm-r8a7778
+ - renesas,pwm-r8a7779
+then:
+ required:
+ - resets
additionalProperties: false
diff --git a/Bindings/pwm/renesas,tpu-pwm.yaml b/Bindings/pwm/renesas,tpu-pwm.yaml
index aa9a457..81ccb21 100644
--- a/Bindings/pwm/renesas,tpu-pwm.yaml
+++ b/Bindings/pwm/renesas,tpu-pwm.yaml
@@ -9,6 +9,15 @@
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+select:
+ properties:
+ compatible:
+ contains:
+ const: renesas,tpu
+ required:
+ - compatible
+ - '#pwm-cells'
+
properties:
compatible:
items:
@@ -58,6 +67,23 @@
- compatible
- reg
- '#pwm-cells'
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,tpu-r8a73a4
+ - renesas,tpu-r8a7740
+ then:
+ required:
+ - resets
additionalProperties: false
diff --git a/Bindings/regulator/max8893.yaml b/Bindings/regulator/max8893.yaml
new file mode 100644
index 0000000..2b5e977
--- /dev/null
+++ b/Bindings/regulator/max8893.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/max8893.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Regulator driver for MAX8893 PMIC from Maxim Integrated.
+
+maintainers:
+ - Sergey Larin <cerg2010cerg2010@mail.ru>
+
+description: |
+ The device has 5 LDO regulators and a single BUCK regulator.
+ Programming is done through I2C bus.
+
+properties:
+ compatible:
+ const: maxim,max8893
+
+ reg:
+ maxItems: 1
+
+ regulators:
+ type: object
+
+ patternProperties:
+ "^(ldo[1-5]|buck)$":
+ $ref: "regulator.yaml#"
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - regulators
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic@3e {
+ compatible = "maxim,max8893";
+ reg = <0x3e>;
+
+ regulators {
+ /* Front camera - s5k6aafx, back - m5mo */
+ /* Numbers used to indicate the sequence */
+ front_1_back_1: buck {
+ regulator-name = "cam_isp_core_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ front_4_back_5: ldo1 {
+ regulator-name = "vt_io_1v8,cam_isp_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ front_3_back_4: ldo2 {
+ regulator-name = "vt_core_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ front_5_back_6: ldo3 {
+ regulator-name = "vt_cam_1v8,vt_sensor_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo4 {
+ /* not used */
+ };
+
+ back_7: ldo5 {
+ regulator-name = "cam_sensor_io_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/regulator/mt6359-regulator.yaml b/Bindings/regulator/mt6359-regulator.yaml
new file mode 100644
index 0000000..8cc413e
--- /dev/null
+++ b/Bindings/regulator/mt6359-regulator.yaml
@@ -0,0 +1,385 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/mt6359-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT6359 Regulator from MediaTek Integrated
+
+maintainers:
+ - Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
+
+description: |
+ List of regulators provided by this controller. It is named
+ according to its regulator type, buck_<name> and ldo_<name>.
+ MT6359 regulators node should be sub node of the MT6397 MFD node.
+
+patternProperties:
+ "^buck_v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$"
+
+ unevaluatedProperties: false
+
+ "^ldo_v(ibr|rf12|usb|camio|efuse|xo22)$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^v(ibr|rf12|usb|camio|efuse|xo22)$"
+
+ unevaluatedProperties: false
+
+ "^ldo_v(rfck|emc|a12|a09|ufs|bbck)$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^v(rfck|emc|a12|a09|ufs|bbck)$"
+
+ unevaluatedProperties: false
+
+ "^ldo_vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$"
+
+ unevaluatedProperties: false
+
+ "^ldo_vsram_(proc2|others|md|proc1|others_sshub)$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^vsram_(proc2|others|md|proc1|others_sshub)$"
+
+ unevaluatedProperties: false
+
+ "^ldo_v(fe|bif|io)28$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^v(fe|bif|io)28$"
+
+ unevaluatedProperties: false
+
+ "^ldo_v(aud|io|aux|rf|m)18$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^v(aud|io|aux|rf|m)18$"
+
+ unevaluatedProperties: false
+
+ "^ldo_vsim[12]$":
+ type: object
+ $ref: "regulator.yaml#"
+
+ properties:
+ regulator-name:
+ pattern: "^vsim[12]$"
+
+ required:
+ - regulator-name
+
+ unevaluatedProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ pmic {
+ regulators {
+ mt6359_vs1_buck_reg: buck_vs1 {
+ regulator-name = "vs1";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+ mt6359_vgpu11_buck_reg: buck_vgpu11 {
+ regulator-name = "vgpu11";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vmodem_buck_reg: buck_vmodem {
+ regulator-name = "vmodem";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <10760>;
+ regulator-enable-ramp-delay = <200>;
+ };
+ mt6359_vpu_buck_reg: buck_vpu {
+ regulator-name = "vpu";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vcore_buck_reg: buck_vcore {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vs2_buck_reg: buck_vs2 {
+ regulator-name = "vs2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1600000>;
+ regulator-enable-ramp-delay = <0>;
+ regulator-always-on;
+ };
+ mt6359_vpa_buck_reg: buck_vpa {
+ regulator-name = "vpa";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <3650000>;
+ regulator-enable-ramp-delay = <300>;
+ };
+ mt6359_vproc2_buck_reg: buck_vproc2 {
+ regulator-name = "vproc2";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vproc1_buck_reg: buck_vproc1 {
+ regulator-name = "vproc1";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <200>;
+ regulator-allowed-modes = <0 1 2>;
+ };
+ mt6359_vcore_sshub_buck_reg: buck_vcore_sshub {
+ regulator-name = "vcore_sshub";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ };
+ mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub {
+ regulator-name = "vgpu11_sshub";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1193750>;
+ };
+ mt6359_vaud18_ldo_reg: ldo_vaud18 {
+ regulator-name = "vaud18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vsim1_ldo_reg: ldo_vsim1 {
+ regulator-name = "vsim1";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ };
+ mt6359_vibr_ldo_reg: ldo_vibr {
+ regulator-name = "vibr";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ mt6359_vrf12_ldo_reg: ldo_vrf12 {
+ regulator-name = "vrf12";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ mt6359_vusb_ldo_reg: ldo_vusb {
+ regulator-name = "vusb";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-enable-ramp-delay = <960>;
+ regulator-always-on;
+ };
+ mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 {
+ regulator-name = "vsram_proc2";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vio18_ldo_reg: ldo_vio18 {
+ regulator-name = "vio18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-enable-ramp-delay = <960>;
+ regulator-always-on;
+ };
+ mt6359_vcamio_ldo_reg: ldo_vcamio {
+ regulator-name = "vcamio";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+ mt6359_vcn18_ldo_reg: ldo_vcn18 {
+ regulator-name = "vcn18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vfe28_ldo_reg: ldo_vfe28 {
+ regulator-name = "vfe28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <120>;
+ };
+ mt6359_vcn13_ldo_reg: ldo_vcn13 {
+ regulator-name = "vcn13";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1300000>;
+ };
+ mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt {
+ regulator-name = "vcn33_1_bt";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi {
+ regulator-name = "vcn33_1_wifi";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_vaux18_ldo_reg: ldo_vaux18 {
+ regulator-name = "vaux18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vsram_others_ldo_reg: ldo_vsram_others {
+ regulator-name = "vsram_others";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <5000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vefuse_ldo_reg: ldo_vefuse {
+ regulator-name = "vefuse";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2000000>;
+ };
+ mt6359_vxo22_ldo_reg: ldo_vxo22 {
+ regulator-name = "vxo22";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-always-on;
+ };
+ mt6359_vrfck_ldo_reg: ldo_vrfck {
+ regulator-name = "vrfck";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1700000>;
+ };
+ mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 {
+ regulator-name = "vrfck";
+ regulator-min-microvolt = <1240000>;
+ regulator-max-microvolt = <1600000>;
+ };
+ mt6359_vbif28_ldo_reg: ldo_vbif28 {
+ regulator-name = "vbif28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vio28_ldo_reg: ldo_vio28 {
+ regulator-name = "vio28";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ mt6359_vemc_ldo_reg: ldo_vemc {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ mt6359_vemc_1_ldo_reg: ldo_vemc_1 {
+ regulator-name = "vemc";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt {
+ regulator-name = "vcn33_2_bt";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi {
+ regulator-name = "vcn33_2_wifi";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3500000>;
+ };
+ mt6359_va12_ldo_reg: ldo_va12 {
+ regulator-name = "va12";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ };
+ mt6359_va09_ldo_reg: ldo_va09 {
+ regulator-name = "va09";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ mt6359_vrf18_ldo_reg: ldo_vrf18 {
+ regulator-name = "vrf18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1810000>;
+ };
+ mt6359_vsram_md_ldo_reg: ldo_vsram_md {
+ regulator-name = "vsram_md";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <10760>;
+ regulator-enable-ramp-delay = <240>;
+ };
+ mt6359_vufs_ldo_reg: ldo_vufs {
+ regulator-name = "vufs";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+ mt6359_vm18_ldo_reg: ldo_vm18 {
+ regulator-name = "vm18";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-always-on;
+ };
+ mt6359_vbbck_ldo_reg: ldo_vbbck {
+ regulator-name = "vbbck";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
+ };
+ mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 {
+ regulator-name = "vsram_proc1";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ regulator-ramp-delay = <7500>;
+ regulator-enable-ramp-delay = <240>;
+ regulator-always-on;
+ };
+ mt6359_vsim2_ldo_reg: ldo_vsim2 {
+ regulator-name = "vsim2";
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3100000>;
+ };
+ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub {
+ regulator-name = "vsram_others_sshub";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1293750>;
+ };
+ };
+ };
+...
diff --git a/Bindings/regulator/qcom,rpmh-regulator.yaml b/Bindings/regulator/qcom,rpmh-regulator.yaml
index e561a5b..34de383 100644
--- a/Bindings/regulator/qcom,rpmh-regulator.yaml
+++ b/Bindings/regulator/qcom,rpmh-regulator.yaml
@@ -33,6 +33,9 @@
The names used for regulator nodes must match those supported by a given
PMIC. Supported regulator node names are
+ For PM6150, smps1 - smps5, ldo1 - ldo19
+ For PM6150L, smps1 - smps8, ldo1 - ldo11, bob
+ For PM7325, smps1 - smps8, ldo1 - ldo19
For PM8005, smps1 - smps4
For PM8009, smps1 - smps2, ldo1 - ldo7
For PM8150, smps1 - smps10, ldo1 - ldo18
@@ -41,15 +44,15 @@
For PM8350C, smps1 - smps10, ldo1 - ldo13, bob
For PM8998, smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2
For PMI8998, bob
- For PM6150, smps1 - smps5, ldo1 - ldo19
- For PM6150L, smps1 - smps8, ldo1 - ldo11, bob
- For PMX55, smps1 - smps7, ldo1 - ldo16
- For PM7325, smps1 - smps8, ldo1 - ldo19
For PMR735A, smps1 - smps3, ldo1 - ldo7
+ For PMX55, smps1 - smps7, ldo1 - ldo16
properties:
compatible:
enum:
+ - qcom,pm6150-rpmh-regulators
+ - qcom,pm6150l-rpmh-regulators
+ - qcom,pm7325-rpmh-regulators
- qcom,pm8005-rpmh-regulators
- qcom,pm8009-rpmh-regulators
- qcom,pm8009-1-rpmh-regulators
@@ -59,11 +62,9 @@
- qcom,pm8350c-rpmh-regulators
- qcom,pm8998-rpmh-regulators
- qcom,pmi8998-rpmh-regulators
- - qcom,pm6150-rpmh-regulators
- - qcom,pm6150l-rpmh-regulators
- - qcom,pmx55-rpmh-regulators
- - qcom,pm7325-rpmh-regulators
+ - qcom,pmm8155au-rpmh-regulators
- qcom,pmr735a-rpmh-regulators
+ - qcom,pmx55-rpmh-regulators
qcom,pmic-id:
description: |
diff --git a/Bindings/regulator/qcom,smd-rpm-regulator.yaml b/Bindings/regulator/qcom,smd-rpm-regulator.yaml
index a35c6cb..83b5357 100644
--- a/Bindings/regulator/qcom,smd-rpm-regulator.yaml
+++ b/Bindings/regulator/qcom,smd-rpm-regulator.yaml
@@ -24,6 +24,10 @@
For mp5496, s2
+ For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
+ l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25,
+ l26, l27, l28, lvs1
+
For pm8841, s1, s2, s3, s4, s5, s6, s7, s8
For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
@@ -68,6 +72,7 @@
compatible:
enum:
- qcom,rpm-mp5496-regulators
+ - qcom,rpm-pm8226-regulators
- qcom,rpm-pm8841-regulators
- qcom,rpm-pm8916-regulators
- qcom,rpm-pm8941-regulators
diff --git a/Bindings/regulator/regulator.yaml b/Bindings/regulator/regulator.yaml
index 6d0bc9c..a6ae9ec 100644
--- a/Bindings/regulator/regulator.yaml
+++ b/Bindings/regulator/regulator.yaml
@@ -117,6 +117,88 @@
description: Enable over current protection.
type: boolean
+ regulator-oc-protection-microamp:
+ description: Set over current protection limit. This is a limit where
+ hardware performs emergency shutdown. Zero can be passed to disable
+ protection and value '1' indicates that protection should be enabled but
+ limit setting can be omitted.
+
+ regulator-oc-error-microamp:
+ description: Set over current error limit. This is a limit where part of
+ the hardware propably is malfunctional and damage prevention is requested.
+ Zero can be passed to disable error detection and value '1' indicates
+ that detection should be enabled but limit setting can be omitted.
+
+ regulator-oc-warn-microamp:
+ description: Set over current warning limit. This is a limit where hardware
+ is assumed still to be functional but approaching limit where it gets
+ damaged. Recovery actions should be initiated. Zero can be passed to
+ disable detection and value '1' indicates that detection should
+ be enabled but limit setting can be omitted.
+
+ regulator-ov-protection-microvolt:
+ description: Set over voltage protection limit. This is a limit where
+ hardware performs emergency shutdown. Zero can be passed to disable
+ protection and value '1' indicates that protection should be enabled but
+ limit setting can be omitted. Limit is given as microvolt offset from
+ voltage set to regulator.
+
+ regulator-ov-error-microvolt:
+ description: Set over voltage error limit. This is a limit where part of
+ the hardware propably is malfunctional and damage prevention is requested
+ Zero can be passed to disable error detection and value '1' indicates
+ that detection should be enabled but limit setting can be omitted. Limit
+ is given as microvolt offset from voltage set to regulator.
+
+ regulator-ov-warn-microvolt:
+ description: Set over voltage warning limit. This is a limit where hardware
+ is assumed still to be functional but approaching limit where it gets
+ damaged. Recovery actions should be initiated. Zero can be passed to
+ disable detection and value '1' indicates that detection should
+ be enabled but limit setting can be omitted. Limit is given as microvolt
+ offset from voltage set to regulator.
+
+ regulator-uv-protection-microvolt:
+ description: Set over under voltage protection limit. This is a limit where
+ hardware performs emergency shutdown. Zero can be passed to disable
+ protection and value '1' indicates that protection should be enabled but
+ limit setting can be omitted. Limit is given as microvolt offset from
+ voltage set to regulator.
+
+ regulator-uv-error-microvolt:
+ description: Set under voltage error limit. This is a limit where part of
+ the hardware propably is malfunctional and damage prevention is requested
+ Zero can be passed to disable error detection and value '1' indicates
+ that detection should be enabled but limit setting can be omitted. Limit
+ is given as microvolt offset from voltage set to regulator.
+
+ regulator-uv-warn-microvolt:
+ description: Set over under voltage warning limit. This is a limit where
+ hardware is assumed still to be functional but approaching limit where
+ it gets damaged. Recovery actions should be initiated. Zero can be passed
+ to disable detection and value '1' indicates that detection should
+ be enabled but limit setting can be omitted. Limit is given as microvolt
+ offset from voltage set to regulator.
+
+ regulator-temp-protection-kelvin:
+ description: Set over temperature protection limit. This is a limit where
+ hardware performs emergency shutdown. Zero can be passed to disable
+ protection and value '1' indicates that protection should be enabled but
+ limit setting can be omitted.
+
+ regulator-temp-error-kelvin:
+ description: Set over temperature error limit. This is a limit where part of
+ the hardware propably is malfunctional and damage prevention is requested
+ Zero can be passed to disable error detection and value '1' indicates
+ that detection should be enabled but limit setting can be omitted.
+
+ regulator-temp-warn-kelvin:
+ description: Set over temperature warning limit. This is a limit where
+ hardware is assumed still to be functional but approaching limit where it
+ gets damaged. Recovery actions should be initiated. Zero can be passed to
+ disable detection and value '1' indicates that detection should
+ be enabled but limit setting can be omitted.
+
regulator-active-discharge:
description: |
tristate, enable/disable active discharge of regulators. The values are:
diff --git a/Bindings/regulator/richtek,rt6160-regulator.yaml b/Bindings/regulator/richtek,rt6160-regulator.yaml
new file mode 100644
index 0000000..0534b0d
--- /dev/null
+++ b/Bindings/regulator/richtek,rt6160-regulator.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/richtek,rt6160-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Richtek RT6160 BuckBoost converter
+
+maintainers:
+ - ChiYuan Huang <cy_huang@richtek.com>
+
+description: |
+ The RT6160 is a high-efficiency buck-boost converter that can provide
+ up to 3A output current from 2025mV to 5200mV. And it support the wide
+ input voltage range from 2200mV to 5500mV.
+
+ Datasheet is available at
+ https://www.richtek.com/assets/product_file/RT6160A/DS6160A-00.pdf
+
+allOf:
+ - $ref: regulator.yaml#
+
+properties:
+ compatible:
+ enum:
+ - richtek,rt6160
+
+ reg:
+ maxItems: 1
+
+ enable-gpios:
+ description: A connection of the 'enable' gpio line.
+ maxItems: 1
+
+ richtek,vsel-active-low:
+ description: |
+ Used to indicate the 'vsel' pin active level. if not specified, use
+ high active level as the default.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rt6160@75 {
+ compatible = "richtek,rt6160";
+ reg = <0x75>;
+ enable-gpios = <&gpio26 2 0>;
+ regulator-name = "rt6160-buckboost";
+ regulator-min-microvolt = <2025000>;
+ regulator-max-microvolt = <5200000>;
+ };
+ };
diff --git a/Bindings/regulator/richtek,rt6245-regulator.yaml b/Bindings/regulator/richtek,rt6245-regulator.yaml
new file mode 100644
index 0000000..796ceac
--- /dev/null
+++ b/Bindings/regulator/richtek,rt6245-regulator.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/richtek,rt6245-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Richtek RT6245 High Current Voltage Regulator
+
+maintainers:
+ - ChiYuan Huang <cy_huang@richtek.com>
+
+description: |
+ The RT6245 is a high-performance, synchronous step-down converter
+ that can deliver up to 14A output current with an input supply
+ voltage range of 4.5V to 17V.
+
+allOf:
+ - $ref: regulator.yaml#
+
+properties:
+ compatible:
+ enum:
+ - richtek,rt6245
+
+ reg:
+ maxItems: 1
+
+ enable-gpios:
+ description: |
+ A connection of the chip 'enable' gpio line. If not provided,
+ it will be treat as a default-on power.
+ maxItems: 1
+
+ richtek,oc-level-select:
+ $ref: "/schemas/types.yaml#/definitions/uint8"
+ enum: [0, 1, 2, 3]
+ description: |
+ Over current level selection. Each respective value means the current
+ limit 8A, 14A, 12A, 10A. If this property is missing then keep in
+ in chip default.
+
+ richtek,ot-level-select:
+ $ref: "/schemas/types.yaml#/definitions/uint8"
+ enum: [0, 1, 2]
+ description: |
+ Over temperature level selection. Each respective value means the degree
+ 150'c, 130'c, 170'c. If this property is missing then keep in chip
+ default.
+
+ richtek,pgdly-time-select:
+ $ref: "/schemas/types.yaml#/definitions/uint8"
+ enum: [0, 1, 2, 3]
+ description: |
+ Power good signal delay time selection. Each respective value means the
+ delay time 0us, 10us, 20us, 40us. If this property is missing then keep
+ in chip default.
+
+
+ richtek,switch-freq-select:
+ $ref: "/schemas/types.yaml#/definitions/uint8"
+ enum: [0, 1, 2]
+ description: |
+ Buck switch frequency selection. Each respective value means 400KHz,
+ 800KHz, 1200KHz. If this property is missing then keep in chip default.
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rt6245@34 {
+ compatible = "richtek,rt6245";
+ status = "okay";
+ reg = <0x34>;
+ enable-gpios = <&gpio26 2 0>;
+
+ regulator-name = "rt6245-regulator";
+ regulator-min-microvolt = <437500>;
+ regulator-max-microvolt = <1387500>;
+ regulator-boot-on;
+ };
+ };
diff --git a/Bindings/regulator/rohm,bd9576-regulator.yaml b/Bindings/regulator/rohm,bd9576-regulator.yaml
index b6515a0..7cb74cc 100644
--- a/Bindings/regulator/rohm,bd9576-regulator.yaml
+++ b/Bindings/regulator/rohm,bd9576-regulator.yaml
@@ -27,6 +27,12 @@
Properties for single regulator.
$ref: "regulator.yaml#"
+ properties:
+ rohm,ocw-fet-ron-micro-ohms:
+ description: |
+ External FET's ON-resistance. Required if VoutS1 OCP/OCW is
+ to be set.
+
required:
- regulator-name
diff --git a/Bindings/remoteproc/fsl,imx-rproc.yaml b/Bindings/remoteproc/fsl,imx-rproc.yaml
index 208a628..fc16d90 100644
--- a/Bindings/remoteproc/fsl,imx-rproc.yaml
+++ b/Bindings/remoteproc/fsl,imx-rproc.yaml
@@ -17,7 +17,11 @@
enum:
- fsl,imx8mq-cm4
- fsl,imx8mm-cm4
+ - fsl,imx8mn-cm7
+ - fsl,imx8mp-cm7
+ - fsl,imx8ulp-cm33
- fsl,imx7d-cm4
+ - fsl,imx7ulp-cm4
- fsl,imx6sx-cm4
clocks:
@@ -49,10 +53,14 @@
minItems: 1
maxItems: 32
+ fsl,auto-boot:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Indicate whether need to load the default firmware and start the remote
+ processor automatically.
+
required:
- compatible
- - clocks
- - syscon
additionalProperties: false
diff --git a/Bindings/remoteproc/qcom,adsp.txt b/Bindings/remoteproc/qcom,adsp.txt
deleted file mode 100644
index 229f908..0000000
--- a/Bindings/remoteproc/qcom,adsp.txt
+++ /dev/null
@@ -1,228 +0,0 @@
-Qualcomm ADSP Peripheral Image Loader
-
-This document defines the binding for a component that loads and boots firmware
-on the Qualcomm ADSP Hexagon core.
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: must be one of:
- "qcom,msm8974-adsp-pil"
- "qcom,msm8996-adsp-pil"
- "qcom,msm8996-slpi-pil"
- "qcom,msm8998-adsp-pas"
- "qcom,msm8998-slpi-pas"
- "qcom,qcs404-adsp-pas"
- "qcom,qcs404-cdsp-pas"
- "qcom,qcs404-wcss-pas"
- "qcom,sc7180-mpss-pas"
- "qcom,sdm845-adsp-pas"
- "qcom,sdm845-cdsp-pas"
- "qcom,sdx55-mpss-pas"
- "qcom,sm8150-adsp-pas"
- "qcom,sm8150-cdsp-pas"
- "qcom,sm8150-mpss-pas"
- "qcom,sm8150-slpi-pas"
- "qcom,sm8250-adsp-pas"
- "qcom,sm8250-cdsp-pas"
- "qcom,sm8250-slpi-pas"
- "qcom,sm8350-adsp-pas"
- "qcom,sm8350-cdsp-pas"
- "qcom,sm8350-slpi-pas"
- "qcom,sm8350-mpss-pas"
-
-- interrupts-extended:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: reference to the interrupts that match interrupt-names
-
-- interrupt-names:
- Usage: required
- Value type: <stringlist>
- Definition: The interrupts needed depends on the compatible
- string:
- qcom,msm8974-adsp-pil:
- qcom,msm8996-adsp-pil:
- qcom,msm8996-slpi-pil:
- qcom,msm8998-adsp-pas:
- qcom,msm8998-slpi-pas:
- qcom,qcs404-adsp-pas:
- qcom,qcs404-cdsp-pas:
- qcom,sdm845-adsp-pas:
- qcom,sdm845-cdsp-pas:
- qcom,sm8150-adsp-pas:
- qcom,sm8150-cdsp-pas:
- qcom,sm8150-slpi-pas:
- qcom,sm8250-adsp-pas:
- qcom,sm8250-cdsp-pas:
- qcom,sm8250-slpi-pas:
- qcom,sm8350-adsp-pas:
- qcom,sm8350-cdsp-pas:
- qcom,sm8350-slpi-pas:
- must be "wdog", "fatal", "ready", "handover", "stop-ack"
- qcom,qcs404-wcss-pas:
- qcom,sc7180-mpss-pas:
- qcom,sdx55-mpss-pas:
- qcom,sm8150-mpss-pas:
- qcom,sm8350-mpss-pas:
- must be "wdog", "fatal", "ready", "handover", "stop-ack",
- "shutdown-ack"
-
-- firmware-name:
- Usage: optional
- Value type: <string>
- Definition: must list the relative firmware image path for the
- Hexagon Core.
-
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: reference to the xo clock and optionally aggre2 clock to be
- held on behalf of the booting Hexagon core
-
-- clock-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "xo" and optionally include "aggre2"
-
-- cx-supply:
- Usage: required
- Value type: <phandle>
- Definition: reference to the regulator to be held on behalf of the
- booting Hexagon core
-
-- px-supply:
- Usage: required
- Value type: <phandle>
- Definition: reference to the px regulator to be held on behalf of the
- booting Hexagon core
-
-- power-domains:
- Usage: required
- Value type: <phandle>
- Definition: reference to power-domains that match the power-domain-names
-
-- power-domain-names:
- Usage: required
- Value type: <stringlist>
- Definition: The power-domains needed depend on the compatible string:
- qcom,msm8974-adsp-pil:
- qcom,msm8996-adsp-pil:
- qcom,msm8998-adsp-pas:
- must be "cx"
- qcom,msm8996-slpi-pil:
- must be "ss_cx"
- qcom,msm8998-slpi-pas:
- must be "ssc_cx"
- qcom,qcs404-adsp-pas:
- must be "lpi_cx"
- qcom,qcs404-cdsp-pas:
- qcom,qcs404-wcss-pas:
- must be "mx"
- qcom,sdm845-adsp-pas:
- qcom,sdm845-cdsp-pas:
- qcom,sm8150-adsp-pas:
- qcom,sm8150-cdsp-pas:
- qcom,sm8250-cdsp-pas:
- qcom,sm8350-cdsp-pas:
- must be "cx", "load_state"
- qcom,sc7180-mpss-pas:
- qcom,sm8150-mpss-pas:
- qcom,sm8350-mpss-pas:
- must be "cx", "load_state", "mss"
- qcom,sdx55-mpss-pas:
- must be "cx", "mss"
- qcom,sm8250-adsp-pas:
- qcom,sm8350-adsp-pas:
- qcom,sm8150-slpi-pas:
- qcom,sm8250-slpi-pas:
- qcom,sm8350-slpi-pas:
- must be "lcx", "lmx", "load_state"
-
-- memory-region:
- Usage: required
- Value type: <phandle>
- Definition: reference to the reserved-memory for the ADSP
-
-- qcom,smem-states:
- Usage: required
- Value type: <phandle>
- Definition: reference to the smem state for requesting the ADSP to
- shut down
-
-- qcom,smem-state-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "stop"
-
-
-= SUBNODES
-The adsp node may have an subnode named either "smd-edge" or "glink-edge" that
-describes the communication edge, channels and devices related to the ADSP.
-See ../soc/qcom/qcom,smd.txt and ../soc/qcom/qcom,glink.txt for details on how
-to describe these.
-
-
-= EXAMPLE
-The following example describes the resources needed to boot control the
-ADSP, as it is found on MSM8974 boards.
-
- adsp {
- compatible = "qcom,msm8974-adsp-pil";
-
- interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog",
- "fatal",
- "ready",
- "handover",
- "stop-ack";
-
- clocks = <&rpmcc RPM_CXO_CLK>;
- clock-names = "xo";
-
- cx-supply = <&pm8841_s2>;
-
- memory-region = <&adsp_region>;
-
- qcom,smem-states = <&adsp_smp2p_out 0>;
- qcom,smem-state-names = "stop";
-
- smd-edge {
- interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
-
- qcom,ipc = <&apcs 8 8>;
- qcom,smd-edge = <1>;
- };
- };
-
-The following example describes the resources needed to boot control the
-SLPI, as it is found on MSM8996 boards.
-
- slpi {
- compatible = "qcom,msm8996-slpi-pil";
- interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
- <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
- <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
- <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
- <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "wdog",
- "fatal",
- "ready",
- "handover",
- "stop-ack";
-
- clocks = <&rpmcc MSM8996_RPM_SMD_XO_CLK_SRC>,
- <&rpmcc MSM8996_RPM_SMD_AGGR2_NOC_CLK>;
- clock-names = "xo", "aggre2";
-
- cx-supply = <&pm8994_l26>;
- px-supply = <&pm8994_lvs2>;
-
- memory-region = <&slpi_region>;
- qcom,smem-states = <&slpi_smp2p_out 0>;
- qcom,smem-state-names = "stop";
- };
diff --git a/Bindings/remoteproc/qcom,adsp.yaml b/Bindings/remoteproc/qcom,adsp.yaml
new file mode 100644
index 0000000..c597ccc
--- /dev/null
+++ b/Bindings/remoteproc/qcom,adsp.yaml
@@ -0,0 +1,547 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/qcom,adsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm ADSP Peripheral Image Loader binding
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+description:
+ This document defines the binding for a component that loads and boots
+ firmware on the Qualcomm ADSP Hexagon core.
+
+properties:
+ compatible:
+ enum:
+ - qcom,msm8974-adsp-pil
+ - qcom,msm8996-adsp-pil
+ - qcom,msm8996-slpi-pil
+ - qcom,msm8998-adsp-pas
+ - qcom,msm8998-slpi-pas
+ - qcom,qcs404-adsp-pas
+ - qcom,qcs404-cdsp-pas
+ - qcom,qcs404-wcss-pas
+ - qcom,sc7180-mpss-pas
+ - qcom,sc8180x-adsp-pas
+ - qcom,sc8180x-cdsp-pas
+ - qcom,sc8180x-mpss-pas
+ - qcom,sdm845-adsp-pas
+ - qcom,sdm845-cdsp-pas
+ - qcom,sdx55-mpss-pas
+ - qcom,sm8150-adsp-pas
+ - qcom,sm8150-cdsp-pas
+ - qcom,sm8150-mpss-pas
+ - qcom,sm8150-slpi-pas
+ - qcom,sm8250-adsp-pas
+ - qcom,sm8250-cdsp-pas
+ - qcom,sm8250-slpi-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-cdsp-pas
+ - qcom,sm8350-slpi-pas
+ - qcom,sm8350-mpss-pas
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 8
+
+ clock-names:
+ minItems: 1
+ maxItems: 8
+
+ interrupts:
+ minItems: 5
+ maxItems: 6
+
+ interrupt-names:
+ minItems: 5
+ maxItems: 6
+
+ resets:
+ minItems: 1
+ maxItems: 3
+
+ reset-names:
+ minItems: 1
+ maxItems: 3
+
+ cx-supply:
+ description: Phandle to the CX regulator
+
+ px-supply:
+ description: Phandle to the PX regulator
+
+ power-domains:
+ minItems: 1
+ maxItems: 3
+
+ power-domain-names:
+ minItems: 1
+ maxItems: 3
+
+ firmware-name:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: Firmware name for the Hexagon core
+
+ memory-region:
+ maxItems: 1
+ description: Reference to the reserved-memory for the Hexagon core
+
+ qcom,smem-states:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: States used by the AP to signal the Hexagon core
+ items:
+ - description: Stop the modem
+
+ qcom,smem-state-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: The names of the state bits used for SMP2P output
+ items:
+ - const: stop
+
+ qcom,halt-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ Phandle reference to a syscon representing TCSR followed by the
+ three offsets within syscon for q6, modem and nc halt registers.
+
+ smd-edge:
+ type: object
+ description:
+ Qualcomm Shared Memory subnode which represents communication edge,
+ channels and devices related to the ADSP.
+
+ glink-edge:
+ type: object
+ description:
+ Qualcomm G-Link subnode which represents communication edge, channels
+ and devices related to the ADSP.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - memory-region
+ - qcom,smem-states
+ - qcom,smem-state-names
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8974-adsp-pil
+ - qcom,msm8996-adsp-pil
+ - qcom,msm8996-slpi-pil
+ - qcom,msm8998-adsp-pas
+ - qcom,qcs404-adsp-pas
+ - qcom,qcs404-wcss-pas
+ - qcom,sc8180x-adsp-pas
+ - qcom,sc8180x-cdsp-pas
+ - qcom,sc8180x-mpss-pas
+ - qcom,sdm845-adsp-pas
+ - qcom,sdm845-cdsp-pas
+ - qcom,sm8150-adsp-pas
+ - qcom,sm8150-cdsp-pas
+ - qcom,sm8150-mpss-pas
+ - qcom,sm8150-slpi-pas
+ - qcom,sm8250-adsp-pas
+ - qcom,sm8250-cdsp-pas
+ - qcom,sm8250-slpi-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-cdsp-pas
+ - qcom,sm8350-slpi-pas
+ - qcom,sm8350-mpss-pas
+ then:
+ properties:
+ clocks:
+ items:
+ - description: XO clock
+ clock-names:
+ items:
+ - const: xo
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-slpi-pas
+ then:
+ properties:
+ clocks:
+ items:
+ - description: XO clock
+ - description: AGGRE2 clock
+ clock-names:
+ items:
+ - const: xo
+ - const: aggre2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs404-cdsp-pas
+ then:
+ properties:
+ clocks:
+ items:
+ - description: XO clock
+ - description: SWAY clock
+ - description: TBU clock
+ - description: BIMC clock
+ - description: AHB AON clock
+ - description: Q6SS SLAVE clock
+ - description: Q6SS MASTER clock
+ - description: Q6 AXIM clock
+ clock-names:
+ items:
+ - const: xo
+ - const: sway
+ - const: tbu
+ - const: bimc
+ - const: ahb_aon
+ - const: q6ss_slave
+ - const: q6ss_master
+ - const: q6_axim
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-mpss-pas
+ then:
+ properties:
+ clocks:
+ items:
+ - description: XO clock
+ - description: IFACE clock
+ - description: BUS clock
+ - description: NAC clock
+ - description: SNOC AXI clock
+ - description: MNOC AXI clock
+ clock-names:
+ items:
+ - const: xo
+ - const: iface
+ - const: bus
+ - const: nav
+ - const: snoc_axi
+ - const: mnoc_axi
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8974-adsp-pil
+ - qcom,msm8996-adsp-pil
+ - qcom,msm8996-slpi-pil
+ - qcom,msm8998-adsp-pas
+ - qcom,msm8998-slpi-pas
+ - qcom,qcs404-adsp-pas
+ - qcom,qcs404-cdsp-pas
+ - qcom,qcs404-wcss-pas
+ - qcom,sc8180x-adsp-pas
+ - qcom,sc8180x-cdsp-pas
+ - qcom,sdm845-adsp-pas
+ - qcom,sdm845-cdsp-pas
+ - qcom,sm8150-adsp-pas
+ - qcom,sm8150-cdsp-pas
+ - qcom,sm8150-slpi-pas
+ - qcom,sm8250-adsp-pas
+ - qcom,sm8250-cdsp-pas
+ - qcom,sm8250-slpi-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-cdsp-pas
+ - qcom,sm8350-slpi-pas
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: Watchdog interrupt
+ - description: Fatal interrupt
+ - description: Ready interrupt
+ - description: Handover interrupt
+ - description: Stop acknowledge interrupt
+ interrupt-names:
+ items:
+ - const: wdog
+ - const: fatal
+ - const: ready
+ - const: handover
+ - const: stop-ack
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-mpss-pas
+ - qcom,sc8180x-mpss-pas
+ - qcom,sdx55-mpss-pas
+ - qcom,sm8150-mpss-pas
+ - qcom,sm8350-mpss-pas
+ then:
+ properties:
+ interrupts:
+ items:
+ - description: Watchdog interrupt
+ - description: Fatal interrupt
+ - description: Ready interrupt
+ - description: Handover interrupt
+ - description: Stop acknowledge interrupt
+ - description: Shutdown acknowledge interrupt
+ interrupt-names:
+ items:
+ - const: wdog
+ - const: fatal
+ - const: ready
+ - const: handover
+ - const: stop-ack
+ - const: shutdown-ack
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8974-adsp-pil
+ then:
+ required:
+ - cx-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-adsp-pil
+ - qcom,msm8998-adsp-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
+ power-domain-names:
+ items:
+ - const: cx
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-slpi-pil
+ - qcom,msm8998-slpi-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: SSC-CX power domain
+ power-domain-names:
+ items:
+ - const: ssc_cx
+ required:
+ - px-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-mpss-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: Load State power domain
+ - description: CX power domain
+ - description: MX power domain
+ - description: MSS power domain
+ power-domain-names:
+ items:
+ - const: load_state
+ - const: cx
+ - const: mx
+ - const: mss
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8150-adsp-pas
+ - qcom,sm8150-cdsp-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: Load State power domain
+ - description: CX power domain
+ power-domain-names:
+ items:
+ - const: load_state
+ - const: cx
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8150-mpss-pas
+ - qcom,sm8350-mpss-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: Load State power domain
+ - description: CX power domain
+ - description: MSS power domain
+ power-domain-names:
+ items:
+ - const: load_state
+ - const: cx
+ - const: mss
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdx55-mpss-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: CX power domain
+ - description: MSS power domain
+ power-domain-names:
+ items:
+ - const: cx
+ - const: mss
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8180x-adsp-pas
+ - qcom,sc8180x-cdsp-pas
+ - qcom,sm8150-slpi-pas
+ - qcom,sm8250-adsp-pas
+ - qcom,sm8250-slpi-pas
+ - qcom,sm8350-adsp-pas
+ - qcom,sm8350-slpi-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: Load State power domain
+ - description: LCX power domain
+ - description: LMX power domain
+ power-domain-names:
+ items:
+ - const: load_state
+ - const: lcx
+ - const: lmx
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8350-cdsp-pas
+ then:
+ properties:
+ power-domains:
+ items:
+ - description: Load State power domain
+ - description: CX power domain
+ - description: MXC power domain
+ power-domain-names:
+ items:
+ - const: load_state
+ - const: cx
+ - const: mxc
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcs404-cdsp-pas
+ then:
+ properties:
+ resets:
+ items:
+ - description: CDSP restart
+ reset-names:
+ items:
+ - const: restart
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-mpss-pas
+ then:
+ properties:
+ resets:
+ items:
+ - description: MSS restart
+ - description: PDC reset
+ reset-names:
+ items:
+ - const: mss_restart
+ - const: pdc_reset
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ adsp {
+ compatible = "qcom,msm8974-adsp-pil";
+
+ interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc RPM_CXO_CLK>;
+ clock-names = "xo";
+
+ cx-supply = <&pm8841_s2>;
+
+ memory-region = <&adsp_region>;
+
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ smd-edge {
+ interrupts = <0 156 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 8 8>;
+ qcom,smd-edge = <1>;
+ };
+ };
diff --git a/Bindings/remoteproc/st,stm32-rproc.yaml b/Bindings/remoteproc/st,stm32-rproc.yaml
index 64afdcf..1e62256 100644
--- a/Bindings/remoteproc/st,stm32-rproc.yaml
+++ b/Bindings/remoteproc/st,stm32-rproc.yaml
@@ -72,7 +72,6 @@
- from local to remote, where ACK from the remote means that communnication
as been stopped on the remote side.
minItems: 1
- maxItems: 4
mbox-names:
items:
@@ -81,7 +80,6 @@
- const: shutdown
- const: detach
minItems: 1
- maxItems: 4
memory-region:
description:
diff --git a/Bindings/remoteproc/ti,k3-r5f-rproc.yaml b/Bindings/remoteproc/ti,k3-r5f-rproc.yaml
index d905d61..130fbaa 100644
--- a/Bindings/remoteproc/ti,k3-r5f-rproc.yaml
+++ b/Bindings/remoteproc/ti,k3-r5f-rproc.yaml
@@ -14,8 +14,12 @@
processor subsystems/clusters (R5FSS). The dual core cluster can be used
either in a LockStep mode providing safety/fault tolerance features or in a
Split mode providing two individual compute cores for doubling the compute
- capacity. These are used together with other processors present on the SoC
- to achieve various system level goals.
+ capacity on most SoCs. These are used together with other processors present
+ on the SoC to achieve various system level goals.
+
+ AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
+ called "Single-CPU" mode, where only Core0 is used, but with ability to use
+ Core1's TCMs as well.
Each Dual-Core R5F sub-system is represented as a single DTS node
representing the cluster, with a pair of child DT nodes representing
@@ -33,6 +37,7 @@
- ti,am654-r5fss
- ti,j721e-r5fss
- ti,j7200-r5fss
+ - ti,am64-r5fss
power-domains:
description: |
@@ -56,11 +61,12 @@
ti,cluster-mode:
$ref: /schemas/types.yaml#/definitions/uint32
- enum: [0, 1]
description: |
Configuration Mode for the Dual R5F cores within the R5F cluster.
- Should be either a value of 1 (LockStep mode) or 0 (Split mode),
- default is LockStep mode if omitted.
+ Should be either a value of 1 (LockStep mode) or 0 (Split mode) on
+ most SoCs (AM65x, J721E, J7200), default is LockStep mode if omitted;
+ and should be either a value of 0 (Split mode) or 2 (Single-CPU mode)
+ on AM64x SoCs, default is Split mode if omitted.
# R5F Processor Child Nodes:
# ==========================
@@ -97,6 +103,7 @@
- ti,am654-r5f
- ti,j721e-r5f
- ti,j7200-r5f
+ - ti,am64-r5f
reg:
items:
@@ -198,6 +205,20 @@
unevaluatedProperties: false
+if:
+ properties:
+ compatible:
+ enum:
+ - ti,am64-r5fss
+then:
+ properties:
+ ti,cluster-mode:
+ enum: [0, 2]
+else:
+ properties:
+ ti,cluster-mode:
+ enum: [0, 1]
+
required:
- compatible
- power-domains
diff --git a/Bindings/remoteproc/ti,keystone-rproc.txt b/Bindings/remoteproc/ti,keystone-rproc.txt
index 461dc1d..463a97c 100644
--- a/Bindings/remoteproc/ti,keystone-rproc.txt
+++ b/Bindings/remoteproc/ti,keystone-rproc.txt
@@ -48,7 +48,7 @@
bindings for the reset argument specifier as per SoC,
Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
for 66AK2HK/66AK2L/66AK2E SoCs or,
- Documentation/devicetree/bindings/reset/ti,sci-reset.txt
+ Documentation/devicetree/bindings/reset/ti,sci-reset.yaml
for 66AK2G SoCs
- interrupts: Should contain an entry for each value in 'interrupt-names'.
@@ -82,7 +82,7 @@
- power-domains: Should contain a phandle to a PM domain provider node
and an args specifier containing the DSP device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Optional properties:
--------------------
diff --git a/Bindings/remoteproc/ti,omap-remoteproc.yaml b/Bindings/remoteproc/ti,omap-remoteproc.yaml
index 73400bc..c6c1212 100644
--- a/Bindings/remoteproc/ti,omap-remoteproc.yaml
+++ b/Bindings/remoteproc/ti,omap-remoteproc.yaml
@@ -65,7 +65,7 @@
OMAP Mailbox specifier denoting the sub-mailbox, to be used for
communication with the remote processor. The specifier format is
as per the bindings,
- Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
+ Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
This property should match with the sub-mailbox node used in
the firmware image.
@@ -116,7 +116,6 @@
list, in the specified order, each representing the corresponding
internal RAM memory region.
minItems: 1
- maxItems: 3
items:
- const: l2ram
- const: l1pram
diff --git a/Bindings/remoteproc/ti,pru-rproc.yaml b/Bindings/remoteproc/ti,pru-rproc.yaml
index 63071ee..d7c3a78 100644
--- a/Bindings/remoteproc/ti,pru-rproc.yaml
+++ b/Bindings/remoteproc/ti,pru-rproc.yaml
@@ -36,6 +36,9 @@
enum:
- ti,am3356-pru # for AM335x SoC family (AM3356+ SoCs only)
- ti,am4376-pru # for AM437x SoC family (AM4376+ SoCs only)
+ - ti,am642-pru # for PRUs in K3 AM64x SoC family
+ - ti,am642-rtu # for RTUs in K3 AM64x SoC family
+ - ti,am642-tx-pru # for Tx_PRUs in K3 AM64x SoC family
- ti,am5728-pru # for AM57xx SoC family
- ti,k2g-pru # for 66AK2G SoC family
- ti,am654-pru # for PRUs in K3 AM65x SoC family
@@ -68,6 +71,7 @@
enum:
- ti,am654-rtu
- ti,j721e-rtu
+ - ti,am642-rtu
then:
properties:
$nodename:
@@ -79,6 +83,7 @@
enum:
- ti,am654-tx-pru
- ti,j721e-tx-pru
+ - ti,am642-tx-pru
then:
properties:
$nodename:
diff --git a/Bindings/reset/fsl,imx-src.yaml b/Bindings/reset/fsl,imx-src.yaml
index 27c5e34..b11ac53 100644
--- a/Bindings/reset/fsl,imx-src.yaml
+++ b/Bindings/reset/fsl,imx-src.yaml
@@ -59,7 +59,6 @@
- description: SRC interrupt
- description: CPU WDOG interrupts out of SRC
minItems: 1
- maxItems: 2
'#reset-cells':
const: 1
diff --git a/Bindings/reset/microchip,rst.yaml b/Bindings/reset/microchip,rst.yaml
new file mode 100644
index 0000000..370579a
--- /dev/null
+++ b/Bindings/reset/microchip,rst.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund <steen.hegelund@microchip.com>
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the following
+ functions
+ - One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+ pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+ const: microchip,sparx5-switch-reset
+
+ reg:
+ items:
+ - description: global control block registers
+
+ reg-names:
+ items:
+ - const: gcb
+
+ "#reset-cells":
+ const: 1
+
+ cpu-syscon:
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+ description: syscon used to access CPU reset
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+ - cpu-syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@11010008 {
+ compatible = "microchip,sparx5-switch-reset";
+ reg = <0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
+ };
+
diff --git a/Bindings/reset/ti,sci-reset.txt b/Bindings/reset/ti,sci-reset.txt
deleted file mode 100644
index 8b1cf02..0000000
--- a/Bindings/reset/ti,sci-reset.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-Texas Instruments System Control Interface (TI-SCI) Reset Controller
-=====================================================================
-
-Some TI SoCs contain a system controller (like the Power Management Micro
-Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
-the state of the various hardware modules present on the SoC. Communication
-between the host processor running an OS and the system controller happens
-through a protocol called TI System Control Interface (TI-SCI protocol).
-For TI SCI details, please refer to the document,
-Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
-
-TI-SCI Reset Controller Node
-============================
-This reset controller node uses the TI SCI protocol to perform the reset
-management of various hardware modules present on the SoC. Must be a child
-node of the associated TI-SCI system controller node.
-
-Required properties:
---------------------
- - compatible : Should be "ti,sci-reset"
- - #reset-cells : Should be 2. Please see the reset consumer node below for
- usage details.
-
-TI-SCI Reset Consumer Nodes
-===========================
-Each of the reset consumer nodes should have the following properties,
-in addition to their own properties.
-
-Required properties:
---------------------
- - resets : A phandle and reset specifier pair, one pair for each reset
- signal that affects the device, or that the device manages.
- The phandle should point to the TI-SCI reset controller node,
- and the reset specifier should have 2 cell-values. The first
- cell should contain the device ID. The second cell should
- contain the reset mask value used by system controller.
- Please refer to the protocol documentation for these values
- to be used for different devices,
- http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
-
-Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
-common reset controller usage by consumers.
-
-Example:
---------
-The following example demonstrates both a TI-SCI reset controller node and a
-consumer (a DSP device) on the 66AK2G SoC.
-
-pmmc: pmmc {
- compatible = "ti,k2g-sci";
-
- k2g_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
-};
-
-dsp0: dsp@10800000 {
- ...
- resets = <&k2g_reset 0x0046 0x1>;
- ...
-};
diff --git a/Bindings/reset/ti,sci-reset.yaml b/Bindings/reset/ti,sci-reset.yaml
new file mode 100644
index 0000000..4639d2c
--- /dev/null
+++ b/Bindings/reset/ti,sci-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI reset controller node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Some TI SoCs contain a system controller (like the Power Management Micro
+ Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+ the state of the various hardware modules present on the SoC. Communication
+ between the host processor running an OS and the system controller happens
+ through a protocol called TI System Control Interface (TI-SCI protocol).
+
+ This reset controller node uses the TI SCI protocol to perform the reset
+ management of various hardware modules present on the SoC. Must be a child
+ node of the associated TI-SCI system controller node.
+
+properties:
+ $nodename:
+ pattern: "^reset-controller$"
+
+ compatible:
+ const: ti,sci-reset
+
+ "#reset-cells":
+ const: 2
+ description:
+ The two cells represent values that the TI-SCI controller defines.
+
+ The first cell should contain the device ID.
+
+ The second cell should contain the reset mask corresponding to the device
+ used by system controller.
+
+ Please see http://processors.wiki.ti.com/index.php/TISCI for
+ protocol documentation for the values to be used for different devices.
+
+
+additionalProperties: false
+
+examples:
+ - |
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
diff --git a/Bindings/riscv/sifive-l2-cache.yaml b/Bindings/riscv/sifive-l2-cache.yaml
index 23b2276..1d38ff7 100644
--- a/Bindings/riscv/sifive-l2-cache.yaml
+++ b/Bindings/riscv/sifive-l2-cache.yaml
@@ -56,7 +56,6 @@
interrupts:
minItems: 3
- maxItems: 4
items:
- description: DirError interrupt
- description: DataError interrupt
diff --git a/Bindings/rng/intel,ixp46x-rng.yaml b/Bindings/rng/intel,ixp46x-rng.yaml
new file mode 100644
index 0000000..61963fa
--- /dev/null
+++ b/Bindings/rng/intel,ixp46x-rng.yaml
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/intel,ixp46x-rng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel IXP46x RNG bindings
+
+description: |
+ The Intel IXP46x has a random number generator at a fixed physical
+ location in memory. Each read is guaranteed to provide a unique
+ 32 bit random number.
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+properties:
+ compatible:
+ const: intel,ixp46x-rng
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ rng@70002100 {
+ compatible = "intel,ixp46x-rng";
+ reg = <0x70002100 4>;
+ };
+
diff --git a/Bindings/rng/mtk-rng.txt b/Bindings/rng/mtk-rng.txt
deleted file mode 100644
index dfdcb5c..0000000
--- a/Bindings/rng/mtk-rng.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Device-Tree bindings for Mediatek random number generator
-found in MediaTek SoC family
-
-Required properties:
-- compatible : Should be
- "mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622
- "mediatek,mt7629-rng", "mediatek,mt7623-rng" : for MT7629
- "mediatek,mt7623-rng" : for MT7623
- "mediatek,mt8516-rng", "mediatek,mt7623-rng" : for MT8516
-- clocks : list of clock specifiers, corresponding to
- entries in clock-names property;
-- clock-names : Should contain "rng" entries;
-- reg : Specifies base physical address and size of the registers
-
-Example:
-
-rng: rng@1020f000 {
- compatible = "mediatek,mt7623-rng";
- reg = <0 0x1020f000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_TRNG>;
- clock-names = "rng";
-};
diff --git a/Bindings/rng/mtk-rng.yaml b/Bindings/rng/mtk-rng.yaml
new file mode 100644
index 0000000..61888e0
--- /dev/null
+++ b/Bindings/rng/mtk-rng.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/rng/mtk-rng.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Random number generator
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+properties:
+ $nodename:
+ pattern: "^rng@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt7623-rng
+ - items:
+ - enum:
+ - mediatek,mt7622-rng
+ - mediatek,mt7629-rng
+ - mediatek,mt8365-rng
+ - mediatek,mt8516-rng
+ - const: mediatek,mt7623-rng
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rng
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt2701-clk.h>
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt7623-rng";
+ reg = <0x1020f000 0x1000>;
+ clocks = <&infracfg CLK_INFRA_TRNG>;
+ clock-names = "rng";
+ };
diff --git a/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml
index b1b0ee7..beeb90e 100644
--- a/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml
+++ b/Bindings/rtc/allwinner,sun6i-a31-rtc.yaml
@@ -32,7 +32,6 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: RTC Alarm 0
- description: RTC Alarm 1
diff --git a/Bindings/rtc/arm,pl031.yaml b/Bindings/rtc/arm,pl031.yaml
new file mode 100644
index 0000000..fa5f2ed
--- /dev/null
+++ b/Bindings/rtc/arm,pl031.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/arm,pl031.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Primecell PL031 Real Time Clock
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: arm,pl031
+ required:
+ - compatible
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - const: arm,pl031
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ start-year: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ rtc@10017000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x10017000 0x1000>;
+ clocks = <&pclk>;
+ clock-names = "apb_pclk";
+ };
diff --git a/Bindings/rtc/epson,rx8900.txt b/Bindings/rtc/epson,rx8900.txt
deleted file mode 100644
index 3f61e51..0000000
--- a/Bindings/rtc/epson,rx8900.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Real Time Clock driver for:
- - Epson RX8900
- - Micro Crystal rv8803
-
-Required properties:
-- compatible: should be: "microcrystal,rv8803" or "epson,rx8900"
-- reg : the I2C address of the device for I2C
-
-Optional properties:
-- epson,vdet-disable : boolean, if present will disable voltage detector.
- Should be set if no backup battery is used.
-- trickle-diode-disable : boolean, if present will disable internal trickle
- charger diode
-
-Example:
-
- rtc: rtc@32 {
- compatible = "epson,rx8900"
- reg = <0x32>;
- epson,vdet-disable;
- trickle-diode-disable;
- };
diff --git a/Bindings/rtc/epson,rx8900.yaml b/Bindings/rtc/epson,rx8900.yaml
new file mode 100644
index 0000000..29fe39b
--- /dev/null
+++ b/Bindings/rtc/epson,rx8900.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/epson,rx8900.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EPSON RX8900 / Microcrystal RV8803 Real-Time Clock DT bindings
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - epson,rx8900
+ - microcrystal,rv8803
+
+ reg:
+ maxItems: 1
+
+ epson,vdet-disable:
+ type: boolean
+ description: |
+ Disable voltage detector. Should be set if no backup battery is used.
+
+ trickle-diode-disable: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ epson,vdet-disable;
+ trickle-diode-disable;
+ };
+ };
diff --git a/Bindings/rtc/faraday,ftrtc010.txt b/Bindings/rtc/faraday,ftrtc010.txt
deleted file mode 100644
index e3938f5..0000000
--- a/Bindings/rtc/faraday,ftrtc010.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* Faraday Technology FTRTC010 Real Time Clock
-
-This RTC appears in for example the Storlink Gemini family of
-SoCs.
-
-Required properties:
-- compatible : Should be one of:
- "faraday,ftrtc010"
- "cortina,gemini-rtc", "faraday,ftrtc010"
-
-Optional properties:
-- clocks: when present should contain clock references to the
- PCLK and EXTCLK clocks. Faraday calls the later CLK1HZ and
- says the clock should be 1 Hz, but implementers actually seem
- to choose different clocks here, like Cortina who chose
- 32768 Hz (a typical low-power clock).
-- clock-names: should name the clocks "PCLK" and "EXTCLK"
- respectively.
-
-Examples:
-
-rtc@45000000 {
- compatible = "cortina,gemini-rtc";
- reg = <0x45000000 0x100>;
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&foo 0>, <&foo 1>;
- clock-names = "PCLK", "EXTCLK";
-};
diff --git a/Bindings/rtc/faraday,ftrtc010.yaml b/Bindings/rtc/faraday,ftrtc010.yaml
new file mode 100644
index 0000000..657c13b
--- /dev/null
+++ b/Bindings/rtc/faraday,ftrtc010.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/faraday,ftrtc010.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Faraday Technology FTRTC010 Real Time Clock
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ This RTC appears in for example the Storlink Gemini family of SoCs.
+
+properties:
+ compatible:
+ oneOf:
+ - const: faraday,ftrtc010
+ - items:
+ - const: cortina,gemini-rtc
+ - const: faraday,ftrtc010
+
+ resets:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ items:
+ - description: PCLK clocks
+ - description: EXTCLK clocks. Faraday calls it CLK1HZ and says the clock
+ should be 1 Hz, but implementers actually seem to choose different
+ clocks here, like Cortina who chose 32768 Hz (a typical low-power clock).
+
+ clock-names:
+ items:
+ - const: "PCLK"
+ - const: "EXTCLK"
+
+required:
+ - compatible
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ rtc@45000000 {
+ compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
+ reg = <0x45000000 0x100>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&foo 0>, <&foo 1>;
+ clock-names = "PCLK", "EXTCLK";
+ };
diff --git a/Bindings/rtc/imxdi-rtc.yaml b/Bindings/rtc/imxdi-rtc.yaml
index 06bd737..4807c95 100644
--- a/Bindings/rtc/imxdi-rtc.yaml
+++ b/Bindings/rtc/imxdi-rtc.yaml
@@ -21,7 +21,6 @@
- description: rtc alarm interrupt
- description: dryice security violation interrupt
minItems: 1
- maxItems: 2
clocks:
maxItems: 1
diff --git a/Bindings/rtc/nxp,pcf8563.yaml b/Bindings/rtc/nxp,pcf8563.yaml
new file mode 100644
index 0000000..a98b727
--- /dev/null
+++ b/Bindings/rtc/nxp,pcf8563.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nxp,pcf8563.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Philips PCF8563/Epson RTC8564 Real Time Clock
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - epson,rtc8564
+ - microcrystal,rv8564
+ - nxp,pca8565
+ - nxp,pcf8563
+ - nxp,pcf85263
+ - nxp,pcf85363
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ start-year: true
+ wakeup-source: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+ };
+...
diff --git a/Bindings/rtc/pcf85363.txt b/Bindings/rtc/pcf85363.txt
deleted file mode 100644
index 94adc1c..0000000
--- a/Bindings/rtc/pcf85363.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-NXP PCF85263/PCF85363 Real Time Clock
-============================
-
-Required properties:
-- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363".
-- reg: I2C address for chip.
-
-Optional properties:
-- interrupts: IRQ line for the RTC (not implemented).
-
-Example:
-
-pcf85363: pcf85363@51 {
- compatible = "nxp,pcf85363";
- reg = <0x51>;
-};
-
diff --git a/Bindings/rtc/pcf8563.txt b/Bindings/rtc/pcf8563.txt
deleted file mode 100644
index 0a900f7..0000000
--- a/Bindings/rtc/pcf8563.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-* Philips PCF8563/Epson RTC8564 Real Time Clock
-
-Philips PCF8563/Epson RTC8564 Real Time Clock
-
-Required properties:
-- compatible: Should contain "nxp,pcf8563",
- "epson,rtc8564" or
- "microcrystal,rv8564" or
- "nxp,pca8565"
-- reg: I2C address for chip.
-
-Optional property:
-- #clock-cells: Should be 0.
-- clock-output-names:
- overwrite the default clock name "pcf8563-clkout"
-
-Example:
-
-pcf8563: pcf8563@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- #clock-cells = <0>;
-};
-
-device {
-...
- clocks = <&pcf8563>;
-...
-};
diff --git a/Bindings/rtc/rtc-m41t80.txt b/Bindings/rtc/rtc-m41t80.txt
index c746cb2..cdd196b 100644
--- a/Bindings/rtc/rtc-m41t80.txt
+++ b/Bindings/rtc/rtc-m41t80.txt
@@ -21,10 +21,19 @@
clock name
- wakeup-source: Enables wake up of host system on alarm
+Optional child node:
+- clock: Provide this if the square wave pin is used as boot-enabled fixed clock.
+
Example:
rtc@68 {
compatible = "st,m41t80";
reg = <0x68>;
interrupt-parent = <&UIC0>;
interrupts = <0x9 0x8>;
+
+ clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
};
diff --git a/Bindings/rtc/ti,bq32000.yaml b/Bindings/rtc/ti,bq32000.yaml
new file mode 100644
index 0000000..bf9c1c4
--- /dev/null
+++ b/Bindings/rtc/ti,bq32000.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/ti,bq32000.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI BQ32000 I2C Serial Real-Time Clock
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ const: ti,bq32000
+
+ reg:
+ const: 0x68
+
+ interrupts:
+ maxItems: 1
+
+ start-year: true
+
+ trickle-resistor-ohms:
+ enum: [ 1120, 20180 ]
+
+ trickle-diode-disable: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bq32000: rtc@68 {
+ compatible = "ti,bq32000";
+ reg = <0x68>;
+ trickle-resistor-ohms = <1120>;
+ };
+ };
diff --git a/Bindings/rtc/ti,bq32k.txt b/Bindings/rtc/ti,bq32k.txt
deleted file mode 100644
index e204906..0000000
--- a/Bindings/rtc/ti,bq32k.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* TI BQ32000 I2C Serial Real-Time Clock
-
-Required properties:
-- compatible: Should contain "ti,bq32000".
-- reg: I2C address for chip
-
-Optional properties:
-- trickle-resistor-ohms : Selected resistor for trickle charger
- Values usable are 1120 and 20180
- Should be given if trickle charger should be enabled
-- trickle-diode-disable : Do not use internal trickle charger diode
- Should be given if internal trickle charger diode should be disabled
-Example:
- bq32000: rtc@68 {
- compatible = "ti,bq32000";
- trickle-resistor-ohms = <1120>;
- reg = <0x68>;
- };
diff --git a/Bindings/rtc/xlnx,zynqmp-rtc.yaml b/Bindings/rtc/xlnx,zynqmp-rtc.yaml
new file mode 100644
index 0000000..bdb72d3
--- /dev/null
+++ b/Bindings/rtc/xlnx,zynqmp-rtc.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
+
+description:
+ RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
+ The RTC controller has separate IRQ lines for seconds and alarm.
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+
+ interrupt-names:
+ items:
+ - const: alarm
+ - const: sec
+
+ calibration:
+ description: |
+ calibration value for 1 sec period which will
+ be programmed directly to calibration register.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x1
+ maximum: 0x1FFFFF
+ default: 0x198233
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rtc: rtc@ffa60000 {
+ compatible = "xlnx,zynqmp-rtc";
+ reg = <0x0 0xffa60000 0x0 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 26 4>, <0 27 4>;
+ interrupt-names = "alarm", "sec";
+ calibration = <0x198233>;
+ };
+ };
diff --git a/Bindings/rtc/xlnx-rtc.txt b/Bindings/rtc/xlnx-rtc.txt
deleted file mode 100644
index 0df6f01..0000000
--- a/Bindings/rtc/xlnx-rtc.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
-
-RTC controller for the Xilinx Zynq MPSoC Real Time Clock
-Separate IRQ lines for seconds and alarm
-
-Required properties:
-- compatible: Should be "xlnx,zynqmp-rtc"
-- reg: Physical base address of the controller and length
- of memory mapped region.
-- interrupts: IRQ lines for the RTC.
-- interrupt-names: interrupt line names eg. "sec" "alarm"
-
-Optional:
-- calibration: calibration value for 1 sec period which will
- be programmed directly to calibration register
-
-Example:
-rtc: rtc@ffa60000 {
- compatible = "xlnx,zynqmp-rtc";
- reg = <0x0 0xffa60000 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <0 26 4>, <0 27 4>;
- interrupt-names = "alarm", "sec";
- calibration = <0x198233>;
-};
diff --git a/Bindings/serial/8250.yaml b/Bindings/serial/8250.yaml
index 41f57c4..a0bf061 100644
--- a/Bindings/serial/8250.yaml
+++ b/Bindings/serial/8250.yaml
@@ -10,7 +10,7 @@
- devicetree@vger.kernel.org
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
- if:
anyOf:
- required:
diff --git a/Bindings/serial/8250_omap.yaml b/Bindings/serial/8250_omap.yaml
new file mode 100644
index 0000000..1c826fc
--- /dev/null
+++ b/Bindings/serial/8250_omap.yaml
@@ -0,0 +1,118 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/8250_omap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for 8250 compliant UARTs on TI's OMAP2+ and K3 SoCs
+
+maintainers:
+ - Vignesh Raghavendra <vigneshr@ti.com>
+
+allOf:
+ - $ref: /schemas/serial/serial.yaml#
+ - $ref: /schemas/serial/rs485.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - ti,am3352-uart
+ - ti,am4372-uart
+ - ti,am654-uart
+ - ti,dra742-uart
+ - ti,omap2-uart
+ - ti,omap3-uart
+ - ti,omap4-uart
+ - items:
+ - enum:
+ - ti,am64-uart
+ - ti,j721e-uart
+ - const: ti,am654-uart
+
+ ti,hwmods:
+ description:
+ Must be "uart<n>", n being the instance number (1-based)
+ This property is applicable only on legacy platforms mainly omap2/3
+ and ti81xx and should not be used on other platforms.
+ $ref: /schemas/types.yaml#/definitions/string
+ deprecated: true
+
+ dmas:
+ minItems: 1
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ description:
+ First entry is module IRQ required for normal IO operation.
+ Second entry is optional and corresponds to system wakeup IRQ
+ where supported.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fclk
+
+ rts-gpios: true
+ cts-gpios: true
+ dtr-gpios: true
+ dsr-gpios: true
+ rng-gpios: true
+ dcd-gpios: true
+ rs485-rts-delay: true
+ rs485-rts-active-low: true
+ rs485-rx-during-tx: true
+ rs485-rts-active-high: true
+ linux,rs485-enabled-at-boot-time: true
+ rts-gpio: true
+ power-domains: true
+ clock-frequency: true
+ current-speed: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+if:
+ properties:
+ compatible:
+ oneOf:
+ - const: ti,omap2-uart
+ - const: ti,omap3-uart
+ - const: ti,omap4-uart
+
+then:
+ properties:
+ ti,hwmods:
+ items:
+ - pattern: "^uart([1-9])$"
+
+else:
+ properties:
+ ti,hwmods: false
+
+examples:
+ - |
+ serial@49042000 {
+ compatible = "ti,omap3-uart";
+ reg = <0x49042000 0x400>;
+ interrupts = <80>;
+ dmas = <&sdma 81 &sdma 82>;
+ dma-names = "tx", "rx";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
diff --git a/Bindings/serial/amlogic,meson-uart.yaml b/Bindings/serial/amlogic,meson-uart.yaml
index 75ebc99..7487aa6 100644
--- a/Bindings/serial/amlogic,meson-uart.yaml
+++ b/Bindings/serial/amlogic,meson-uart.yaml
@@ -55,6 +55,11 @@
- const: pclk
- const: baud
+ fifo-size:
+ description: The fifo size supported by the UART channel.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [64, 128]
+
required:
- compatible
- reg
diff --git a/Bindings/serial/brcm,bcm7271-uart.yaml b/Bindings/serial/brcm,bcm7271-uart.yaml
index 46c6274..6d17658 100644
--- a/Bindings/serial/brcm,bcm7271-uart.yaml
+++ b/Bindings/serial/brcm,bcm7271-uart.yaml
@@ -10,7 +10,7 @@
- Al Cooper <alcooperx@gmail.com>
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
description: |+
The Broadcom UART is based on the basic 8250 UART but with
diff --git a/Bindings/serial/fsl-imx-uart.yaml b/Bindings/serial/fsl-imx-uart.yaml
index 2b06c6c..9d94929 100644
--- a/Bindings/serial/fsl-imx-uart.yaml
+++ b/Bindings/serial/fsl-imx-uart.yaml
@@ -71,6 +71,18 @@
received, and that the peripheral should invert its input using the
INVR registers.
+ fsl,dma-info:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 2
+ description: |
+ First cell contains the size of DMA buffer chunks, second cell contains
+ the amount of chunks used for the device. Multiplying both numbers is
+ the total size of memory used for receiving data.
+ When not being configured the system will use default settings, which
+ are sensible for most use cases. If you need low latency processing on
+ slow connections this needs to be configured appropriately.
+
uart-has-rtscts: true
rs485-rts-delay: true
diff --git a/Bindings/serial/fsl-lpuart.yaml b/Bindings/serial/fsl-lpuart.yaml
index bd21060..a90c971 100644
--- a/Bindings/serial/fsl-lpuart.yaml
+++ b/Bindings/serial/fsl-lpuart.yaml
@@ -36,14 +36,12 @@
- description: ipg clock
- description: baud clock
minItems: 1
- maxItems: 2
clock-names:
items:
- const: ipg
- const: baud
minItems: 1
- maxItems: 2
dmas:
items:
diff --git a/Bindings/serial/ingenic,uart.yaml b/Bindings/serial/ingenic,uart.yaml
index 7748d8c..b432d4d 100644
--- a/Bindings/serial/ingenic,uart.yaml
+++ b/Bindings/serial/ingenic,uart.yaml
@@ -10,7 +10,7 @@
- Paul Cercueil <paul@crapouillou.net>
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
properties:
$nodename:
diff --git a/Bindings/serial/mvebu-uart.txt b/Bindings/serial/mvebu-uart.txt
index b7e0e32..2d0dbdf 100644
--- a/Bindings/serial/mvebu-uart.txt
+++ b/Bindings/serial/mvebu-uart.txt
@@ -5,10 +5,10 @@
- compatible:
- "marvell,armada-3700-uart" for the standard variant of the UART
(32 bytes FIFO, no DMA, level interrupts, 8-bit access to the
- FIFO, baudrate limited to 230400).
+ FIFO), called also UART1.
- "marvell,armada-3700-uart-ext" for the extended variant of the
UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
- accesses to the FIFO, baudrate unlimited by the dividers).
+ accesses to the FIFO), called also UART2.
- reg: offset and length of the register set for the device.
- clocks: UART reference clock used to derive the baudrate. If no clock
is provided (possible only with the "marvell,armada-3700-uart"
@@ -33,7 +33,7 @@
Example:
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
- reg = <0x12000 0x200>;
+ reg = <0x12000 0x18>;
clocks = <&xtalclk>;
interrupts =
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
diff --git a/Bindings/serial/omap_serial.txt b/Bindings/serial/omap_serial.txt
deleted file mode 100644
index c2db8ca..0000000
--- a/Bindings/serial/omap_serial.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-OMAP UART controller
-
-Required properties:
-- compatible : should be "ti,am64-uart", "ti,am654-uart" for AM64 controllers
-- compatible : should be "ti,j721e-uart", "ti,am654-uart" for J721E controllers
-- compatible : should be "ti,am654-uart" for AM654 controllers
-- compatible : should be "ti,omap2-uart" for OMAP2 controllers
-- compatible : should be "ti,omap3-uart" for OMAP3 controllers
-- compatible : should be "ti,omap4-uart" for OMAP4 controllers
-- compatible : should be "ti,am4372-uart" for AM437x controllers
-- compatible : should be "ti,am3352-uart" for AM335x controllers
-- compatible : should be "ti,dra742-uart" for DRA7x controllers
-- reg : address and length of the register space
-- interrupts or interrupts-extended : Should contain the uart interrupt
- specifier or both the interrupt
- controller phandle and interrupt
- specifier.
-- ti,hwmods : Must be "uart<n>", n being the instance number (1-based)
-
-Optional properties:
-- clock-frequency : frequency of the clock input to the UART
-- dmas : DMA specifier, consisting of a phandle to the DMA controller
- node and a DMA channel number.
-- dma-names : "rx" for receive channel, "tx" for transmit channel.
-- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
-- rs485-rts-active-high: drive RTS high when sending (default is low).
-- clocks: phandle to the functional clock as per
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-Example:
-
- uart4: serial@49042000 {
- compatible = "ti,omap3-uart";
- reg = <0x49042000 0x400>;
- interrupts = <80>;
- dmas = <&sdma 81 &sdma 82>;
- dma-names = "tx", "rx";
- ti,hwmods = "uart4";
- clock-frequency = <48000000>;
- };
diff --git a/Bindings/serial/pl011.yaml b/Bindings/serial/pl011.yaml
index 1f8e9f2..5ea00f8 100644
--- a/Bindings/serial/pl011.yaml
+++ b/Bindings/serial/pl011.yaml
@@ -10,7 +10,7 @@
- Rob Herring <robh@kernel.org>
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
@@ -24,12 +24,9 @@
properties:
compatible:
- oneOf:
- - items:
- - const: arm,pl011
- - const: arm,primecell
- - items:
- - const: arm,primecell
+ items:
+ - const: arm,pl011
+ - const: arm,primecell
reg:
maxItems: 1
@@ -103,7 +100,7 @@
poll-rate-ms: [ auto-poll ]
poll-timeout-ms: [ auto-poll ]
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/Bindings/serial/qca,ar9330-uart.yaml b/Bindings/serial/qca,ar9330-uart.yaml
index a344369..a644e5a 100644
--- a/Bindings/serial/qca,ar9330-uart.yaml
+++ b/Bindings/serial/qca,ar9330-uart.yaml
@@ -10,7 +10,7 @@
- Oleksij Rempel <o.rempel@pengutronix.de>
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
properties:
compatible:
@@ -35,7 +35,7 @@
- clocks
- clock-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/Bindings/serial/renesas,em-uart.yaml b/Bindings/serial/renesas,em-uart.yaml
index 82aefdb..e98ec48 100644
--- a/Bindings/serial/renesas,em-uart.yaml
+++ b/Bindings/serial/renesas,em-uart.yaml
@@ -35,7 +35,7 @@
- clocks
- clock-names
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/Bindings/serial/renesas,scif.yaml b/Bindings/serial/renesas,scif.yaml
index 22d7682..6b8731f 100644
--- a/Bindings/serial/renesas,scif.yaml
+++ b/Bindings/serial/renesas,scif.yaml
@@ -64,6 +64,10 @@
- const: renesas,rcar-gen3-scif # R-Car Gen3 and RZ/G2
- const: renesas,scif # generic SCIF compatible UART
+ - items:
+ - enum:
+ - renesas,scif-r9a07g044 # RZ/G2{L,LC}
+
reg:
maxItems: 1
diff --git a/Bindings/serial/samsung_uart.yaml b/Bindings/serial/samsung_uart.yaml
index 97ec8a0..f064e5b 100644
--- a/Bindings/serial/samsung_uart.yaml
+++ b/Bindings/serial/samsung_uart.yaml
@@ -44,7 +44,6 @@
clock-names:
description: N = 0 is allowed for SoCs without internal baud clock mux.
minItems: 2
- maxItems: 5
items:
- const: uart
- pattern: '^clk_uart_baud[0-3]$'
@@ -82,7 +81,7 @@
unevaluatedProperties: false
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
- if:
properties:
diff --git a/Bindings/serial/serial.yaml b/Bindings/serial/serial.yaml
index 2fdf4ed..c75ba3f 100644
--- a/Bindings/serial/serial.yaml
+++ b/Bindings/serial/serial.yaml
@@ -23,6 +23,8 @@
$nodename:
pattern: "^serial(@.*)?$"
+ label: true
+
cts-gpios:
maxItems: 1
description:
diff --git a/Bindings/serial/sifive-serial.yaml b/Bindings/serial/sifive-serial.yaml
index 5fa94da..09aae43 100644
--- a/Bindings/serial/sifive-serial.yaml
+++ b/Bindings/serial/sifive-serial.yaml
@@ -12,7 +12,7 @@
- Palmer Dabbelt <palmer@sifive.com>
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
properties:
compatible:
@@ -49,7 +49,7 @@
- interrupts
- clocks
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
diff --git a/Bindings/serial/snps-dw-apb-uart.yaml b/Bindings/serial/snps-dw-apb-uart.yaml
index 87ef1e2..b49fda5 100644
--- a/Bindings/serial/snps-dw-apb-uart.yaml
+++ b/Bindings/serial/snps-dw-apb-uart.yaml
@@ -10,7 +10,7 @@
- Rob Herring <robh@kernel.org>
allOf:
- - $ref: /schemas/serial.yaml#
+ - $ref: serial.yaml#
properties:
compatible:
@@ -23,6 +23,7 @@
- items:
- enum:
- rockchip,px30-uart
+ - rockchip,rk1808-uart
- rockchip,rk3036-uart
- rockchip,rk3066-uart
- rockchip,rk3188-uart
@@ -31,6 +32,7 @@
- rockchip,rk3328-uart
- rockchip,rk3368-uart
- rockchip,rk3399-uart
+ - rockchip,rk3568-uart
- rockchip,rv1108-uart
- const: snps,dw-apb-uart
- items:
diff --git a/Bindings/serial/st,stm32-uart.yaml b/Bindings/serial/st,stm32-uart.yaml
index 71a6426..f50f4ca 100644
--- a/Bindings/serial/st,stm32-uart.yaml
+++ b/Bindings/serial/st,stm32-uart.yaml
@@ -112,8 +112,7 @@
- interrupts
- clocks
-additionalProperties:
- type: object
+unevaluatedProperties: false
examples:
- |
diff --git a/Bindings/soc/mediatek/pwrap.txt b/Bindings/soc/mediatek/pwrap.txt
index 8051c17..d74a7a5 100644
--- a/Bindings/soc/mediatek/pwrap.txt
+++ b/Bindings/soc/mediatek/pwrap.txt
@@ -27,6 +27,7 @@
"mediatek,mt8135-pwrap" for MT8135 SoCs
"mediatek,mt8173-pwrap" for MT8173 SoCs
"mediatek,mt8183-pwrap" for MT8183 SoCs
+ "mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC
- reg-names: Must include the following entries:
diff --git a/Bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
new file mode 100644
index 0000000..2cd3bc6
--- /dev/null
+++ b/Bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description: |
+ The PolarFire SoC system controller is communicated with via a mailbox.
+ This document describes the bindings for the client portion of that mailbox.
+
+
+properties:
+ mboxes:
+ maxItems: 1
+
+ compatible:
+ const: microchip,polarfire-soc-sys-controller
+
+required:
+ - compatible
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ syscontroller: syscontroller {
+ compatible = "microchip,polarfire-soc-sys-controller";
+ mboxes = <&mbox 0>;
+ };
diff --git a/Bindings/soc/qcom/qcom,geni-se.yaml b/Bindings/soc/qcom/qcom,geni-se.yaml
index 8467195..4663c2b 100644
--- a/Bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Bindings/soc/qcom/qcom,geni-se.yaml
@@ -164,7 +164,6 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: UART core irq
- description: Wakeup irq (RX GPIO)
diff --git a/Bindings/soc/qcom/qcom,smd-rpm.yaml b/Bindings/soc/qcom/qcom,smd-rpm.yaml
index 2684f22..d511f01 100644
--- a/Bindings/soc/qcom/qcom,smd-rpm.yaml
+++ b/Bindings/soc/qcom/qcom,smd-rpm.yaml
@@ -32,12 +32,14 @@
enum:
- qcom,rpm-apq8084
- qcom,rpm-ipq6018
+ - qcom,rpm-msm8226
- qcom,rpm-msm8916
- qcom,rpm-msm8974
- qcom,rpm-msm8976
- qcom,rpm-msm8996
- qcom,rpm-msm8998
- qcom,rpm-sdm660
+ - qcom,rpm-sm6125
- qcom,rpm-qcs404
qcom,smd-channels:
diff --git a/Bindings/soc/rockchip/grf.txt b/Bindings/soc/rockchip/grf.txt
deleted file mode 100644
index f96511a..0000000
--- a/Bindings/soc/rockchip/grf.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Rockchip General Register Files (GRF)
-
-The general register file will be used to do static set by software, which
-is composed of many registers for system control.
-
-From RK3368 SoCs, the GRF is divided into two sections,
-- GRF, used for general non-secure system,
-- SGRF, used for general secure system,
-- PMUGRF, used for always on system
-
-On RK3328 SoCs, the GRF adds a section for USB2PHYGRF,
-
-ON RK3308 SoC, the GRF is divided into four sections:
-- GRF, used for general non-secure system,
-- SGRF, used for general secure system,
-- DETECTGRF, used for audio codec system,
-- COREGRF, used for pvtm,
-
-Required Properties:
-
-- compatible: GRF should be one of the following:
- - "rockchip,px30-grf", "syscon": for px30
- - "rockchip,rk3036-grf", "syscon": for rk3036
- - "rockchip,rk3066-grf", "syscon": for rk3066
- - "rockchip,rk3188-grf", "syscon": for rk3188
- - "rockchip,rk3228-grf", "syscon": for rk3228
- - "rockchip,rk3288-grf", "syscon": for rk3288
- - "rockchip,rk3308-grf", "syscon": for rk3308
- - "rockchip,rk3328-grf", "syscon": for rk3328
- - "rockchip,rk3368-grf", "syscon": for rk3368
- - "rockchip,rk3399-grf", "syscon": for rk3399
- - "rockchip,rv1108-grf", "syscon": for rv1108
-- compatible: DETECTGRF should be one of the following:
- - "rockchip,rk3308-detect-grf", "syscon": for rk3308
-- compatilbe: COREGRF should be one of the following:
- - "rockchip,rk3308-core-grf", "syscon": for rk3308
-- compatible: PMUGRF should be one of the following:
- - "rockchip,px30-pmugrf", "syscon": for px30
- - "rockchip,rk3368-pmugrf", "syscon": for rk3368
- - "rockchip,rk3399-pmugrf", "syscon": for rk3399
-- compatible: SGRF should be one of the following:
- - "rockchip,rk3288-sgrf", "syscon": for rk3288
-- compatible: USB2PHYGRF should be one of the following:
- - "rockchip,px30-usb2phy-grf", "syscon": for px30
- - "rockchip,rk3328-usb2phy-grf", "syscon": for rk3328
-- compatible: USBGRF should be one of the following:
- - "rockchip,rv1108-usbgrf", "syscon": for rv1108
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-Example: GRF and PMUGRF of RK3399 SoCs
-
- pmugrf: syscon@ff320000 {
- compatible = "rockchip,rk3399-pmugrf", "syscon";
- reg = <0x0 0xff320000 0x0 0x1000>;
- };
-
- grf: syscon@ff770000 {
- compatible = "rockchip,rk3399-grf", "syscon";
- reg = <0x0 0xff770000 0x0 0x10000>;
- };
diff --git a/Bindings/soc/rockchip/grf.yaml b/Bindings/soc/rockchip/grf.yaml
new file mode 100644
index 0000000..62fa72c
--- /dev/null
+++ b/Bindings/soc/rockchip/grf.yaml
@@ -0,0 +1,261 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/rockchip/grf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip General Register Files (GRF)
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - rockchip,rk3288-sgrf
+ - rockchip,rv1108-pmugrf
+ - rockchip,rv1108-usbgrf
+ - const: syscon
+ - items:
+ - enum:
+ - rockchip,px30-grf
+ - rockchip,px30-pmugrf
+ - rockchip,px30-usb2phy-grf
+ - rockchip,rk3036-grf
+ - rockchip,rk3066-grf
+ - rockchip,rk3188-grf
+ - rockchip,rk3228-grf
+ - rockchip,rk3288-grf
+ - rockchip,rk3308-core-grf
+ - rockchip,rk3308-detect-grf
+ - rockchip,rk3308-grf
+ - rockchip,rk3308-usb2phy-grf
+ - rockchip,rk3328-grf
+ - rockchip,rk3328-usb2phy-grf
+ - rockchip,rk3368-grf
+ - rockchip,rk3368-pmugrf
+ - rockchip,rk3399-grf
+ - rockchip,rk3399-pmugrf
+ - rockchip,rk3568-grf
+ - rockchip,rk3568-pmugrf
+ - rockchip,rv1108-grf
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties:
+ type: object
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,px30-grf
+
+ then:
+ properties:
+ lvds:
+ description:
+ Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3288-grf
+
+ then:
+ properties:
+ edp-phy:
+ description:
+ Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,rk3066-grf
+ - rockchip,rk3188-grf
+ - rockchip,rk3288-grf
+
+ then:
+ properties:
+ usbphy:
+ type: object
+
+ $ref: "/schemas/phy/rockchip-usb-phy.yaml#"
+
+ unevaluatedProperties: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3328-grf
+
+ then:
+ properties:
+ gpio:
+ type: object
+
+ $ref: "/schemas/gpio/rockchip,rk3328-grf-gpio.yaml#"
+
+ unevaluatedProperties: false
+
+ power-controller:
+ type: object
+
+ $ref: "/schemas/power/rockchip,power-controller.yaml#"
+
+ unevaluatedProperties: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: rockchip,rk3399-grf
+
+ then:
+ properties:
+ mipi-dphy-rx0:
+ type: object
+
+ $ref: "/schemas/phy/rockchip-mipi-dphy-rx0.yaml#"
+
+ unevaluatedProperties: false
+
+ pcie-phy:
+ description:
+ Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
+
+ patternProperties:
+ "phy@[0-9a-f]+$":
+ description:
+ Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,px30-pmugrf
+ - rockchip,rk3036-grf
+ - rockchip,rk3308-grf
+ - rockchip,rk3368-pmugrf
+
+ then:
+ properties:
+ reboot-mode:
+ type: object
+
+ $ref: "/schemas/power/reset/syscon-reboot-mode.yaml#"
+
+ unevaluatedProperties: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,px30-usb2phy-grf
+ - rockchip,rk3228-grf
+ - rockchip,rk3308-usb2phy-grf
+ - rockchip,rk3328-usb2phy-grf
+ - rockchip,rk3399-grf
+ - rockchip,rv1108-grf
+
+ then:
+ required:
+ - "#address-cells"
+ - "#size-cells"
+
+ patternProperties:
+ "usb2phy@[0-9a-f]+$":
+ type: object
+
+ $ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#"
+
+ unevaluatedProperties: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - rockchip,px30-pmugrf
+ - rockchip,px30-grf
+ - rockchip,rk3228-grf
+ - rockchip,rk3288-grf
+ - rockchip,rk3328-grf
+ - rockchip,rk3368-pmugrf
+ - rockchip,rk3368-grf
+ - rockchip,rk3399-pmugrf
+ - rockchip,rk3399-grf
+
+ then:
+ properties:
+ io-domains:
+ description:
+ Documentation/devicetree/bindings/power/rockchip-io-domain.txt
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/rk3399-power.h>
+ grf: syscon@ff770000 {
+ compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
+ reg = <0xff770000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mipi_dphy_rx0: mipi-dphy-rx0 {
+ compatible = "rockchip,rk3399-mipi-dphy-rx0";
+ clocks = <&cru SCLK_MIPIDPHY_REF>,
+ <&cru SCLK_DPHY_RX0_CFG>,
+ <&cru PCLK_VIO_GRF>;
+ clock-names = "dphy-ref", "dphy-cfg", "grf";
+ power-domains = <&power RK3399_PD_VIO>;
+ #phy-cells = <0>;
+ };
+
+ u2phy0: usb2phy@e450 {
+ compatible = "rockchip,rk3399-usb2phy";
+ reg = <0xe450 0x10>;
+ clocks = <&cru SCLK_USB2PHY0_REF>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_usbphy0_480m";
+
+ u2phy0_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "linestate";
+ };
+
+ u2phy0_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ };
+ };
+ };
diff --git a/Bindings/soc/rockchip/power_domain.txt b/Bindings/soc/rockchip/power_domain.txt
deleted file mode 100644
index 8304ece..0000000
--- a/Bindings/soc/rockchip/power_domain.txt
+++ /dev/null
@@ -1,136 +0,0 @@
-* Rockchip Power Domains
-
-Rockchip processors include support for multiple power domains which can be
-powered up/down by software based on different application scenes to save power.
-
-Required properties for power domain controller:
-- compatible: Should be one of the following.
- "rockchip,px30-power-controller" - for PX30 SoCs.
- "rockchip,rk3036-power-controller" - for RK3036 SoCs.
- "rockchip,rk3066-power-controller" - for RK3066 SoCs.
- "rockchip,rk3128-power-controller" - for RK3128 SoCs.
- "rockchip,rk3188-power-controller" - for RK3188 SoCs.
- "rockchip,rk3228-power-controller" - for RK3228 SoCs.
- "rockchip,rk3288-power-controller" - for RK3288 SoCs.
- "rockchip,rk3328-power-controller" - for RK3328 SoCs.
- "rockchip,rk3366-power-controller" - for RK3366 SoCs.
- "rockchip,rk3368-power-controller" - for RK3368 SoCs.
- "rockchip,rk3399-power-controller" - for RK3399 SoCs.
-- #power-domain-cells: Number of cells in a power-domain specifier.
- Should be 1 for multiple PM domains.
-- #address-cells: Should be 1.
-- #size-cells: Should be 0.
-
-Required properties for power domain sub nodes:
-- reg: index of the power domain, should use macros in:
- "include/dt-bindings/power/px30-power.h" - for PX30 type power domain.
- "include/dt-bindings/power/rk3036-power.h" - for RK3036 type power domain.
- "include/dt-bindings/power/rk3066-power.h" - for RK3066 type power domain.
- "include/dt-bindings/power/rk3128-power.h" - for RK3128 type power domain.
- "include/dt-bindings/power/rk3188-power.h" - for RK3188 type power domain.
- "include/dt-bindings/power/rk3228-power.h" - for RK3228 type power domain.
- "include/dt-bindings/power/rk3288-power.h" - for RK3288 type power domain.
- "include/dt-bindings/power/rk3328-power.h" - for RK3328 type power domain.
- "include/dt-bindings/power/rk3366-power.h" - for RK3366 type power domain.
- "include/dt-bindings/power/rk3368-power.h" - for RK3368 type power domain.
- "include/dt-bindings/power/rk3399-power.h" - for RK3399 type power domain.
-- clocks (optional): phandles to clocks which need to be enabled while power domain
- switches state.
-- pm_qos (optional): phandles to qos blocks which need to be saved and restored
- while power domain switches state.
-
-Qos Example:
-
- qos_gpu: qos_gpu@ffaf0000 {
- compatible ="syscon";
- reg = <0x0 0xffaf0000 0x0 0x20>;
- };
-
-Example:
-
- power: power-controller {
- compatible = "rockchip,rk3288-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_gpu {
- reg = <RK3288_PD_GPU>;
- clocks = <&cru ACLK_GPU>;
- pm_qos = <&qos_gpu>;
- };
- };
-
- power: power-controller {
- compatible = "rockchip,rk3368-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_gpu_1 {
- reg = <RK3368_PD_GPU_1>;
- clocks = <&cru ACLK_GPU_CFG>;
- };
- };
-
-Example 2:
- power: power-controller {
- compatible = "rockchip,rk3399-power-controller";
- #power-domain-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pd_vio {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <RK3399_PD_VIO>;
-
- pd_vo {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <RK3399_PD_VO>;
-
- pd_vopb {
- reg = <RK3399_PD_VOPB>;
- };
-
- pd_vopl {
- reg = <RK3399_PD_VOPL>;
- };
- };
- };
- };
-
-Node of a device using power domains must have a power-domains property,
-containing a phandle to the power device node and an index specifying which
-power domain to use.
-The index should use macros in:
- "include/dt-bindings/power/px30-power.h" - for px30 type power domain.
- "include/dt-bindings/power/rk3036-power.h" - for rk3036 type power domain.
- "include/dt-bindings/power/rk3128-power.h" - for rk3128 type power domain.
- "include/dt-bindings/power/rk3128-power.h" - for rk3228 type power domain.
- "include/dt-bindings/power/rk3288-power.h" - for rk3288 type power domain.
- "include/dt-bindings/power/rk3328-power.h" - for rk3328 type power domain.
- "include/dt-bindings/power/rk3366-power.h" - for rk3366 type power domain.
- "include/dt-bindings/power/rk3368-power.h" - for rk3368 type power domain.
- "include/dt-bindings/power/rk3399-power.h" - for rk3399 type power domain.
-
-Example of the node using power domain:
-
- node {
- /* ... */
- power-domains = <&power RK3288_PD_GPU>;
- /* ... */
- };
-
- node {
- /* ... */
- power-domains = <&power RK3368_PD_GPU_1>;
- /* ... */
- };
-
- node {
- /* ... */
- power-domains = <&power RK3399_PD_VOPB>;
- /* ... */
- };
diff --git a/Bindings/soc/ti/sci-pm-domain.txt b/Bindings/soc/ti/sci-pm-domain.txt
deleted file mode 100644
index 6217e64..0000000
--- a/Bindings/soc/ti/sci-pm-domain.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Texas Instruments TI-SCI Generic Power Domain
----------------------------------------------
-
-Some TI SoCs contain a system controller (like the PMMC, etc...) that is
-responsible for controlling the state of the IPs that are present.
-Communication between the host processor running an OS and the system
-controller happens through a protocol known as TI-SCI [1].
-
-[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
-
-PM Domain Node
-==============
-The PM domain node represents the global PM domain managed by the PMMC, which
-in this case is the implementation as documented by the generic PM domain
-bindings in Documentation/devicetree/bindings/power/power-domain.yaml. Because
-this relies on the TI SCI protocol to communicate with the PMMC it must be a
-child of the pmmc node.
-
-Required Properties:
---------------------
-- compatible: should be "ti,sci-pm-domain"
-- #power-domain-cells: Can be one of the following:
- 1: Containing the device id of each node
- 2: First entry should be device id
- Second entry should be one of the floowing:
- TI_SCI_PD_EXCLUSIVE: To allow device to be
- exclusively controlled by
- the requesting hosts.
- TI_SCI_PD_SHARED: To allow device to be shared
- by multiple hosts.
-
-Example (K2G):
--------------
- pmmc: pmmc {
- compatible = "ti,k2g-sci";
- ...
-
- k2g_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
- };
- };
-
-PM Domain Consumers
-===================
-Hardware blocks belonging to a PM domain should contain a "power-domains"
-property that is a phandle pointing to the corresponding PM domain node
-along with an index representing the device id to be passed to the PMMC
-for device control.
-
-Required Properties:
---------------------
-- power-domains: phandle pointing to the corresponding PM domain node
- and an ID representing the device.
-
-See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list
-of valid identifiers for k2g.
-
-Example (K2G):
---------------------
- uart0: serial@2530c00 {
- compatible = "ns16550a";
- ...
- power-domains = <&k2g_pds 0x002c>;
- };
diff --git a/Bindings/soc/ti/sci-pm-domain.yaml b/Bindings/soc/ti/sci-pm-domain.yaml
new file mode 100644
index 0000000..9e6cb4e
--- /dev/null
+++ b/Bindings/soc/ti/sci-pm-domain.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI generic power domain node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+allOf:
+ - $ref: /schemas/power/power-domain.yaml#
+
+description: |
+ Some TI SoCs contain a system controller (like the Power Management Micro
+ Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+ the state of the various hardware modules present on the SoC. Communication
+ between the host processor running an OS and the system controller happens
+ through a protocol called TI System Control Interface (TI-SCI protocol).
+
+ This PM domain node represents the global PM domain managed by the TI-SCI
+ controller. Since this relies on the TI SCI protocol to communicate with
+ the TI-SCI controller, it must be a child of the TI-SCI controller node.
+
+properties:
+ compatible:
+ const: ti,sci-pm-domain
+
+ "#power-domain-cells":
+ enum: [1, 2]
+ description:
+ The two cells represent values that the TI-SCI controller defines.
+
+ The first cell should contain the device ID.
+
+ The second cell, if cell-value is 2, should be one of the following
+ TI_SCI_PD_EXCLUSIVE - Allows the device to be exclusively controlled
+ or
+ TI_SCI_PD_SHARED - Allows the device to be shared by multiple hosts.
+ Please refer to dt-bindings/soc/ti,sci_pm_domain.h for the definitions.
+
+ Please see http://processors.wiki.ti.com/index.php/TISCI for
+ protocol documentation for the values to be used for different devices.
+
+additionalProperties: false
+
+examples:
+ - |
+ k2g_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <1>;
+ };
+
+ - |
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
diff --git a/Bindings/soc/ti/ti,pruss.yaml b/Bindings/soc/ti/ti,pruss.yaml
index dbc6282..9790617 100644
--- a/Bindings/soc/ti/ti,pruss.yaml
+++ b/Bindings/soc/ti/ti,pruss.yaml
@@ -100,7 +100,6 @@
properties:
reg:
minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
- maxItems: 3
items:
- description: Address and size of the Data RAM0.
- description: Address and size of the Data RAM1.
@@ -111,7 +110,6 @@
reg-names:
minItems: 2
- maxItems: 3
items:
- const: dram0
- const: dram1
diff --git a/Bindings/sound/allwinner,sun4i-a10-i2s.yaml b/Bindings/sound/allwinner,sun4i-a10-i2s.yaml
index a16e37b..39b66e9 100644
--- a/Bindings/sound/allwinner,sun4i-a10-i2s.yaml
+++ b/Bindings/sound/allwinner,sun4i-a10-i2s.yaml
@@ -20,6 +20,9 @@
- const: allwinner,sun6i-a31-i2s
- const: allwinner,sun8i-a83t-i2s
- const: allwinner,sun8i-h3-i2s
+ - items:
+ - const: allwinner,sun8i-v3-i2s
+ - const: allwinner,sun8i-h3-i2s
- const: allwinner,sun50i-a64-codec-i2s
- items:
- const: allwinner,sun50i-a64-i2s
diff --git a/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml b/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml
index 9718358..26eca21 100644
--- a/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml
+++ b/Bindings/sound/allwinner,sun8i-a23-codec-analog.yaml
@@ -12,12 +12,15 @@
properties:
compatible:
- enum:
+ oneOf:
# FIXME: This is documented in the PRCM binding, but needs to be
# migrated here at some point
# - allwinner,sun8i-a23-codec-analog
- - allwinner,sun8i-h3-codec-analog
- - allwinner,sun8i-v3s-codec-analog
+ - const: allwinner,sun8i-h3-codec-analog
+ - items:
+ - const: allwinner,sun8i-v3-codec-analog
+ - const: allwinner,sun8i-h3-codec-analog
+ - const: allwinner,sun8i-v3s-codec-analog
reg:
maxItems: 1
diff --git a/Bindings/sound/allwinner,sun8i-a33-codec.yaml b/Bindings/sound/allwinner,sun8i-a33-codec.yaml
index 67405e6..19f111f 100644
--- a/Bindings/sound/allwinner,sun8i-a33-codec.yaml
+++ b/Bindings/sound/allwinner,sun8i-a33-codec.yaml
@@ -12,7 +12,11 @@
properties:
"#sound-dai-cells":
- const: 0
+ minimum: 0
+ maximum: 1
+ description:
+ A value of 0 is deprecated. When used, it only allows access to
+ the ADC/DAC and AIF1 (the CPU DAI), not the other two AIFs/DAIs.
compatible:
oneOf:
@@ -50,7 +54,7 @@
examples:
- |
audio-codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x400>;
interrupts = <0 29 4>;
diff --git a/Bindings/sound/cs42l42.txt b/Bindings/sound/cs42l42.txt
index 7dfaa2a..5d416fd 100644
--- a/Bindings/sound/cs42l42.txt
+++ b/Bindings/sound/cs42l42.txt
@@ -81,6 +81,13 @@
< x1 x2 x3 x4 >
Default = < 15 8 4 1>
+ - cirrus,hs-bias-sense-disable: This is boolean property. If present the
+ HSBIAS sense is disabled. Configures HSBIAS output current sense through
+ the external 2.21-k resistor. HSBIAS_SENSE is hardware feature to reduce
+ the potential pop noise during the headset plug out slowly. But on some
+ platforms ESD voltage will affect it causing test to fail, especially
+ with CTIA headset type. For different hardware setups, a designer might
+ want to tweak default behavior.
Example:
diff --git a/Bindings/sound/fsl,spdif.yaml b/Bindings/sound/fsl,spdif.yaml
index 4454aca..f226ec1 100644
--- a/Bindings/sound/fsl,spdif.yaml
+++ b/Bindings/sound/fsl,spdif.yaml
@@ -25,6 +25,7 @@
- fsl,imx8mq-spdif
- fsl,imx8mm-spdif
- fsl,imx8mn-spdif
+ - fsl,imx8ulp-spdif
reg:
maxItems: 1
diff --git a/Bindings/sound/fsl-sai.txt b/Bindings/sound/fsl-sai.txt
index 0dc83cc..c71c586 100644
--- a/Bindings/sound/fsl-sai.txt
+++ b/Bindings/sound/fsl-sai.txt
@@ -9,8 +9,10 @@
- compatible : Compatible list, contains "fsl,vf610-sai",
"fsl,imx6sx-sai", "fsl,imx6ul-sai",
- "fsl,imx7ulp-sai", "fsl,imx8mq-sai" or
- "fsl,imx8qm-sai".
+ "fsl,imx7ulp-sai", "fsl,imx8mq-sai",
+ "fsl,imx8qm-sai", "fsl,imx8mm-sai",
+ "fsl,imx8mn-sai", "fsl,imx8mp-sai", or
+ "fsl,imx8ulp-sai".
- reg : Offset and length of the register set for the device.
diff --git a/Bindings/sound/imx-audio-card.yaml b/Bindings/sound/imx-audio-card.yaml
new file mode 100644
index 0000000..d1816dd
--- /dev/null
+++ b/Bindings/sound/imx-audio-card.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/imx-audio-card.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX audio sound card.
+
+maintainers:
+ - Shengjiu Wang <shengjiu.wang@nxp.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx-audio-card
+
+ model:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: User specified audio sound card name
+
+ audio-routing:
+ $ref: /schemas/types.yaml#/definitions/non-unique-string-array
+ description:
+ A list of the connections between audio components. Each entry is a
+ pair of strings, the first being the connection's sink, the second
+ being the connection's source. Valid names could be power supplies,
+ MicBias of codec and the jacks on the board.
+
+patternProperties:
+ ".*-dai-link$":
+ description:
+ Each subnode represents a dai link. Subnodes of each dai links would be
+ cpu/codec dais.
+
+ type: object
+
+ properties:
+ link-name:
+ description: Indicates dai-link name and PCM stream name.
+ $ref: /schemas/types.yaml#/definitions/string
+ maxItems: 1
+
+ format:
+ description: audio format.
+ items:
+ enum:
+ - i2s
+ - dsp_b
+
+ dai-tdm-slot-num:
+ description: see tdm-slot.txt.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ dai-tdm-slot-width:
+ description: see tdm-slot.txt.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ cpu:
+ description: Holds subnode which indicates cpu dai.
+ type: object
+ properties:
+ sound-dai: true
+
+ codec:
+ description: Holds subnode which indicates codec dai.
+ type: object
+ properties:
+ sound-dai: true
+
+ fsl,mclk-equal-bclk:
+ description: Indicates mclk can be equal to bclk, especially for sai interface
+ $ref: /schemas/types.yaml#/definitions/flag
+
+ required:
+ - link-name
+ - cpu
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - model
+
+additionalProperties: false
+
+examples:
+ - |
+ sound-ak4458 {
+ compatible = "fsl,imx-audio-card";
+ model = "ak4458-audio";
+ pri-dai-link {
+ link-name = "akcodec";
+ format = "i2s";
+ fsl,mclk-equal-bclk;
+ cpu {
+ sound-dai = <&sai1>;
+ };
+ codec {
+ sound-dai = <&ak4458_1>, <&ak4458_2>;
+ };
+ };
+ fe-dai-link {
+ link-name = "HiFi-ASRC-FE";
+ format = "i2s";
+ cpu {
+ sound-dai = <&easrc>;
+ };
+ };
+ be-dai-link {
+ link-name = "HiFi-ASRC-BE";
+ format = "dsp_b";
+ dai-tdm-slot-num = <8>;
+ dai-tdm-slot-width = <32>;
+ fsl,mclk-equal-bclk;
+ cpu {
+ sound-dai = <&sai1>;
+ };
+ codec {
+ sound-dai = <&ak4458_1>, <&ak4458_2>;
+ };
+ };
+ };
diff --git a/Bindings/sound/imx-audmux.txt b/Bindings/sound/imx-audmux.txt
deleted file mode 100644
index 2db4dcb..0000000
--- a/Bindings/sound/imx-audmux.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Freescale Digital Audio Mux (AUDMUX) device
-
-Required properties:
-
- - compatible : "fsl,imx21-audmux" for AUDMUX version firstly used
- on i.MX21, or "fsl,imx31-audmux" for the version
- firstly used on i.MX31.
-
- - reg : Should contain AUDMUX registers location and length.
-
-An initial configuration can be setup using child nodes.
-
-Required properties of optional child nodes:
-
- - fsl,audmux-port : Integer of the audmux port that is configured by this
- child node.
-
- - fsl,port-config : List of configuration options for the specific port.
- For imx31-audmux and above, it is a list of tuples
- <ptcr pdcr>. For imx21-audmux it is a list of pcr
- values.
-
-Example:
-
-audmux@21d8000 {
- compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
- reg = <0x021d8000 0x4000>;
-};
diff --git a/Bindings/sound/imx-audmux.yaml b/Bindings/sound/imx-audmux.yaml
new file mode 100644
index 0000000..dab45c3
--- /dev/null
+++ b/Bindings/sound/imx-audmux.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/imx-audmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Digital Audio Mux device
+
+maintainers:
+ - Oleksij Rempel <o.rempel@pengutronix.de>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx27-audmux
+ - const: fsl,imx21-audmux
+ - items:
+ - enum:
+ - fsl,imx25-audmux
+ - fsl,imx35-audmux
+ - fsl,imx50-audmux
+ - fsl,imx51-audmux
+ - fsl,imx53-audmux
+ - fsl,imx6q-audmux
+ - fsl,imx6sl-audmux
+ - fsl,imx6sll-audmux
+ - fsl,imx6sx-audmux
+ - const: fsl,imx31-audmux
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: audmux
+
+patternProperties:
+ "^mux-[0-9a-z]*$":
+ type: object
+ properties:
+ fsl,audmux-port:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Integer of the audmux port that is configured by this child node
+
+ fsl,port-config:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ List of configuration options for the specific port.
+ For imx31-audmux and above, it is a list of tuples ptcr pdcr.
+ For imx21-audmux it is a list of pcr values.
+
+ required:
+ - fsl,audmux-port
+ - fsl,port-config
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ audmux@21d8000 {
+ compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
+ reg = <0x021d8000 0x4000>;
+ };
+ - |
+ audmux@10016000 {
+ compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
+ reg = <0x10016000 0x1000>;
+ clocks = <&clks 1>;
+ clock-names = "audmux";
+
+ mux-ssi0 {
+ fsl,audmux-port = <0>;
+ fsl,port-config = <0xcb205000>;
+ };
+
+ mux-pins4 {
+ fsl,audmux-port = <2>;
+ fsl,port-config = <0x00001000>;
+ };
+ };
+ - |
+ #include <dt-bindings/sound/fsl-imx-audmux.h>
+ audmux@21d8000 {
+ compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
+ reg = <0x021d8000 0x4000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+
+ mux-ssi1 {
+ fsl,audmux-port = <0>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN 0
+ IMX_AUDMUX_V2_PTCR_TFSEL(2) 0
+ IMX_AUDMUX_V2_PTCR_TCSEL(2) 0
+ IMX_AUDMUX_V2_PTCR_TFSDIR 0
+ IMX_AUDMUX_V2_PTCR_TCLKDIR IMX_AUDMUX_V2_PDCR_RXDSEL(2)
+ >;
+ };
+
+ mux-pins3 {
+ fsl,audmux-port = <2>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN IMX_AUDMUX_V2_PDCR_RXDSEL(0)
+ 0 IMX_AUDMUX_V2_PDCR_TXRXEN
+ >;
+ };
+ };
diff --git a/Bindings/sound/nvidia,tegra-audio-graph-card.yaml b/Bindings/sound/nvidia,tegra-audio-graph-card.yaml
index 2499709..5bdd30a 100644
--- a/Bindings/sound/nvidia,tegra-audio-graph-card.yaml
+++ b/Bindings/sound/nvidia,tegra-audio-graph-card.yaml
@@ -28,7 +28,6 @@
minItems: 2
clock-names:
- minItems: 2
items:
- const: pll_a
- const: plla_out0
diff --git a/Bindings/sound/nvidia,tegra210-i2s.yaml b/Bindings/sound/nvidia,tegra210-i2s.yaml
index 38e52e7..6337070 100644
--- a/Bindings/sound/nvidia,tegra210-i2s.yaml
+++ b/Bindings/sound/nvidia,tegra210-i2s.yaml
@@ -34,7 +34,6 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: I2S bit clock
- description:
@@ -48,7 +47,6 @@
clock-names:
minItems: 1
- maxItems: 2
items:
- const: i2s
- const: sync_input
diff --git a/Bindings/sound/nxp,tfa989x.yaml b/Bindings/sound/nxp,tfa989x.yaml
new file mode 100644
index 0000000..ffb8fcf
--- /dev/null
+++ b/Bindings/sound/nxp,tfa989x.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/nxp,tfa989x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP/Goodix TFA989X (TFA1) Audio Amplifiers
+
+maintainers:
+ - Stephan Gerhold <stephan@gerhold.net>
+
+properties:
+ compatible:
+ enum:
+ - nxp,tfa9895
+ - nxp,tfa9897
+
+ reg:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 0
+
+ sound-name-prefix:
+ $ref: /schemas/types.yaml#/definitions/string
+ description:
+ Used as prefix for sink/source names of the component. Must be a
+ unique string among multiple instances of the same component.
+
+ vddd-supply:
+ description: regulator phandle for the VDDD power supply.
+
+required:
+ - compatible
+ - reg
+ - '#sound-dai-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ audio-codec@34 {
+ compatible = "nxp,tfa9895";
+ reg = <0x34>;
+ sound-name-prefix = "Speaker Left";
+ #sound-dai-cells = <0>;
+ };
+ audio-codec@36 {
+ compatible = "nxp,tfa9895";
+ reg = <0x36>;
+ sound-name-prefix = "Speaker Right";
+ #sound-dai-cells = <0>;
+ };
+ };
diff --git a/Bindings/sound/qcom,wcd934x.yaml b/Bindings/sound/qcom,wcd934x.yaml
index e8f716b..9b225db 100644
--- a/Bindings/sound/qcom,wcd934x.yaml
+++ b/Bindings/sound/qcom,wcd934x.yaml
@@ -77,6 +77,31 @@
minimum: 1800000
maximum: 2850000
+ qcom,hphl-jack-type-normally-closed:
+ description: Indicates that HPHL jack switch type is normally closed
+ type: boolean
+
+ qcom,ground-jack-type-normally-closed:
+ description: Indicates that Headset Ground switch type is normally closed
+ type: boolean
+
+ qcom,mbhc-headset-vthreshold-microvolt:
+ description: Voltage threshold value for headset detection
+ minimum: 0
+ maximum: 2850000
+
+ qcom,mbhc-headphone-vthreshold-microvolt:
+ description: Voltage threshold value for headphone detection
+ minimum: 0
+ maximum: 2850000
+
+ qcom,mbhc-buttons-vthreshold-microvolt:
+ description:
+ Array of 8 Voltage threshold values corresponding to headset
+ button0 - button7
+ minItems: 8
+ maxItems: 8
+
clock-output-names:
const: mclk
@@ -159,6 +184,11 @@
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
+ qcom,hphl-jack-type-normally-closed;
+ qcom,ground-jack-type-normally-closed;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
clock-names = "extclk";
clocks = <&rpmhcc 2>;
diff --git a/Bindings/sound/qcom,wcd938x-sdw.yaml b/Bindings/sound/qcom,wcd938x-sdw.yaml
new file mode 100644
index 0000000..49a267b
--- /dev/null
+++ b/Bindings/sound/qcom,wcd938x-sdw.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,wcd938x-sdw.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Qualcomm SoundWire Slave devices on WCD9380/WCD9385
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
+ It has RX and TX Soundwire slave devices. This bindings is for the
+ slave devices.
+
+properties:
+ compatible:
+ const: sdw20217010d00
+
+ reg:
+ maxItems: 1
+
+ qcom,tx-port-mapping:
+ description: |
+ Specifies static port mapping between slave and master tx ports.
+ In the order of slave port index.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 4
+ maxItems: 4
+
+ qcom,rx-port-mapping:
+ description: |
+ Specifies static port mapping between slave and master rx ports.
+ In the order of slave port index.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 5
+ maxItems: 5
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soundwire@3210000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03210000 0x2000>;
+ wcd938x_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+ };
+
+ soundwire@3230000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03230000 0x2000>;
+ wcd938x_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 3 4 5>;
+ };
+ };
+
+...
diff --git a/Bindings/sound/qcom,wcd938x.yaml b/Bindings/sound/qcom,wcd938x.yaml
new file mode 100644
index 0000000..cb74ce4
--- /dev/null
+++ b/Bindings/sound/qcom,wcd938x.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/qcom,wcd938x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bindings for Qualcomm WCD9380/WCD9385 Audio Codec
+
+maintainers:
+ - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+
+description: |
+ Qualcomm WCD9380/WCD9385 Codec is a standalone Hi-Fi audio codec IC.
+ It has RX and TX Soundwire slave devices.
+
+properties:
+ compatible:
+ enum:
+ - qcom,wcd9380-codec
+ - qcom,wcd9385-codec
+
+ reset-gpios:
+ description: GPIO spec for reset line to use
+ maxItems: 1
+
+ vdd-buck-supply:
+ description: A reference to the 1.8V buck supply
+
+ vdd-rxtx-supply:
+ description: A reference to the 1.8V rx supply
+
+ vdd-io-supply:
+ description: A reference to the 1.8V I/O supply
+
+ qcom,tx-device:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: A reference to Soundwire tx device phandle
+
+ qcom,rx-device:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: A reference to Soundwire rx device phandle
+
+ qcom,micbias1-microvolt:
+ description: micbias1 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,micbias2-microvolt:
+ description: micbias2 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,micbias3-microvolt:
+ description: micbias3 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,micbias4-microvolt:
+ description: micbias4 voltage
+ minimum: 1800000
+ maximum: 2850000
+
+ qcom,hphl-jack-type-normally-closed:
+ description: Indicates that HPHL jack switch type is normally closed
+ type: boolean
+
+ qcom,ground-jack-type-normally-closed:
+ description: Indicates that Headset Ground switch type is normally closed
+ type: boolean
+
+ qcom,mbhc-headset-vthreshold-microvolt:
+ description: Voltage threshold value for headset detection
+ minimum: 0
+ maximum: 2850000
+
+ qcom,mbhc-headphone-vthreshold-microvolt:
+ description: Voltage threshold value for headphone detection
+ minimum: 0
+ maximum: 2850000
+
+ qcom,mbhc-buttons-vthreshold-microvolt:
+ description:
+ Array of 8 Voltage threshold values corresponding to headset
+ button0 - button7
+ minItems: 8
+ maxItems: 8
+
+ '#sound-dai-cells':
+ const: 1
+
+required:
+ - compatible
+ - reset-gpios
+ - qcom,tx-device
+ - qcom,rx-device
+ - qcom,micbias1-microvolt
+ - qcom,micbias2-microvolt
+ - qcom,micbias3-microvolt
+ - qcom,micbias4-microvolt
+ - "#sound-dai-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ codec {
+ compatible = "qcom,wcd9380-codec";
+ reset-gpios = <&tlmm 32 0>;
+ #sound-dai-cells = <1>;
+ qcom,tx-device = <&wcd938x_tx>;
+ qcom,rx-device = <&wcd938x_rx>;
+ qcom,micbias1-microvolt = <1800000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <1800000>;
+ qcom,micbias4-microvolt = <1800000>;
+ qcom,hphl-jack-type-normally-closed;
+ qcom,ground-jack-type-normally-closed;
+ qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+ qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+ };
+
+ /* ... */
+
+ soundwire@3210000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03210000 0x2000>;
+ wcd938x_rx: codec@0,4 {
+ compatible = "sdw20217010d00";
+ reg = <0 4>;
+ qcom,rx-port-mapping = <1 2 3 4 5>;
+ };
+ };
+
+ soundwire@3230000 {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x03230000 0x2000>;
+ wcd938x_tx: codec@0,3 {
+ compatible = "sdw20217010d00";
+ reg = <0 3>;
+ qcom,tx-port-mapping = <2 3 4 5>;
+ };
+ };
+
+...
diff --git a/Bindings/sound/renesas,rsnd.yaml b/Bindings/sound/renesas,rsnd.yaml
index 605de3a..ee936d1a 100644
--- a/Bindings/sound/renesas,rsnd.yaml
+++ b/Bindings/sound/renesas,rsnd.yaml
@@ -86,9 +86,11 @@
power-domains: true
resets:
+ minItems: 1
maxItems: 11
reset-names:
+ minItems: 1
maxItems: 11
clocks:
@@ -110,6 +112,13 @@
- pattern: '^dvc\.[0-1]$'
- pattern: '^clk_(a|b|c|i)$'
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port(@[0-9a-f]+)?:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
port:
$ref: audio-graph-port.yaml#
unevaluatedProperties: false
@@ -257,7 +266,6 @@
- "#sound-dai-cells"
allOf:
- - $ref: audio-graph.yaml#
- if:
properties:
compatible:
diff --git a/Bindings/sound/sgtl5000.yaml b/Bindings/sound/sgtl5000.yaml
index 70b4a88..e762c32 100644
--- a/Bindings/sound/sgtl5000.yaml
+++ b/Bindings/sound/sgtl5000.yaml
@@ -75,6 +75,10 @@
$ref: "/schemas/types.yaml#/definitions/uint32"
enum: [ 0, 1, 2, 3 ]
+ port:
+ $ref: audio-graph-port.yaml#
+ unevaluatedProperties: false
+
required:
- compatible
- reg
diff --git a/Bindings/sound/st,stm32-sai.yaml b/Bindings/sound/st,stm32-sai.yaml
index f2443b6..06e8346 100644
--- a/Bindings/sound/st,stm32-sai.yaml
+++ b/Bindings/sound/st,stm32-sai.yaml
@@ -26,7 +26,6 @@
- description: Base address and size of SAI common register set.
- description: Base address and size of SAI identification register set.
minItems: 1
- maxItems: 2
ranges:
maxItems: 1
@@ -81,14 +80,12 @@
- description: sai_ck clock feeding the internal clock generator.
- description: MCLK clock from a SAI set as master clock provider.
minItems: 1
- maxItems: 2
clock-names:
items:
- const: sai_ck
- const: MCLK
minItems: 1
- maxItems: 2
dmas:
maxItems: 1
diff --git a/Bindings/sound/tlv320aic32x4.txt b/Bindings/sound/tlv320aic32x4.txt
index ca75890..f59125b 100644
--- a/Bindings/sound/tlv320aic32x4.txt
+++ b/Bindings/sound/tlv320aic32x4.txt
@@ -6,6 +6,7 @@
- compatible - "string" - One of:
"ti,tlv320aic32x4" TLV320AIC3204
"ti,tlv320aic32x6" TLV320AIC3206, TLV320AIC3256
+ "ti,tas2505" TAS2505, TAS2521
- reg: I2C slave address
- supply-*: Required supply regulators are:
"iov" - digital IO power supply
diff --git a/Bindings/sound/wm8750.txt b/Bindings/sound/wm8750.txt
deleted file mode 100644
index 682f221..0000000
--- a/Bindings/sound/wm8750.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-WM8750 and WM8987 audio CODECs
-
-These devices support both I2C and SPI (configured with pin strapping
-on the board).
-
-Required properties:
-
- - compatible : "wlf,wm8750" or "wlf,wm8987"
-
- - reg : the I2C address of the device for I2C, the chip select
- number for SPI.
-
-Example:
-
-wm8750: codec@1a {
- compatible = "wlf,wm8750";
- reg = <0x1a>;
-};
diff --git a/Bindings/sound/wm8750.yaml b/Bindings/sound/wm8750.yaml
new file mode 100644
index 0000000..24246ac
--- /dev/null
+++ b/Bindings/sound/wm8750.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/sound/wm8750.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: WM8750 and WM8987 audio CODECs
+
+description: |
+ These devices support both I2C and SPI (configured with pin strapping
+ on the board).
+
+maintainers:
+ - Mark Brown <broonie@kernel.org>
+
+properties:
+ compatible:
+ enum:
+ - wlf,wm8750
+ - wlf,wm8987
+
+ reg:
+ description:
+ The I2C address of the device for I2C, the chip select number for SPI
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - reg
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ codec@1a {
+ compatible = "wlf,wm8750";
+ reg = <0x1a>;
+ };
+ };
diff --git a/Bindings/spi/amlogic,meson-gx-spicc.yaml b/Bindings/spi/amlogic,meson-gx-spicc.yaml
index e3fb553..4d46c49 100644
--- a/Bindings/spi/amlogic,meson-gx-spicc.yaml
+++ b/Bindings/spi/amlogic,meson-gx-spicc.yaml
@@ -35,7 +35,6 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: controller register bus clock
- description: baud rate generator and delay control clock
diff --git a/Bindings/spi/brcm,spi-bcm-qspi.yaml b/Bindings/spi/brcm,spi-bcm-qspi.yaml
index 6ee19d4..ec58739 100644
--- a/Bindings/spi/brcm,spi-bcm-qspi.yaml
+++ b/Bindings/spi/brcm,spi-bcm-qspi.yaml
@@ -56,7 +56,6 @@
reg-names:
minItems: 1
- maxItems: 5
items:
- const: mspi
- const: bspi
@@ -71,7 +70,6 @@
interrupt-names:
oneOf:
- minItems: 1
- maxItems: 7
items:
- const: mspi_done
- const: mspi_halted
diff --git a/Bindings/spi/renesas,rzn1-spi.txt b/Bindings/spi/renesas,rzn1-spi.txt
deleted file mode 100644
index fb1a672..0000000
--- a/Bindings/spi/renesas,rzn1-spi.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-Renesas RZ/N1 SPI Controller
-
-This controller is based on the Synopsys DW Synchronous Serial Interface and
-inherits all properties defined in snps,dw-apb-ssi.txt except for the
-compatible property.
-
-Required properties:
-- compatible : The device specific string followed by the generic RZ/N1 string.
- Therefore it must be one of:
- "renesas,r9a06g032-spi", "renesas,rzn1-spi"
- "renesas,r9a06g033-spi", "renesas,rzn1-spi"
diff --git a/Bindings/spi/snps,dw-apb-ssi.yaml b/Bindings/spi/snps,dw-apb-ssi.yaml
index 4825157..ca91201 100644
--- a/Bindings/spi/snps,dw-apb-ssi.yaml
+++ b/Bindings/spi/snps,dw-apb-ssi.yaml
@@ -67,6 +67,12 @@
const: baikal,bt1-sys-ssi
- description: Canaan Kendryte K210 SoS SPI Controller
const: canaan,k210-spi
+ - description: Renesas RZ/N1 SPI Controller
+ items:
+ - enum:
+ - renesas,r9a06g032-spi # RZ/N1D
+ - renesas,r9a06g033-spi # RZ/N1S
+ - const: renesas,rzn1-spi # RZ/N1
reg:
minItems: 1
diff --git a/Bindings/spi/spi-cadence.txt b/Bindings/spi/spi-cadence.txt
deleted file mode 100644
index 05a2ef9..0000000
--- a/Bindings/spi/spi-cadence.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Cadence SPI controller Device Tree Bindings
--------------------------------------------
-
-Required properties:
-- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
-- reg : Physical base address and size of SPI registers map.
-- interrupts : Property with a value describing the interrupt
- number.
-- clock-names : List of input clock names - "ref_clk", "pclk"
- (See clock bindings for details).
-- clocks : Clock phandles (see clock bindings for details).
-
-Optional properties:
-- num-cs : Number of chip selects used.
- If a decoder is used, this will be the number of
- chip selects after the decoder.
-- is-decoded-cs : Flag to indicate whether decoder is used or not.
-
-Example:
-
- spi@e0007000 {
- compatible = "xlnx,zynq-spi-r1p6";
- clock-names = "ref_clk", "pclk";
- clocks = <&clkc 26>, <&clkc 35>;
- interrupt-parent = <&intc>;
- interrupts = <0 49 4>;
- num-cs = <4>;
- is-decoded-cs = <0>;
- reg = <0xe0007000 0x1000>;
- } ;
diff --git a/Bindings/spi/spi-cadence.yaml b/Bindings/spi/spi-cadence.yaml
new file mode 100644
index 0000000..9787be2
--- /dev/null
+++ b/Bindings/spi/spi-cadence.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence SPI controller Device Tree Bindings
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - cdns,spi-r1p6
+ - xlnx,zynq-spi-r1p6
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: pclk
+
+ clocks:
+ maxItems: 2
+
+ num-cs:
+ description: |
+ Number of chip selects used. If a decoder is used,
+ this will be the number of chip selects after the
+ decoder.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 4
+ default: 4
+
+ is-decoded-cs:
+ description: |
+ Flag to indicate whether decoder is used or not.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1 ]
+ default: 0
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi@e0007000 {
+ compatible = "xlnx,zynq-spi-r1p6";
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clkc 26>, <&clkc 35>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 49 4>;
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ reg = <0xe0007000 0x1000>;
+ };
+...
diff --git a/Bindings/spi/spi-controller.yaml b/Bindings/spi/spi-controller.yaml
index 0477396..faef4f6 100644
--- a/Bindings/spi/spi-controller.yaml
+++ b/Bindings/spi/spi-controller.yaml
@@ -114,8 +114,11 @@
Compatible of the SPI device.
reg:
- minimum: 0
- maximum: 256
+ minItems: 1
+ maxItems: 256
+ items:
+ minimum: 0
+ maximum: 256
description:
Chip select used by the device.
diff --git a/Bindings/spi/spi-davinci.txt b/Bindings/spi/spi-davinci.txt
index e2198a3..200c7fc 100644
--- a/Bindings/spi/spi-davinci.txt
+++ b/Bindings/spi/spi-davinci.txt
@@ -25,7 +25,7 @@
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
For 66AK2G this property should be set per binding,
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
SoC-specific Required Properties:
diff --git a/Bindings/spi/spi-rockchip.yaml b/Bindings/spi/spi-rockchip.yaml
index 1e6cf29..7f987e7 100644
--- a/Bindings/spi/spi-rockchip.yaml
+++ b/Bindings/spi/spi-rockchip.yaml
@@ -33,6 +33,7 @@
- rockchip,rk3328-spi
- rockchip,rk3368-spi
- rockchip,rk3399-spi
+ - rockchip,rv1126-spi
- const: rockchip,rk3066-spi
reg:
diff --git a/Bindings/spi/spi-xilinx.txt b/Bindings/spi/spi-xilinx.txt
deleted file mode 100644
index 5f4ed3e..0000000
--- a/Bindings/spi/spi-xilinx.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Xilinx SPI controller Device Tree Bindings
--------------------------------------------------
-
-Required properties:
-- compatible : Should be "xlnx,xps-spi-2.00.a", "xlnx,xps-spi-2.00.b" or "xlnx,axi-quad-spi-1.00.a"
-- reg : Physical base address and size of SPI registers map.
-- interrupts : Property with a value describing the interrupt
- number.
-
-Optional properties:
-- xlnx,num-ss-bits : Number of chip selects used.
-- xlnx,num-transfer-bits : Number of bits per transfer. This will be 8 if not specified
-
-Example:
- axi_quad_spi@41e00000 {
- compatible = "xlnx,xps-spi-2.00.a";
- interrupt-parent = <&intc>;
- interrupts = <0 31 1>;
- reg = <0x41e00000 0x10000>;
- xlnx,num-ss-bits = <0x1>;
- xlnx,num-transfer-bits = <32>;
- };
-
diff --git a/Bindings/spi/spi-xilinx.yaml b/Bindings/spi/spi-xilinx.yaml
new file mode 100644
index 0000000..593f769
--- /dev/null
+++ b/Bindings/spi/spi-xilinx.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/spi-xilinx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx SPI controller Device Tree Bindings
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - xlnx,xps-spi-2.00.a
+ - xlnx,xps-spi-2.00.b
+ - xlnx,axi-quad-spi-1.00.a
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ xlnx,num-ss-bits:
+ description: Number of chip selects used.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 32
+
+ xlnx,num-transfer-bits:
+ description: Number of bits per transfer. This will be 8 if not specified.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8, 16, 32]
+ default: 8
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi0: spi@41e00000 {
+ compatible = "xlnx,xps-spi-2.00.a";
+ interrupt-parent = <&intc>;
+ interrupts = <0 31 1>;
+ reg = <0x41e00000 0x10000>;
+ xlnx,num-ss-bits = <0x1>;
+ xlnx,num-transfer-bits = <32>;
+ };
+...
diff --git a/Bindings/spi/spi-zynqmp-qspi.txt b/Bindings/spi/spi-zynqmp-qspi.txt
deleted file mode 100644
index 0f6d37f..0000000
--- a/Bindings/spi/spi-zynqmp-qspi.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
--------------------------------------------------------------------
-
-Required properties:
-- compatible : Should be "xlnx,zynqmp-qspi-1.0".
-- reg : Physical base address and size of GQSPI registers map.
-- interrupts : Property with a value describing the interrupt
- number.
-- clock-names : List of input clock names - "ref_clk", "pclk"
- (See clock bindings for details).
-- clocks : Clock phandles (see clock bindings for details).
-
-Optional properties:
-- num-cs : Number of chip selects used.
-
-Example:
- qspi: spi@ff0f0000 {
- compatible = "xlnx,zynqmp-qspi-1.0";
- clock-names = "ref_clk", "pclk";
- clocks = <&misc_clk &misc_clk>;
- interrupts = <0 15 4>;
- interrupt-parent = <&gic>;
- num-cs = <1>;
- reg = <0x0 0xff0f0000 0x1000>,<0x0 0xc0000000 0x8000000>;
- };
diff --git a/Bindings/spi/spi-zynqmp-qspi.yaml b/Bindings/spi/spi-zynqmp-qspi.yaml
new file mode 100644
index 0000000..ea72c80
--- /dev/null
+++ b/Bindings/spi/spi-zynqmp-qspi.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-qspi-1.0
+
+ reg:
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: pclk
+
+ clocks:
+ maxItems: 2
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ qspi: spi@ff0f0000 {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
+ clock-names = "ref_clk", "pclk";
+ interrupts = <0 15 4>;
+ interrupt-parent = <&gic>;
+ reg = <0x0 0xff0f0000 0x0 0x1000>,
+ <0x0 0xc0000000 0x0 0x8000000>;
+ };
+ };
diff --git a/Bindings/spmi/hisilicon,hisi-spmi-controller.yaml b/Bindings/spmi/hisilicon,hisi-spmi-controller.yaml
new file mode 100644
index 0000000..f882903
--- /dev/null
+++ b/Bindings/spmi/hisilicon,hisi-spmi-controller.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/hisilicon,hisi-spmi-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon SPMI controller
+
+maintainers:
+ - Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
+
+description: |
+ The HiSilicon SPMI BUS controller is found on some Kirin-based designs.
+ It is a MIPI System Power Management (SPMI) controller.
+
+ The PMIC part is provided by
+ ./Documentation/devicetree/bindings/mfd/hisilicon,hi6421-spmi-pmic.yaml.
+
+allOf:
+ - $ref: spmi.yaml#
+
+properties:
+
+ $nodename:
+ pattern: "spmi@[0-9a-f]"
+
+ compatible:
+ const: hisilicon,kirin970-spmi-controller
+
+ reg:
+ maxItems: 1
+
+ hisilicon,spmi-channel:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ number of the Kirin 970 SPMI channel where the SPMI devices are connected.
+
+required:
+ - compatible
+ - reg
+ - hisilicon,spmi-channel
+
+patternProperties:
+ "@[0-9a-f]$":
+ type: object
+
+ description: |
+ PMIC properties, which are specific to the used SPMI PMIC device(s).
+ When used in combination with HiSilicon 6421v600, the properties
+ are documented at
+ drivers/staging/hikey9xx/hisilicon,hi6421-spmi-pmic.yaml.
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ spmi: spmi@fff24000 {
+ compatible = "hisilicon,kirin970-spmi-controller";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ reg = <0x0 0xfff24000 0x0 0x1000>;
+ hisilicon,spmi-channel = <2>;
+
+ pmic@0 {
+ reg = <0 0>;
+ /* pmic properties */
+ };
+ };
+ };
diff --git a/Bindings/spmi/spmi.yaml b/Bindings/spmi/spmi.yaml
index 1739409..1d243fa 100644
--- a/Bindings/spmi/spmi.yaml
+++ b/Bindings/spmi/spmi.yaml
@@ -40,14 +40,15 @@
properties:
reg:
- minItems: 1
- maxItems: 2
items:
- - minimum: 0
- maximum: 0xf
- - enum: [ 0 ]
- description: |
- 0 means user ID address. 1 is reserved for group ID address.
+ - minItems: 1
+ items:
+ - minimum: 0
+ maximum: 0xf
+ - enum: [ 0 ]
+ description:
+ 0 means user ID address. 1 is reserved for group ID
+ address.
required:
- reg
diff --git a/Bindings/sram/sram.yaml b/Bindings/sram/sram.yaml
index c1a5afa..3eda504 100644
--- a/Bindings/sram/sram.yaml
+++ b/Bindings/sram/sram.yaml
@@ -28,6 +28,8 @@
contains:
enum:
- mmio-sram
+ - amlogic,meson-gxbb-sram
+ - arm,juno-sram-ns
- atmel,sama5d2-securam
- rockchip,rk3288-pmu-sram
@@ -80,6 +82,9 @@
- amlogic,meson8b-smp-sram
- amlogic,meson-gxbb-scp-shmem
- amlogic,meson-axg-scp-shmem
+ - arm,juno-scp-shmem
+ - arm,scmi-shmem
+ - arm,scp-shmem
- renesas,smp-sram
- rockchip,rk3066-smp-sram
- samsung,exynos4210-sysram
diff --git a/Bindings/submitting-patches.rst b/Bindings/submitting-patches.rst
index 104fa8f..8087780 100644
--- a/Bindings/submitting-patches.rst
+++ b/Bindings/submitting-patches.rst
@@ -7,8 +7,8 @@
I. For patch submitters
=======================
- 0) Normal patch submission rules from Documentation/process/submitting-patches.rst
- applies.
+ 0) Normal patch submission rules from
+ Documentation/process/submitting-patches.rst applies.
1) The Documentation/ and include/dt-bindings/ portion of the patch should
be a separate patch. The preferred subject prefix for binding patches is::
@@ -25,8 +25,8 @@
make dt_binding_check
- See Documentation/devicetree/bindings/writing-schema.rst for more details about
- schema and tools setup.
+ See Documentation/devicetree/bindings/writing-schema.rst for more details
+ about schema and tools setup.
3) DT binding files should be dual licensed. The preferred license tag is
(GPL-2.0-only OR BSD-2-Clause).
@@ -84,7 +84,8 @@
III. Notes
==========
- 0) Please see :doc:`ABI` for details regarding devicetree ABI.
+ 0) Please see Documentation/devicetree/bindings/ABI.rst for details
+ regarding devicetree ABI.
1) This document is intended as a general familiarization with the process as
decided at the 2013 Kernel Summit. When in doubt, the current word of the
diff --git a/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
index bf97d1f..6e0b110 100644
--- a/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+++ b/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml
@@ -23,14 +23,12 @@
clocks:
minItems: 1
- maxItems: 2
items:
- description: Bus Clock
- description: Module Clock
clock-names:
minItems: 1
- maxItems: 2
items:
- const: bus
- const: mod
diff --git a/Bindings/thermal/nvidia,tegra30-tsensor.yaml b/Bindings/thermal/nvidia,tegra30-tsensor.yaml
new file mode 100644
index 0000000..a35da25
--- /dev/null
+++ b/Bindings/thermal/nvidia,tegra30-tsensor.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/nvidia,tegra30-tsensor.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra30 Thermal Sensor
+
+maintainers:
+ - Dmitry Osipenko <digetx@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ TSENSOR provides thermal and voltage sensors which monitor temperature
+ and voltage of the chip. Sensors are placed across the die to gauge the
+ temperature of the whole chip. The TSENSOR module:
+
+ Generates an interrupt to SW to lower temperature via DVFS on reaching
+ a certain thermal/voltage threshold.
+
+ Generates a signal to the CAR to reduce CPU frequency by half on reaching
+ a certain thermal/voltage threshold.
+
+ Generates a signal to the PMC when the temperature reaches dangerously high
+ levels to reset the chip and sets a flag in the PMC.
+
+ TSENSOR has two channels which monitor two different spots of the SoC.
+
+properties:
+ compatible:
+ const: nvidia,tegra30-tsensor
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#thermal-sensor-cells":
+ const: 1
+
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+ assigned-clocks: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+ - interrupts
+ - "#thermal-sensor-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ thermal-sensor@70014000 {
+ compatible = "nvidia,tegra30-tsensor";
+ reg = <0x70014000 0x500>;
+ interrupts = <0 102 4>;
+ clocks = <&clk 100>;
+ resets = <&rst 100>;
+
+ #thermal-sensor-cells = <1>;
+ };
diff --git a/Bindings/thermal/qcom-tsens.yaml b/Bindings/thermal/qcom-tsens.yaml
index 0242fd9..4a2eaf2 100644
--- a/Bindings/thermal/qcom-tsens.yaml
+++ b/Bindings/thermal/qcom-tsens.yaml
@@ -46,6 +46,8 @@
- qcom,msm8996-tsens
- qcom,msm8998-tsens
- qcom,sc7180-tsens
+ - qcom,sc7280-tsens
+ - qcom,sc8180x-tsens
- qcom,sdm845-tsens
- qcom,sm8150-tsens
- qcom,sm8250-tsens
@@ -77,7 +79,6 @@
nvmem-cell-names:
minItems: 1
- maxItems: 2
items:
- const: calib
- enum:
diff --git a/Bindings/thermal/rockchip-thermal.txt b/Bindings/thermal/rockchip-thermal.txt
deleted file mode 100644
index 7f94669..0000000
--- a/Bindings/thermal/rockchip-thermal.txt
+++ /dev/null
@@ -1,85 +0,0 @@
-* Temperature Sensor ADC (TSADC) on rockchip SoCs
-
-Required properties:
-- compatible : should be "rockchip,<name>-tsadc"
- "rockchip,px30-tsadc": found on PX30 SoCs
- "rockchip,rv1108-tsadc": found on RV1108 SoCs
- "rockchip,rk3228-tsadc": found on RK3228 SoCs
- "rockchip,rk3288-tsadc": found on RK3288 SoCs
- "rockchip,rk3328-tsadc": found on RK3328 SoCs
- "rockchip,rk3368-tsadc": found on RK3368 SoCs
- "rockchip,rk3399-tsadc": found on RK3399 SoCs
-- reg : physical base address of the controller and length of memory mapped
- region.
-- interrupts : The interrupt number to the cpu. The interrupt specifier format
- depends on the interrupt controller.
-- clocks : Must contain an entry for each entry in clock-names.
-- clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
- the peripheral clock.
-- resets : Must contain an entry for each entry in reset-names.
- See ../reset/reset.txt for details.
-- reset-names : Must include the name "tsadc-apb".
-- pinctrl-names : The pin control state names;
-- pinctrl-0 : The "init" pinctrl state, it will be set before device probe.
-- pinctrl-1 : The "default" pinctrl state, it will be set after reset the
- TSADC controller.
-- pinctrl-2 : The "sleep" pinctrl state, it will be in for suspend.
-- #thermal-sensor-cells : Should be 1. See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml for a description.
-
-Optional properties:
-- rockchip,hw-tshut-temp : The hardware-controlled shutdown temperature value.
-- rockchip,hw-tshut-mode : The hardware-controlled shutdown mode 0:CRU 1:GPIO.
-- rockchip,hw-tshut-polarity : The hardware-controlled active polarity 0:LOW
- 1:HIGH.
-- rockchip,grf : The phandle of the syscon node for the general register file.
-
-Exiample:
-tsadc: tsadc@ff280000 {
- compatible = "rockchip,rk3288-tsadc";
- reg = <0xff280000 0x100>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
- clock-names = "tsadc", "apb_pclk";
- resets = <&cru SRST_TSADC>;
- reset-names = "tsadc-apb";
- pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
- pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
- #thermal-sensor-cells = <1>;
- rockchip,hw-tshut-temp = <95000>;
- rockchip,hw-tshut-mode = <0>;
- rockchip,hw-tshut-polarity = <0>;
-};
-
-Example: referring to thermal sensors:
-thermal-zones {
- cpu_thermal: cpu_thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <5000>; /* milliseconds */
-
- /* sensor ID */
- thermal-sensors = <&tsadc 1>;
-
- trips {
- cpu_alert0: cpu_alert {
- temperature = <70000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- cpu_crit: cpu_crit {
- temperature = <90000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert0>;
- cooling-device =
- <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-};
diff --git a/Bindings/thermal/rockchip-thermal.yaml b/Bindings/thermal/rockchip-thermal.yaml
new file mode 100644
index 0000000..b96ea27
--- /dev/null
+++ b/Bindings/thermal/rockchip-thermal.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/rockchip-thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Temperature Sensor ADC (TSADC) on Rockchip SoCs
+
+maintainers:
+ - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,px30-tsadc # PX30 SoCs
+ - rockchip,rv1108-tsadc # RV1108 SoCs
+ - rockchip,rk3228-tsadc # RK3228 SoCs
+ - rockchip,rk3288-tsadc # RK3288 SoCs
+ - rockchip,rk3328-tsadc # RK3328 SoCs
+ - rockchip,rk3368-tsadc # RK3368 SoCs
+ - rockchip,rk3399-tsadc # RK3399 SoCs
+ - rockchip,rk3568-tsadc # RK3568 SoCs
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: tsadc
+ - const: apb_pclk
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: tsadc-apb
+
+ "#thermal-sensor-cells":
+ const: 1
+
+ rockchip,grf:
+ description: The phandle of the syscon node for the general register file.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ rockchip,hw-tshut-temp:
+ description: The hardware-controlled shutdown temperature value.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ rockchip,hw-tshut-mode:
+ description: The hardware-controlled shutdown mode 0:CRU 1:GPIO.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+ rockchip,hw-tshut-polarity:
+ description: The hardware-controlled active polarity 0:LOW 1:HIGH.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#thermal-sensor-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/rk3288-cru.h>
+
+ tsadc: tsadc@ff280000 {
+ compatible = "rockchip,rk3288-tsadc";
+ reg = <0xff280000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "apb_pclk";
+ resets = <&cru SRST_TSADC>;
+ reset-names = "tsadc-apb";
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-temp = <95000>;
+ rockchip,hw-tshut-mode = <0>;
+ rockchip,hw-tshut-polarity = <0>;
+ };
diff --git a/Bindings/timer/allwinner,sun4i-a10-timer.yaml b/Bindings/timer/allwinner,sun4i-a10-timer.yaml
index 1c7cf32..53fd24b 100644
--- a/Bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -12,11 +12,18 @@
properties:
compatible:
- enum:
- - allwinner,sun4i-a10-timer
- - allwinner,sun8i-a23-timer
- - allwinner,sun8i-v3s-timer
- - allwinner,suniv-f1c100s-timer
+ oneOf:
+ - enum:
+ - allwinner,sun4i-a10-timer
+ - allwinner,sun8i-a23-timer
+ - allwinner,sun8i-v3s-timer
+ - allwinner,suniv-f1c100s-timer
+ - items:
+ - enum:
+ - allwinner,sun50i-a64-timer
+ - allwinner,sun50i-h6-timer
+ - allwinner,sun50i-h616-timer
+ - const: allwinner,sun8i-a23-timer
reg:
maxItems: 1
@@ -34,8 +41,8 @@
- if:
properties:
compatible:
- items:
- const: allwinner,sun4i-a10-timer
+ enum:
+ - allwinner,sun4i-a10-timer
then:
properties:
@@ -46,8 +53,8 @@
- if:
properties:
compatible:
- items:
- const: allwinner,sun8i-a23-timer
+ enum:
+ - allwinner,sun8i-a23-timer
then:
properties:
@@ -58,20 +65,9 @@
- if:
properties:
compatible:
- items:
- const: allwinner,sun8i-v3s-timer
-
- then:
- properties:
- interrupts:
- minItems: 3
- maxItems: 3
-
- - if:
- properties:
- compatible:
- items:
- const: allwinner,suniv-f1c100s-timer
+ enum:
+ - allwinner,sun8i-v3s-timer
+ - allwinner,suniv-f1c100s-timer
then:
properties:
diff --git a/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml
index b6a6d03..2ecac75 100644
--- a/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml
+++ b/Bindings/timer/allwinner,sun5i-a13-hstimer.yaml
@@ -24,7 +24,6 @@
interrupts:
minItems: 2
- maxItems: 4
items:
- description: Timer 0 Interrupt
- description: Timer 1 Interrupt
diff --git a/Bindings/timer/arm,arch_timer.yaml b/Bindings/timer/arm,arch_timer.yaml
index 7f5e3af..df8ce87 100644
--- a/Bindings/timer/arm,arch_timer.yaml
+++ b/Bindings/timer/arm,arch_timer.yaml
@@ -35,7 +35,6 @@
interrupts:
minItems: 1
- maxItems: 5
items:
- description: secure timer irq
- description: non-secure timer irq
diff --git a/Bindings/timer/arm,arch_timer_mmio.yaml b/Bindings/timer/arm,arch_timer_mmio.yaml
index d83a1f9..cd2176c 100644
--- a/Bindings/timer/arm,arch_timer_mmio.yaml
+++ b/Bindings/timer/arm,arch_timer_mmio.yaml
@@ -71,14 +71,12 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: physical timer irq
- description: virtual timer irq
reg:
minItems: 1
- maxItems: 2
items:
- description: 1st view base address
- description: 2nd optional view base address
diff --git a/Bindings/timer/arm,twd-timer.yaml b/Bindings/timer/arm,twd-timer.yaml
new file mode 100644
index 0000000..5684df6
--- /dev/null
+++ b/Bindings/timer/arm,twd-timer.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Timer-Watchdog Timer
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description:
+ ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
+ Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
+ and watchdog.
+
+ The TWD is usually attached to a GIC to deliver its two per-processor
+ interrupts.
+
+properties:
+ compatible:
+ enum:
+ - arm,cortex-a9-twd-timer
+ - arm,cortex-a5-twd-timer
+ - arm,arm11mp-twd-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ always-on:
+ description:
+ If present, the timer is powered through an always-on power domain,
+ therefore it never loses context.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@2c000600 {
+ compatible = "arm,arm11mp-twd-timer";
+ reg = <0x2c000600 0x20>;
+ interrupts = <GIC_PPI 13 0xf01>;
+ };
diff --git a/Bindings/timer/arm,twd.txt b/Bindings/timer/arm,twd.txt
deleted file mode 100644
index 383ea19..0000000
--- a/Bindings/timer/arm,twd.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* ARM Timer Watchdog
-
-ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
-Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
-and watchdog.
-
-The TWD is usually attached to a GIC to deliver its two per-processor
-interrupts.
-
-** Timer node required properties:
-
-- compatible : Should be one of:
- "arm,cortex-a9-twd-timer"
- "arm,cortex-a5-twd-timer"
- "arm,arm11mp-twd-timer"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD timer
- register window.
-
-Optional
-
-- always-on : a boolean property. If present, the timer is powered through
- an always-on power domain, therefore it never loses context.
-
-Example:
-
- twd-timer@2c000600 {
- compatible = "arm,arm11mp-twd-timer"";
- reg = <0x2c000600 0x20>;
- interrupts = <1 13 0xf01>;
- };
-
-** Watchdog node properties:
-
-- compatible : Should be one of:
- "arm,cortex-a9-twd-wdt"
- "arm,cortex-a5-twd-wdt"
- "arm,arm11mp-twd-wdt"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD watchdog
- register window.
-
-Example:
-
- twd-watchdog@2c000620 {
- compatible = "arm,arm11mp-twd-wdt";
- reg = <0x2c000620 0x20>;
- interrupts = <1 14 0xf01>;
- };
diff --git a/Bindings/timer/intel,ixp4xx-timer.yaml b/Bindings/timer/intel,ixp4xx-timer.yaml
index a8de99b..f32575d 100644
--- a/Bindings/timer/intel,ixp4xx-timer.yaml
+++ b/Bindings/timer/intel,ixp4xx-timer.yaml
@@ -22,7 +22,6 @@
interrupts:
minItems: 1
- maxItems: 2
items:
- description: Timer 1 interrupt
- description: Timer 2 interrupt
diff --git a/Bindings/timer/renesas,tmu.yaml b/Bindings/timer/renesas,tmu.yaml
index f0f0f12..c571691 100644
--- a/Bindings/timer/renesas,tmu.yaml
+++ b/Bindings/timer/renesas,tmu.yaml
@@ -36,6 +36,7 @@
- renesas,tmu-r8a77980 # R-Car V3H
- renesas,tmu-r8a77990 # R-Car E3
- renesas,tmu-r8a77995 # R-Car D3
+ - renesas,tmu-r8a779a0 # R-Car V3U
- const: renesas,tmu
reg:
diff --git a/Bindings/timer/renesas,tpu.txt b/Bindings/timer/renesas,tpu.txt
deleted file mode 100644
index 1d46f9d..0000000
--- a/Bindings/timer/renesas,tpu.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Renesas H8/300 Timer Pulse Unit
-
-The TPU is a 16bit timer/counter with configurable clock inputs and
-programmable compare match.
-This implementation support only cascade mode.
-
-Required Properties:
-
- - compatible: must contain "renesas,tpu"
- - reg: base address and length of the registers block in 2 channel.
- - clocks: a list of phandle, one for each entry in clock-names.
- - clock-names: must contain "peripheral_clk" for the functional clock.
-
-
-Example:
- tpu: tpu@ffffe0 {
- compatible = "renesas,tpu";
- reg = <0xffffe0 16>, <0xfffff0 12>;
- clocks = <&pclk>;
- clock-names = "peripheral_clk";
- };
diff --git a/Bindings/timer/renesas,tpu.yaml b/Bindings/timer/renesas,tpu.yaml
new file mode 100644
index 0000000..01554df
--- /dev/null
+++ b/Bindings/timer/renesas,tpu.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas H8/300 Timer Pulse Unit
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description:
+ The TPU is a 16bit timer/counter with configurable clock inputs and
+ programmable compare match.
+ This implementation supports only cascade mode.
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: renesas,tpu
+ '#pwm-cells': false
+ required:
+ - compatible
+
+properties:
+ compatible:
+ const: renesas,tpu
+
+ reg:
+ items:
+ - description: First channel
+ - description: Second channel
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ tpu: tpu@ffffe0 {
+ compatible = "renesas,tpu";
+ reg = <0xffffe0 16>, <0xfffff0 12>;
+ clocks = <&pclk>;
+ clock-names = "fck";
+ };
diff --git a/Bindings/trivial-devices.yaml b/Bindings/trivial-devices.yaml
index 8341e9d..919a4bf 100644
--- a/Bindings/trivial-devices.yaml
+++ b/Bindings/trivial-devices.yaml
@@ -73,6 +73,8 @@
- dallas,ds4510
# Digital Thermometer and Thermostat
- dallas,ds75
+ # Delta Electronics DPS920AB 920W 54V Power Supply
+ - delta,dps920ab
# 1/4 Brick DC/DC Regulated Power Module
- delta,q54sj108a2
# Devantech SRF02 ultrasonic ranger in I2C mode
@@ -103,6 +105,8 @@
- fsl,mpl3115
# MPR121: Proximity Capacitive Touch Sensor Controller
- fsl,mpr121
+ # Monolithic Power Systems Inc. multi-phase controller mp2888
+ - mps,mp2888
# Monolithic Power Systems Inc. multi-phase controller mp2975
- mps,mp2975
# G751: Digital Temperature Sensor and Thermal Watchdog with Two-Wire Interface
@@ -173,8 +177,14 @@
- meas,tsys01
# MEMSIC magnetometer
- memsic,mmc35240
+ # MEMSIC 3-axis accelerometer
+ - memsic,mx4005
# MEMSIC 2-axis 8-bit digital accelerometer
- memsic,mxc6225
+ # MEMSIC 2-axis 8-bit digital accelerometer
+ - memsic,mxc6255
+ # MEMSIC 3-axis accelerometer
+ - memsic,mxc6655
# Microchip differential I2C ADC, 1 Channel, 18 bit
- microchip,mcp3421
# Microchip differential I2C ADC, 2 Channel, 18 bit
@@ -259,6 +269,10 @@
- sensirion,sgpc3
# Sensirion multi-pixel gas sensor with I2C interface
- sensirion,sgp30
+ # Sensortek 3 axis accelerometer
+ - sensortek,stk8312
+ # Sensortek 3 axis accelerometer
+ - sensortek,stk8ba50
# SGX Sensortech VZ89X Sensors
- sgx,vz89x
# Relative Humidity and Temperature Sensors
@@ -268,6 +282,8 @@
# Socionext SynQuacer TPM MMIO module
- socionext,synquacer-tpm-mmio
# i2c serial eeprom (24cxx)
+ - sparkfun,qwiic-joystick
+ # SparkFun Qwiic Joystick (COM-15168) with i2c interface
- st,24c256
# Ambient Light Sensor with SMBUS/Two Wire Serial Interface
- taos,tsl2550
diff --git a/Bindings/usb/allwinner,sun4i-a10-musb.yaml b/Bindings/usb/allwinner,sun4i-a10-musb.yaml
index 0f520f1..933fa35 100644
--- a/Bindings/usb/allwinner,sun4i-a10-musb.yaml
+++ b/Bindings/usb/allwinner,sun4i-a10-musb.yaml
@@ -22,6 +22,9 @@
- allwinner,sun8i-a83t-musb
- allwinner,sun50i-h6-musb
- const: allwinner,sun8i-a33-musb
+ - items:
+ - const: allwinner,sun50i-h616-musb
+ - const: allwinner,sun8i-h3-musb
reg:
maxItems: 1
diff --git a/Bindings/usb/cdns,usb3.yaml b/Bindings/usb/cdns,usb3.yaml
index a407e11..dc9d6ed 100644
--- a/Bindings/usb/cdns,usb3.yaml
+++ b/Bindings/usb/cdns,usb3.yaml
@@ -28,9 +28,9 @@
interrupts:
minItems: 3
items:
- - description: OTG/DRD controller interrupt
- description: XHCI host controller interrupt
- description: Device controller interrupt
+ - description: OTG/DRD controller interrupt
- description: interrupt used to wake up core, e.g when usbcmd.rs is
cleared by xhci core, this interrupt is optional
@@ -75,6 +75,7 @@
- reg
- reg-names
- interrupts
+ - interrupt-names
additionalProperties: false
diff --git a/Bindings/usb/dwc2.yaml b/Bindings/usb/dwc2.yaml
index e5ee51b..10c7d9b 100644
--- a/Bindings/usb/dwc2.yaml
+++ b/Bindings/usb/dwc2.yaml
@@ -24,6 +24,7 @@
- rockchip,rk3188-usb
- rockchip,rk3228-usb
- rockchip,rk3288-usb
+ - rockchip,rk3308-usb
- rockchip,rk3328-usb
- rockchip,rk3368-usb
- rockchip,rv1108-usb
diff --git a/Bindings/usb/maxim,max3420-udc.yaml b/Bindings/usb/maxim,max3420-udc.yaml
index 4241d38..1d893d3 100644
--- a/Bindings/usb/maxim,max3420-udc.yaml
+++ b/Bindings/usb/maxim,max3420-udc.yaml
@@ -30,14 +30,12 @@
- description: usb irq from max3420
- description: vbus detection irq
minItems: 1
- maxItems: 2
interrupt-names:
items:
- const: udc
- const: vbus
minItems: 1
- maxItems: 2
spi-max-frequency:
maximum: 26000000
diff --git a/Bindings/usb/nvidia,tegra-xudc.yaml b/Bindings/usb/nvidia,tegra-xudc.yaml
index e60e590..8428415 100644
--- a/Bindings/usb/nvidia,tegra-xudc.yaml
+++ b/Bindings/usb/nvidia,tegra-xudc.yaml
@@ -25,7 +25,6 @@
reg:
minItems: 2
- maxItems: 3
items:
- description: XUSB device controller registers
- description: XUSB device PCI Config registers
@@ -33,7 +32,6 @@
reg-names:
minItems: 2
- maxItems: 3
items:
- const: base
- const: fpci
@@ -45,7 +43,6 @@
clocks:
minItems: 4
- maxItems: 5
items:
- description: Clock to enable core XUSB dev clock.
- description: Clock to enable XUSB super speed clock.
@@ -55,7 +52,6 @@
clock-names:
minItems: 4
- maxItems: 5
items:
- const: dev
- const: ss
diff --git a/Bindings/usb/nxp,isp1760.yaml b/Bindings/usb/nxp,isp1760.yaml
new file mode 100644
index 0000000..a88f99a
--- /dev/null
+++ b/Bindings/usb/nxp,isp1760.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/nxp,isp1760.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP ISP1760 family controller bindings
+
+maintainers:
+ - Sebastian Siewior <bigeasy@linutronix.de>
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description: |
+ NXP ISP1760 family, which includes ISP1760/1761/1763 devicetree controller
+ bindings
+
+properties:
+ compatible:
+ enum:
+ - nxp,usb-isp1760
+ - nxp,usb-isp1761
+ - nxp,usb-isp1763
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: Host controller interrupt
+ - description: Device controller interrupt in isp1761
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: host
+ - const: peripheral
+
+ bus-width:
+ description:
+ Number of data lines.
+ enum: [8, 16, 32]
+ default: 32
+
+ dr_mode:
+ enum:
+ - host
+ - peripheral
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ usb@40200000 {
+ compatible = "nxp,usb-isp1763";
+ reg = <0x40200000 0x100000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <16>;
+ dr_mode = "host";
+ };
+
+...
diff --git a/Bindings/usb/qcom,dwc3.yaml b/Bindings/usb/qcom,dwc3.yaml
index 413299b..4e64517 100644
--- a/Bindings/usb/qcom,dwc3.yaml
+++ b/Bindings/usb/qcom,dwc3.yaml
@@ -19,6 +19,8 @@
- qcom,sc7280-dwc3
- qcom,sdm845-dwc3
- qcom,sdx55-dwc3
+ - qcom,sm4250-dwc3
+ - qcom,sm6115-dwc3
- qcom,sm8150-dwc3
- qcom,sm8250-dwc3
- qcom,sm8350-dwc3
diff --git a/Bindings/usb/realtek,rts5411.yaml b/Bindings/usb/realtek,rts5411.yaml
new file mode 100644
index 0000000..04ee255
--- /dev/null
+++ b/Bindings/usb/realtek,rts5411.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/realtek,rts5411.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Binding for the Realtek RTS5411 USB 3.0 hub controller
+
+maintainers:
+ - Matthias Kaehlcke <mka@chromium.org>
+
+allOf:
+ - $ref: usb-device.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - usbbda,5411
+ - usbbda,411
+
+ reg: true
+
+ vdd-supply:
+ description:
+ phandle to the regulator that provides power to the hub.
+
+ companion-hub:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description:
+ phandle to the companion hub on the controller.
+
+required:
+ - companion-hub
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ usb {
+ dr_mode = "host";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 2.0 hub on port 1 */
+ hub_2_0: hub@1 {
+ compatible = "usbbda,5411";
+ reg = <1>;
+ vdd-supply = <&pp3300_hub>;
+ companion-hub = <&hub_3_0>;
+ };
+
+ /* 3.0 hub on port 2 */
+ hub_3_0: hub@2 {
+ compatible = "usbbda,411";
+ reg = <2>;
+ vdd-supply = <&pp3300_hub>;
+ companion-hub = <&hub_2_0>;
+ };
+ };
diff --git a/Bindings/usb/renesas,usbhs.yaml b/Bindings/usb/renesas,usbhs.yaml
index e67223d..ad73339 100644
--- a/Bindings/usb/renesas,usbhs.yaml
+++ b/Bindings/usb/renesas,usbhs.yaml
@@ -53,7 +53,6 @@
clocks:
minItems: 1
- maxItems: 3
items:
- description: USB 2.0 host
- description: USB 2.0 peripheral
@@ -86,7 +85,6 @@
dma-names:
minItems: 2
- maxItems: 4
items:
- const: ch0
- const: ch1
@@ -100,7 +98,6 @@
resets:
minItems: 1
- maxItems: 2
items:
- description: USB 2.0 host
- description: USB 2.0 peripheral
diff --git a/Bindings/usb/ti,j721e-usb.yaml b/Bindings/usb/ti,j721e-usb.yaml
index 7ec87a7..a634774 100644
--- a/Bindings/usb/ti,j721e-usb.yaml
+++ b/Bindings/usb/ti,j721e-usb.yaml
@@ -27,7 +27,7 @@
description:
PM domain provider node and an args specifier containing
the USB device id value. See,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
maxItems: 1
clocks:
diff --git a/Bindings/usb/ti,keystone-dwc3.yaml b/Bindings/usb/ti,keystone-dwc3.yaml
index 9a068d3..f6e91a5 100644
--- a/Bindings/usb/ti,keystone-dwc3.yaml
+++ b/Bindings/usb/ti,keystone-dwc3.yaml
@@ -47,7 +47,7 @@
description: Should contain a phandle to a PM domain provider node
and an args specifier containing the USB device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
phys:
maxItems: 1
diff --git a/Bindings/vendor-prefixes.yaml b/Bindings/vendor-prefixes.yaml
index b868cef..07fb0d2 100644
--- a/Bindings/vendor-prefixes.yaml
+++ b/Bindings/vendor-prefixes.yaml
@@ -249,6 +249,8 @@
description: Colorful GRP, Shenzhen Xueyushi Technology Ltd.
"^compulab,.*":
description: CompuLab Ltd.
+ "^congatec,.*":
+ description: congatec GmbH
"^coreriver,.*":
description: CORERIVER Semiconductor Co.,Ltd.
"^corpro,.*":
@@ -315,6 +317,8 @@
description: DPTechnics
"^dragino,.*":
description: Dragino Technology Co., Limited
+ "^ds,.*":
+ description: DaSheng, Inc.
"^dserve,.*":
description: dServe Technology B.V.
"^dynaimage,.*":
@@ -409,6 +413,8 @@
description: Firefly
"^focaltech,.*":
description: FocalTech Systems Co.,Ltd
+ "^forlinx,.*":
+ description: Baoding Forlinx Embedded Technology Co., Ltd.
"^frida,.*":
description: Shenzhen Frida LCD Co., Ltd.
"^friendlyarm,.*":
@@ -472,7 +478,7 @@
"^hirschmann,.*":
description: Hirschmann Automation and Control GmbH
"^hisilicon,.*":
- description: Hisilicon Limited.
+ description: HiSilicon Limited.
"^hit,.*":
description: Hitachi Ltd.
"^hitex,.*":
@@ -533,6 +539,8 @@
description: Innolux Corporation
"^inside-secure,.*":
description: INSIDE Secure
+ "^insignal,.*":
+ description: Insignal Ltd.
"^inspur,.*":
description: Inspur Corporation
"^intel,.*":
@@ -830,6 +838,8 @@
description: Opal Kelly Incorporated
"^opencores,.*":
description: OpenCores.org
+ "^openembed,.*":
+ description: OpenEmbed
"^openrisc,.*":
description: OpenRISC.io
"^option,.*":
@@ -1076,6 +1086,8 @@
description: Sony Corporation
"^spansion,.*":
description: Spansion Inc.
+ "^sparkfun,.*":
+ description: SparkFun Electronics
"^sprd,.*":
description: Spreadtrum Communications Inc.
"^sst,.*":
@@ -1085,6 +1097,8 @@
(formerly part of MStar Semiconductor, Inc.)
"^st,.*":
description: STMicroelectronics
+ "^starfive,.*":
+ description: StarFive Technology Co. Ltd.
"^starry,.*":
description: Starry Electronic Technology (ShenZhen) Co., LTD
"^startek,.*":
@@ -1244,6 +1258,8 @@
description: Western Digital Corp.
"^we,.*":
description: Würth Elektronik GmbH.
+ "^welltech,.*":
+ description: Welltech Computer Co., Limited.
"^wetek,.*":
description: WeTek Electronics, limited.
"^wexler,.*":
diff --git a/Bindings/virtio/mmio.txt b/Bindings/virtio/mmio.txt
deleted file mode 100644
index 0a575f3..0000000
--- a/Bindings/virtio/mmio.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-* virtio memory mapped device
-
-See https://ozlabs.org/~rusty/virtio-spec/ for more details.
-
-Required properties:
-
-- compatible: "virtio,mmio" compatibility string
-- reg: control registers base address and size including configuration space
-- interrupts: interrupt generated by the device
-
-Required properties for virtio-iommu:
-
-- #iommu-cells: When the node corresponds to a virtio-iommu device, it is
- linked to DMA masters using the "iommus" or "iommu-map"
- properties [1][2]. #iommu-cells specifies the size of the
- "iommus" property. For virtio-iommu #iommu-cells must be
- 1, each cell describing a single endpoint ID.
-
-Optional properties:
-
-- iommus: If the device accesses memory through an IOMMU, it should
- have an "iommus" property [1]. Since virtio-iommu itself
- does not access memory through an IOMMU, the "virtio,mmio"
- node cannot have both an "#iommu-cells" and an "iommus"
- property.
-
-Example:
-
- virtio_block@3000 {
- compatible = "virtio,mmio";
- reg = <0x3000 0x100>;
- interrupts = <41>;
-
- /* Device has endpoint ID 23 */
- iommus = <&viommu 23>
- }
-
- viommu: iommu@3100 {
- compatible = "virtio,mmio";
- reg = <0x3100 0x100>;
- interrupts = <42>;
-
- #iommu-cells = <1>
- }
-
-[1] Documentation/devicetree/bindings/iommu/iommu.txt
-[2] Documentation/devicetree/bindings/pci/pci-iommu.txt
diff --git a/Bindings/virtio/mmio.yaml b/Bindings/virtio/mmio.yaml
new file mode 100644
index 0000000..d465970
--- /dev/null
+++ b/Bindings/virtio/mmio.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/virtio/mmio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: virtio memory mapped devices
+
+maintainers:
+ - Jean-Philippe Brucker <jean-philippe@linaro.org>
+
+description:
+ See https://www.oasis-open.org/committees/tc_home.php?wg_abbrev=virtio for
+ more details.
+
+properties:
+ compatible:
+ const: virtio,mmio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#iommu-cells':
+ description: Required when the node corresponds to a virtio-iommu device.
+ const: 1
+
+ iommus:
+ description: Required for devices making accesses thru an IOMMU.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ virtio@3000 {
+ compatible = "virtio,mmio";
+ reg = <0x3000 0x100>;
+ interrupts = <41>;
+
+ /* Device has endpoint ID 23 */
+ iommus = <&viommu 23>;
+ };
+
+ viommu: iommu@3100 {
+ compatible = "virtio,mmio";
+ reg = <0x3100 0x100>;
+ interrupts = <42>;
+
+ #iommu-cells = <1>;
+ };
+
+...
diff --git a/Bindings/watchdog/arm,sbsa-gwdt.yaml b/Bindings/watchdog/arm,sbsa-gwdt.yaml
new file mode 100644
index 0000000..6bfa463
--- /dev/null
+++ b/Bindings/watchdog/arm,sbsa-gwdt.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/arm,sbsa-gwdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SBSA (Server Base System Architecture) Generic Watchdog
+
+maintainers:
+ - Fu Wei <fu.wei@linaro.org>
+
+description: |
+ The SBSA Generic Watchdog Timer is used to force a reset of the system after
+ two stages of timeout have elapsed. A detailed definition of the watchdog
+ timer can be found in the ARM document: ARM-DEN-0029 - Server Base System
+ Architecture (SBSA)
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: arm,sbsa-gwdt
+
+ reg:
+ items:
+ - description: Watchdog control frame
+ - description: Refresh frame
+
+ interrupts:
+ description: The Watchdog Signal 0 (WS0) SPI (Shared Peripheral Interrupt)
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+
+ watchdog@2a440000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x2a440000 0x1000>,
+ <0x2a450000 0x1000>;
+ interrupts = <0 27 4>;
+ timeout-sec = <30>;
+ };
+...
diff --git a/Bindings/watchdog/arm,twd-wdt.yaml b/Bindings/watchdog/arm,twd-wdt.yaml
new file mode 100644
index 0000000..bb89018
--- /dev/null
+++ b/Bindings/watchdog/arm,twd-wdt.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Timer-Watchdog Watchdog
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description:
+ ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
+ Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
+ and watchdog.
+
+ The TWD is usually attached to a GIC to deliver its two per-processor
+ interrupts.
+
+properties:
+ compatible:
+ enum:
+ - arm,cortex-a9-twd-wdt
+ - arm,cortex-a5-twd-wdt
+ - arm,arm11mp-twd-wdt
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ watchdog@2c000620 {
+ compatible = "arm,arm11mp-twd-wdt";
+ reg = <0x2c000620 0x20>;
+ interrupts = <GIC_PPI 14 0xf01>;
+ };
diff --git a/Bindings/watchdog/atmel,sama5d4-wdt.yaml b/Bindings/watchdog/atmel,sama5d4-wdt.yaml
new file mode 100644
index 0000000..9856cd7
--- /dev/null
+++ b/Bindings/watchdog/atmel,sama5d4-wdt.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller
+
+maintainers:
+ - Eugen Hristev <eugen.hristev@microchip.com>
+
+allOf:
+ - $ref: "watchdog.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - atmel,sama5d4-wdt
+ - microchip,sam9x60-wdt
+ - microchip,sama7g5-wdt
+
+ reg:
+ maxItems: 1
+
+ atmel,watchdog-type:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: should be hardware or software.
+ oneOf:
+ - description:
+ Enable watchdog fault reset. A watchdog fault triggers
+ watchdog reset.
+ const: hardware
+ - description:
+ Enable watchdog fault interrupt. A watchdog fault asserts
+ watchdog interrupt.
+ const: software
+ default: hardware
+
+ atmel,idle-halt:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ present if you want to stop the watchdog when the CPU is in idle state.
+ CAUTION: This property should be used with care, it actually makes the
+ watchdog not counting when the CPU is in idle state, therefore the
+ watchdog reset time depends on mean CPU usage and will not reset at all
+ if the CPU stop working while it is in idle state, which is probably
+ not what you want.
+
+ atmel,dbg-halt:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ present if you want to stop the watchdog when the CPU is in debug state.
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ watchdog@fc068640 {
+ compatible = "atmel,sama5d4-wdt";
+ reg = <0xfc068640 0x10>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
+ timeout-sec = <10>;
+ atmel,watchdog-type = "hardware";
+ atmel,dbg-halt;
+ atmel,idle-halt;
+ };
+
+...
diff --git a/Bindings/watchdog/atmel-sama5d4-wdt.txt b/Bindings/watchdog/atmel-sama5d4-wdt.txt
deleted file mode 100644
index 44727fc..0000000
--- a/Bindings/watchdog/atmel-sama5d4-wdt.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-* Atmel SAMA5D4 Watchdog Timer (WDT) Controller
-
-Required properties:
-- compatible: "atmel,sama5d4-wdt" or "microchip,sam9x60-wdt"
-- reg: base physical address and length of memory mapped region.
-
-Optional properties:
-- timeout-sec: watchdog timeout value (in seconds).
-- interrupts: interrupt number to the CPU.
-- atmel,watchdog-type: should be "hardware" or "software".
- "hardware": enable watchdog fault reset. A watchdog fault triggers
- watchdog reset.
- "software": enable watchdog fault interrupt. A watchdog fault asserts
- watchdog interrupt.
-- atmel,idle-halt: present if you want to stop the watchdog when the CPU is
- in idle state.
- CAUTION: This property should be used with care, it actually makes the
- watchdog not counting when the CPU is in idle state, therefore the
- watchdog reset time depends on mean CPU usage and will not reset at all
- if the CPU stop working while it is in idle state, which is probably
- not what you want.
-- atmel,dbg-halt: present if you want to stop the watchdog when the CPU is
- in debug state.
-
-Example:
- watchdog@fc068640 {
- compatible = "atmel,sama5d4-wdt";
- reg = <0xfc068640 0x10>;
- interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
- timeout-sec = <10>;
- atmel,watchdog-type = "hardware";
- atmel,dbg-halt;
- atmel,idle-halt;
- };
diff --git a/Bindings/watchdog/mstar,msc313e-wdt.yaml b/Bindings/watchdog/mstar,msc313e-wdt.yaml
new file mode 100644
index 0000000..e3e8b86
--- /dev/null
+++ b/Bindings/watchdog/mstar,msc313e-wdt.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/mstar,msc313e-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar Watchdog Device Tree Bindings
+
+maintainers:
+ - Daniel Palmer <daniel@0x0f.com>
+ - Romain Perier <romain.perier@gmail.com>
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ enum:
+ - mstar,msc313e-wdt
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ watchdog@6000 {
+ compatible = "mstar,msc313e-wdt";
+ reg = <0x6000 0x1f>;
+ clocks = <&xtal_div2>;
+ };
diff --git a/Bindings/watchdog/mtk-wdt.txt b/Bindings/watchdog/mtk-wdt.txt
index e36ba60..416d716 100644
--- a/Bindings/watchdog/mtk-wdt.txt
+++ b/Bindings/watchdog/mtk-wdt.txt
@@ -1,5 +1,8 @@
Mediatek SoCs Watchdog timer
+The watchdog supports a pre-timeout interrupt that fires timeout-sec/2
+before the expiry.
+
Required properties:
- compatible should contain:
@@ -13,10 +16,12 @@
"mediatek,mt8183-wdt": for MT8183
"mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516
"mediatek,mt8192-wdt": for MT8192
+ "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195
- reg : Specifies base physical address and size of the registers.
Optional properties:
+- interrupts: Watchdog pre-timeout (bark) interrupt.
- timeout-sec: contains the watchdog timeout in seconds.
- #reset-cells: Should be 1.
@@ -26,6 +31,7 @@
compatible = "mediatek,mt8183-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
timeout-sec = <10>;
#reset-cells = <1>;
};
diff --git a/Bindings/watchdog/qcom-wdt.yaml b/Bindings/watchdog/qcom-wdt.yaml
index b8e4118..ba60bdf 100644
--- a/Bindings/watchdog/qcom-wdt.yaml
+++ b/Bindings/watchdog/qcom-wdt.yaml
@@ -17,6 +17,7 @@
enum:
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sc7180
+ - qcom,apss-wdt-sc7280
- qcom,apss-wdt-sdm845
- qcom,apss-wdt-sdx55
- qcom,apss-wdt-sm8150
diff --git a/Bindings/watchdog/sbsa-gwdt.txt b/Bindings/watchdog/sbsa-gwdt.txt
deleted file mode 100644
index 6f2d5f9..0000000
--- a/Bindings/watchdog/sbsa-gwdt.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* SBSA (Server Base System Architecture) Generic Watchdog
-
-The SBSA Generic Watchdog Timer is used to force a reset of the system
-after two stages of timeout have elapsed. A detailed definition of the
-watchdog timer can be found in the ARM document: ARM-DEN-0029 - Server
-Base System Architecture (SBSA)
-
-Required properties:
-- compatible: Should at least contain "arm,sbsa-gwdt".
-
-- reg: Each entry specifies the base physical address of a register frame
- and the length of that frame; currently, two frames must be defined,
- in this order:
- 1: Watchdog control frame;
- 2: Refresh frame.
-
-- interrupts: Should contain the Watchdog Signal 0 (WS0) SPI (Shared
- Peripheral Interrupt) number of SBSA Generic Watchdog.
-
-Optional properties
-- timeout-sec: Watchdog timeout values (in seconds).
-
-Example for FVP Foundation Model v8:
-
-watchdog@2a440000 {
- compatible = "arm,sbsa-gwdt";
- reg = <0x0 0x2a440000 0 0x1000>,
- <0x0 0x2a450000 0 0x1000>;
- interrupts = <0 27 4>;
- timeout-sec = <30>;
-};
diff --git a/Bindings/watchdog/snps,dw-wdt.yaml b/Bindings/watchdog/snps,dw-wdt.yaml
index b58596b..6461eb4 100644
--- a/Bindings/watchdog/snps,dw-wdt.yaml
+++ b/Bindings/watchdog/snps,dw-wdt.yaml
@@ -27,6 +27,7 @@
- rockchip,rk3328-wdt
- rockchip,rk3368-wdt
- rockchip,rk3399-wdt
+ - rockchip,rk3568-wdt
- rockchip,rv1108-wdt
- const: snps,dw-wdt
diff --git a/Bindings/watchdog/st,stm32-iwdg.yaml b/Bindings/watchdog/st,stm32-iwdg.yaml
index 3f1ba1d..481bf91 100644
--- a/Bindings/watchdog/st,stm32-iwdg.yaml
+++ b/Bindings/watchdog/st,stm32-iwdg.yaml
@@ -27,7 +27,6 @@
- description: Low speed clock
- description: Optional peripheral clock
minItems: 1
- maxItems: 2
clock-names:
items:
diff --git a/Bindings/writing-bindings.rst b/Bindings/writing-bindings.rst
index 45ff426..f7dfb98 100644
--- a/Bindings/writing-bindings.rst
+++ b/Bindings/writing-bindings.rst
@@ -52,7 +52,8 @@
constraints specific to the device.
- DO use common property unit suffixes for properties with scientific units.
- See property-units.txt.
+ Recommended suffixes are listed at
+ https://github.com/devicetree-org/dt-schema/blob/master/schemas/property-units.yaml
- DO define properties in terms of constraints. How many entries? What are
possible values? What is the order?
diff --git a/include/dt-bindings/clock/actions,s500-cmu.h b/include/dt-bindings/clock/actions,s500-cmu.h
index a250a52..a237eb2 100644
--- a/include/dt-bindings/clock/actions,s500-cmu.h
+++ b/include/dt-bindings/clock/actions,s500-cmu.h
@@ -74,10 +74,12 @@
#define CLK_RMII_REF 54
#define CLK_GPIO 55
-/* system clock (part 2) */
+/* additional clocks */
#define CLK_APB 56
#define CLK_DMAC 57
+#define CLK_NIC 58
+#define CLK_ETHERNET 59
-#define CLK_NR_CLKS (CLK_DMAC + 1)
+#define CLK_NR_CLKS (CLK_ETHERNET + 1)
#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */
diff --git a/include/dt-bindings/clock/hi3559av100-clock.h b/include/dt-bindings/clock/hi3559av100-clock.h
new file mode 100644
index 0000000..5fe7689
--- /dev/null
+++ b/include/dt-bindings/clock/hi3559av100-clock.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later or BSD-2-Clause */
+/*
+ * Copyright (c) 2019-2020, Huawei Tech. Co., Ltd.
+ *
+ * Author: Dongjiu Geng <gengdongjiu@huawei.com>
+ */
+
+#ifndef __DTS_HI3559AV100_CLOCK_H
+#define __DTS_HI3559AV100_CLOCK_H
+
+/* fixed rate */
+#define HI3559AV100_FIXED_1188M 1
+#define HI3559AV100_FIXED_1000M 2
+#define HI3559AV100_FIXED_842M 3
+#define HI3559AV100_FIXED_792M 4
+#define HI3559AV100_FIXED_750M 5
+#define HI3559AV100_FIXED_710M 6
+#define HI3559AV100_FIXED_680M 7
+#define HI3559AV100_FIXED_667M 8
+#define HI3559AV100_FIXED_631M 9
+#define HI3559AV100_FIXED_600M 10
+#define HI3559AV100_FIXED_568M 11
+#define HI3559AV100_FIXED_500M 12
+#define HI3559AV100_FIXED_475M 13
+#define HI3559AV100_FIXED_428M 14
+#define HI3559AV100_FIXED_400M 15
+#define HI3559AV100_FIXED_396M 16
+#define HI3559AV100_FIXED_300M 17
+#define HI3559AV100_FIXED_250M 18
+#define HI3559AV100_FIXED_198M 19
+#define HI3559AV100_FIXED_187p5M 20
+#define HI3559AV100_FIXED_150M 21
+#define HI3559AV100_FIXED_148p5M 22
+#define HI3559AV100_FIXED_125M 23
+#define HI3559AV100_FIXED_107M 24
+#define HI3559AV100_FIXED_100M 25
+#define HI3559AV100_FIXED_99M 26
+#define HI3559AV100_FIXED_74p25M 27
+#define HI3559AV100_FIXED_72M 28
+#define HI3559AV100_FIXED_60M 29
+#define HI3559AV100_FIXED_54M 30
+#define HI3559AV100_FIXED_50M 31
+#define HI3559AV100_FIXED_49p5M 32
+#define HI3559AV100_FIXED_37p125M 33
+#define HI3559AV100_FIXED_36M 34
+#define HI3559AV100_FIXED_32p4M 35
+#define HI3559AV100_FIXED_27M 36
+#define HI3559AV100_FIXED_25M 37
+#define HI3559AV100_FIXED_24M 38
+#define HI3559AV100_FIXED_12M 39
+#define HI3559AV100_FIXED_3M 40
+#define HI3559AV100_FIXED_1p6M 41
+#define HI3559AV100_FIXED_400K 42
+#define HI3559AV100_FIXED_100K 43
+#define HI3559AV100_FIXED_200M 44
+#define HI3559AV100_FIXED_75M 75
+
+#define HI3559AV100_I2C0_CLK 50
+#define HI3559AV100_I2C1_CLK 51
+#define HI3559AV100_I2C2_CLK 52
+#define HI3559AV100_I2C3_CLK 53
+#define HI3559AV100_I2C4_CLK 54
+#define HI3559AV100_I2C5_CLK 55
+#define HI3559AV100_I2C6_CLK 56
+#define HI3559AV100_I2C7_CLK 57
+#define HI3559AV100_I2C8_CLK 58
+#define HI3559AV100_I2C9_CLK 59
+#define HI3559AV100_I2C10_CLK 60
+#define HI3559AV100_I2C11_CLK 61
+
+#define HI3559AV100_SPI0_CLK 62
+#define HI3559AV100_SPI1_CLK 63
+#define HI3559AV100_SPI2_CLK 64
+#define HI3559AV100_SPI3_CLK 65
+#define HI3559AV100_SPI4_CLK 66
+#define HI3559AV100_SPI5_CLK 67
+#define HI3559AV100_SPI6_CLK 68
+
+#define HI3559AV100_EDMAC_CLK 69
+#define HI3559AV100_EDMAC_AXICLK 70
+#define HI3559AV100_EDMAC1_CLK 71
+#define HI3559AV100_EDMAC1_AXICLK 72
+#define HI3559AV100_VDMAC_CLK 73
+
+/* mux clocks */
+#define HI3559AV100_FMC_MUX 80
+#define HI3559AV100_SYSAPB_MUX 81
+#define HI3559AV100_UART_MUX 82
+#define HI3559AV100_SYSBUS_MUX 83
+#define HI3559AV100_A73_MUX 84
+#define HI3559AV100_MMC0_MUX 85
+#define HI3559AV100_MMC1_MUX 86
+#define HI3559AV100_MMC2_MUX 87
+#define HI3559AV100_MMC3_MUX 88
+
+/* gate clocks */
+#define HI3559AV100_FMC_CLK 90
+#define HI3559AV100_UART0_CLK 91
+#define HI3559AV100_UART1_CLK 92
+#define HI3559AV100_UART2_CLK 93
+#define HI3559AV100_UART3_CLK 94
+#define HI3559AV100_UART4_CLK 95
+#define HI3559AV100_MMC0_CLK 96
+#define HI3559AV100_MMC1_CLK 97
+#define HI3559AV100_MMC2_CLK 98
+#define HI3559AV100_MMC3_CLK 99
+
+#define HI3559AV100_ETH_CLK 100
+#define HI3559AV100_ETH_MACIF_CLK 101
+#define HI3559AV100_ETH1_CLK 102
+#define HI3559AV100_ETH1_MACIF_CLK 103
+
+/* complex */
+#define HI3559AV100_MAC0_CLK 110
+#define HI3559AV100_MAC1_CLK 111
+#define HI3559AV100_SATA_CLK 112
+#define HI3559AV100_USB_CLK 113
+#define HI3559AV100_USB1_CLK 114
+
+/* pll clocks */
+#define HI3559AV100_APLL_CLK 250
+#define HI3559AV100_GPLL_CLK 251
+
+#define HI3559AV100_CRG_NR_CLKS 256
+
+#define HI3559AV100_SHUB_SOURCE_SOC_24M 0
+#define HI3559AV100_SHUB_SOURCE_SOC_200M 1
+#define HI3559AV100_SHUB_SOURCE_SOC_300M 2
+#define HI3559AV100_SHUB_SOURCE_PLL 3
+#define HI3559AV100_SHUB_SOURCE_CLK 4
+
+#define HI3559AV100_SHUB_I2C0_CLK 10
+#define HI3559AV100_SHUB_I2C1_CLK 11
+#define HI3559AV100_SHUB_I2C2_CLK 12
+#define HI3559AV100_SHUB_I2C3_CLK 13
+#define HI3559AV100_SHUB_I2C4_CLK 14
+#define HI3559AV100_SHUB_I2C5_CLK 15
+#define HI3559AV100_SHUB_I2C6_CLK 16
+#define HI3559AV100_SHUB_I2C7_CLK 17
+
+#define HI3559AV100_SHUB_SPI_SOURCE_CLK 20
+#define HI3559AV100_SHUB_SPI4_SOURCE_CLK 21
+#define HI3559AV100_SHUB_SPI0_CLK 22
+#define HI3559AV100_SHUB_SPI1_CLK 23
+#define HI3559AV100_SHUB_SPI2_CLK 24
+#define HI3559AV100_SHUB_SPI3_CLK 25
+#define HI3559AV100_SHUB_SPI4_CLK 26
+
+#define HI3559AV100_SHUB_UART_CLK_32K 30
+#define HI3559AV100_SHUB_UART_SOURCE_CLK 31
+#define HI3559AV100_SHUB_UART_DIV_CLK 32
+#define HI3559AV100_SHUB_UART0_CLK 33
+#define HI3559AV100_SHUB_UART1_CLK 34
+#define HI3559AV100_SHUB_UART2_CLK 35
+#define HI3559AV100_SHUB_UART3_CLK 36
+#define HI3559AV100_SHUB_UART4_CLK 37
+#define HI3559AV100_SHUB_UART5_CLK 38
+#define HI3559AV100_SHUB_UART6_CLK 39
+
+#define HI3559AV100_SHUB_EDMAC_CLK 40
+
+#define HI3559AV100_SHUB_NR_CLKS 50
+
+#endif /* __DTS_HI3559AV100_CLOCK_H */
+
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 82b1fc8..2e60ce4 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -7,134 +7,6 @@
#ifndef __DT_BINDINGS_CLOCK_IMX_H
#define __DT_BINDINGS_CLOCK_IMX_H
-/* SCU Clocks */
-
-#define IMX_CLK_DUMMY 0
-
-/* CPU */
-#define IMX_A35_CLK 1
-
-/* LSIO SS */
-#define IMX_LSIO_MEM_CLK 2
-#define IMX_LSIO_BUS_CLK 3
-#define IMX_LSIO_PWM0_CLK 10
-#define IMX_LSIO_PWM1_CLK 11
-#define IMX_LSIO_PWM2_CLK 12
-#define IMX_LSIO_PWM3_CLK 13
-#define IMX_LSIO_PWM4_CLK 14
-#define IMX_LSIO_PWM5_CLK 15
-#define IMX_LSIO_PWM6_CLK 16
-#define IMX_LSIO_PWM7_CLK 17
-#define IMX_LSIO_GPT0_CLK 18
-#define IMX_LSIO_GPT1_CLK 19
-#define IMX_LSIO_GPT2_CLK 20
-#define IMX_LSIO_GPT3_CLK 21
-#define IMX_LSIO_GPT4_CLK 22
-#define IMX_LSIO_FSPI0_CLK 23
-#define IMX_LSIO_FSPI1_CLK 24
-
-/* Connectivity SS */
-#define IMX_CONN_AXI_CLK_ROOT 30
-#define IMX_CONN_AHB_CLK_ROOT 31
-#define IMX_CONN_IPG_CLK_ROOT 32
-#define IMX_CONN_SDHC0_CLK 40
-#define IMX_CONN_SDHC1_CLK 41
-#define IMX_CONN_SDHC2_CLK 42
-#define IMX_CONN_ENET0_ROOT_CLK 43
-#define IMX_CONN_ENET0_BYPASS_CLK 44
-#define IMX_CONN_ENET0_RGMII_CLK 45
-#define IMX_CONN_ENET1_ROOT_CLK 46
-#define IMX_CONN_ENET1_BYPASS_CLK 47
-#define IMX_CONN_ENET1_RGMII_CLK 48
-#define IMX_CONN_GPMI_BCH_IO_CLK 49
-#define IMX_CONN_GPMI_BCH_CLK 50
-#define IMX_CONN_USB2_ACLK 51
-#define IMX_CONN_USB2_BUS_CLK 52
-#define IMX_CONN_USB2_LPM_CLK 53
-
-/* HSIO SS */
-#define IMX_HSIO_AXI_CLK 60
-#define IMX_HSIO_PER_CLK 61
-
-/* Display controller SS */
-#define IMX_DC_AXI_EXT_CLK 70
-#define IMX_DC_AXI_INT_CLK 71
-#define IMX_DC_CFG_CLK 72
-#define IMX_DC0_PLL0_CLK 80
-#define IMX_DC0_PLL1_CLK 81
-#define IMX_DC0_DISP0_CLK 82
-#define IMX_DC0_DISP1_CLK 83
-#define IMX_DC0_BYPASS0_CLK 84
-#define IMX_DC0_BYPASS1_CLK 85
-
-/* MIPI-LVDS SS */
-#define IMX_MIPI_IPG_CLK 90
-#define IMX_MIPI0_PIXEL_CLK 100
-#define IMX_MIPI0_BYPASS_CLK 101
-#define IMX_MIPI0_LVDS_PIXEL_CLK 102
-#define IMX_MIPI0_LVDS_BYPASS_CLK 103
-#define IMX_MIPI0_LVDS_PHY_CLK 104
-#define IMX_MIPI0_I2C0_CLK 105
-#define IMX_MIPI0_I2C1_CLK 106
-#define IMX_MIPI0_PWM0_CLK 107
-#define IMX_MIPI1_PIXEL_CLK 108
-#define IMX_MIPI1_BYPASS_CLK 109
-#define IMX_MIPI1_LVDS_PIXEL_CLK 110
-#define IMX_MIPI1_LVDS_BYPASS_CLK 111
-#define IMX_MIPI1_LVDS_PHY_CLK 112
-#define IMX_MIPI1_I2C0_CLK 113
-#define IMX_MIPI1_I2C1_CLK 114
-#define IMX_MIPI1_PWM0_CLK 115
-
-/* IMG SS */
-#define IMX_IMG_AXI_CLK 120
-#define IMX_IMG_IPG_CLK 121
-#define IMX_IMG_PXL_CLK 122
-
-/* MIPI-CSI SS */
-#define IMX_CSI0_CORE_CLK 130
-#define IMX_CSI0_ESC_CLK 131
-#define IMX_CSI0_PWM0_CLK 132
-#define IMX_CSI0_I2C0_CLK 133
-
-/* PARALLER CSI SS */
-#define IMX_PARALLEL_CSI_DPLL_CLK 140
-#define IMX_PARALLEL_CSI_PIXEL_CLK 141
-#define IMX_PARALLEL_CSI_MCLK_CLK 142
-
-/* VPU SS */
-#define IMX_VPU_ENC_CLK 150
-#define IMX_VPU_DEC_CLK 151
-
-/* GPU SS */
-#define IMX_GPU0_CORE_CLK 160
-#define IMX_GPU0_SHADER_CLK 161
-
-/* ADMA SS */
-#define IMX_ADMA_IPG_CLK_ROOT 165
-#define IMX_ADMA_UART0_CLK 170
-#define IMX_ADMA_UART1_CLK 171
-#define IMX_ADMA_UART2_CLK 172
-#define IMX_ADMA_UART3_CLK 173
-#define IMX_ADMA_SPI0_CLK 174
-#define IMX_ADMA_SPI1_CLK 175
-#define IMX_ADMA_SPI2_CLK 176
-#define IMX_ADMA_SPI3_CLK 177
-#define IMX_ADMA_CAN0_CLK 178
-#define IMX_ADMA_CAN1_CLK 179
-#define IMX_ADMA_CAN2_CLK 180
-#define IMX_ADMA_I2C0_CLK 181
-#define IMX_ADMA_I2C1_CLK 182
-#define IMX_ADMA_I2C2_CLK 183
-#define IMX_ADMA_I2C3_CLK 184
-#define IMX_ADMA_FTM0_CLK 185
-#define IMX_ADMA_FTM1_CLK 186
-#define IMX_ADMA_ADC0_CLK 187
-#define IMX_ADMA_PWM_CLK 188
-#define IMX_ADMA_LCD_CLK 189
-
-#define IMX_SCU_CLK_END 190
-
/* LPCG clocks */
/* LSIO SS LPCG */
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 82e907c..afa74d7 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -405,25 +405,6 @@
#define IMX8MQ_VIDEO2_PLL1_REF_SEL 266
-#define IMX8MQ_SYS1_PLL_40M_CG 267
-#define IMX8MQ_SYS1_PLL_80M_CG 268
-#define IMX8MQ_SYS1_PLL_100M_CG 269
-#define IMX8MQ_SYS1_PLL_133M_CG 270
-#define IMX8MQ_SYS1_PLL_160M_CG 271
-#define IMX8MQ_SYS1_PLL_200M_CG 272
-#define IMX8MQ_SYS1_PLL_266M_CG 273
-#define IMX8MQ_SYS1_PLL_400M_CG 274
-#define IMX8MQ_SYS1_PLL_800M_CG 275
-#define IMX8MQ_SYS2_PLL_50M_CG 276
-#define IMX8MQ_SYS2_PLL_100M_CG 277
-#define IMX8MQ_SYS2_PLL_125M_CG 278
-#define IMX8MQ_SYS2_PLL_166M_CG 279
-#define IMX8MQ_SYS2_PLL_200M_CG 280
-#define IMX8MQ_SYS2_PLL_250M_CG 281
-#define IMX8MQ_SYS2_PLL_333M_CG 282
-#define IMX8MQ_SYS2_PLL_500M_CG 283
-#define IMX8MQ_SYS2_PLL_1000M_CG 284
-
#define IMX8MQ_CLK_GPU_CORE 285
#define IMX8MQ_CLK_GPU_SHADER 286
#define IMX8MQ_CLK_M4_CORE 287
diff --git a/include/dt-bindings/clock/jz4760-cgu.h b/include/dt-bindings/clock/jz4760-cgu.h
new file mode 100644
index 0000000..4bb2e19
--- /dev/null
+++ b/include/dt-bindings/clock/jz4760-cgu.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,jz4760-cgu DT binding.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
+#define __DT_BINDINGS_CLOCK_JZ4760_CGU_H__
+
+#define JZ4760_CLK_EXT 0
+#define JZ4760_CLK_OSC32K 1
+#define JZ4760_CLK_PLL0 2
+#define JZ4760_CLK_PLL0_HALF 3
+#define JZ4760_CLK_PLL1 4
+#define JZ4760_CLK_CCLK 5
+#define JZ4760_CLK_HCLK 6
+#define JZ4760_CLK_SCLK 7
+#define JZ4760_CLK_H2CLK 8
+#define JZ4760_CLK_MCLK 9
+#define JZ4760_CLK_PCLK 10
+#define JZ4760_CLK_MMC_MUX 11
+#define JZ4760_CLK_MMC0 12
+#define JZ4760_CLK_MMC1 13
+#define JZ4760_CLK_MMC2 14
+#define JZ4760_CLK_CIM 15
+#define JZ4760_CLK_UHC 16
+#define JZ4760_CLK_GPU 17
+#define JZ4760_CLK_GPS 18
+#define JZ4760_CLK_SSI_MUX 19
+#define JZ4760_CLK_PCM 20
+#define JZ4760_CLK_I2S 21
+#define JZ4760_CLK_OTG 22
+#define JZ4760_CLK_SSI0 23
+#define JZ4760_CLK_SSI1 24
+#define JZ4760_CLK_SSI2 25
+#define JZ4760_CLK_DMA 26
+#define JZ4760_CLK_I2C0 27
+#define JZ4760_CLK_I2C1 28
+#define JZ4760_CLK_UART0 29
+#define JZ4760_CLK_UART1 30
+#define JZ4760_CLK_UART2 31
+#define JZ4760_CLK_UART3 32
+#define JZ4760_CLK_IPU 33
+#define JZ4760_CLK_ADC 34
+#define JZ4760_CLK_AIC 35
+#define JZ4760_CLK_VPU 36
+#define JZ4760_CLK_UHC_PHY 37
+#define JZ4760_CLK_OTG_PHY 38
+#define JZ4760_CLK_EXT512 39
+#define JZ4760_CLK_RTC 40
+#define JZ4760_CLK_LPCLK_DIV 41
+#define JZ4760_CLK_TVE 42
+#define JZ4760_CLK_LPCLK 43
+
+#endif /* __DT_BINDINGS_CLOCK_JZ4760_CGU_H__ */
diff --git a/include/dt-bindings/clock/mt8173-clk.h b/include/dt-bindings/clock/mt8173-clk.h
index 3acebe9..3d00c98 100644
--- a/include/dt-bindings/clock/mt8173-clk.h
+++ b/include/dt-bindings/clock/mt8173-clk.h
@@ -186,7 +186,6 @@
#define CLK_INFRA_PMICWRAP 11
#define CLK_INFRA_CLK_13M 12
#define CLK_INFRA_CA53SEL 13
-#define CLK_INFRA_CA57SEL 14 /* Deprecated. Don't use it. */
#define CLK_INFRA_CA72SEL 14
#define CLK_INFRA_NR_CLK 15
diff --git a/include/dt-bindings/clock/qcom,camcc-sm8250.h b/include/dt-bindings/clock/qcom,camcc-sm8250.h
new file mode 100644
index 0000000..383ead1
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,camcc-sm8250.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8250_H
+
+/* CAM_CC clocks */
+#define CAM_CC_BPS_AHB_CLK 0
+#define CAM_CC_BPS_AREG_CLK 1
+#define CAM_CC_BPS_AXI_CLK 2
+#define CAM_CC_BPS_CLK 3
+#define CAM_CC_BPS_CLK_SRC 4
+#define CAM_CC_CAMNOC_AXI_CLK 5
+#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
+#define CAM_CC_CAMNOC_DCD_XO_CLK 7
+#define CAM_CC_CCI_0_CLK 8
+#define CAM_CC_CCI_0_CLK_SRC 9
+#define CAM_CC_CCI_1_CLK 10
+#define CAM_CC_CCI_1_CLK_SRC 11
+#define CAM_CC_CORE_AHB_CLK 12
+#define CAM_CC_CPAS_AHB_CLK 13
+#define CAM_CC_CPHY_RX_CLK_SRC 14
+#define CAM_CC_CSI0PHYTIMER_CLK 15
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC 16
+#define CAM_CC_CSI1PHYTIMER_CLK 17
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC 18
+#define CAM_CC_CSI2PHYTIMER_CLK 19
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC 20
+#define CAM_CC_CSI3PHYTIMER_CLK 21
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC 22
+#define CAM_CC_CSI4PHYTIMER_CLK 23
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC 24
+#define CAM_CC_CSI5PHYTIMER_CLK 25
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC 26
+#define CAM_CC_CSIPHY0_CLK 27
+#define CAM_CC_CSIPHY1_CLK 28
+#define CAM_CC_CSIPHY2_CLK 29
+#define CAM_CC_CSIPHY3_CLK 30
+#define CAM_CC_CSIPHY4_CLK 31
+#define CAM_CC_CSIPHY5_CLK 32
+#define CAM_CC_FAST_AHB_CLK_SRC 33
+#define CAM_CC_FD_CORE_CLK 34
+#define CAM_CC_FD_CORE_CLK_SRC 35
+#define CAM_CC_FD_CORE_UAR_CLK 36
+#define CAM_CC_GDSC_CLK 37
+#define CAM_CC_ICP_AHB_CLK 38
+#define CAM_CC_ICP_CLK 39
+#define CAM_CC_ICP_CLK_SRC 40
+#define CAM_CC_IFE_0_AHB_CLK 41
+#define CAM_CC_IFE_0_AREG_CLK 42
+#define CAM_CC_IFE_0_AXI_CLK 43
+#define CAM_CC_IFE_0_CLK 44
+#define CAM_CC_IFE_0_CLK_SRC 45
+#define CAM_CC_IFE_0_CPHY_RX_CLK 46
+#define CAM_CC_IFE_0_CSID_CLK 47
+#define CAM_CC_IFE_0_CSID_CLK_SRC 48
+#define CAM_CC_IFE_0_DSP_CLK 49
+#define CAM_CC_IFE_1_AHB_CLK 50
+#define CAM_CC_IFE_1_AREG_CLK 51
+#define CAM_CC_IFE_1_AXI_CLK 52
+#define CAM_CC_IFE_1_CLK 53
+#define CAM_CC_IFE_1_CLK_SRC 54
+#define CAM_CC_IFE_1_CPHY_RX_CLK 55
+#define CAM_CC_IFE_1_CSID_CLK 56
+#define CAM_CC_IFE_1_CSID_CLK_SRC 57
+#define CAM_CC_IFE_1_DSP_CLK 58
+#define CAM_CC_IFE_LITE_AHB_CLK 59
+#define CAM_CC_IFE_LITE_AXI_CLK 60
+#define CAM_CC_IFE_LITE_CLK 61
+#define CAM_CC_IFE_LITE_CLK_SRC 62
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK 63
+#define CAM_CC_IFE_LITE_CSID_CLK 64
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC 65
+#define CAM_CC_IPE_0_AHB_CLK 66
+#define CAM_CC_IPE_0_AREG_CLK 67
+#define CAM_CC_IPE_0_AXI_CLK 68
+#define CAM_CC_IPE_0_CLK 69
+#define CAM_CC_IPE_0_CLK_SRC 70
+#define CAM_CC_JPEG_CLK 71
+#define CAM_CC_JPEG_CLK_SRC 72
+#define CAM_CC_MCLK0_CLK 73
+#define CAM_CC_MCLK0_CLK_SRC 74
+#define CAM_CC_MCLK1_CLK 75
+#define CAM_CC_MCLK1_CLK_SRC 76
+#define CAM_CC_MCLK2_CLK 77
+#define CAM_CC_MCLK2_CLK_SRC 78
+#define CAM_CC_MCLK3_CLK 79
+#define CAM_CC_MCLK3_CLK_SRC 80
+#define CAM_CC_MCLK4_CLK 81
+#define CAM_CC_MCLK4_CLK_SRC 82
+#define CAM_CC_MCLK5_CLK 83
+#define CAM_CC_MCLK5_CLK_SRC 84
+#define CAM_CC_MCLK6_CLK 85
+#define CAM_CC_MCLK6_CLK_SRC 86
+#define CAM_CC_PLL0 87
+#define CAM_CC_PLL0_OUT_EVEN 88
+#define CAM_CC_PLL0_OUT_ODD 89
+#define CAM_CC_PLL1 90
+#define CAM_CC_PLL1_OUT_EVEN 91
+#define CAM_CC_PLL2 92
+#define CAM_CC_PLL2_OUT_MAIN 93
+#define CAM_CC_PLL3 94
+#define CAM_CC_PLL3_OUT_EVEN 95
+#define CAM_CC_PLL4 96
+#define CAM_CC_PLL4_OUT_EVEN 97
+#define CAM_CC_SBI_AHB_CLK 98
+#define CAM_CC_SBI_AXI_CLK 99
+#define CAM_CC_SBI_CLK 100
+#define CAM_CC_SBI_CPHY_RX_CLK 101
+#define CAM_CC_SBI_CSID_CLK 102
+#define CAM_CC_SBI_CSID_CLK_SRC 103
+#define CAM_CC_SBI_DIV_CLK_SRC 104
+#define CAM_CC_SBI_IFE_0_CLK 105
+#define CAM_CC_SBI_IFE_1_CLK 106
+#define CAM_CC_SLEEP_CLK 107
+#define CAM_CC_SLEEP_CLK_SRC 108
+#define CAM_CC_SLOW_AHB_CLK_SRC 109
+#define CAM_CC_XO_CLK_SRC 110
+
+/* CAM_CC resets */
+#define CAM_CC_BPS_BCR 0
+#define CAM_CC_ICP_BCR 1
+#define CAM_CC_IFE_0_BCR 2
+#define CAM_CC_IFE_1_BCR 3
+#define CAM_CC_IPE_0_BCR 4
+#define CAM_CC_SBI_BCR 5
+
+/* CAM_CC GDSCRs */
+#define BPS_GDSC 0
+#define IPE_0_GDSC 1
+#define SBI_GDSC 2
+#define IFE_0_GDSC 3
+#define IFE_1_GDSC 4
+#define TITAN_TOP_GDSC 5
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
index fdaca6a..ce001cb 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
@@ -55,6 +55,15 @@
#define DISP_CC_MDSS_VSYNC_CLK_SRC 45
#define DISP_CC_PLL0 46
#define DISP_CC_PLL1 47
+#define DISP_CC_MDSS_EDP_AUX_CLK 48
+#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 49
+#define DISP_CC_MDSS_EDP_GTC_CLK 50
+#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 51
+#define DISP_CC_MDSS_EDP_LINK_CLK 52
+#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 53
+#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54
+#define DISP_CC_MDSS_EDP_PIXEL_CLK 55
+#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56
/* DISP_CC Reset */
#define DISP_CC_MDSS_CORE_BCR 0
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
index fdaca6a..ce001cb 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sm8250.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -55,6 +55,15 @@
#define DISP_CC_MDSS_VSYNC_CLK_SRC 45
#define DISP_CC_PLL0 46
#define DISP_CC_PLL1 47
+#define DISP_CC_MDSS_EDP_AUX_CLK 48
+#define DISP_CC_MDSS_EDP_AUX_CLK_SRC 49
+#define DISP_CC_MDSS_EDP_GTC_CLK 50
+#define DISP_CC_MDSS_EDP_GTC_CLK_SRC 51
+#define DISP_CC_MDSS_EDP_LINK_CLK 52
+#define DISP_CC_MDSS_EDP_LINK_CLK_SRC 53
+#define DISP_CC_MDSS_EDP_LINK_INTF_CLK 54
+#define DISP_CC_MDSS_EDP_PIXEL_CLK 55
+#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC 56
/* DISP_CC Reset */
#define DISP_CC_MDSS_CORE_BCR 0
diff --git a/include/dt-bindings/clock/qcom,gcc-mdm9607.h b/include/dt-bindings/clock/qcom,gcc-mdm9607.h
new file mode 100644
index 0000000..357a680
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-mdm9607.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H
+#define _DT_BINDINGS_CLK_MSM_GCC_9607_H
+
+#define GPLL0 0
+#define GPLL0_EARLY 1
+#define GPLL1 2
+#define GPLL1_VOTE 3
+#define GPLL2 4
+#define GPLL2_EARLY 5
+#define PCNOC_BFDCD_CLK_SRC 6
+#define SYSTEM_NOC_BFDCD_CLK_SRC 7
+#define GCC_SMMU_CFG_CLK 8
+#define APSS_AHB_CLK_SRC 9
+#define GCC_QDSS_DAP_CLK 10
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22
+#define BLSP1_UART1_APPS_CLK_SRC 23
+#define BLSP1_UART2_APPS_CLK_SRC 24
+#define CRYPTO_CLK_SRC 25
+#define GP1_CLK_SRC 26
+#define GP2_CLK_SRC 27
+#define GP3_CLK_SRC 28
+#define PDM2_CLK_SRC 29
+#define SDCC1_APPS_CLK_SRC 30
+#define SDCC2_APPS_CLK_SRC 31
+#define APSS_TCU_CLK_SRC 32
+#define USB_HS_SYSTEM_CLK_SRC 33
+#define GCC_BLSP1_AHB_CLK 34
+#define GCC_BLSP1_SLEEP_CLK 35
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 36
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 37
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 38
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 39
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 40
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 41
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK 42
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK 43
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK 44
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK 45
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK 46
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK 47
+#define GCC_BLSP1_UART1_APPS_CLK 48
+#define GCC_BLSP1_UART2_APPS_CLK 49
+#define GCC_BOOT_ROM_AHB_CLK 50
+#define GCC_CRYPTO_AHB_CLK 51
+#define GCC_CRYPTO_AXI_CLK 52
+#define GCC_CRYPTO_CLK 53
+#define GCC_GP1_CLK 54
+#define GCC_GP2_CLK 55
+#define GCC_GP3_CLK 56
+#define GCC_MSS_CFG_AHB_CLK 57
+#define GCC_PDM2_CLK 58
+#define GCC_PDM_AHB_CLK 59
+#define GCC_PRNG_AHB_CLK 60
+#define GCC_SDCC1_AHB_CLK 61
+#define GCC_SDCC1_APPS_CLK 62
+#define GCC_SDCC2_AHB_CLK 63
+#define GCC_SDCC2_APPS_CLK 64
+#define GCC_USB2A_PHY_SLEEP_CLK 65
+#define GCC_USB_HS_AHB_CLK 66
+#define GCC_USB_HS_SYSTEM_CLK 67
+#define GCC_APSS_TCU_CLK 68
+#define GCC_MSS_Q6_BIMC_AXI_CLK 69
+#define BIMC_PLL 70
+#define BIMC_PLL_VOTE 71
+#define BIMC_DDR_CLK_SRC 72
+#define BLSP1_UART3_APPS_CLK_SRC 73
+#define BLSP1_UART4_APPS_CLK_SRC 74
+#define BLSP1_UART5_APPS_CLK_SRC 75
+#define BLSP1_UART6_APPS_CLK_SRC 76
+#define GCC_BLSP1_UART3_APPS_CLK 77
+#define GCC_BLSP1_UART4_APPS_CLK 78
+#define GCC_BLSP1_UART5_APPS_CLK 79
+#define GCC_BLSP1_UART6_APPS_CLK 80
+#define GCC_APSS_AHB_CLK 81
+#define GCC_APSS_AXI_CLK 82
+#define GCC_USB_HS_PHY_CFG_AHB_CLK 83
+#define GCC_USB_HSIC_CLK_SRC 84
+#define GCC_USB_HSIC_IO_CAL_CLK_SRC 85
+#define GCC_USB_HSIC_SYSTEM_CLK_SRC 86
+
+/* Resets */
+#define USB2_HS_PHY_ONLY_BCR 0
+#define QUSB2_PHY_BCR 1
+#define GCC_MSS_RESTART 2
+#define USB_HS_HSIC_BCR 3
+#define USB_HS_BCR 4
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sm6125.h b/include/dt-bindings/clock/qcom,gcc-sm6125.h
new file mode 100644
index 0000000..08ea180
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm6125.h
@@ -0,0 +1,240 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM6125_H
+
+#define GPLL0_OUT_AUX2 0
+#define GPLL0_OUT_MAIN 1
+#define GPLL6_OUT_MAIN 2
+#define GPLL7_OUT_MAIN 3
+#define GPLL8_OUT_MAIN 4
+#define GPLL9_OUT_MAIN 5
+#define GPLL0_OUT_EARLY 6
+#define GPLL3_OUT_EARLY 7
+#define GPLL4_OUT_MAIN 8
+#define GPLL5_OUT_MAIN 9
+#define GPLL6_OUT_EARLY 10
+#define GPLL7_OUT_EARLY 11
+#define GPLL8_OUT_EARLY 12
+#define GPLL9_OUT_EARLY 13
+#define GCC_AHB2PHY_CSI_CLK 14
+#define GCC_AHB2PHY_USB_CLK 15
+#define GCC_APC_VS_CLK 16
+#define GCC_BOOT_ROM_AHB_CLK 17
+#define GCC_CAMERA_AHB_CLK 18
+#define GCC_CAMERA_XO_CLK 19
+#define GCC_CAMSS_AHB_CLK_SRC 20
+#define GCC_CAMSS_CCI_AHB_CLK 21
+#define GCC_CAMSS_CCI_CLK 22
+#define GCC_CAMSS_CCI_CLK_SRC 23
+#define GCC_CAMSS_CPHY_CSID0_CLK 24
+#define GCC_CAMSS_CPHY_CSID1_CLK 25
+#define GCC_CAMSS_CPHY_CSID2_CLK 26
+#define GCC_CAMSS_CPHY_CSID3_CLK 27
+#define GCC_CAMSS_CPP_AHB_CLK 28
+#define GCC_CAMSS_CPP_AXI_CLK 29
+#define GCC_CAMSS_CPP_CLK 30
+#define GCC_CAMSS_CPP_CLK_SRC 31
+#define GCC_CAMSS_CPP_VBIF_AHB_CLK 32
+#define GCC_CAMSS_CSI0_AHB_CLK 33
+#define GCC_CAMSS_CSI0_CLK 34
+#define GCC_CAMSS_CSI0_CLK_SRC 35
+#define GCC_CAMSS_CSI0PHYTIMER_CLK 36
+#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 37
+#define GCC_CAMSS_CSI0PIX_CLK 38
+#define GCC_CAMSS_CSI0RDI_CLK 39
+#define GCC_CAMSS_CSI1_AHB_CLK 40
+#define GCC_CAMSS_CSI1_CLK 41
+#define GCC_CAMSS_CSI1_CLK_SRC 42
+#define GCC_CAMSS_CSI1PHYTIMER_CLK 43
+#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 44
+#define GCC_CAMSS_CSI1PIX_CLK 45
+#define GCC_CAMSS_CSI1RDI_CLK 46
+#define GCC_CAMSS_CSI2_AHB_CLK 47
+#define GCC_CAMSS_CSI2_CLK 48
+#define GCC_CAMSS_CSI2_CLK_SRC 49
+#define GCC_CAMSS_CSI2PHYTIMER_CLK 50
+#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 51
+#define GCC_CAMSS_CSI2PIX_CLK 52
+#define GCC_CAMSS_CSI2RDI_CLK 53
+#define GCC_CAMSS_CSI3_AHB_CLK 54
+#define GCC_CAMSS_CSI3_CLK 55
+#define GCC_CAMSS_CSI3_CLK_SRC 56
+#define GCC_CAMSS_CSI3PIX_CLK 57
+#define GCC_CAMSS_CSI3RDI_CLK 58
+#define GCC_CAMSS_CSI_VFE0_CLK 59
+#define GCC_CAMSS_CSI_VFE1_CLK 60
+#define GCC_CAMSS_CSIPHY0_CLK 61
+#define GCC_CAMSS_CSIPHY1_CLK 62
+#define GCC_CAMSS_CSIPHY2_CLK 63
+#define GCC_CAMSS_CSIPHY_CLK_SRC 64
+#define GCC_CAMSS_GP0_CLK 65
+#define GCC_CAMSS_GP0_CLK_SRC 66
+#define GCC_CAMSS_GP1_CLK 67
+#define GCC_CAMSS_GP1_CLK_SRC 68
+#define GCC_CAMSS_ISPIF_AHB_CLK 69
+#define GCC_CAMSS_JPEG_AHB_CLK 70
+#define GCC_CAMSS_JPEG_AXI_CLK 71
+#define GCC_CAMSS_JPEG_CLK 72
+#define GCC_CAMSS_JPEG_CLK_SRC 73
+#define GCC_CAMSS_MCLK0_CLK 74
+#define GCC_CAMSS_MCLK0_CLK_SRC 75
+#define GCC_CAMSS_MCLK1_CLK 76
+#define GCC_CAMSS_MCLK1_CLK_SRC 77
+#define GCC_CAMSS_MCLK2_CLK 78
+#define GCC_CAMSS_MCLK2_CLK_SRC 79
+#define GCC_CAMSS_MCLK3_CLK 80
+#define GCC_CAMSS_MCLK3_CLK_SRC 81
+#define GCC_CAMSS_MICRO_AHB_CLK 82
+#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 83
+#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 84
+#define GCC_CAMSS_TOP_AHB_CLK 85
+#define GCC_CAMSS_VFE0_AHB_CLK 86
+#define GCC_CAMSS_VFE0_CLK 87
+#define GCC_CAMSS_VFE0_CLK_SRC 88
+#define GCC_CAMSS_VFE0_STREAM_CLK 89
+#define GCC_CAMSS_VFE1_AHB_CLK 90
+#define GCC_CAMSS_VFE1_CLK 91
+#define GCC_CAMSS_VFE1_CLK_SRC 92
+#define GCC_CAMSS_VFE1_STREAM_CLK 93
+#define GCC_CAMSS_VFE_TSCTR_CLK 94
+#define GCC_CAMSS_VFE_VBIF_AHB_CLK 95
+#define GCC_CAMSS_VFE_VBIF_AXI_CLK 96
+#define GCC_CE1_AHB_CLK 97
+#define GCC_CE1_AXI_CLK 98
+#define GCC_CE1_CLK 99
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 100
+#define GCC_CPUSS_GNOC_CLK 101
+#define GCC_DISP_AHB_CLK 102
+#define GCC_DISP_GPLL0_DIV_CLK_SRC 103
+#define GCC_DISP_HF_AXI_CLK 104
+#define GCC_DISP_THROTTLE_CORE_CLK 105
+#define GCC_DISP_XO_CLK 106
+#define GCC_GP1_CLK 107
+#define GCC_GP1_CLK_SRC 108
+#define GCC_GP2_CLK 109
+#define GCC_GP2_CLK_SRC 110
+#define GCC_GP3_CLK 111
+#define GCC_GP3_CLK_SRC 112
+#define GCC_GPU_CFG_AHB_CLK 113
+#define GCC_GPU_GPLL0_CLK_SRC 114
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 115
+#define GCC_GPU_MEMNOC_GFX_CLK 116
+#define GCC_GPU_SNOC_DVM_GFX_CLK 117
+#define GCC_GPU_THROTTLE_CORE_CLK 118
+#define GCC_GPU_THROTTLE_XO_CLK 119
+#define GCC_MSS_VS_CLK 120
+#define GCC_PDM2_CLK 121
+#define GCC_PDM2_CLK_SRC 122
+#define GCC_PDM_AHB_CLK 123
+#define GCC_PDM_XO4_CLK 124
+#define GCC_PRNG_AHB_CLK 125
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 126
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 127
+#define GCC_QMIP_DISP_AHB_CLK 128
+#define GCC_QMIP_GPU_CFG_AHB_CLK 129
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 130
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 131
+#define GCC_QUPV3_WRAP0_CORE_CLK 132
+#define GCC_QUPV3_WRAP0_S0_CLK 133
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 134
+#define GCC_QUPV3_WRAP0_S1_CLK 135
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 136
+#define GCC_QUPV3_WRAP0_S2_CLK 137
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 138
+#define GCC_QUPV3_WRAP0_S3_CLK 139
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 140
+#define GCC_QUPV3_WRAP0_S4_CLK 141
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 142
+#define GCC_QUPV3_WRAP0_S5_CLK 143
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 144
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 145
+#define GCC_QUPV3_WRAP1_CORE_CLK 146
+#define GCC_QUPV3_WRAP1_S0_CLK 147
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 148
+#define GCC_QUPV3_WRAP1_S1_CLK 149
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 150
+#define GCC_QUPV3_WRAP1_S2_CLK 151
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 152
+#define GCC_QUPV3_WRAP1_S3_CLK 153
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 154
+#define GCC_QUPV3_WRAP1_S4_CLK 155
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 156
+#define GCC_QUPV3_WRAP1_S5_CLK 157
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 158
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 159
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 160
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 161
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 162
+#define GCC_SDCC1_AHB_CLK 163
+#define GCC_SDCC1_APPS_CLK 164
+#define GCC_SDCC1_APPS_CLK_SRC 165
+#define GCC_SDCC1_ICE_CORE_CLK 166
+#define GCC_SDCC1_ICE_CORE_CLK_SRC 167
+#define GCC_SDCC2_AHB_CLK 168
+#define GCC_SDCC2_APPS_CLK 169
+#define GCC_SDCC2_APPS_CLK_SRC 170
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 171
+#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 172
+#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 173
+#define GCC_UFS_PHY_AHB_CLK 174
+#define GCC_UFS_PHY_AXI_CLK 175
+#define GCC_UFS_PHY_AXI_CLK_SRC 176
+#define GCC_UFS_PHY_ICE_CORE_CLK 177
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 178
+#define GCC_UFS_PHY_PHY_AUX_CLK 179
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 180
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 181
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 182
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 183
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 184
+#define GCC_USB30_PRIM_MASTER_CLK 185
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 186
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 187
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 188
+#define GCC_USB30_PRIM_SLEEP_CLK 189
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 190
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 191
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 192
+#define GCC_VDDA_VS_CLK 193
+#define GCC_VDDCX_VS_CLK 194
+#define GCC_VDDMX_VS_CLK 195
+#define GCC_VIDEO_AHB_CLK 196
+#define GCC_VIDEO_AXI0_CLK 197
+#define GCC_VIDEO_THROTTLE_CORE_CLK 198
+#define GCC_VIDEO_XO_CLK 199
+#define GCC_VS_CTRL_AHB_CLK 200
+#define GCC_VS_CTRL_CLK 201
+#define GCC_VS_CTRL_CLK_SRC 202
+#define GCC_VSENSOR_CLK_SRC 203
+#define GCC_WCSS_VS_CLK 204
+#define GCC_USB3_PRIM_CLKREF_CLK 205
+#define GCC_SYS_NOC_COMPUTE_SF_AXI_CLK 206
+#define GCC_BIMC_GPU_AXI_CLK 207
+#define GCC_UFS_MEM_CLKREF_CLK 208
+
+/* GDSCs */
+#define USB30_PRIM_GDSC 0
+#define UFS_PHY_GDSC 1
+#define CAMSS_VFE0_GDSC 2
+#define CAMSS_VFE1_GDSC 3
+#define CAMSS_TOP_GDSC 4
+#define CAM_CPP_GDSC 5
+#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 6
+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 7
+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 8
+#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 9
+
+#define GCC_QUSB2PHY_PRIM_BCR 0
+#define GCC_QUSB2PHY_SEC_BCR 1
+#define GCC_UFS_PHY_BCR 2
+#define GCC_USB30_PRIM_BCR 3
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 4
+#define GCC_USB3_PHY_PRIM_SP0_BCR 5
+#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 6
+#define GCC_CAMSS_MICRO_BCR 7
+
+#endif
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
new file mode 100644
index 0000000..1d89865
--- /dev/null
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A07G044 CPG Core Clocks */
+#define R9A07G044_CLK_I 0
+#define R9A07G044_CLK_I2 1
+#define R9A07G044_CLK_G 2
+#define R9A07G044_CLK_S0 3
+#define R9A07G044_CLK_S1 4
+#define R9A07G044_CLK_SPI0 5
+#define R9A07G044_CLK_SPI1 6
+#define R9A07G044_CLK_SD0 7
+#define R9A07G044_CLK_SD1 8
+#define R9A07G044_CLK_M0 9
+#define R9A07G044_CLK_M1 10
+#define R9A07G044_CLK_M2 11
+#define R9A07G044_CLK_M3 12
+#define R9A07G044_CLK_M4 13
+#define R9A07G044_CLK_HP 14
+#define R9A07G044_CLK_TSU 15
+#define R9A07G044_CLK_ZT 16
+#define R9A07G044_CLK_P0 17
+#define R9A07G044_CLK_P1 18
+#define R9A07G044_CLK_P2 19
+#define R9A07G044_CLK_AT 20
+#define R9A07G044_OSCCLK 21
+
+/* R9A07G044 Module Clocks */
+#define R9A07G044_CLK_GIC600 0
+#define R9A07G044_CLK_IA55 1
+#define R9A07G044_CLK_SYC 2
+#define R9A07G044_CLK_DMAC 3
+#define R9A07G044_CLK_SYSC 4
+#define R9A07G044_CLK_MTU 5
+#define R9A07G044_CLK_GPT 6
+#define R9A07G044_CLK_ETH0 7
+#define R9A07G044_CLK_ETH1 8
+#define R9A07G044_CLK_I2C0 9
+#define R9A07G044_CLK_I2C1 10
+#define R9A07G044_CLK_I2C2 11
+#define R9A07G044_CLK_I2C3 12
+#define R9A07G044_CLK_SCIF0 13
+#define R9A07G044_CLK_SCIF1 14
+#define R9A07G044_CLK_SCIF2 15
+#define R9A07G044_CLK_SCIF3 16
+#define R9A07G044_CLK_SCIF4 17
+#define R9A07G044_CLK_SCI0 18
+#define R9A07G044_CLK_SCI1 19
+#define R9A07G044_CLK_GPIO 20
+#define R9A07G044_CLK_SDHI0 21
+#define R9A07G044_CLK_SDHI1 22
+#define R9A07G044_CLK_USB0 23
+#define R9A07G044_CLK_USB1 24
+#define R9A07G044_CLK_CANFD 25
+#define R9A07G044_CLK_SSI0 26
+#define R9A07G044_CLK_SSI1 27
+#define R9A07G044_CLK_SSI2 28
+#define R9A07G044_CLK_SSI3 29
+#define R9A07G044_CLK_MHU 30
+#define R9A07G044_CLK_OSTM0 31
+#define R9A07G044_CLK_OSTM1 32
+#define R9A07G044_CLK_OSTM2 33
+#define R9A07G044_CLK_WDT0 34
+#define R9A07G044_CLK_WDT1 35
+#define R9A07G044_CLK_WDT2 36
+#define R9A07G044_CLK_WDT_PON 37
+#define R9A07G044_CLK_GPU 38
+#define R9A07G044_CLK_ISU 39
+#define R9A07G044_CLK_H264 40
+#define R9A07G044_CLK_CRU 41
+#define R9A07G044_CLK_MIPI_DSI 42
+#define R9A07G044_CLK_LCDC 43
+#define R9A07G044_CLK_SRC 44
+#define R9A07G044_CLK_RSPI0 45
+#define R9A07G044_CLK_RSPI1 46
+#define R9A07G044_CLK_RSPI2 47
+#define R9A07G044_CLK_ADC 48
+#define R9A07G044_CLK_TSU_PCLK 49
+#define R9A07G044_CLK_SPI 50
+#define R9A07G044_CLK_MIPI_DSI_V 51
+#define R9A07G044_CLK_MIPI_DSI_PIN 52
+
+#endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */
diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h
index 4cdaf13..e02770b 100644
--- a/include/dt-bindings/clock/stm32mp1-clks.h
+++ b/include/dt-bindings/clock/stm32mp1-clks.h
@@ -248,4 +248,31 @@
#define STM32MP1_LAST_CLK 232
+/* SCMI clock identifiers */
+#define CK_SCMI0_HSE 0
+#define CK_SCMI0_HSI 1
+#define CK_SCMI0_CSI 2
+#define CK_SCMI0_LSE 3
+#define CK_SCMI0_LSI 4
+#define CK_SCMI0_PLL2_Q 5
+#define CK_SCMI0_PLL2_R 6
+#define CK_SCMI0_MPU 7
+#define CK_SCMI0_AXI 8
+#define CK_SCMI0_BSEC 9
+#define CK_SCMI0_CRYP1 10
+#define CK_SCMI0_GPIOZ 11
+#define CK_SCMI0_HASH1 12
+#define CK_SCMI0_I2C4 13
+#define CK_SCMI0_I2C6 14
+#define CK_SCMI0_IWDG1 15
+#define CK_SCMI0_RNG1 16
+#define CK_SCMI0_RTC 17
+#define CK_SCMI0_RTCAPB 18
+#define CK_SCMI0_SPI6 19
+#define CK_SCMI0_USART1 20
+
+#define CK_SCMI1_PLL3_Q 0
+#define CK_SCMI1_PLL3_R 1
+#define CK_SCMI1_MCU 2
+
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
diff --git a/include/dt-bindings/interconnect/qcom,sc7280.h b/include/dt-bindings/interconnect/qcom,sc7280.h
new file mode 100644
index 0000000..21b0004
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,sc7280.h
@@ -0,0 +1,165 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Qualcomm SC7280 interconnect IDs
+ *
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SC7280_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_SC7280_H
+
+#define MASTER_QSPI_0 0
+#define MASTER_QUP_0 1
+#define MASTER_QUP_1 2
+#define MASTER_A1NOC_CFG 3
+#define MASTER_PCIE_0 4
+#define MASTER_PCIE_1 5
+#define MASTER_SDCC_1 6
+#define MASTER_SDCC_2 7
+#define MASTER_SDCC_4 8
+#define MASTER_UFS_MEM 9
+#define MASTER_USB2 10
+#define MASTER_USB3_0 11
+#define SLAVE_A1NOC_SNOC 12
+#define SLAVE_ANOC_PCIE_GEM_NOC 13
+#define SLAVE_SERVICE_A1NOC 14
+
+#define MASTER_QDSS_BAM 0
+#define MASTER_A2NOC_CFG 1
+#define MASTER_CNOC_A2NOC 2
+#define MASTER_CRYPTO 3
+#define MASTER_IPA 4
+#define MASTER_QDSS_ETR 5
+#define SLAVE_A2NOC_SNOC 6
+#define SLAVE_SERVICE_A2NOC 7
+
+#define MASTER_QUP_CORE_0 0
+#define MASTER_QUP_CORE_1 1
+#define SLAVE_QUP_CORE_0 2
+#define SLAVE_QUP_CORE_1 3
+
+#define MASTER_CNOC3_CNOC2 0
+#define MASTER_QDSS_DAP 1
+#define SLAVE_AHB2PHY_SOUTH 2
+#define SLAVE_AHB2PHY_NORTH 3
+#define SLAVE_CAMERA_CFG 4
+#define SLAVE_CLK_CTL 5
+#define SLAVE_CDSP_CFG 6
+#define SLAVE_RBCPR_CX_CFG 7
+#define SLAVE_RBCPR_MX_CFG 8
+#define SLAVE_CRYPTO_0_CFG 9
+#define SLAVE_CX_RDPM 10
+#define SLAVE_DCC_CFG 11
+#define SLAVE_DISPLAY_CFG 12
+#define SLAVE_GFX3D_CFG 13
+#define SLAVE_HWKM 14
+#define SLAVE_IMEM_CFG 15
+#define SLAVE_IPA_CFG 16
+#define SLAVE_IPC_ROUTER_CFG 17
+#define SLAVE_LPASS 18
+#define SLAVE_CNOC_MSS 19
+#define SLAVE_MX_RDPM 20
+#define SLAVE_PCIE_0_CFG 21
+#define SLAVE_PCIE_1_CFG 22
+#define SLAVE_PDM 23
+#define SLAVE_PIMEM_CFG 24
+#define SLAVE_PKA_WRAPPER_CFG 25
+#define SLAVE_PMU_WRAPPER_CFG 26
+#define SLAVE_QDSS_CFG 27
+#define SLAVE_QSPI_0 28
+#define SLAVE_QUP_0 29
+#define SLAVE_QUP_1 30
+#define SLAVE_SDCC_1 31
+#define SLAVE_SDCC_2 32
+#define SLAVE_SDCC_4 33
+#define SLAVE_SECURITY 34
+#define SLAVE_TCSR 35
+#define SLAVE_TLMM 36
+#define SLAVE_UFS_MEM_CFG 37
+#define SLAVE_USB2 38
+#define SLAVE_USB3_0 39
+#define SLAVE_VENUS_CFG 40
+#define SLAVE_VSENSE_CTRL_CFG 41
+#define SLAVE_A1NOC_CFG 42
+#define SLAVE_A2NOC_CFG 43
+#define SLAVE_CNOC2_CNOC3 44
+#define SLAVE_CNOC_MNOC_CFG 45
+#define SLAVE_SNOC_CFG 46
+
+#define MASTER_CNOC2_CNOC3 0
+#define MASTER_GEM_NOC_CNOC 1
+#define MASTER_GEM_NOC_PCIE_SNOC 2
+#define SLAVE_AOSS 3
+#define SLAVE_APPSS 4
+#define SLAVE_CNOC3_CNOC2 5
+#define SLAVE_CNOC_A2NOC 6
+#define SLAVE_DDRSS_CFG 7
+#define SLAVE_BOOT_IMEM 8
+#define SLAVE_IMEM 9
+#define SLAVE_PIMEM 10
+#define SLAVE_PCIE_0 11
+#define SLAVE_PCIE_1 12
+#define SLAVE_QDSS_STM 13
+#define SLAVE_TCU 14
+
+#define MASTER_CNOC_DC_NOC 0
+#define SLAVE_LLCC_CFG 1
+#define SLAVE_GEM_NOC_CFG 2
+
+#define MASTER_GPU_TCU 0
+#define MASTER_SYS_TCU 1
+#define MASTER_APPSS_PROC 2
+#define MASTER_COMPUTE_NOC 3
+#define MASTER_GEM_NOC_CFG 4
+#define MASTER_GFX3D 5
+#define MASTER_MNOC_HF_MEM_NOC 6
+#define MASTER_MNOC_SF_MEM_NOC 7
+#define MASTER_ANOC_PCIE_GEM_NOC 8
+#define MASTER_SNOC_GC_MEM_NOC 9
+#define MASTER_SNOC_SF_MEM_NOC 10
+#define SLAVE_MSS_PROC_MS_MPU_CFG 11
+#define SLAVE_MCDMA_MS_MPU_CFG 12
+#define SLAVE_GEM_NOC_CNOC 13
+#define SLAVE_LLCC 14
+#define SLAVE_MEM_NOC_PCIE_SNOC 15
+#define SLAVE_SERVICE_GEM_NOC_1 16
+#define SLAVE_SERVICE_GEM_NOC_2 17
+#define SLAVE_SERVICE_GEM_NOC 18
+
+#define MASTER_CNOC_LPASS_AG_NOC 0
+#define SLAVE_LPASS_CORE_CFG 1
+#define SLAVE_LPASS_LPI_CFG 2
+#define SLAVE_LPASS_MPU_CFG 3
+#define SLAVE_LPASS_TOP_CFG 4
+#define SLAVE_SERVICES_LPASS_AML_NOC 5
+#define SLAVE_SERVICE_LPASS_AG_NOC 6
+
+#define MASTER_LLCC 0
+#define SLAVE_EBI1 1
+
+#define MASTER_CNOC_MNOC_CFG 0
+#define MASTER_VIDEO_P0 1
+#define MASTER_VIDEO_PROC 2
+#define MASTER_CAMNOC_HF 3
+#define MASTER_CAMNOC_ICP 4
+#define MASTER_CAMNOC_SF 5
+#define MASTER_MDP0 6
+#define SLAVE_MNOC_HF_MEM_NOC 7
+#define SLAVE_MNOC_SF_MEM_NOC 8
+#define SLAVE_SERVICE_MNOC 9
+
+#define MASTER_CDSP_NOC_CFG 0
+#define MASTER_CDSP_PROC 1
+#define SLAVE_CDSP_MEM_NOC 2
+#define SLAVE_SERVICE_NSP_NOC 3
+
+#define MASTER_A1NOC_SNOC 0
+#define MASTER_A2NOC_SNOC 1
+#define MASTER_SNOC_CFG 2
+#define MASTER_PIMEM 3
+#define MASTER_GIC 4
+#define SLAVE_SNOC_GEM_NOC_GC 5
+#define SLAVE_SNOC_GEM_NOC_SF 6
+#define SLAVE_SERVICE_SNOC 7
+
+#endif
diff --git a/include/dt-bindings/leds/rt4831-backlight.h b/include/dt-bindings/leds/rt4831-backlight.h
new file mode 100644
index 0000000..125c635
--- /dev/null
+++ b/include/dt-bindings/leds/rt4831-backlight.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for rt4831 backlight bindings.
+ *
+ * Copyright (C) 2020, Richtek Technology Corp.
+ * Author: ChiYuan Huang <cy_huang@richtek.com>
+ */
+
+#ifndef _DT_BINDINGS_RT4831_BACKLIGHT_H
+#define _DT_BINDINGS_RT4831_BACKLIGHT_H
+
+#define RT4831_BLOVPLVL_17V 0
+#define RT4831_BLOVPLVL_21V 1
+#define RT4831_BLOVPLVL_25V 2
+#define RT4831_BLOVPLVL_29V 3
+
+#define RT4831_BLED_CH1EN (1 << 0)
+#define RT4831_BLED_CH2EN (1 << 1)
+#define RT4831_BLED_CH3EN (1 << 2)
+#define RT4831_BLED_CH4EN (1 << 3)
+#define RT4831_BLED_ALLCHEN ((1 << 4) - 1)
+
+#endif /* _DT_BINDINGS_RT4831_BACKLIGHT_H */
diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h
index 4c23eef..eb91a6c 100644
--- a/include/dt-bindings/mailbox/qcom-ipcc.h
+++ b/include/dt-bindings/mailbox/qcom-ipcc.h
@@ -29,5 +29,6 @@
#define IPCC_CLIENT_PCIE1 14
#define IPCC_CLIENT_PCIE2 15
#define IPCC_CLIENT_SPSS 16
+#define IPCC_CLIENT_WPSS 24
#endif
diff --git a/include/dt-bindings/mfd/qcom-pm8008.h b/include/dt-bindings/mfd/qcom-pm8008.h
new file mode 100644
index 0000000..eca9448
--- /dev/null
+++ b/include/dt-bindings/mfd/qcom-pm8008.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2021 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_MFD_QCOM_PM8008_H
+#define __DT_BINDINGS_MFD_QCOM_PM8008_H
+
+/* PM8008 IRQ numbers */
+#define PM8008_IRQ_MISC_UVLO 0
+#define PM8008_IRQ_MISC_OVLO 1
+#define PM8008_IRQ_MISC_OTST2 2
+#define PM8008_IRQ_MISC_OTST3 3
+#define PM8008_IRQ_MISC_LDO_OCP 4
+#define PM8008_IRQ_TEMP_ALARM 5
+#define PM8008_IRQ_GPIO1 6
+#define PM8008_IRQ_GPIO2 7
+
+#endif
diff --git a/include/dt-bindings/pinctrl/apple.h b/include/dt-bindings/pinctrl/apple.h
new file mode 100644
index 0000000..ea0a6f4
--- /dev/null
+++ b/include/dt-bindings/pinctrl/apple.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
+/*
+ * This header provides constants for Apple pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_APPLE_H
+#define _DT_BINDINGS_PINCTRL_APPLE_H
+
+#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16))
+#define APPLE_PIN(pinmux) ((pinmux) & 0xffff)
+#define APPLE_FUNC(pinmux) ((pinmux) >> 16)
+
+#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */
diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
index 0359bfd..93064c7 100644
--- a/include/dt-bindings/pinctrl/hisi.h
+++ b/include/dt-bindings/pinctrl/hisi.h
@@ -1,7 +1,7 @@
/*
* This header provides constants for hisilicon pinctrl bindings.
*
- * Copyright (c) 2015 Hisilicon Limited.
+ * Copyright (c) 2015 HiSilicon Limited.
* Copyright (c) 2015 Linaro Limited.
*
* This program is free software; you can redistribute it and/or modify
diff --git a/include/dt-bindings/pinctrl/mt8365-pinfunc.h b/include/dt-bindings/pinctrl/mt8365-pinfunc.h
new file mode 100644
index 0000000..e2ec8af
--- /dev/null
+++ b/include/dt-bindings/pinctrl/mt8365-pinfunc.h
@@ -0,0 +1,858 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ */
+#ifndef __MT8365_PINFUNC_H
+#define __MT8365_PINFUNC_H
+
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
+#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1)
+#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2)
+#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3)
+#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4)
+#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5)
+#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7)
+
+#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
+#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1)
+#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2)
+#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3)
+#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4)
+#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5)
+#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7)
+
+#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
+#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1)
+#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2)
+#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3)
+#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4)
+#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5)
+#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7)
+
+#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
+#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1)
+#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2)
+#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3)
+#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4)
+#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5)
+#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6)
+#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7)
+
+#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
+#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1)
+#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2)
+#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3)
+#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4)
+#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5)
+#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6)
+#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7)
+
+#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
+#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1)
+#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2)
+#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3)
+#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4)
+#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5)
+#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6)
+#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7)
+
+#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
+#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1)
+#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2)
+#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3)
+#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4)
+#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5)
+#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6)
+#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7)
+
+#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
+#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1)
+#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3)
+#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4)
+#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5)
+#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7)
+
+#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
+#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1)
+#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2)
+#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3)
+#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4)
+#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5)
+#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7)
+
+#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
+#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1)
+#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2)
+#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3)
+#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4)
+#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5)
+#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7)
+
+#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
+#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1)
+#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2)
+#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3)
+#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4)
+#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5)
+#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7)
+
+#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
+#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1)
+#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2)
+#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3)
+#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4)
+#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5)
+#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7)
+
+#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
+#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1)
+#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2)
+#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3)
+#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4)
+#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5)
+#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7)
+
+#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
+#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1)
+#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2)
+#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3)
+#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4)
+#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5)
+#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7)
+
+#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
+#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1)
+#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2)
+#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3)
+#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4)
+#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5)
+#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6)
+#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7)
+
+#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
+#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1)
+#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2)
+#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3)
+#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4)
+#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5)
+#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6)
+#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7)
+
+#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
+#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1)
+#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2)
+#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3)
+#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4)
+#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5)
+#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6)
+#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7)
+
+#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
+#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1)
+#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2)
+#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3)
+#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4)
+#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5)
+#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6)
+#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7)
+
+#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
+#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1)
+#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2)
+#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3)
+#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4)
+#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5)
+#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6)
+#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7)
+
+#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
+#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1)
+#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2)
+#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7)
+
+#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
+#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1)
+#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2)
+#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7)
+
+#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
+#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1)
+#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2)
+#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3)
+#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4)
+#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7)
+
+#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
+#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1)
+#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7)
+
+#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
+#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1)
+#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2)
+#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3)
+#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4)
+#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5)
+#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6)
+#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7)
+
+#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
+#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1)
+#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7)
+
+#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
+#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1)
+#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2)
+#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3)
+#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4)
+#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5)
+#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6)
+#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7)
+
+#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
+#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1)
+#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3)
+#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4)
+#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5)
+#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6)
+#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7)
+
+#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
+#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1)
+#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3)
+#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4)
+#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5)
+#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6)
+#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7)
+
+#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
+#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1)
+#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2)
+#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3)
+#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4)
+#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5)
+#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6)
+#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7)
+
+#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
+#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1)
+#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2)
+#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3)
+#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4)
+#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5)
+#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6)
+#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7)
+
+#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
+#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1)
+#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2)
+#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3)
+#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4)
+#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5)
+#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6)
+
+#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
+#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1)
+#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2)
+#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3)
+#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4)
+#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5)
+#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6)
+
+#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
+#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1)
+#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2)
+#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3)
+#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4)
+#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5)
+
+#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
+#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1)
+#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2)
+#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3)
+#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4)
+#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5)
+
+#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
+#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1)
+#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2)
+#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3)
+#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4)
+#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5)
+
+#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
+#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1)
+#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2)
+#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7)
+
+#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
+#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1)
+#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2)
+#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7)
+
+#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
+#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1)
+#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2)
+#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3)
+#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4)
+#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5)
+#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6)
+#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7)
+
+#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
+#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1)
+#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2)
+#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3)
+#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4)
+#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5)
+#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6)
+#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7)
+
+#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
+#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1)
+#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2)
+#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3)
+#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4)
+#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5)
+#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6)
+#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7)
+
+#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
+#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1)
+#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2)
+#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3)
+#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4)
+#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5)
+#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6)
+#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7)
+
+#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0)
+#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1)
+#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2)
+
+#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0)
+#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1)
+#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2)
+
+#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0)
+#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1)
+
+#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0)
+#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1)
+
+#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0)
+#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1)
+
+#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0)
+#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1)
+
+#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0)
+#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1)
+#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2)
+
+#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0)
+#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1)
+
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0)
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1)
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2)
+#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3)
+
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0)
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1)
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2)
+#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3)
+
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0)
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1)
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2)
+#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3)
+
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0)
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1)
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2)
+#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3)
+
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0)
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1)
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2)
+#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3)
+
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0)
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1)
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2)
+#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3)
+
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0)
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1)
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2)
+#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3)
+
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0)
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1)
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2)
+#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3)
+
+#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1)
+
+#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1)
+
+#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0)
+#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1)
+#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6)
+#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7)
+
+#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
+#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1)
+#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6)
+#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7)
+
+#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0)
+#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1)
+
+#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0)
+#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1)
+
+#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0)
+#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1)
+
+#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0)
+#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1)
+
+#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0)
+#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1)
+#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2)
+#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7)
+
+#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0)
+#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1)
+#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2)
+#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7)
+
+#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0)
+#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1)
+#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2)
+#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4)
+#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5)
+#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7)
+
+#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0)
+#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1)
+#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2)
+#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4)
+#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5)
+#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7)
+
+#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0)
+#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1)
+#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2)
+#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3)
+#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4)
+#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5)
+#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7)
+
+#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0)
+#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1)
+#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2)
+#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4)
+#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5)
+#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7)
+
+#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0)
+#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1)
+#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2)
+#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7)
+
+#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0)
+#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1)
+#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2)
+#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5)
+#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7)
+
+#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0)
+#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1)
+#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2)
+#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5)
+#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7)
+
+#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0)
+#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1)
+#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2)
+#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5)
+#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7)
+
+#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0)
+#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1)
+#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5)
+#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7)
+
+#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
+#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1)
+#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5)
+#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7)
+
+#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0)
+#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1)
+#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5)
+#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7)
+
+#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0)
+#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1)
+#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5)
+#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7)
+
+#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1)
+#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5)
+#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7)
+
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5)
+#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6)
+
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5)
+#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6)
+
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5)
+#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6)
+
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5)
+#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6)
+
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5)
+#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6)
+
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3)
+#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5)
+
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0)
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1)
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2)
+#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3)
+
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6)
+#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7)
+
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6)
+#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7)
+
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6)
+#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7)
+
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6)
+#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7)
+
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6)
+#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7)
+
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0)
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1)
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2)
+#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3)
+
+#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0)
+#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1)
+#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2)
+
+#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0)
+#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1)
+#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2)
+
+#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0)
+#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1)
+#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2)
+
+#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0)
+#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1)
+#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2)
+
+#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0)
+#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1)
+#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2)
+
+#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0)
+#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1)
+#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2)
+
+#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0)
+#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1)
+#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2)
+
+#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0)
+#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1)
+#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2)
+
+#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0)
+#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1)
+#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2)
+
+#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0)
+#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1)
+#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2)
+
+#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0)
+#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1)
+#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2)
+
+#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0)
+#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1)
+
+#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0)
+#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1)
+#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2)
+#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7)
+
+#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0)
+#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1)
+#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2)
+#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7)
+
+#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0)
+#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1)
+#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2)
+#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7)
+
+#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0)
+#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1)
+#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2)
+#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7)
+
+#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0)
+#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1)
+#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2)
+#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7)
+
+#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0)
+#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1)
+#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2)
+#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3)
+#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4)
+#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5)
+
+#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4)
+#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5)
+
+#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0)
+#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1)
+#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2)
+#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3)
+#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4)
+#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5)
+
+#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0)
+#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1)
+#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2)
+#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3)
+#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4)
+#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5)
+
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6)
+#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7)
+
+#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6)
+#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7)
+
+#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3)
+#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4)
+#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5)
+#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6)
+#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7)
+
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0)
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1)
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2)
+#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7)
+
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0)
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1)
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2)
+#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7)
+
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0)
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1)
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2)
+#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7)
+
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0)
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1)
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2)
+#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7)
+
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0)
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1)
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2)
+#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7)
+
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0)
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1)
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2)
+#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7)
+
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1)
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2)
+#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7)
+
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1)
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2)
+#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7)
+
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0)
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1)
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2)
+#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7)
+
+#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0)
+#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1)
+#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2)
+
+#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0)
+#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1)
+#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2)
+
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0)
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1)
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2)
+#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3)
+
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0)
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1)
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2)
+#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3)
+
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0)
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1)
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2)
+#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3)
+
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0)
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1)
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2)
+#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3)
+
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3)
+#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7)
+
+#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0)
+#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1)
+#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7)
+
+#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0)
+#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1)
+#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7)
+
+#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0)
+#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1)
+#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7)
+
+#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0)
+#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1)
+
+#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0)
+#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1)
+
+#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0)
+#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1)
+
+#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0)
+#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1)
+
+#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0)
+#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1)
+
+#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0)
+#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1)
+
+#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0)
+#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1)
+
+#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0)
+#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1)
+
+#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0)
+#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1)
+
+#endif /* __MT8365_PINFUNC_H */
diff --git a/include/dt-bindings/power/imx8mm-power.h b/include/dt-bindings/power/imx8mm-power.h
new file mode 100644
index 0000000..fc9c2e1
--- /dev/null
+++ b/include/dt-bindings/power/imx8mm-power.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2020 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#ifndef __DT_BINDINGS_IMX8MM_POWER_H__
+#define __DT_BINDINGS_IMX8MM_POWER_H__
+
+#define IMX8MM_POWER_DOMAIN_HSIOMIX 0
+#define IMX8MM_POWER_DOMAIN_PCIE 1
+#define IMX8MM_POWER_DOMAIN_OTG1 2
+#define IMX8MM_POWER_DOMAIN_OTG2 3
+#define IMX8MM_POWER_DOMAIN_GPUMIX 4
+#define IMX8MM_POWER_DOMAIN_GPU 5
+#define IMX8MM_POWER_DOMAIN_VPUMIX 6
+#define IMX8MM_POWER_DOMAIN_VPUG1 7
+#define IMX8MM_POWER_DOMAIN_VPUG2 8
+#define IMX8MM_POWER_DOMAIN_VPUH1 9
+#define IMX8MM_POWER_DOMAIN_DISPMIX 10
+#define IMX8MM_POWER_DOMAIN_MIPI 11
+
+#endif
diff --git a/include/dt-bindings/power/imx8mn-power.h b/include/dt-bindings/power/imx8mn-power.h
new file mode 100644
index 0000000..102ee85
--- /dev/null
+++ b/include/dt-bindings/power/imx8mn-power.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (C) 2020 Compass Electronics Group, LLC
+ */
+
+#ifndef __DT_BINDINGS_IMX8MN_POWER_H__
+#define __DT_BINDINGS_IMX8MN_POWER_H__
+
+#define IMX8MN_POWER_DOMAIN_HSIOMIX 0
+#define IMX8MN_POWER_DOMAIN_OTG1 1
+#define IMX8MN_POWER_DOMAIN_GPUMIX 2
+#define IMX8MN_POWER_DOMAIN_DISPMIX 3
+#define IMX8MN_POWER_DOMAIN_MIPI 4
+
+#endif
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index eedb5d9..8b5708b 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -81,6 +81,19 @@
#define SC7280_LCX 7
#define SC7280_MSS 8
+/* SC8180X Power Domain Indexes */
+#define SC8180X_CX 0
+#define SC8180X_CX_AO 1
+#define SC8180X_EBI 2
+#define SC8180X_GFX 3
+#define SC8180X_LCX 4
+#define SC8180X_LMX 5
+#define SC8180X_MMCX 6
+#define SC8180X_MMCX_AO 7
+#define SC8180X_MSS 8
+#define SC8180X_MX 9
+#define SC8180X_MX_AO 10
+
/* SDM845 Power Domain performance levels */
#define RPMH_REGULATOR_LEVEL_RETENTION 16
#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
@@ -95,6 +108,14 @@
#define RPMH_REGULATOR_LEVEL_TURBO 384
#define RPMH_REGULATOR_LEVEL_TURBO_L1 416
+/* MDM9607 Power Domains */
+#define MDM9607_VDDCX 0
+#define MDM9607_VDDCX_AO 1
+#define MDM9607_VDDCX_VFL 2
+#define MDM9607_VDDMX 3
+#define MDM9607_VDDMX_AO 4
+#define MDM9607_VDDMX_VFL 5
+
/* MSM8939 Power Domains */
#define MSM8939_VDDMDCX 0
#define MSM8939_VDDMDCX_AO 1
diff --git a/include/dt-bindings/power/rk3568-power.h b/include/dt-bindings/power/rk3568-power.h
new file mode 100644
index 0000000..6cc1af1
--- /dev/null
+++ b/include/dt-bindings/power/rk3568-power.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__
+#define __DT_BINDINGS_POWER_RK3568_POWER_H__
+
+/* VD_CORE */
+#define RK3568_PD_CPU_0 0
+#define RK3568_PD_CPU_1 1
+#define RK3568_PD_CPU_2 2
+#define RK3568_PD_CPU_3 3
+#define RK3568_PD_CORE_ALIVE 4
+
+/* VD_PMU */
+#define RK3568_PD_PMU 5
+
+/* VD_NPU */
+#define RK3568_PD_NPU 6
+
+/* VD_GPU */
+#define RK3568_PD_GPU 7
+
+/* VD_LOGIC */
+#define RK3568_PD_VI 8
+#define RK3568_PD_VO 9
+#define RK3568_PD_RGA 10
+#define RK3568_PD_VPU 11
+#define RK3568_PD_CENTER 12
+#define RK3568_PD_RKVDEC 13
+#define RK3568_PD_RKVENC 14
+#define RK3568_PD_PIPE 15
+#define RK3568_PD_LOGIC_ALIVE 16
+
+#endif
diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h
index f0c3aae..f3a0ed3 100644
--- a/include/dt-bindings/reset/stm32mp1-resets.h
+++ b/include/dt-bindings/reset/stm32mp1-resets.h
@@ -7,6 +7,7 @@
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_
#define _DT_BINDINGS_STM32MP1_RESET_H_
+#define MCU_HOLD_BOOT_R 2144
#define LTDC_R 3072
#define DSI_R 3076
#define DDRPERFM_R 3080
@@ -105,4 +106,18 @@
#define GPIOJ_R 19785
#define GPIOK_R 19786
+/* SCMI reset domain identifiers */
+#define RST_SCMI0_SPI6 0
+#define RST_SCMI0_I2C4 1
+#define RST_SCMI0_I2C6 2
+#define RST_SCMI0_USART1 3
+#define RST_SCMI0_STGEN 4
+#define RST_SCMI0_GPIOZ 5
+#define RST_SCMI0_CRYP1 6
+#define RST_SCMI0_HASH1 7
+#define RST_SCMI0_RNG1 8
+#define RST_SCMI0_MDMA 9
+#define RST_SCMI0_MCU 10
+#define RST_SCMI0_MCU_HOLD_BOOT 11
+
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
diff --git a/include/dt-bindings/sound/qcom,q6afe.h b/include/dt-bindings/sound/qcom,q6afe.h
index f64b5d2..66c21ab 100644
--- a/include/dt-bindings/sound/qcom,q6afe.h
+++ b/include/dt-bindings/sound/qcom,q6afe.h
@@ -129,6 +129,8 @@
#define TX_CODEC_DMA_TX_5 124
#define RX_CODEC_DMA_RX_6 125
#define RX_CODEC_DMA_RX_7 126
+#define QUINARY_MI2S_RX 127
+#define QUINARY_MI2S_TX 128
#define LPASS_CLK_ID_PRI_MI2S_IBIT 1
#define LPASS_CLK_ID_PRI_MI2S_EBIT 2
diff --git a/src/arm/am335x-baltos.dtsi b/src/arm/am335x-baltos.dtsi
index 3ea2861..1103a2c 100644
--- a/src/arm/am335x-baltos.dtsi
+++ b/src/arm/am335x-baltos.dtsi
@@ -393,10 +393,10 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
-&gpio3 {
+&gpio3_target {
ti,no-reset-on-init;
};
diff --git a/src/arm/am335x-boneblack-wireless.dts b/src/arm/am335x-boneblack-wireless.dts
index 86cad99..8011664 100644
--- a/src/arm/am335x-boneblack-wireless.dts
+++ b/src/arm/am335x-boneblack-wireless.dts
@@ -101,7 +101,7 @@
};
&gpio3 {
- ls_buf_en {
+ ls-buf-en-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/src/arm/am335x-boneblue.dts b/src/arm/am335x-boneblue.dts
index 69acaf4..0afcc2e 100644
--- a/src/arm/am335x-boneblue.dts
+++ b/src/arm/am335x-boneblue.dts
@@ -436,7 +436,7 @@
};
&gpio3 {
- ls_buf_en {
+ ls-buf-en-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/src/arm/am335x-bonegreen-wireless.dts b/src/arm/am335x-bonegreen-wireless.dts
index 7615327..74db0fc 100644
--- a/src/arm/am335x-bonegreen-wireless.dts
+++ b/src/arm/am335x-bonegreen-wireless.dts
@@ -101,7 +101,7 @@
};
&gpio1 {
- ls_buf_en {
+ ls-buf-en-hog {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>;
output-high;
@@ -118,7 +118,7 @@
/* an external pulldown on U21 pin 4. */
&gpio3 {
- bt_aud_in {
+ bt-aud-in-hog {
gpio-hog;
gpios = <16 GPIO_ACTIVE_HIGH>;
output-low;
diff --git a/src/arm/am335x-cm-t335.dts b/src/arm/am335x-cm-t335.dts
index 36d963d..688e14e 100644
--- a/src/arm/am335x-cm-t335.dts
+++ b/src/arm/am335x-cm-t335.dts
@@ -333,7 +333,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
@@ -496,7 +496,7 @@
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
/* WLS1271 WiFi */
wlcore: wlcore@1 {
compatible = "ti,wl1271";
diff --git a/src/arm/am335x-evm.dts b/src/arm/am335x-evm.dts
index 902e295..9cf39c9 100644
--- a/src/arm/am335x-evm.dts
+++ b/src/arm/am335x-evm.dts
@@ -495,7 +495,7 @@
&epwmss0 {
status = "okay";
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins>;
diff --git a/src/arm/am335x-evmsk.dts b/src/arm/am335x-evmsk.dts
index d5f8d5e..001657b 100644
--- a/src/arm/am335x-evmsk.dts
+++ b/src/arm/am335x-evmsk.dts
@@ -510,7 +510,7 @@
&epwmss2 {
status = "okay";
- ecap2: ecap@100 {
+ ecap2: pwm@100 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap2_pins>;
@@ -646,7 +646,7 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
diff --git a/src/arm/am335x-icev2.dts b/src/arm/am335x-icev2.dts
index e923d06..5e598ac 100644
--- a/src/arm/am335x-icev2.dts
+++ b/src/arm/am335x-icev2.dts
@@ -458,14 +458,14 @@
};
&gpio3 {
- p4 {
+ pr1-mii-ctl-hog {
gpio-hog;
gpios = <4 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PR1_MII_CTRL";
};
- p10 {
+ mux-mii-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
/* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */
diff --git a/src/arm/am335x-moxa-uc-2100-common.dtsi b/src/arm/am335x-moxa-uc-2100-common.dtsi
index 4e90f9c..8121a19 100644
--- a/src/arm/am335x-moxa-uc-2100-common.dtsi
+++ b/src/arm/am335x-moxa-uc-2100-common.dtsi
@@ -150,7 +150,7 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
diff --git a/src/arm/am335x-moxa-uc-8100-common.dtsi b/src/arm/am335x-moxa-uc-8100-common.dtsi
index 98d8ed4..39e5d2c 100644
--- a/src/arm/am335x-moxa-uc-8100-common.dtsi
+++ b/src/arm/am335x-moxa-uc-8100-common.dtsi
@@ -353,7 +353,7 @@
status = "okay";
};
-&gpio0 {
+&gpio0_target {
ti,no-reset-on-init;
};
diff --git a/src/arm/am335x-osd3358-sm-red.dts b/src/arm/am335x-osd3358-sm-red.dts
index f841afb..5403e47 100644
--- a/src/arm/am335x-osd3358-sm-red.dts
+++ b/src/arm/am335x-osd3358-sm-red.dts
@@ -25,10 +25,6 @@
regulator-always-on;
};
-&mmc1 {
- vmmc-supply = <&vmmcsd_fixed>;
-};
-
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
pinctrl-names = "default";
@@ -37,68 +33,6 @@
status = "okay";
};
-&am33xx_pinmux {
- nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- >;
- };
-
- nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
- >;
- };
-
- mcasp0_pins: mcasp0-pins {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
- AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
- AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
- >;
- };
-
- flash_enable: flash-enable {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */
- >;
- };
-
- imu_interrupt: imu-interrupt {
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */
- >;
- };
-
- ethernet_interrupt: ethernet-interrupt{
- pinctrl-single,pins = <
- AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */
- >;
- };
-};
-
&lcdc {
status = "okay";
@@ -167,10 +101,6 @@
};
};
-&rtc {
- system-power-controller;
-};
-
&mcasp0 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
@@ -267,6 +197,66 @@
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;
+ nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ >;
+ };
+
+ nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)
+ >;
+ };
+
+ mcasp0_pins: mcasp0-pins {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mcasp0_ahclkr.mcasp0_axr2*/
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLUP, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
+ AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.GPIO1_27 */
+ >;
+ };
+
+ flash_enable: flash-enable {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* rmii1_ref_clk.gpio0_29 */
+ >;
+ };
+
+ imu_interrupt: imu-interrupt {
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_rx_er.gpio3_2 */
+ >;
+ };
+
+ ethernet_interrupt: ethernet-interrupt{
+ pinctrl-single,pins = <
+ AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mii1_col.gpio3_0 */
+ >;
+ };
+
user_leds_s0: user-leds-s0 {
pinctrl-single,pins = <
AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */
@@ -427,6 +417,7 @@
&mmc1 {
status = "okay";
+ vmmc-supply = <&vmmcsd_fixed>;
bus-width = <0x4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
@@ -434,6 +425,7 @@
};
&rtc {
+ system-power-controller;
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/src/arm/am335x-shc.dts b/src/arm/am335x-shc.dts
index 1eaa265..2bfe60d 100644
--- a/src/arm/am335x-shc.dts
+++ b/src/arm/am335x-shc.dts
@@ -140,14 +140,14 @@
};
&gpio1 {
- hmtc_rst {
+ hmtc-rst-hog {
gpio-hog;
gpios = <24 GPIO_ACTIVE_LOW>;
output-high;
line-name = "homematic_reset";
};
- hmtc_prog {
+ hmtc-prog-hog {
gpio-hog;
gpios = <27 GPIO_ACTIVE_LOW>;
output-high;
@@ -156,14 +156,14 @@
};
&gpio3 {
- zgb_rst {
+ zgb-rst-hog {
gpio-hog;
gpios = <18 GPIO_ACTIVE_LOW>;
output-low;
line-name = "zigbee_reset";
};
- zgb_boot {
+ zgb-boot-hog {
gpio-hog;
gpios = <19 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/src/arm/am33xx-clocks.dtsi b/src/arm/am33xx-clocks.dtsi
index dced92a..b7b7106 100644
--- a/src/arm/am33xx-clocks.dtsi
+++ b/src/arm/am33xx-clocks.dtsi
@@ -164,7 +164,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0490>, <0x045c>, <0x0468>;
+ reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@@ -204,7 +204,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0488>, <0x0420>, <0x042c>;
+ reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@@ -220,7 +220,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0494>, <0x0434>, <0x0440>;
+ reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@@ -244,7 +244,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x0498>, <0x0448>, <0x0454>;
+ reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@@ -261,7 +261,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x048c>, <0x0470>, <0x049c>;
+ reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;
};
dpll_per_m2_ck: dpll_per_m2_ck@4ac {
diff --git a/src/arm/am33xx-l4.dtsi b/src/arm/am33xx-l4.dtsi
index 039a9ab..859e760 100644
--- a/src/arm/am33xx-l4.dtsi
+++ b/src/arm/am33xx-l4.dtsi
@@ -1486,7 +1486,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
+ mbox_wkupm3: mbox-wkup-m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
@@ -1789,7 +1789,7 @@
};
};
- target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
+ gpio3_target: target-module@ae000 { /* 0x481ae000, ap 56 3a.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0xae000 0x4>,
<0xae010 0x4>,
@@ -1995,15 +1995,12 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap0: ecap@100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap0: pwm@100 {
+ compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
- interrupts = <31>;
- interrupt-names = "ecap0";
status = "disabled";
};
@@ -2017,8 +2014,7 @@
};
ehrpwm0: pwm@200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
@@ -2056,15 +2052,12 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap1: ecap@100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap1: pwm@100 {
+ compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
- interrupts = <47>;
- interrupt-names = "ecap1";
status = "disabled";
};
@@ -2078,8 +2071,7 @@
};
ehrpwm1: pwm@200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
@@ -2117,15 +2109,12 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap2: ecap@100 {
- compatible = "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap2: pwm@100 {
+ compatible = "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
- interrupts = <61>;
- interrupt-names = "ecap2";
status = "disabled";
};
@@ -2139,8 +2128,7 @@
};
ehrpwm2: pwm@200 {
- compatible = "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
diff --git a/src/arm/am437x-gp-evm.dts b/src/arm/am437x-gp-evm.dts
index 6e4d05d..e267768 100644
--- a/src/arm/am437x-gp-evm.dts
+++ b/src/arm/am437x-gp-evm.dts
@@ -786,7 +786,7 @@
pinctrl-0 = <&gpio0_pins>;
status = "okay";
- p23 {
+ sel-emmc-nand-hog {
gpio-hog;
gpios = <23 GPIO_ACTIVE_HIGH>;
/* SelEMMCorNAND selects between eMMC and NAND:
@@ -813,13 +813,16 @@
status = "okay";
};
+&gpio5_target {
+ ti,no-reset-on-init;
+};
+
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&display_mux_pins>;
status = "okay";
- ti,no-reset-on-init;
- p8 {
+ sel-lcd-hdmi-hog {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
diff --git a/src/arm/am437x-l4.dtsi b/src/arm/am437x-l4.dtsi
index e217ffc..40ef397 100644
--- a/src/arm/am437x-l4.dtsi
+++ b/src/arm/am437x-l4.dtsi
@@ -194,7 +194,7 @@
ranges = <0x0 0x9000 0x1000>;
uart0: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
};
@@ -712,7 +712,7 @@
ranges = <0x0 0x22000 0x1000>;
uart1: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -740,7 +740,7 @@
ranges = <0x0 0x24000 0x1000>;
uart2: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1168,7 +1168,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
+ mbox_wkupm3: mbox-wkup-m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
@@ -1399,7 +1399,7 @@
ranges = <0x0 0xa6000 0x1000>;
uart3: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1427,7 +1427,7 @@
ranges = <0x0 0xa8000 0x1000>;
uart4: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1455,7 +1455,7 @@
ranges = <0x0 0xaa000 0x1000>;
uart5: serial@0 {
- compatible = "ti,am4372-uart","ti,omap2-uart";
+ compatible = "ti,am4372-uart";
reg = <0x0 0x2000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
@@ -1747,10 +1747,9 @@
ranges = <0 0 0x1000>;
status = "disabled";
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
@@ -1760,8 +1759,7 @@
ehrpwm0: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
@@ -1799,10 +1797,9 @@
ranges = <0 0 0x1000>;
status = "disabled";
- ecap1: ecap@100 {
+ ecap1: pwm@100 {
compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
@@ -1812,8 +1809,7 @@
ehrpwm1: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
@@ -1851,10 +1847,9 @@
ranges = <0 0 0x1000>;
status = "disabled";
- ecap2: ecap@100 {
+ ecap2: pwm@100 {
compatible = "ti,am4372-ecap",
- "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x100 0x80>;
clocks = <&l4ls_gclk>;
@@ -1864,8 +1859,7 @@
ehrpwm2: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
@@ -1905,8 +1899,7 @@
ehrpwm3: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
@@ -1946,8 +1939,7 @@
ehrpwm4: pwm@48308200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
@@ -1987,8 +1979,7 @@
ehrpwm5: pwm@200 {
compatible = "ti,am4372-ehrpwm",
- "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x200 0x80>;
clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
@@ -2070,7 +2061,7 @@
};
};
- target-module@22000 { /* 0x48322000, ap 116 64.0 */
+ gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x22000 0x4>,
<0x22010 0x4>,
diff --git a/src/arm/am43x-epos-evm.dts b/src/arm/am43x-epos-evm.dts
index f517d1e..aae0af1 100644
--- a/src/arm/am43x-epos-evm.dts
+++ b/src/arm/am43x-epos-evm.dts
@@ -725,7 +725,7 @@
pinctrl-0 = <&display_mux_pins>;
status = "okay";
- p1 {
+ sel-lcd-hdmi-hog {
/*
* SelLCDorHDMI selects between display and audio paths:
* Low: HDMI display with audio via HDMI
@@ -860,7 +860,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi0_pins_default>;
pinctrl-1 = <&spi0_pins_sleep>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
};
&spi1 {
@@ -868,7 +868,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_pins_default>;
pinctrl-1 = <&spi1_pins_sleep>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
};
&usb2_phy1 {
diff --git a/src/arm/am43xx-clocks.dtsi b/src/arm/am43xx-clocks.dtsi
index c726cd8..314fc59 100644
--- a/src/arm/am43xx-clocks.dtsi
+++ b/src/arm/am43xx-clocks.dtsi
@@ -204,7 +204,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+ reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
};
dpll_core_x2_ck: dpll_core_x2_ck {
@@ -250,7 +250,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+ reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
@@ -276,7 +276,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2da0>, <0x2da4>, <0x2dac>;
+ reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
@@ -294,7 +294,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+ reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
@@ -313,7 +313,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2de0>, <0x2de4>, <0x2dec>;
+ reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
};
dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
@@ -557,7 +557,7 @@
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
- reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+ reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
};
dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
diff --git a/src/arm/am5718.dtsi b/src/arm/am5718.dtsi
index ebf4d3c..6d7530a 100644
--- a/src/arm/am5718.dtsi
+++ b/src/arm/am5718.dtsi
@@ -17,17 +17,13 @@
* VCP1, VCP2
* MLB
* ISS
- * USB3, USB4
+ * USB3
*/
&usb3_tm {
status = "disabled";
};
-&usb4_tm {
- status = "disabled";
-};
-
&atl_tm {
status = "disabled";
};
diff --git a/src/arm/am57xx-cl-som-am57x.dts b/src/arm/am57xx-cl-som-am57x.dts
index 0d5fe2b..aed8156 100644
--- a/src/arm/am57xx-cl-som-am57x.dts
+++ b/src/arm/am57xx-cl-som-am57x.dts
@@ -454,20 +454,20 @@
&mailbox5 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
status = "okay";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
status = "okay";
};
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
status = "okay";
};
};
@@ -610,12 +610,11 @@
>;
};
-&gpio3 {
- status = "okay";
+&gpio3_target {
ti,no-reset-on-init;
};
-&gpio2 {
+&gpio2_target {
status = "okay";
ti,no-reset-on-init;
};
diff --git a/src/arm/arm-realview-eb.dtsi b/src/arm/arm-realview-eb.dtsi
index a534a8e..04e8a27 100644
--- a/src/arm/arm-realview-eb.dtsi
+++ b/src/arm/arm-realview-eb.dtsi
@@ -148,7 +148,7 @@
usb: usb@4f000000 {
compatible = "nxp,usb-isp1761";
reg = <0x4f000000 0x20000>;
- port1-otg;
+ dr_mode = "peripheral";
};
bridge {
diff --git a/src/arm/arm-realview-pb1176.dts b/src/arm/arm-realview-pb1176.dts
index f925782..366687f 100644
--- a/src/arm/arm-realview-pb1176.dts
+++ b/src/arm/arm-realview-pb1176.dts
@@ -166,7 +166,7 @@
reg = <0x3b000000 0x20000>;
interrupt-parent = <&intc_fpga1176>;
interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
- port1-otg;
+ dr_mode = "peripheral";
};
bridge {
diff --git a/src/arm/arm-realview-pb11mp.dts b/src/arm/arm-realview-pb11mp.dts
index 0c7dabe..228a51a 100644
--- a/src/arm/arm-realview-pb11mp.dts
+++ b/src/arm/arm-realview-pb11mp.dts
@@ -712,7 +712,7 @@
reg = <0x4f000000 0x20000>;
interrupt-parent = <&intc_tc11mp>;
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
- port1-otg;
+ dr_mode = "peripheral";
};
};
};
diff --git a/src/arm/arm-realview-pbx.dtsi b/src/arm/arm-realview-pbx.dtsi
index ac95667..ccf6f75 100644
--- a/src/arm/arm-realview-pbx.dtsi
+++ b/src/arm/arm-realview-pbx.dtsi
@@ -164,7 +164,7 @@
usb: usb@4f000000 {
compatible = "nxp,usb-isp1761";
reg = <0x4f000000 0x20000>;
- port1-otg;
+ dr_mode = "peripheral";
};
bridge {
diff --git a/src/arm/aspeed-ast2500-evb.dts b/src/arm/aspeed-ast2500-evb.dts
index 8bec21e..583a241 100644
--- a/src/arm/aspeed-ast2500-evb.dts
+++ b/src/arm/aspeed-ast2500-evb.dts
@@ -13,7 +13,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-ast2600-evb-a1.dts b/src/arm/aspeed-ast2600-evb-a1.dts
new file mode 100644
index 0000000..dd71480
--- /dev/null
+++ b/src/arm/aspeed-ast2600-evb-a1.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2021 IBM Corp.
+
+#include "aspeed-ast2600-evb.dts"
+
+/ {
+ model = "AST2600 A1 EVB";
+
+ /delete-node/regulator-vcc-sdhci0;
+ /delete-node/regulator-vcc-sdhci1;
+ /delete-node/regulator-vccq-sdhci0;
+ /delete-node/regulator-vccq-sdhci1;
+};
+
+/delete-node/ &sdc;
diff --git a/src/arm/aspeed-ast2600-evb.dts b/src/arm/aspeed-ast2600-evb.dts
index 2772796..b7eb552 100644
--- a/src/arm/aspeed-ast2600-evb.dts
+++ b/src/arm/aspeed-ast2600-evb.dts
@@ -4,6 +4,7 @@
/dts-v1/;
#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "AST2600 EVB";
@@ -21,6 +22,46 @@
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
+
+ vcc_sdhci0: regulator-vcc-sdhci0 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHCI0 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhci0: regulator-vccq-sdhci0 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHCI0 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>,
+ <1800000 0>;
+ };
+
+ vcc_sdhci1: regulator-vcc-sdhci1 {
+ compatible = "regulator-fixed";
+ regulator-name = "SDHCI1 Vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vccq_sdhci1: regulator-vccq-sdhci1 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHCI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 ASPEED_GPIO(V, 3) GPIO_ACTIVE_HIGH>;
+ gpios-states = <1>;
+ states = <3300000 1>,
+ <1800000 0>;
+ };
};
&mdio0 {
@@ -107,7 +148,8 @@
&emmc {
non-removable;
bus-width = <4>;
- max-frequency = <52000000>;
+ max-frequency = <100000000>;
+ clk-phase-mmc-hs200 = <9>, <225>;
};
&rtc {
@@ -121,37 +163,7 @@
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- u-boot@0 {
- reg = <0x0 0xe0000>; // 896KB
- label = "u-boot";
- };
-
- u-boot-env@e0000 {
- reg = <0xe0000 0x20000>; // 128KB
- label = "u-boot-env";
- };
-
- kernel@100000 {
- reg = <0x100000 0x900000>; // 9MB
- label = "kernel";
- };
-
- rofs@a00000 {
- reg = <0xa00000 0x2000000>; // 32MB
- label = "rofs";
- };
-
- rwfs@6000000 {
- reg = <0x2a00000 0x1600000>; // 22MB
- label = "rwfs";
- };
- };
+#include "openbmc-flash-layout-64.dtsi"
};
};
@@ -245,3 +257,46 @@
&uhci {
status = "okay";
};
+
+&sdc {
+ status = "okay";
+};
+
+/*
+ * The signal voltage of sdhci0 and sdhci1 on AST2600-A2 EVB is able to be
+ * toggled by GPIO pins.
+ * In the reference design, GPIOV0 of AST2600-A2 EVB is connected to the
+ * power load switch that provides 3.3v to sdhci0 vdd, GPIOV1 is connected to
+ * a 1.8v and a 3.3v power load switch that provides signal voltage to
+ * sdhci0 bus.
+ * If GPIOV0 is active high, sdhci0 is enabled, otherwise, sdhci0 is disabled.
+ * If GPIOV1 is active high, 3.3v power load switch is enabled, sdhci0 signal
+ * voltage is 3.3v, otherwise, 1.8v power load switch will be enabled,
+ * sdhci0 signal voltage becomes 1.8v.
+ * AST2600-A2 EVB also supports toggling signal voltage for sdhci1.
+ * The design is the same as sdhci0, it uses GPIOV2 as power-gpio and GPIOV3
+ * as power-switch-gpio.
+ */
+&sdhci0 {
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ sdhci-drive-type = /bits/ 8 <3>;
+ sdhci-caps-mask = <0x7 0x0>;
+ sdhci,wp-inverted;
+ vmmc-supply = <&vcc_sdhci0>;
+ vqmmc-supply = <&vccq_sdhci0>;
+ clk-phase-sd-hs = <7>, <200>;
+};
+
+&sdhci1 {
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ sdhci-drive-type = /bits/ 8 <3>;
+ sdhci-caps-mask = <0x7 0x0>;
+ sdhci,wp-inverted;
+ vmmc-supply = <&vcc_sdhci1>;
+ vqmmc-supply = <&vccq_sdhci1>;
+ clk-phase-sd-hs = <7>, <200>;
+};
diff --git a/src/arm/aspeed-bmc-amd-ethanolx.dts b/src/arm/aspeed-bmc-amd-ethanolx.dts
index 6aeb47c..79d1784 100644
--- a/src/arm/aspeed-bmc-amd-ethanolx.dts
+++ b/src/arm/aspeed-bmc-amd-ethanolx.dts
@@ -34,7 +34,7 @@
};
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
leds {
compatible = "gpio-leds";
diff --git a/src/arm/aspeed-bmc-ampere-mtjade.dts b/src/arm/aspeed-bmc-ampere-mtjade.dts
index 8f5ec22..57b0c45 100644
--- a/src/arm/aspeed-bmc-ampere-mtjade.dts
+++ b/src/arm/aspeed-bmc-ampere-mtjade.dts
@@ -9,7 +9,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
@@ -110,6 +110,30 @@
linux,code = <ASPEED_GPIO(Q, 5)>;
};
+ psu1_vin_good {
+ label = "PSU1_VIN_GOOD";
+ gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 4)>;
+ };
+
+ psu2_vin_good {
+ label = "PSU2_VIN_GOOD";
+ gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(H, 5)>;
+ };
+
+ psu1_present {
+ label = "PSU1_PRESENT";
+ gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(I, 0)>;
+ };
+
+ psu2_present {
+ label = "PSU2_PRESENT";
+ gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
+ linux,code = <ASPEED_GPIO(I, 1)>;
+ };
+
};
gpioA0mux: mux-controller {
@@ -280,7 +304,7 @@
m25p,fast-read;
label = "bmc";
/* spi-max-frequency = <50000000>; */
-#include "openbmc-flash-layout.dtsi"
+#include "openbmc-flash-layout-64.dtsi"
};
};
@@ -332,6 +356,16 @@
status = "okay";
};
+&mac0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rmii1_default>;
+ clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
+ <&syscon ASPEED_CLK_MAC1RCLK>;
+ clock-names = "MACCLK", "RCLK";
+ use-ncsi;
+};
+
&mac1 {
status = "okay";
pinctrl-names = "default";
@@ -426,6 +460,19 @@
status = "okay";
};
+&i2c10 {
+ status = "okay";
+ adm1278@10 {
+ compatible = "adi,adm1278";
+ reg = <0x10>;
+ };
+
+ adm1278@11 {
+ compatible = "adi,adm1278";
+ reg = <0x11>;
+ };
+};
+
&gfx {
status = "okay";
memory-region = <&gfx_memory>;
@@ -529,8 +576,9 @@
"S1_DDR_SAVE","","",
/*G0-G7*/ "S0_FW_BOOT_OK","SHD_REQ_L","","S0_OVERTEMP_L","","",
"","",
- /*H0-H7*/ "","","","","","","","",
- /*I0-I7*/ "","","S1_BMC_SPECIAL_BOOT","","","","","",
+ /*H0-H7*/ "","","","","PSU1_VIN_GOOD","PSU2_VIN_GOOD","","",
+ /*I0-I7*/ "PSU1_PRESENT","PSU2_PRESENT","S1_BMC_SPECIAL_BOOT",
+ "","","","","",
/*J0-J7*/ "S0_HIGHTEMP_L","S0_FAULT_L","S0_SCP_AUTH_FAIL_L","",
"","","","",
/*K0-K7*/ "","","","","","","","",
@@ -540,7 +588,8 @@
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","UID_BUTTON","","",
- /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","","","RESET_BUTTON","","",
+ /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN",
+ "OCP_MAIN_PWREN","RESET_BUTTON","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
diff --git a/src/arm/aspeed-bmc-arm-centriq2400-rep.dts b/src/arm/aspeed-bmc-arm-centriq2400-rep.dts
index c2ece0b..3395de9 100644
--- a/src/arm/aspeed-bmc-arm-centriq2400-rep.dts
+++ b/src/arm/aspeed-bmc-arm-centriq2400-rep.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts b/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts
index 2c29ac0..7c6af7f 100644
--- a/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts
+++ b/src/arm/aspeed-bmc-arm-stardragon4800-rep2.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-asrock-e3c246d4i.dts b/src/arm/aspeed-bmc-asrock-e3c246d4i.dts
index dcab6e7..33e413c 100644
--- a/src/arm/aspeed-bmc-asrock-e3c246d4i.dts
+++ b/src/arm/aspeed-bmc-asrock-e3c246d4i.dts
@@ -15,7 +15,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-bytedance-g220a.dts b/src/arm/aspeed-bmc-bytedance-g220a.dts
index 5ef88c3..01dace8 100644
--- a/src/arm/aspeed-bmc-bytedance-g220a.dts
+++ b/src/arm/aspeed-bmc-bytedance-g220a.dts
@@ -55,7 +55,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-facebook-cmm.dts b/src/arm/aspeed-bmc-facebook-cmm.dts
index 2fb8b14..90a3f48 100644
--- a/src/arm/aspeed-bmc-facebook-cmm.dts
+++ b/src/arm/aspeed-bmc-facebook-cmm.dts
@@ -280,7 +280,7 @@
chosen {
stdout-path = &uart1;
- bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlyprintk";
+ bootargs = "console=ttyS1,9600n8 root=/dev/ram rw earlycon";
};
ast-adc-hwmon {
diff --git a/src/arm/aspeed-bmc-facebook-tiogapass.dts b/src/arm/aspeed-bmc-facebook-tiogapass.dts
index 7b4b2b1..b6b1635 100644
--- a/src/arm/aspeed-bmc-facebook-tiogapass.dts
+++ b/src/arm/aspeed-bmc-facebook-tiogapass.dts
@@ -37,7 +37,7 @@
};
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-ibm-everest.dts b/src/arm/aspeed-bmc-ibm-everest.dts
index 3295c8c..d26a9e1 100644
--- a/src/arm/aspeed-bmc-ibm-everest.dts
+++ b/src/arm/aspeed-bmc-ibm-everest.dts
@@ -202,6 +202,35 @@
linux,code = <12>;
};
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* RTC battery fault LED at the back */
+ led-rtc-battery {
+ gpios = <&gpio0 ASPEED_GPIO(H, 0) GPIO_ACTIVE_LOW>;
+ };
+
+ /* BMC Card fault LED at the back */
+ led-bmc {
+ gpios = <&gpio0 ASPEED_GPIO(H, 1) GPIO_ACTIVE_LOW>;
+ };
+
+ /* Enclosure Identify LED at the back */
+ led-rear-enc-id0 {
+ gpios = <&gpio0 ASPEED_GPIO(H, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ /* Enclosure fault LED at the back */
+ led-rear-enc-fault0 {
+ gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ /* PCIE slot power LED */
+ led-pcieslot-power {
+ gpios = <&gpio0 ASPEED_GPIO(P, 4) GPIO_ACTIVE_LOW>;
+ };
+ };
};
&gpio0 {
@@ -214,7 +243,7 @@
/*F0-F7*/ "PIN_HOLE_RESET_IN_N","","",
"PIN_HOLE_RESET_OUT_N","","","","",
/*G0-G7*/ "","","","","","","","",
- /*H0-H7*/ "","","","","","","","",
+ /*H0-H7*/ "led-rtc-battery","led-bmc","led-rear-enc-id0","led-rear-enc-fault0","","","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
@@ -222,7 +251,7 @@
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
- /*P0-P7*/ "","","","","","","","",
+ /*P0-P7*/ "","","","","led-pcieslot-power","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","I2C_FLASH_MICRO_N","","",
/*S0-S7*/ "","","","","","","","",
@@ -353,10 +382,47 @@
&i2c1 {
status = "okay";
+};
- pca2: pca9552@61 {
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "atmel,24c128";
+ reg = <0x54>;
+ };
+
+ power-supply@68 {
+ compatible = "ibm,cffps";
+ reg = <0x68>;
+ };
+
+ power-supply@69 {
+ compatible = "ibm,cffps";
+ reg = <0x69>;
+ };
+
+ power-supply@6a {
+ compatible = "ibm,cffps";
+ reg = <0x6a>;
+ };
+
+ power-supply@6b {
+ compatible = "ibm,cffps";
+ reg = <0x6b>;
+ };
+};
+
+&i2c4 {
+ status = "okay";
+
+ pca2: pca9552@65 {
compatible = "nxp,pca9552";
- reg = <0x61>;
+ reg = <0x65>;
#address-cells = <1>;
#size-cells = <0>;
@@ -424,12 +490,222 @@
reg = <9>;
type = <PCA955X_TYPE_GPIO>;
};
-
};
- pca3: pca9552@62 {
+ i2c-switch@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ i2c-mux-idle-disconnect;
+
+ i2c4mux0chn0: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ eeprom@52 {
+ compatible = "atmel,24c64";
+ reg = <0x52>;
+ };
+
+ pca_cable_card_c01: pca9551@62 {
+ compatible = "nxp,pca9551";
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c01-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c01-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+
+ i2c4mux0chn1: i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ pca_cable_card_c02: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c02-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c02-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+
+ i2c4mux0chn2: i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ eeprom@51 {
+ compatible = "atmel,24c64";
+ reg = <0x51>;
+ };
+
+ pca_cable_card_c03: pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c03-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c03-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+ };
+};
+
+&i2c5 {
+ status = "okay";
+
+ pca3: pca9552@66 {
compatible = "nxp,pca9552";
- reg = <0x62>;
+ reg = <0x66>;
#address-cells = <1>;
#size-cells = <0>;
@@ -512,87 +788,6 @@
};
-};
-
-&i2c2 {
- status = "okay";
-};
-
-&i2c3 {
- status = "okay";
-
- eeprom@54 {
- compatible = "atmel,24c128";
- reg = <0x54>;
- };
-
- power-supply@68 {
- compatible = "ibm,cffps";
- reg = <0x68>;
- };
-
- power-supply@69 {
- compatible = "ibm,cffps";
- reg = <0x69>;
- };
-
- power-supply@6a {
- compatible = "ibm,cffps";
- reg = <0x6a>;
- };
-
- power-supply@6b {
- compatible = "ibm,cffps";
- reg = <0x6b>;
- };
-};
-
-&i2c4 {
- status = "okay";
-
- i2c-switch@70 {
- compatible = "nxp,pca9546";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "okay";
- i2c-mux-idle-disconnect;
-
- i2c4mux0chn0: i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- eeprom@52 {
- compatible = "atmel,24c64";
- reg = <0x52>;
- };
- };
-
- i2c4mux0chn1: i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
- };
- };
-
- i2c4mux0chn2: i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- eeprom@51 {
- compatible = "atmel,24c64";
- reg = <0x51>;
- };
- };
- };
-};
-
-&i2c5 {
- status = "okay";
-
i2c-switch@70 {
compatible = "nxp,pca9546";
reg = <0x70>;
@@ -609,6 +804,62 @@
compatible = "atmel,24c64";
reg = <0x50>;
};
+
+ pca_cable_card_c04: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c04-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c04-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c5mux0chn1: i2c@1 {
@@ -619,6 +870,62 @@
compatible = "atmel,24c64";
reg = <0x51>;
};
+
+ pca_cable_card_c05: pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c05-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c05-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c5mux0chn2: i2c@2 {
@@ -629,6 +936,62 @@
compatible = "atmel,24c64";
reg = <0x52>;
};
+
+ pca_cable_card_c06: pca9551@62 {
+ compatible = "nxp,pca9551";
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c06-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c06-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c5mux0chn3: i2c@3 {
@@ -639,6 +1002,62 @@
compatible = "atmel,24c64";
reg = <0x53>;
};
+
+ pca_cable_card_c07: pca9551@63 {
+ compatible = "nxp,pca9551";
+ reg = <0x63>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c07-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c07-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
};
};
@@ -659,8 +1078,64 @@
#size-cells = <0>;
reg = <0>;
eeprom@50 {
- compatible = "atmel,24c64";
- reg = <0x50>;
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ };
+
+ pca_cable_card_c08: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c08-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c08-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
};
};
@@ -672,6 +1147,62 @@
compatible = "atmel,24c64";
reg = <0x52>;
};
+
+ pca_cable_card_c09: pca9551@62 {
+ compatible = "nxp,pca9551";
+ reg = <0x62>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c09-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c09-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c6mux0chn2: i2c@2 {
@@ -682,6 +1213,62 @@
compatible = "atmel,24c64";
reg = <0x53>;
};
+
+ pca_cable_card_c10: pca9551@63 {
+ compatible = "nxp,pca9551";
+ reg = <0x63>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c10-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c10-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
};
i2c6mux0chn3: i2c@3 {
@@ -692,12 +1279,1013 @@
compatible = "atmel,24c64";
reg = <0x51>;
};
+
+ pca_cable_card_c11: pca9551@61 {
+ compatible = "nxp,pca9551";
+ reg = <0x61>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "cablecard-c11-cxp-top";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "cablecard-c11-cxp-bot";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@2 {
+ reg = <2>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@3 {
+ reg = <3>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@4 {
+ reg = <4>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@5 {
+ reg = <5>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@6 {
+ reg = <6>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+ };
+ };
+
+ pca_pcie_slot: pca9552@65 {
+ compatible = "nxp,pca9552";
+ reg = <0x65>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ gpio@0 {
+ reg = <0>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@1 {
+ label = "pcieslot-c01";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "pcieslot-c02";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "pcieslot-c03";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "pcieslot-c04";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "pcieslot-c05";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "pcieslot-c06";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "pcieslot-c07";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "pcieslot-c08";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "pcieslot-c09";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "pcieslot-c10";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "pcieslot-c11";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@12 {
+ reg = <12>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@13 {
+ reg = <13>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
};
};
};
&i2c7 {
status = "okay";
+
+ pic0_dimm: pca9552@31 {
+ compatible = "ibm,pca9552";
+ reg = <0x31>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm5";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm6";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm7";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm8";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm9";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm10";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm11";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm12";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm13";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm14";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm15";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic1_dimm: pca9552@32 {
+ compatible = "ibm,pca9552";
+ reg = <0x32>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm16";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm17";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm18";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm19";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm20";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm21";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm22";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm23";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm24";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm25";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm26";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm27";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm28";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm29";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm30";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm31";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic2_dimm: pca9552@33 {
+ compatible = "ibm,pca9552";
+ reg = <0x33>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm32";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm33";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm34";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm35";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm36";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm37";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm38";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm39";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm40";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm41";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm42";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm43";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm44";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm45";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm46";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm47";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic3_dimm: pca9552@30 {
+ compatible = "ibm,pca9552";
+ reg = <0x30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "ddimm48";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "ddimm49";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "ddimm50";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "ddimm51";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "ddimm52";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "ddimm53";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "ddimm54";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "ddimm55";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "ddimm56";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "ddimm57";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "ddimm58";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "ddimm59";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "ddimm60";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "ddimm61";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "ddimm62";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "ddimm63";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic0_vrm_misc: pca9552@34 {
+ compatible = "ibm,pca9552";
+ reg = <0x34>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "planar";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "tpm";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "cpu3-c61";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "cpu0-c14";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "opencapi-connector3";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "opencapi-connector4";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "opencapi-connector5";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@8 {
+ label = "vrm4";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "vrm5";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "vrm6";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "vrm7";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "vrm12";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "vrm13";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "vrm14";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "vrm15";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
+
+ pic1_vrm_misc: pca9552@35 {
+ compatible = "ibm,pca9552";
+ reg = <0x35>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "dasd-backplane";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "power-distribution";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "cpu1-c19";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "cpu2-c56";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "opencapi-connector0";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "opencapi-connector1";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "opencapi-connector2";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@7 {
+ reg = <7>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ led@8 {
+ label = "vrm0";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "vrm1";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "vrm2";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "vrm3";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "vrm8";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "vrm9";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@14 {
+ label = "vrm10";
+ reg = <14>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@15 {
+ label = "vrm11";
+ reg = <15>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
&i2c8 {
@@ -863,6 +2451,48 @@
compatible = "atmel,24c32";
reg = <0x50>;
};
+
+ pca_oppanel: pca9551@60 {
+ compatible = "nxp,pca9551";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "front-sys-id0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "front-check-log0";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "front-enc-fault1";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "front-sys-pwron0";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+ };
};
i2c14mux0chn3: i2c@3 {
@@ -901,6 +2531,138 @@
};
};
+ pca_fan_nvme: pca9552@60 {
+ compatible = "nxp,pca9552";
+ reg = <0x60>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ led@0 {
+ label = "nvme0";
+ reg = <0>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@1 {
+ label = "nvme1";
+ reg = <1>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@2 {
+ label = "nvme2";
+ reg = <2>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@3 {
+ label = "nvme3";
+ reg = <3>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@4 {
+ label = "nvme4";
+ reg = <4>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@5 {
+ label = "nvme5";
+ reg = <5>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@6 {
+ label = "nvme6";
+ reg = <6>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@7 {
+ label = "nvme7";
+ reg = <7>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@8 {
+ label = "nvme8";
+ reg = <8>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@9 {
+ label = "nvme9";
+ reg = <9>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@10 {
+ label = "fan0";
+ reg = <10>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@11 {
+ label = "fan1";
+ reg = <11>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@12 {
+ label = "fan2";
+ reg = <12>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ led@13 {
+ label = "fan3";
+ reg = <13>;
+ retain-state-shutdown;
+ default-state = "keep";
+ type = <PCA955X_TYPE_LED>;
+ };
+
+ gpio@14 {
+ reg = <14>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+
+ gpio@15 {
+ reg = <15>;
+ type = <PCA955X_TYPE_GPIO>;
+ };
+ };
+
pca0: pca9552@61 {
compatible = "nxp,pca9552";
#address-cells = <1>;
diff --git a/src/arm/aspeed-bmc-ibm-rainier-4u.dts b/src/arm/aspeed-bmc-ibm-rainier-4u.dts
index f7fd3b3..342546a 100644
--- a/src/arm/aspeed-bmc-ibm-rainier-4u.dts
+++ b/src/arm/aspeed-bmc-ibm-rainier-4u.dts
@@ -19,33 +19,3 @@
reg = <0x6b>;
};
};
-
-&fan0 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan1 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan2 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan3 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan4 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
-
-&fan5 {
- tach-pulses = <4>;
- /delete-property/ maxim,fan-dual-tach;
-};
diff --git a/src/arm/aspeed-bmc-inspur-fp5280g2.dts b/src/arm/aspeed-bmc-inspur-fp5280g2.dts
index 0759389..1752f32 100644
--- a/src/arm/aspeed-bmc-inspur-fp5280g2.dts
+++ b/src/arm/aspeed-bmc-inspur-fp5280g2.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-inspur-on5263m5.dts b/src/arm/aspeed-bmc-inspur-on5263m5.dts
index 80c92e0..5a98a19 100644
--- a/src/arm/aspeed-bmc-inspur-on5263m5.dts
+++ b/src/arm/aspeed-bmc-inspur-on5263m5.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "earlyprintk";
+ bootargs = "earlycon";
};
memory {
diff --git a/src/arm/aspeed-bmc-intel-s2600wf.dts b/src/arm/aspeed-bmc-intel-s2600wf.dts
index 6e9baf3..d5b7d28 100644
--- a/src/arm/aspeed-bmc-intel-s2600wf.dts
+++ b/src/arm/aspeed-bmc-intel-s2600wf.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "earlyprintk";
+ bootargs = "earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-lenovo-hr630.dts b/src/arm/aspeed-bmc-lenovo-hr630.dts
index c29e5f4..8f543cc 100644
--- a/src/arm/aspeed-bmc-lenovo-hr630.dts
+++ b/src/arm/aspeed-bmc-lenovo-hr630.dts
@@ -27,7 +27,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-lenovo-hr855xg2.dts b/src/arm/aspeed-bmc-lenovo-hr855xg2.dts
index 084c455..bcc1820 100644
--- a/src/arm/aspeed-bmc-lenovo-hr855xg2.dts
+++ b/src/arm/aspeed-bmc-lenovo-hr855xg2.dts
@@ -27,7 +27,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=tty0 console=ttyS4,115200 earlyprintk";
+ bootargs = "console=tty0 console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-microsoft-olympus.dts b/src/arm/aspeed-bmc-microsoft-olympus.dts
index 7331991..3ef8358 100644
--- a/src/arm/aspeed-bmc-microsoft-olympus.dts
+++ b/src/arm/aspeed-bmc-microsoft-olympus.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/src/arm/aspeed-bmc-opp-lanyang.dts b/src/arm/aspeed-bmc-opp-lanyang.dts
index 42b37a2..c084763 100644
--- a/src/arm/aspeed-bmc-opp-lanyang.dts
+++ b/src/arm/aspeed-bmc-opp-lanyang.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-mihawk.dts b/src/arm/aspeed-bmc-opp-mihawk.dts
index 15c1f0a..a52a289 100644
--- a/src/arm/aspeed-bmc-opp-mihawk.dts
+++ b/src/arm/aspeed-bmc-opp-mihawk.dts
@@ -57,7 +57,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-mowgli.dts b/src/arm/aspeed-bmc-opp-mowgli.dts
index 8503152..7d38d12 100644
--- a/src/arm/aspeed-bmc-opp-mowgli.dts
+++ b/src/arm/aspeed-bmc-opp-mowgli.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-nicole.dts b/src/arm/aspeed-bmc-opp-nicole.dts
index 91dced7..3d4bdad 100644
--- a/src/arm/aspeed-bmc-opp-nicole.dts
+++ b/src/arm/aspeed-bmc-opp-nicole.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-palmetto.dts b/src/arm/aspeed-bmc-opp-palmetto.dts
index eb4e93a..cd660c1 100644
--- a/src/arm/aspeed-bmc-opp-palmetto.dts
+++ b/src/arm/aspeed-bmc-opp-palmetto.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/src/arm/aspeed-bmc-opp-romulus.dts b/src/arm/aspeed-bmc-opp-romulus.dts
index fd2e014..084f548 100644
--- a/src/arm/aspeed-bmc-opp-romulus.dts
+++ b/src/arm/aspeed-bmc-opp-romulus.dts
@@ -9,7 +9,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-swift.dts b/src/arm/aspeed-bmc-opp-swift.dts
index d56b5ed..4816486 100644
--- a/src/arm/aspeed-bmc-opp-swift.dts
+++ b/src/arm/aspeed-bmc-opp-swift.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-tacoma.dts b/src/arm/aspeed-bmc-opp-tacoma.dts
index c1478d2..e863ec0 100644
--- a/src/arm/aspeed-bmc-opp-tacoma.dts
+++ b/src/arm/aspeed-bmc-opp-tacoma.dts
@@ -13,7 +13,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200n8";
+ bootargs = "console=ttyS4,115200n8 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-vesnin.dts b/src/arm/aspeed-bmc-opp-vesnin.dts
index 01074b6..328ef47 100644
--- a/src/arm/aspeed-bmc-opp-vesnin.dts
+++ b/src/arm/aspeed-bmc-opp-vesnin.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/src/arm/aspeed-bmc-opp-witherspoon.dts b/src/arm/aspeed-bmc-opp-witherspoon.dts
index 85d58a6..230f358 100644
--- a/src/arm/aspeed-bmc-opp-witherspoon.dts
+++ b/src/arm/aspeed-bmc-opp-witherspoon.dts
@@ -10,7 +10,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-opp-zaius.dts b/src/arm/aspeed-bmc-opp-zaius.dts
index 4bcc820..7ae4ea0 100644
--- a/src/arm/aspeed-bmc-opp-zaius.dts
+++ b/src/arm/aspeed-bmc-opp-zaius.dts
@@ -17,7 +17,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-portwell-neptune.dts b/src/arm/aspeed-bmc-portwell-neptune.dts
index 03c1614..61bc74b 100644
--- a/src/arm/aspeed-bmc-portwell-neptune.dts
+++ b/src/arm/aspeed-bmc-portwell-neptune.dts
@@ -14,7 +14,7 @@
};
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-bmc-quanta-q71l.dts b/src/arm/aspeed-bmc-quanta-q71l.dts
index a68ff06..9605e53 100644
--- a/src/arm/aspeed-bmc-quanta-q71l.dts
+++ b/src/arm/aspeed-bmc-quanta-q71l.dts
@@ -28,7 +28,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "console=ttyS4,115200 earlyprintk";
+ bootargs = "console=ttyS4,115200 earlycon";
};
memory@40000000 {
diff --git a/src/arm/aspeed-bmc-supermicro-x11spi.dts b/src/arm/aspeed-bmc-supermicro-x11spi.dts
index bc16ad2..50f3c6a 100644
--- a/src/arm/aspeed-bmc-supermicro-x11spi.dts
+++ b/src/arm/aspeed-bmc-supermicro-x11spi.dts
@@ -11,7 +11,7 @@
chosen {
stdout-path = &uart5;
- bootargs = "earlyprintk";
+ bootargs = "earlycon";
};
memory@80000000 {
diff --git a/src/arm/aspeed-g5.dtsi b/src/arm/aspeed-g5.dtsi
index d733c1f..329eaee 100644
--- a/src/arm/aspeed-g5.dtsi
+++ b/src/arm/aspeed-g5.dtsi
@@ -264,6 +264,7 @@
reg-io-width = <4>;
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
resets = <&syscon ASPEED_RESET_CRT1>;
+ syscon = <&syscon>;
status = "disabled";
interrupts = <0x19>;
};
diff --git a/src/arm/aspeed-g6-pinctrl.dtsi b/src/arm/aspeed-g6-pinctrl.dtsi
index 7028e21..7e90d71 100644
--- a/src/arm/aspeed-g6-pinctrl.dtsi
+++ b/src/arm/aspeed-g6-pinctrl.dtsi
@@ -862,11 +862,21 @@
groups = "SGPM1";
};
+ pinctrl_sgpm2_default: sgpm2_default {
+ function = "SGPM2";
+ groups = "SGPM2";
+ };
+
pinctrl_sgps1_default: sgps1_default {
function = "SGPS1";
groups = "SGPS1";
};
+ pinctrl_sgps2_default: sgps2_default {
+ function = "SGPS2";
+ groups = "SGPS2";
+ };
+
pinctrl_sioonctrl_default: sioonctrl_default {
function = "SIOONCTRL";
groups = "SIOONCTRL";
diff --git a/src/arm/bcm-cygnus.dtsi b/src/arm/bcm-cygnus.dtsi
index 0025c88..8ecb786 100644
--- a/src/arm/bcm-cygnus.dtsi
+++ b/src/arm/bcm-cygnus.dtsi
@@ -460,7 +460,7 @@
status = "disabled";
};
- nand: nand@18046000 {
+ nand_controller: nand-controller@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>,
<0x18046f00 0x20>;
diff --git a/src/arm/bcm-hr2.dtsi b/src/arm/bcm-hr2.dtsi
index e8df458..84cda16 100644
--- a/src/arm/bcm-hr2.dtsi
+++ b/src/arm/bcm-hr2.dtsi
@@ -179,7 +179,7 @@
status = "disabled";
};
- nand: nand@26000 {
+ nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x26000 0x600>,
<0x11b408 0x600>,
diff --git a/src/arm/bcm-nsp.dtsi b/src/arm/bcm-nsp.dtsi
index b4d2cc7..748df79 100644
--- a/src/arm/bcm-nsp.dtsi
+++ b/src/arm/bcm-nsp.dtsi
@@ -269,7 +269,7 @@
dma-coherent;
};
- nand: nand@26000 {
+ nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>,
<0x11b408 0x600>,
diff --git a/src/arm/bcm2711-rpi-4-b.dts b/src/arm/bcm2711-rpi-4-b.dts
index 3b4ab94..f24bdd0 100644
--- a/src/arm/bcm2711-rpi-4-b.dts
+++ b/src/arm/bcm2711-rpi-4-b.dts
@@ -1,11 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "bcm2711.dtsi"
-#include "bcm2835-rpi.dtsi"
+#include "bcm2711-rpi.dtsi"
#include "bcm283x-rpi-usb-peripheral.dtsi"
-#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
-
/ {
compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
model = "Raspberry Pi 4 Model B";
@@ -15,25 +13,12 @@
stdout-path = "serial1:115200n8";
};
- /* Will be filled by the bootloader */
- memory@0 {
- device_type = "memory";
- reg = <0 0 0>;
- };
-
- aliases {
- emmc2bus = &emmc2bus;
- ethernet0 = &genet;
- pcie0 = &pcie0;
- blconfig = &blconfig;
- };
-
leds {
- act {
+ led-act {
gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
@@ -79,31 +64,15 @@
status = "okay";
};
-&firmware {
- firmware_clocks: clocks {
- compatible = "raspberrypi,firmware-clocks";
- #clock-cells = <1>;
- };
-
- expgpio: gpio {
- compatible = "raspberrypi,firmware-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-line-names = "BT_ON",
- "WL_ON",
- "PWR_LED_OFF",
- "GLOBAL_RESET",
- "VDD_SD_IO_SEL",
- "CAM_GPIO",
- "SD_PWR_ON",
- "";
- status = "okay";
- };
-
- reset: reset {
- compatible = "raspberrypi,firmware-reset";
- #reset-cells = <1>;
- };
+&expgpio {
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "PWR_LED_OFF",
+ "GLOBAL_RESET",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "";
};
&gpio {
@@ -180,23 +149,13 @@
};
&hdmi0 {
- clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
- clock-names = "hdmi", "bvb", "audio", "cec";
- wifi-2.4ghz-coexistence;
status = "okay";
};
&hdmi1 {
- clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
- clock-names = "hdmi", "bvb", "audio", "cec";
- wifi-2.4ghz-coexistence;
status = "okay";
};
-&hvs {
- clocks = <&firmware_clocks 4>;
-};
-
&pixelvalve0 {
status = "okay";
};
@@ -219,22 +178,6 @@
status = "okay";
};
-&rmem {
- /*
- * RPi4's co-processor will copy the board's bootloader configuration
- * into memory for the OS to consume. It'll also update this node with
- * its placement information.
- */
- blconfig: nvram@0 {
- compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x0 0x0>;
- no-map;
- status = "disabled";
- };
-};
-
/* SDHCI is used to control the SDIO for wireless */
&sdhci {
#address-cells = <1>;
@@ -309,10 +252,6 @@
status = "okay";
};
-&vchiq {
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-};
-
&vc4 {
status = "okay";
};
diff --git a/src/arm/bcm2711-rpi-400.dts b/src/arm/bcm2711-rpi-400.dts
new file mode 100644
index 0000000..f4d2fc2
--- /dev/null
+++ b/src/arm/bcm2711-rpi-400.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2711-rpi-4-b.dts"
+
+/ {
+ compatible = "raspberrypi,400", "brcm,bcm2711";
+ model = "Raspberry Pi 400";
+
+ chosen {
+ /* 8250 auxiliary UART instead of pl011 */
+ stdout-path = "serial1:115200n8";
+ };
+
+ leds {
+ /delete-node/ led-act;
+
+ led-pwr {
+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&expgpio 5 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&expgpio {
+ gpio-line-names = "BT_ON",
+ "WL_ON",
+ "",
+ "GLOBAL_RESET",
+ "VDD_SD_IO_SEL",
+ "CAM_GPIO",
+ "SD_PWR_ON",
+ "SD_OC_N";
+};
+
+&genet_mdio {
+ clock-frequency = <1950000>;
+};
+
+&pm {
+ /delete-property/ system-power-controller;
+};
diff --git a/src/arm/bcm2711-rpi.dtsi b/src/arm/bcm2711-rpi.dtsi
new file mode 100644
index 0000000..ca266c5
--- /dev/null
+++ b/src/arm/bcm2711-rpi.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm2835-rpi.dtsi"
+
+#include <dt-bindings/reset/raspberrypi,firmware-reset.h>
+
+/ {
+ /* Will be filled by the bootloader */
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0 0>;
+ };
+
+ aliases {
+ emmc2bus = &emmc2bus;
+ ethernet0 = &genet;
+ pcie0 = &pcie0;
+ blconfig = &blconfig;
+ };
+};
+
+&firmware {
+ firmware_clocks: clocks {
+ compatible = "raspberrypi,firmware-clocks";
+ #clock-cells = <1>;
+ };
+
+ expgpio: gpio {
+ compatible = "raspberrypi,firmware-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "okay";
+ };
+
+ reset: reset {
+ compatible = "raspberrypi,firmware-reset";
+ #reset-cells = <1>;
+ };
+};
+
+&hdmi0 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ wifi-2.4ghz-coexistence;
+};
+
+&hdmi1 {
+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
+ clock-names = "hdmi", "bvb", "audio", "cec";
+ wifi-2.4ghz-coexistence;
+};
+
+&hvs {
+ clocks = <&firmware_clocks 4>;
+};
+
+&rmem {
+ /*
+ * RPi4's co-processor will copy the board's bootloader configuration
+ * into memory for the OS to consume. It'll also update this node with
+ * its placement information.
+ */
+ blconfig: nvram@0 {
+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0 0x0 0x0>;
+ no-map;
+ status = "disabled";
+ };
+};
+
+&vchiq {
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/src/arm/bcm2711.dtsi b/src/arm/bcm2711.dtsi
index 720beec..b8a4096 100644
--- a/src/arm/bcm2711.dtsi
+++ b/src/arm/bcm2711.dtsi
@@ -413,7 +413,7 @@
ranges = <0x0 0x7e000000 0x0 0xfe000000 0x01800000>;
dma-ranges = <0x0 0xc0000000 0x0 0x00000000 0x40000000>;
- emmc2: emmc2@7e340000 {
+ emmc2: mmc@7e340000 {
compatible = "brcm,bcm2711-emmc2";
reg = <0x0 0x7e340000 0x100>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
@@ -1087,5 +1087,6 @@
};
&vec {
+ compatible = "brcm,bcm2711-vec";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/src/arm/bcm2835-rpi-a-plus.dts b/src/arm/bcm2835-rpi-a-plus.dts
index 6c8ce39..40b9405 100644
--- a/src/arm/bcm2835-rpi-a-plus.dts
+++ b/src/arm/bcm2835-rpi-a-plus.dts
@@ -14,11 +14,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/src/arm/bcm2835-rpi-a.dts b/src/arm/bcm2835-rpi-a.dts
index 17fdd48..11edb58 100644
--- a/src/arm/bcm2835-rpi-a.dts
+++ b/src/arm/bcm2835-rpi-a.dts
@@ -14,7 +14,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/src/arm/bcm2835-rpi-b-plus.dts b/src/arm/bcm2835-rpi-b-plus.dts
index b0355c2..1b435c6 100644
--- a/src/arm/bcm2835-rpi-b-plus.dts
+++ b/src/arm/bcm2835-rpi-b-plus.dts
@@ -15,11 +15,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/src/arm/bcm2835-rpi-b-rev2.dts b/src/arm/bcm2835-rpi-b-rev2.dts
index 33b3b5c..a23c25c 100644
--- a/src/arm/bcm2835-rpi-b-rev2.dts
+++ b/src/arm/bcm2835-rpi-b-rev2.dts
@@ -15,7 +15,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/src/arm/bcm2835-rpi-b.dts b/src/arm/bcm2835-rpi-b.dts
index 2b69957..1b63d6b 100644
--- a/src/arm/bcm2835-rpi-b.dts
+++ b/src/arm/bcm2835-rpi-b.dts
@@ -15,7 +15,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
diff --git a/src/arm/bcm2835-rpi-cm1.dtsi b/src/arm/bcm2835-rpi-cm1.dtsi
index 58059c2..e4e6b6a 100644
--- a/src/arm/bcm2835-rpi-cm1.dtsi
+++ b/src/arm/bcm2835-rpi-cm1.dtsi
@@ -5,7 +5,7 @@
/ {
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
diff --git a/src/arm/bcm2835-rpi-zero-w.dts b/src/arm/bcm2835-rpi-zero-w.dts
index f65448c..33b2b77 100644
--- a/src/arm/bcm2835-rpi-zero-w.dts
+++ b/src/arm/bcm2835-rpi-zero-w.dts
@@ -23,7 +23,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_LOW>;
};
};
diff --git a/src/arm/bcm2835-rpi-zero.dts b/src/arm/bcm2835-rpi-zero.dts
index 6dd93c6..6f9b3a9 100644
--- a/src/arm/bcm2835-rpi-zero.dts
+++ b/src/arm/bcm2835-rpi-zero.dts
@@ -18,7 +18,7 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/src/arm/bcm2835-rpi.dtsi b/src/arm/bcm2835-rpi.dtsi
index d94357b..87ddcad 100644
--- a/src/arm/bcm2835-rpi.dtsi
+++ b/src/arm/bcm2835-rpi.dtsi
@@ -4,7 +4,7 @@
leds {
compatible = "gpio-leds";
- act {
+ led-act {
label = "ACT";
default-state = "keep";
linux,default-trigger = "heartbeat";
diff --git a/src/arm/bcm2836-rpi-2-b.dts b/src/arm/bcm2836-rpi-2-b.dts
index 0455a68..d8af8ee 100644
--- a/src/arm/bcm2836-rpi-2-b.dts
+++ b/src/arm/bcm2836-rpi-2-b.dts
@@ -15,11 +15,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 47 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&gpio 35 GPIO_ACTIVE_HIGH>;
default-state = "keep";
diff --git a/src/arm/bcm2837-rpi-3-a-plus.dts b/src/arm/bcm2837-rpi-3-a-plus.dts
index 28be033..77099a7 100644
--- a/src/arm/bcm2837-rpi-3-a-plus.dts
+++ b/src/arm/bcm2837-rpi-3-a-plus.dts
@@ -19,11 +19,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
diff --git a/src/arm/bcm2837-rpi-3-b-plus.dts b/src/arm/bcm2837-rpi-3-b-plus.dts
index 3734314..6101026 100644
--- a/src/arm/bcm2837-rpi-3-b-plus.dts
+++ b/src/arm/bcm2837-rpi-3-b-plus.dts
@@ -20,11 +20,11 @@
};
leds {
- act {
+ led-act {
gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
};
- pwr {
+ led-pwr {
label = "PWR";
gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
default-state = "keep";
diff --git a/src/arm/bcm2837-rpi-3-b.dts b/src/arm/bcm2837-rpi-3-b.dts
index 054ecaa..dd4a486 100644
--- a/src/arm/bcm2837-rpi-3-b.dts
+++ b/src/arm/bcm2837-rpi-3-b.dts
@@ -20,7 +20,7 @@
};
leds {
- act {
+ led-act {
gpios = <&expgpio 2 GPIO_ACTIVE_HIGH>;
};
};
diff --git a/src/arm/bcm2837-rpi-cm3.dtsi b/src/arm/bcm2837-rpi-cm3.dtsi
index 925cb37..828a205 100644
--- a/src/arm/bcm2837-rpi-cm3.dtsi
+++ b/src/arm/bcm2837-rpi-cm3.dtsi
@@ -14,7 +14,7 @@
* Since there is no upstream GPIO driver yet,
* remove the incomplete node.
*/
- /delete-node/ act;
+ /delete-node/ led-act;
};
reg_3v3: fixed-regulator {
diff --git a/src/arm/bcm283x-rpi-usb-otg.dtsi b/src/arm/bcm283x-rpi-usb-otg.dtsi
index 20322de..e2fd961 100644
--- a/src/arm/bcm283x-rpi-usb-otg.dtsi
+++ b/src/arm/bcm283x-rpi-usb-otg.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
&usb {
dr_mode = "otg";
- g-rx-fifo-size = <558>;
+ g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
/*
* According to dwc2 the sum of all device EP
diff --git a/src/arm/bcm283x-rpi-usb-peripheral.dtsi b/src/arm/bcm283x-rpi-usb-peripheral.dtsi
index 1409d1b..0ff0e9e 100644
--- a/src/arm/bcm283x-rpi-usb-peripheral.dtsi
+++ b/src/arm/bcm283x-rpi-usb-peripheral.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
&usb {
dr_mode = "peripheral";
- g-rx-fifo-size = <558>;
+ g-rx-fifo-size = <256>;
g-np-tx-fifo-size = <32>;
g-tx-fifo-size = <256 256 512 512 512 768 768>;
};
diff --git a/src/arm/bcm283x.dtsi b/src/arm/bcm283x.dtsi
index b83a864..0f3be55 100644
--- a/src/arm/bcm283x.dtsi
+++ b/src/arm/bcm283x.dtsi
@@ -420,7 +420,7 @@
status = "disabled";
};
- sdhci: sdhci@7e300000 {
+ sdhci: mmc@7e300000 {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
diff --git a/src/arm/bcm4708-luxul-xwc-1000.dts b/src/arm/bcm4708-luxul-xwc-1000.dts
index 8636600..c81944c 100644
--- a/src/arm/bcm4708-luxul-xwc-1000.dts
+++ b/src/arm/bcm4708-luxul-xwc-1000.dts
@@ -24,8 +24,8 @@
reg = <0x00000000 0x08000000>;
};
- nand: nand@18028000 {
- nandcs@0 {
+ nand_controller: nand-controller@18028000 {
+ nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
diff --git a/src/arm/bcm47094-dlink-dir-885l.dts b/src/arm/bcm47094-dlink-dir-885l.dts
index e635a15..a6e2aeb 100644
--- a/src/arm/bcm47094-dlink-dir-885l.dts
+++ b/src/arm/bcm47094-dlink-dir-885l.dts
@@ -25,8 +25,8 @@
<0x88000000 0x08000000>;
};
- nand: nand@18028000 {
- nandcs@0 {
+ nand_controller: nand-controller@18028000 {
+ nand@0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
diff --git a/src/arm/bcm47094.dtsi b/src/arm/bcm47094.dtsi
index 2a8f731..6282363 100644
--- a/src/arm/bcm47094.dtsi
+++ b/src/arm/bcm47094.dtsi
@@ -11,7 +11,7 @@
&pinctrl {
compatible = "brcm,bcm4709-pinmux";
- pinmux_mdio: mdio {
+ pinmux_mdio: mdio-pins {
groups = "mdio_grp";
function = "mdio";
};
diff --git a/src/arm/bcm5301x-nand-cs0.dtsi b/src/arm/bcm5301x-nand-cs0.dtsi
index 925a7c9..be9a00f 100644
--- a/src/arm/bcm5301x-nand-cs0.dtsi
+++ b/src/arm/bcm5301x-nand-cs0.dtsi
@@ -6,8 +6,8 @@
*/
/ {
- nand@18028000 {
- nandcs: nandcs@0 {
+ nand-controller@18028000 {
+ nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
#address-cells = <1>;
diff --git a/src/arm/bcm5301x.dtsi b/src/arm/bcm5301x.dtsi
index 7db72a2..f920892 100644
--- a/src/arm/bcm5301x.dtsi
+++ b/src/arm/bcm5301x.dtsi
@@ -458,18 +458,18 @@
function = "spi";
};
- pinmux_i2c: i2c {
+ pinmux_i2c: i2c-pins {
groups = "i2c_grp";
function = "i2c";
};
- pinmux_pwm: pwm {
+ pinmux_pwm: pwm-pins {
groups = "pwm0_grp", "pwm1_grp",
"pwm2_grp", "pwm3_grp";
function = "pwm";
};
- pinmux_uart1: uart1 {
+ pinmux_uart1: uart1-pins {
groups = "uart1_grp";
function = "uart1";
};
@@ -501,7 +501,7 @@
reg = <0x18004000 0x14>;
};
- nand: nand@18028000 {
+ nand_controller: nand-controller@18028000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
reg-names = "nand", "iproc-idm", "iproc-ext";
@@ -520,27 +520,27 @@
<0x1811b408 0x004>,
<0x180293a0 0x01c>;
reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "spi_lr_fullness_reached",
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
"spi_lr_session_aborted",
"spi_lr_impatient",
"spi_lr_session_done",
- "spi_lr_overhead",
- "mspi_done",
- "mspi_halted";
+ "spi_lr_overread";
clocks = <&iprocmed>;
clock-names = "iprocmed";
num-cs = <2>;
#address-cells = <1>;
#size-cells = <0>;
- spi_nor: spi-nor@0 {
+ spi_nor: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <20000000>;
diff --git a/src/arm/bcm63138.dtsi b/src/arm/bcm63138.dtsi
index 9c0325c..cca49a2 100644
--- a/src/arm/bcm63138.dtsi
+++ b/src/arm/bcm63138.dtsi
@@ -203,7 +203,7 @@
status = "disabled";
};
- nand: nand@2000 {
+ nand_controller: nand-controller@2000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
diff --git a/src/arm/bcm7445-bcm97445svmb.dts b/src/arm/bcm7445-bcm97445svmb.dts
index 8313b7c..f92d2cf 100644
--- a/src/arm/bcm7445-bcm97445svmb.dts
+++ b/src/arm/bcm7445-bcm97445svmb.dts
@@ -14,10 +14,10 @@
};
};
-&nand {
+&nand_controller {
status = "okay";
- nandcs@1 {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <1>;
nand-ecc-step-size = <512>;
diff --git a/src/arm/bcm7445.dtsi b/src/arm/bcm7445.dtsi
index 58f67c9..5ac2042 100644
--- a/src/arm/bcm7445.dtsi
+++ b/src/arm/bcm7445.dtsi
@@ -148,7 +148,7 @@
reg-names = "aon-ctrl", "aon-sram";
};
- nand: nand@3e2800 {
+ nand_controller: nand-controller@3e2800 {
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/src/arm/bcm911360_entphn.dts b/src/arm/bcm911360_entphn.dts
index b2d323f..a76c74b 100644
--- a/src/arm/bcm911360_entphn.dts
+++ b/src/arm/bcm911360_entphn.dts
@@ -82,8 +82,8 @@
status = "okay";
};
-&nand {
- nandcs@1 {
+&nand_controller {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm953012k.dts b/src/arm/bcm953012k.dts
index 046c59f..de40bd5 100644
--- a/src/arm/bcm953012k.dts
+++ b/src/arm/bcm953012k.dts
@@ -49,8 +49,8 @@
};
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958300k.dts b/src/arm/bcm958300k.dts
index b4a1392..dda3e11 100644
--- a/src/arm/bcm958300k.dts
+++ b/src/arm/bcm958300k.dts
@@ -60,8 +60,8 @@
status = "okay";
};
-&nand {
- nandcs@1 {
+&nand_controller {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958305k.dts b/src/arm/bcm958305k.dts
index 3378683..ea3c6b8 100644
--- a/src/arm/bcm958305k.dts
+++ b/src/arm/bcm958305k.dts
@@ -68,8 +68,8 @@
status = "okay";
};
-&nand {
- nandcs@1 {
+&nand_controller {
+ nand@1 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958522er.dts b/src/arm/bcm958522er.dts
index 5443fc0..1f73885 100644
--- a/src/arm/bcm958522er.dts
+++ b/src/arm/bcm958522er.dts
@@ -74,8 +74,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958525er.dts b/src/arm/bcm958525er.dts
index e1e3c26..b6b9ca8 100644
--- a/src/arm/bcm958525er.dts
+++ b/src/arm/bcm958525er.dts
@@ -74,8 +74,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958525xmc.dts b/src/arm/bcm958525xmc.dts
index f161ba2..ecf426f 100644
--- a/src/arm/bcm958525xmc.dts
+++ b/src/arm/bcm958525xmc.dts
@@ -90,8 +90,8 @@
};
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958622hr.dts b/src/arm/bcm958622hr.dts
index 83cb877..8ca18da 100644
--- a/src/arm/bcm958622hr.dts
+++ b/src/arm/bcm958622hr.dts
@@ -78,8 +78,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958623hr.dts b/src/arm/bcm958623hr.dts
index 4e106ce..9747378 100644
--- a/src/arm/bcm958623hr.dts
+++ b/src/arm/bcm958623hr.dts
@@ -78,8 +78,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958625hr.dts b/src/arm/bcm958625hr.dts
index cda6cc2..0f92b77 100644
--- a/src/arm/bcm958625hr.dts
+++ b/src/arm/bcm958625hr.dts
@@ -89,8 +89,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm958625k.dts b/src/arm/bcm958625k.dts
index ffbff00..9e984ca 100644
--- a/src/arm/bcm958625k.dts
+++ b/src/arm/bcm958625k.dts
@@ -68,8 +68,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/bcm963138dvt.dts b/src/arm/bcm963138dvt.dts
index 5b17727..df5c8ab 100644
--- a/src/arm/bcm963138dvt.dts
+++ b/src/arm/bcm963138dvt.dts
@@ -31,10 +31,10 @@
status = "okay";
};
-&nand {
+&nand_controller {
status = "okay";
- nandcs@0 {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
diff --git a/src/arm/bcm988312hr.dts b/src/arm/bcm988312hr.dts
index 3fd39c4..5475dab 100644
--- a/src/arm/bcm988312hr.dts
+++ b/src/arm/bcm988312hr.dts
@@ -74,8 +74,8 @@
status = "okay";
};
-&nand {
- nandcs@0 {
+&nand_controller {
+ nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
nand-on-flash-bbt;
diff --git a/src/arm/da850.dtsi b/src/arm/da850.dtsi
index 7cf31b6..c3942b4 100644
--- a/src/arm/da850.dtsi
+++ b/src/arm/da850.dtsi
@@ -574,8 +574,7 @@
status = "disabled";
};
ehrpwm0: pwm@300000 {
- compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
clocks = <&psc1 17>, <&ehrpwm_tbclk>;
@@ -584,8 +583,7 @@
status = "disabled";
};
ehrpwm1: pwm@302000 {
- compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
- "ti,am33xx-ehrpwm";
+ compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm";
#pwm-cells = <3>;
reg = <0x302000 0x2000>;
clocks = <&psc1 17>, <&ehrpwm_tbclk>;
@@ -593,9 +591,8 @@
power-domains = <&psc1 17>;
status = "disabled";
};
- ecap0: ecap@306000 {
- compatible = "ti,da850-ecap", "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap0: pwm@306000 {
+ compatible = "ti,da850-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x306000 0x80>;
clocks = <&psc1 20>;
@@ -603,9 +600,8 @@
power-domains = <&psc1 20>;
status = "disabled";
};
- ecap1: ecap@307000 {
- compatible = "ti,da850-ecap", "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap1: pwm@307000 {
+ compatible = "ti,da850-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x307000 0x80>;
clocks = <&psc1 20>;
@@ -613,9 +609,8 @@
power-domains = <&psc1 20>;
status = "disabled";
};
- ecap2: ecap@308000 {
- compatible = "ti,da850-ecap", "ti,am3352-ecap",
- "ti,am33xx-ecap";
+ ecap2: pwm@308000 {
+ compatible = "ti,da850-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x308000 0x80>;
clocks = <&psc1 20>;
diff --git a/src/arm/dm816x.dtsi b/src/arm/dm816x.dtsi
index 3551a64..a9e7274 100644
--- a/src/arm/dm816x.dtsi
+++ b/src/arm/dm816x.dtsi
@@ -314,8 +314,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <70>;
- dmas = <&edma 58 0 &edma 59 0>;
- dma-names = "tx", "rx";
};
i2c2: i2c@4802a000 {
@@ -325,8 +323,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <71>;
- dmas = <&edma 60 0 &edma 61 0>;
- dma-names = "tx", "rx";
};
intc: interrupt-controller@48200000 {
@@ -351,7 +347,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <12>;
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <0 0 0>;
};
diff --git a/src/arm/dra7-evm.dts b/src/arm/dra7-evm.dts
index 38530db..87deb6a 100644
--- a/src/arm/dra7-evm.dts
+++ b/src/arm/dra7-evm.dts
@@ -319,7 +319,7 @@
};
pcf_lcd: gpio@20 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
@@ -330,7 +330,7 @@
};
pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
@@ -362,11 +362,11 @@
clock-frequency = <400000>;
pcf_hdmi: gpio@26 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
- p1 {
+ hdmi-audio-hog {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
diff --git a/src/arm/dra7-ipu-dsp-common.dtsi b/src/arm/dra7-ipu-dsp-common.dtsi
index a25749a..a5bdc64 100644
--- a/src/arm/dra7-ipu-dsp-common.dtsi
+++ b/src/arm/dra7-ipu-dsp-common.dtsi
@@ -5,17 +5,17 @@
&mailbox5 {
status = "okay";
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
status = "okay";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
status = "okay";
};
};
&mailbox6 {
status = "okay";
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
status = "okay";
};
};
diff --git a/src/arm/dra7-l4.dtsi b/src/arm/dra7-l4.dtsi
index 149144c..956a26d 100644
--- a/src/arm/dra7-l4.dtsi
+++ b/src/arm/dra7-l4.dtsi
@@ -1159,7 +1159,7 @@
ranges = <0x0 0x20000 0x1000>;
uart3: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1343,7 +1343,7 @@
};
};
- target-module@55000 { /* 0x48055000, ap 13 0e.0 */
+ gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55000 0x4>,
<0x55010 0x4>,
@@ -1376,7 +1376,7 @@
};
};
- target-module@57000 { /* 0x48057000, ap 15 06.0 */
+ gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x57000 0x4>,
<0x57010 0x4>,
@@ -1562,7 +1562,7 @@
ranges = <0x0 0x66000 0x1000>;
uart5: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1594,7 +1594,7 @@
ranges = <0x0 0x68000 0x1000>;
uart6: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1626,7 +1626,7 @@
ranges = <0x0 0x6a000 0x1000>;
uart1: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1658,7 +1658,7 @@
ranges = <0x0 0x6c000 0x1000>;
uart2: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -1690,7 +1690,7 @@
ranges = <0x0 0x6e000 0x1000>;
uart4: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2424,7 +2424,7 @@
ranges = <0x0 0x20000 0x1000>;
uart7: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2454,7 +2454,7 @@
ranges = <0x0 0x22000 0x1000>;
uart8: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2484,7 +2484,7 @@
ranges = <0x0 0x24000 0x1000>;
uart9: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
@@ -2561,7 +2561,7 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap0: ecap@100 {
+ ecap0: pwm@100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
@@ -2607,7 +2607,7 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap1: ecap@100 {
+ ecap1: pwm@100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
@@ -2653,7 +2653,7 @@
status = "disabled";
ranges = <0 0 0x1000>;
- ecap2: ecap@100 {
+ ecap2: pwm@100 {
compatible = "ti,dra746-ecap",
"ti,am3352-ecap";
#pwm-cells = <3>;
@@ -4129,28 +4129,6 @@
};
};
- usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x140000 0x4>,
- <0x140010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x140000 0x20000>;
- };
-
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x170010 0x4>;
@@ -4530,7 +4508,7 @@
ranges = <0x0 0xb000 0x1000>;
uart10: serial@0 {
- compatible = "ti,dra742-uart", "ti,omap4-uart";
+ compatible = "ti,dra742-uart";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
diff --git a/src/arm/dra71-evm.dts b/src/arm/dra71-evm.dts
index 6d2cca6..a643644 100644
--- a/src/arm/dra71-evm.dts
+++ b/src/arm/dra71-evm.dts
@@ -187,7 +187,7 @@
};
&pcf_hdmi {
- p0 {
+ hdmi-i2c-disable-hog {
/*
* PM_OEn to High: Disable routing I2C3 to PM_I2C
* With this PM_SEL(p3) should not matter
diff --git a/src/arm/dra71x.dtsi b/src/arm/dra71x.dtsi
index cad0e4a..9c270d8 100644
--- a/src/arm/dra71x.dtsi
+++ b/src/arm/dra71x.dtsi
@@ -11,7 +11,3 @@
&rtctarget {
status = "disabled";
};
-
-&usb4_tm {
- status = "disabled";
-};
diff --git a/src/arm/dra72-evm-common.dtsi b/src/arm/dra72-evm-common.dtsi
index b65b2dd..f128252 100644
--- a/src/arm/dra72-evm-common.dtsi
+++ b/src/arm/dra72-evm-common.dtsi
@@ -226,7 +226,7 @@
};
pcf_gpio_21: gpio@21 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x21>;
lines-initial-states = <0x1408>;
gpio-controller;
@@ -256,7 +256,7 @@
clock-frequency = <400000>;
pcf_hdmi: pcf8575@26 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
@@ -268,7 +268,7 @@
*/
lines-initial-states = <0x0f2b>;
- p1 {
+ hdmi-audio-hog {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
diff --git a/src/arm/dra72x.dtsi b/src/arm/dra72x.dtsi
index d403acc..9061726 100644
--- a/src/arm/dra72x.dtsi
+++ b/src/arm/dra72x.dtsi
@@ -77,12 +77,12 @@
};
&mailbox5 {
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -90,7 +90,7 @@
};
&mailbox6 {
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
@@ -108,7 +108,3 @@
&pcie2_rc {
compatible = "ti,dra726-pcie-rc", "ti,dra7-pcie";
};
-
-&usb4_tm {
- status = "disabled";
-};
diff --git a/src/arm/dra74-ipu-dsp-common.dtsi b/src/arm/dra74-ipu-dsp-common.dtsi
index b1147a4..3256631 100644
--- a/src/arm/dra74-ipu-dsp-common.dtsi
+++ b/src/arm/dra74-ipu-dsp-common.dtsi
@@ -6,7 +6,7 @@
#include "dra7-ipu-dsp-common.dtsi"
&mailbox6 {
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
status = "okay";
};
};
diff --git a/src/arm/dra74x.dtsi b/src/arm/dra74x.dtsi
index e1850d6..cfb39dd 100644
--- a/src/arm/dra74x.dtsi
+++ b/src/arm/dra74x.dtsi
@@ -49,49 +49,6 @@
reg = <0x41500000 0x100>;
};
- target-module@48940000 {
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x48940000 0x4>,
- <0x48940010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x48940000 0x20000>;
-
- omap_dwc3_4: omap_dwc3_4@0 {
- compatible = "ti,dwc3";
- reg = <0 0x10000>;
- interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- utmi-mode = <2>;
- ranges;
- status = "disabled";
- usb4: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x17000>;
- interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- maximum-speed = "high-speed";
- dr_mode = "otg";
- };
- };
- };
target-module@41501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
@@ -188,12 +145,12 @@
};
&mailbox5 {
- mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
+ mbox_ipu1_ipc3x: mbox-ipu1-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
+ mbox_dsp1_ipc3x: mbox-dsp1-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -201,12 +158,12 @@
};
&mailbox6 {
- mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
+ mbox_ipu2_ipc3x: mbox-ipu2-ipc3x {
ti,mbox-tx = <6 2 2>;
ti,mbox-rx = <4 2 2>;
status = "disabled";
};
- mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
+ mbox_dsp2_ipc3x: mbox-dsp2-ipc3x {
ti,mbox-tx = <5 2 2>;
ti,mbox-rx = <1 2 2>;
status = "disabled";
@@ -224,3 +181,52 @@
&pcie2_rc {
compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
};
+
+&l4_per3 {
+ segment@0 {
+ usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
+ compatible = "ti,sysc-omap4", "ti,sysc";
+ reg = <0x140000 0x4>,
+ <0x140010 0x4>;
+ reg-names = "rev", "sysc";
+ ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>,
+ <SYSC_IDLE_SMART_WKUP>;
+ /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
+ clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x140000 0x20000>;
+
+ omap_dwc3_4: omap_dwc3_4@0 {
+ compatible = "ti,dwc3";
+ reg = <0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ utmi-mode = <2>;
+ ranges;
+ status = "disabled";
+ usb4: usb@10000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000 0x17000>;
+ interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
+ maximum-speed = "high-speed";
+ dr_mode = "otg";
+ };
+ };
+ };
+ };
+};
diff --git a/src/arm/dra76-evm.dts b/src/arm/dra76-evm.dts
index 9bd01ae..e2b7fcb 100644
--- a/src/arm/dra76-evm.dts
+++ b/src/arm/dra76-evm.dts
@@ -158,12 +158,6 @@
regulator-max-microvolt = <1800000>;
};
- clk_ov5640_fixed: clock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- };
-
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
@@ -355,7 +349,7 @@
};
pcf_lcd: pcf8757@20 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
@@ -366,7 +360,7 @@
};
pcf_gpio_21: pcf8757@21 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
@@ -377,11 +371,11 @@
};
pcf_hdmi: pcf8575@26 {
- compatible = "ti,pcf8575", "nxp,pcf8575";
+ compatible = "nxp,pcf8575";
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
- p1 {
+ hdmi-audio-hog {
/* vin6_sel_s0: high: VIN6, low: audio */
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
@@ -406,27 +400,6 @@
};
};
-&i2c5 {
- status = "okay";
- clock-frequency = <400000>;
-
- ov5640@3c {
- compatible = "ovti,ov5640";
- reg = <0x3c>;
-
- clocks = <&clk_ov5640_fixed>;
- clock-names = "xclk";
-
- port {
- csi2_cam0: endpoint {
- remote-endpoint = <&csi2_phy0>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
- };
- };
-};
-
&cpu0 {
vdd-supply = <&buck10_reg>;
};
@@ -573,14 +546,6 @@
};
};
-&csi2_0 {
- csi2_phy0: endpoint {
- remote-endpoint = <&csi2_cam0>;
- clock-lanes = <0>;
- data-lanes = <1 2>;
- };
-};
-
&ipu2 {
status = "okay";
memory-region = <&ipu2_cma_pool>;
diff --git a/src/arm/exynos3250-rinato.dts b/src/arm/exynos3250-rinato.dts
index c52b9cf..f6ba5e4 100644
--- a/src/arm/exynos3250-rinato.dts
+++ b/src/arm/exynos3250-rinato.dts
@@ -653,7 +653,7 @@
mmc-pwrseq = <&wlan_pwrseq>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4334-fmac";
+ compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx1>;
diff --git a/src/arm/exynos4210-i9100.dts b/src/arm/exynos4210-i9100.dts
index 525ff3d..5592217 100644
--- a/src/arm/exynos4210-i9100.dts
+++ b/src/arm/exynos4210-i9100.dts
@@ -314,7 +314,8 @@
};
&fimc_1 {
- status = "okay";
+ /* Back camera not implemented */
+ status = "disabled";
assigned-clocks = <&clock CLK_MOUT_FIMC1>, <&clock CLK_SCLK_FIMC1>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
@@ -330,7 +331,8 @@
};
&fimc_3 {
- status = "okay";
+ /* Back camera not implemented */
+ status = "disabled";
assigned-clocks = <&clock CLK_MOUT_FIMC3>, <&clock CLK_SCLK_FIMC3>;
assigned-clock-parents = <&clock CLK_SCLK_MPLL>;
@@ -806,7 +808,7 @@
pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4330-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx2>;
diff --git a/src/arm/exynos4210-trats.dts b/src/arm/exynos4210-trats.dts
index d2406c9..3eb8df3 100644
--- a/src/arm/exynos4210-trats.dts
+++ b/src/arm/exynos4210-trats.dts
@@ -521,7 +521,7 @@
pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4330-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx2>;
diff --git a/src/arm/exynos4210-universal_c210.dts b/src/arm/exynos4210-universal_c210.dts
index dd44ad2..f052853 100644
--- a/src/arm/exynos4210-universal_c210.dts
+++ b/src/arm/exynos4210-universal_c210.dts
@@ -614,7 +614,7 @@
pinctrl-0 = <&sd3_clk>, <&sd3_cmd>, <&sd3_bus4>;
brcmf: wifi@1 {
- compatible = "brcm,bcm4330-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpx2>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm/exynos4412-itop-scp-core.dtsi b/src/arm/exynos4412-itop-scp-core.dtsi
index 4583d34..b3726d4 100644
--- a/src/arm/exynos4412-itop-scp-core.dtsi
+++ b/src/arm/exynos4412-itop-scp-core.dtsi
@@ -163,6 +163,7 @@
<1025000>, <950000>,
<918750>, <900000>,
<875000>, <831250>;
+ wakeup-source;
regulators {
ldo1_reg: LDO1 {
diff --git a/src/arm/exynos4412-midas.dtsi b/src/arm/exynos4412-midas.dtsi
index fc77c1b..968c794 100644
--- a/src/arm/exynos4412-midas.dtsi
+++ b/src/arm/exynos4412-midas.dtsi
@@ -668,6 +668,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&max77686_irq>;
pinctrl-names = "default";
+ wakeup-source;
reg = <0x09>;
#clock-cells = <1>;
diff --git a/src/arm/exynos4412-n710x.dts b/src/arm/exynos4412-n710x.dts
index c49dbb7..2c79214 100644
--- a/src/arm/exynos4412-n710x.dts
+++ b/src/arm/exynos4412-n710x.dts
@@ -50,8 +50,8 @@
reg = <0x48>;
interrupt-parent = <&gpm2>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
- x-size = <720>;
- y-size = <1280>;
+ touchscreen-size-x = <720>;
+ touchscreen-size-y = <1280>;
avdd-supply = <&ldo23_reg>;
vdd-supply = <&ldo24_reg>;
};
diff --git a/src/arm/exynos4412-odroid-common.dtsi b/src/arm/exynos4412-odroid-common.dtsi
index 5bd0586..5b1d459 100644
--- a/src/arm/exynos4412-odroid-common.dtsi
+++ b/src/arm/exynos4412-odroid-common.dtsi
@@ -282,6 +282,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&max77686_irq>;
+ wakeup-source;
reg = <0x09>;
#clock-cells = <1>;
diff --git a/src/arm/exynos4412-origen.dts b/src/arm/exynos4412-origen.dts
index e1f6de5..5479ef0 100644
--- a/src/arm/exynos4412-origen.dts
+++ b/src/arm/exynos4412-origen.dts
@@ -144,6 +144,7 @@
<1200000>, <1200000>,
<1200000>, <1200000>,
<1200000>, <1200000>;
+ wakeup-source;
s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
diff --git a/src/arm/exynos4412-p4note.dtsi b/src/arm/exynos4412-p4note.dtsi
index 9e75089..22c3086 100644
--- a/src/arm/exynos4412-p4note.dtsi
+++ b/src/arm/exynos4412-p4note.dtsi
@@ -325,6 +325,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&max77686_irq>;
pinctrl-names = "default";
+ wakeup-source;
reg = <0x09>;
#clock-cells = <1>;
diff --git a/src/arm/exynos5250-arndale.dts b/src/arm/exynos5250-arndale.dts
index a161f62..a771542 100644
--- a/src/arm/exynos5250-arndale.dts
+++ b/src/arm/exynos5250-arndale.dts
@@ -218,6 +218,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&s5m8767_irq>;
+ wakeup-source;
vinb1-supply = <&main_dc_reg>;
vinb2-supply = <&main_dc_reg>;
diff --git a/src/arm/exynos5410-odroidxu.dts b/src/arm/exynos5410-odroidxu.dts
index 949c072..884fef5 100644
--- a/src/arm/exynos5410-odroidxu.dts
+++ b/src/arm/exynos5410-odroidxu.dts
@@ -190,6 +190,7 @@
pinctrl-names = "default";
pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>,
<&pmic_dvs_3>;
+ wakeup-source;
#clock-cells = <1>;
inl1-supply = <&buck5_reg>;
diff --git a/src/arm/exynos5420-arndale-octa.dts b/src/arm/exynos5420-arndale-octa.dts
index 1aad485..dfc7f14 100644
--- a/src/arm/exynos5420-arndale-octa.dts
+++ b/src/arm/exynos5420-arndale-octa.dts
@@ -352,6 +352,7 @@
interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&s2mps11_irq>;
+ wakeup-source;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
diff --git a/src/arm/exynos5420-smdk5420.dts b/src/arm/exynos5420-smdk5420.dts
index d506da9..a4f0e3f 100644
--- a/src/arm/exynos5420-smdk5420.dts
+++ b/src/arm/exynos5420-smdk5420.dts
@@ -132,6 +132,7 @@
pmic@66 {
compatible = "samsung,s2mps11-pmic";
reg = <0x66>;
+ wakeup-source;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
diff --git a/src/arm/exynos5422-odroid-core.dtsi b/src/arm/exynos5422-odroid-core.dtsi
index 6d690b1..e7958db 100644
--- a/src/arm/exynos5422-odroid-core.dtsi
+++ b/src/arm/exynos5422-odroid-core.dtsi
@@ -512,6 +512,7 @@
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&s2mps11_irq>;
+ wakeup-source;
s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
diff --git a/src/arm/exynos5422-odroidhc1.dts b/src/arm/exynos5422-odroidhc1.dts
index 20c222b..d91f7fa 100644
--- a/src/arm/exynos5422-odroidhc1.dts
+++ b/src/arm/exynos5422-odroidhc1.dts
@@ -22,7 +22,7 @@
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
- max_brightness = <255>;
+ max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
diff --git a/src/arm/exynos5422-odroidxu4.dts b/src/arm/exynos5422-odroidxu4.dts
index ede7822..1c24f9b 100644
--- a/src/arm/exynos5422-odroidxu4.dts
+++ b/src/arm/exynos5422-odroidxu4.dts
@@ -24,7 +24,7 @@
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
- max_brightness = <255>;
+ max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
diff --git a/src/arm/exynos54xx-odroidxu-leds.dtsi b/src/arm/exynos54xx-odroidxu-leds.dtsi
index 2fc3e86..982752e 100644
--- a/src/arm/exynos54xx-odroidxu-leds.dtsi
+++ b/src/arm/exynos54xx-odroidxu-leds.dtsi
@@ -22,7 +22,7 @@
* Green LED is much brighter than the others
* so limit its max brightness
*/
- max_brightness = <127>;
+ max-brightness = <127>;
linux,default-trigger = "mmc0";
};
@@ -30,7 +30,7 @@
label = "blue:heartbeat";
pwms = <&pwm 2 2000000 0>;
pwm-names = "pwm2";
- max_brightness = <255>;
+ max-brightness = <255>;
linux,default-trigger = "heartbeat";
};
};
diff --git a/src/arm/gemini-dlink-dir-685.dts b/src/arm/gemini-dlink-dir-685.dts
index cc39289..c79a2a0 100644
--- a/src/arm/gemini-dlink-dir-685.dts
+++ b/src/arm/gemini-dlink-dir-685.dts
@@ -61,9 +61,9 @@
#size-cells = <0>;
/* Collides with IDE pins, that's cool (we do not use them) */
- gpio-sck = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
@@ -169,7 +169,7 @@
* The touchpad input is connected to a GPIO bit-banged
* I2C bus.
*/
- gpio-i2c {
+ i2c {
compatible = "i2c-gpio";
/* Collides with ICE */
sda-gpios = <&gpio0 5 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
@@ -492,8 +492,7 @@
display-controller@6a000000 {
status = "okay";
- port@0 {
- reg = <0>;
+ port {
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
diff --git a/src/arm/gemini-dlink-dns-313.dts b/src/arm/gemini-dlink-dns-313.dts
index c6f3d90..eba1c94 100644
--- a/src/arm/gemini-dlink-dns-313.dts
+++ b/src/arm/gemini-dlink-dns-313.dts
@@ -82,7 +82,7 @@
/* Global Mixed-Mode Technology G751 mounted on GPIO I2C */
- gpio-i2c {
+ i2c {
compatible = "i2c-gpio";
sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
@@ -140,7 +140,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
/* Uses MDC and MDIO */
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
diff --git a/src/arm/gemini-nas4220b.dts b/src/arm/gemini-nas4220b.dts
index 43c45f7..13112a8 100644
--- a/src/arm/gemini-nas4220b.dts
+++ b/src/arm/gemini-nas4220b.dts
@@ -62,7 +62,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
diff --git a/src/arm/gemini-rut1xx.dts b/src/arm/gemini-rut1xx.dts
index 9611ddf..0ebda4e 100644
--- a/src/arm/gemini-rut1xx.dts
+++ b/src/arm/gemini-rut1xx.dts
@@ -56,7 +56,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
@@ -125,18 +125,6 @@
};
};
- ethernet@60000000 {
- status = "okay";
-
- ethernet-port@0 {
- phy-mode = "rgmii";
- phy-handle = <&phy0>;
- };
- ethernet-port@1 {
- /* Not used in this platform */
- };
- };
-
usb@68000000 {
status = "okay";
};
diff --git a/src/arm/gemini-sl93512r.dts b/src/arm/gemini-sl93512r.dts
index a0916d3..c78e55f 100644
--- a/src/arm/gemini-sl93512r.dts
+++ b/src/arm/gemini-sl93512r.dts
@@ -87,9 +87,9 @@
#address-cells = <1>;
#size-cells = <0>;
/* Check pin collisions */
- gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
diff --git a/src/arm/gemini-sq201.dts b/src/arm/gemini-sq201.dts
index 0c6e6d3..1b64cc8 100644
--- a/src/arm/gemini-sq201.dts
+++ b/src/arm/gemini-sq201.dts
@@ -72,9 +72,9 @@
#address-cells = <1>;
#size-cells = <0>;
/* Check pin collisions */
- gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- gpio-miso = <&gpio1 30 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+ sck-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ miso-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+ mosi-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
diff --git a/src/arm/gemini-wbd111.dts b/src/arm/gemini-wbd111.dts
index 3a2761d..5602ba8 100644
--- a/src/arm/gemini-wbd111.dts
+++ b/src/arm/gemini-wbd111.dts
@@ -68,7 +68,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
diff --git a/src/arm/gemini-wbd222.dts b/src/arm/gemini-wbd222.dts
index 52b4dbc..a4a260c 100644
--- a/src/arm/gemini-wbd222.dts
+++ b/src/arm/gemini-wbd222.dts
@@ -67,7 +67,7 @@
};
};
- mdio0: ethernet-phy {
+ mdio0: mdio {
compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */
diff --git a/src/arm/gemini.dtsi b/src/arm/gemini.dtsi
index 065ed10..cc053af 100644
--- a/src/arm/gemini.dtsi
+++ b/src/arm/gemini.dtsi
@@ -191,7 +191,7 @@
};
rtc@45000000 {
- compatible = "cortina,gemini-rtc";
+ compatible = "cortina,gemini-rtc", "faraday,ftrtc010";
reg = <0x45000000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_RTC>;
@@ -286,6 +286,7 @@
clock-names = "PCLK", "PCICLK";
pinctrl-names = "default";
pinctrl-0 = <&pci_default_pins>;
+ device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -356,6 +357,14 @@
};
};
+ crypto: crypto@62000000 {
+ compatible = "cortina,sl3516-crypto";
+ reg = <0x62000000 0x10000>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ resets = <&syscon GEMINI_RESET_SECURITY>;
+ clocks = <&syscon GEMINI_CLK_GATE_SECURITY>;
+ };
+
ide@63000000 {
compatible = "cortina,gemini-pata", "faraday,ftide010";
reg = <0x63000000 0x1000>;
@@ -409,8 +418,6 @@
clock-names = "PCLK", "TVE";
pinctrl-names = "default";
pinctrl-0 = <&tvc_default_pins>;
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
diff --git a/src/arm/hi3620.dtsi b/src/arm/hi3620.dtsi
index 905900b..cf48ec1 100644
--- a/src/arm/hi3620.dtsi
+++ b/src/arm/hi3620.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. Hi3620 SoC
+ * HiSilicon Ltd. Hi3620 SoC
*
- * Copyright (C) 2012-2013 Hisilicon Ltd.
+ * Copyright (C) 2012-2013 HiSilicon Ltd.
* Copyright (C) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
diff --git a/src/arm/hip01-ca9x2.dts b/src/arm/hip01-ca9x2.dts
index 0314763..f3faf24 100644
--- a/src/arm/hip01-ca9x2.dts
+++ b/src/arm/hip01-ca9x2.dts
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. HiP01 SoC
+ * HiSilicon Ltd. HiP01 SoC
*
- * Copyright (C) 2014 Hisilicon Ltd.
+ * Copyright (C) 2014 HiSilicon Ltd.
* Copyright (C) 2014 Huawei Ltd.
*
* Author: Wang Long <long.wanglong@huawei.com>
diff --git a/src/arm/hip01.dtsi b/src/arm/hip01.dtsi
index 2a79636..e17f36b 100644
--- a/src/arm/hip01.dtsi
+++ b/src/arm/hip01.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. HiP01 SoC
+ * HiSilicon Ltd. HiP01 SoC
*
- * Copyright (c) 2014 Hisilicon Ltd.
+ * Copyright (c) 2014 HiSilicon Ltd.
* Copyright (c) 2014 Huawei Ltd.
*
* Author: Wang Long <long.wanglong@huawei.com>
diff --git a/src/arm/hip04.dtsi b/src/arm/hip04.dtsi
index bccf5ba..2424cc5 100644
--- a/src/arm/hip04.dtsi
+++ b/src/arm/hip04.dtsi
@@ -1,8 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Hisilicon Ltd. HiP04 SoC
+ * HiSilicon Ltd. HiP04 SoC
*
- * Copyright (C) 2013-2014 Hisilicon Ltd.
+ * Copyright (C) 2013-2014 HiSilicon Ltd.
* Copyright (C) 2013-2014 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
diff --git a/src/arm/hisi-x5hd2-dkb.dts b/src/arm/hisi-x5hd2-dkb.dts
index 22b122d..7758c19 100644
--- a/src/arm/hisi-x5hd2-dkb.dts
+++ b/src/arm/hisi-x5hd2-dkb.dts
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014 Linaro Ltd.
- * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 HiSilicon Limited.
*/
/dts-v1/;
diff --git a/src/arm/hisi-x5hd2.dtsi b/src/arm/hisi-x5hd2.dtsi
index 9721138..dc991ba 100644
--- a/src/arm/hisi-x5hd2.dtsi
+++ b/src/arm/hisi-x5hd2.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2014 Linaro Ltd.
- * Copyright (c) 2013-2014 Hisilicon Limited.
+ * Copyright (c) 2013-2014 HiSilicon Limited.
*/
#include <dt-bindings/clock/hix5hd2-clock.h>
diff --git a/src/arm/imx25-pinfunc.h b/src/arm/imx25-pinfunc.h
index f984b70..908caf8 100644
--- a/src/arm/imx25-pinfunc.h
+++ b/src/arm/imx25-pinfunc.h
@@ -563,15 +563,15 @@
#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x00 0x000
#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x05 0x000
-#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x00 0x000
+#define MX25_PAD_GPIO_A__GPIO_1_0 0x1f4 0x3f0 0x000 0x00 0x000
#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x06 0x000
#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x02 0x000
-#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x00 0x000
+#define MX25_PAD_GPIO_B__GPIO_1_1 0x1f8 0x3f4 0x000 0x00 0x000
#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x02 0x001
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x06 0x001
-#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x00 0x000
+#define MX25_PAD_GPIO_C__GPIO_1_2 0x1fc 0x3f8 0x000 0x00 0x000
#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x01 0x000
#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x02 0x001
#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x03 0x001
@@ -580,18 +580,18 @@
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x06 0x000
#define MX25_PAD_GPIO_C__CSPI2_SS2 0x1fc 0x3f8 0x000 0x07 0x000
-#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x00 0x000
+#define MX25_PAD_GPIO_D__GPIO_1_3 0x200 0x3fc 0x000 0x00 0x000
#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x02 0x001
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x06 0x001
#define MX25_PAD_GPIO_D__CSPI3_SS2 0x200 0x3fc 0x4c4 0x07 0x001
-#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x00 0x000
+#define MX25_PAD_GPIO_E__GPIO_1_4 0x204 0x400 0x000 0x00 0x000
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x01 0x002
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x04 0x000
#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x06 0x002
-#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x00 0x000
+#define MX25_PAD_GPIO_F__GPIO_1_5 0x208 0x404 0x000 0x00 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x04 0x000
#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x06 0x000
diff --git a/src/arm/imx28-lwe.dtsi b/src/arm/imx28-lwe.dtsi
new file mode 100644
index 0000000..bb971e6
--- /dev/null
+++ b/src/arm/imx28-lwe.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2021
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx28.dtsi"
+
+/ {
+ aliases {
+ spi2 = &ssp3;
+ };
+
+ chosen {
+ bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1";
+ };
+
+ memory@40000000 {
+ reg = <0x40000000 0x08000000>;
+ };
+
+ reg_3v3: regulator-reg-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb_5v: regulator-reg-usb-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_fec_3v3: regulator-reg-fec-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "fec-phy";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&duart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&duart_pins_a>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&saif0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif0_pins_a>;
+ #sound-dai-cells = <0>;
+ assigned-clocks = <&clks 53>;
+ assigned-clock-rates = <12000000>;
+ status = "okay";
+};
+
+&saif1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&saif1_pins_a>;
+ fsl,saif-master = <&saif0>;
+ #sound-dai-cells = <0>;
+ status = "okay";
+};
+
+&spi3_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_AUART2_RX__SSP3_D4
+ MX28_PAD_AUART2_TX__SSP3_D5
+ MX28_PAD_SSP3_SCK__SSP3_SCK
+ MX28_PAD_SSP3_MOSI__SSP3_CMD
+ MX28_PAD_SSP3_MISO__SSP3_D0
+ MX28_PAD_SSP3_SS0__SSP3_D3
+ MX28_PAD_AUART2_TX__GPIO_3_9
+ >;
+};
+
+&ssp0 {
+ compatible = "fsl,imx28-mmc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_8bit_pins_a>;
+ bus-width = <8>;
+ vmmc-supply = <®_3v3>;
+ non-removable;
+ status = "okay";
+};
+
+&ssp2 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_pins_a>;
+ status = "okay";
+};
+
+&ssp3 {
+ compatible = "fsl,imx28-spi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi3_pins_a>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <40000000>;
+ reg = <0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0 0x80000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "env0";
+ reg = <0x80000 0x10000>;
+ };
+
+ partition@90000 {
+ label = "env1";
+ reg = <0x90000 0x10000>;
+ };
+
+ partition@100000 {
+ label = "kernel";
+ reg = <0x100000 0x400000>;
+ };
+
+ partition@500000 {
+ label = "swupdate";
+ reg = <0x500000 0x800000>;
+ };
+ };
+ };
+};
+
+&usb0 {
+ vbus-supply = <®_usb_5v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins_b>, <&usb0_id_pins_a>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usb1 {
+ vbus-supply = <®_usb_5v>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb1_pins_b>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
diff --git a/src/arm/imx28-xea.dts b/src/arm/imx28-xea.dts
new file mode 100644
index 0000000..a400c10
--- /dev/null
+++ b/src/arm/imx28-xea.dts
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2021
+ * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
+ */
+
+/dts-v1/;
+#include "imx28-lwe.dtsi"
+
+/ {
+ compatible = "lwn,imx28-xea", "fsl,imx28";
+};
+
+&can0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_b>;
+ status = "okay";
+};
+
+&pinctrl {
+ pinctrl-names = "default";
+ pinctrl-0 = <&hog_pins_a &hog_pins_tiva>;
+
+ hog_pins_a: hog@0 {
+ reg = <0>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D00__GPIO_0_0
+ MX28_PAD_GPMI_D02__GPIO_0_2
+ MX28_PAD_GPMI_D05__GPIO_0_5
+ MX28_PAD_GPMI_CE1N__GPIO_0_17
+ MX28_PAD_GPMI_RDY0__GPIO_0_20
+ MX28_PAD_GPMI_RDY1__GPIO_0_21
+ MX28_PAD_GPMI_RDY2__GPIO_0_22
+ MX28_PAD_GPMI_RDN__GPIO_0_24
+ MX28_PAD_GPMI_CLE__GPIO_0_27
+ MX28_PAD_LCD_VSYNC__GPIO_1_28
+ MX28_PAD_SSP1_SCK__GPIO_2_12
+ MX28_PAD_SSP1_CMD__GPIO_2_13
+ MX28_PAD_SSP2_SS1__GPIO_2_20
+ MX28_PAD_SSP2_SS2__GPIO_2_21
+ MX28_PAD_LCD_D00__GPIO_1_0
+ MX28_PAD_LCD_D01__GPIO_1_1
+ MX28_PAD_LCD_D02__GPIO_1_2
+ MX28_PAD_LCD_D03__GPIO_1_3
+ MX28_PAD_LCD_D04__GPIO_1_4
+ MX28_PAD_LCD_D05__GPIO_1_5
+ MX28_PAD_LCD_D06__GPIO_1_6
+ >;
+ fsl,drive-strength = <MXS_DRIVE_4mA>;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ hog_pins_tiva: hog@1 {
+ reg = <1>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_RDY3__GPIO_0_23
+ MX28_PAD_GPMI_WRN__GPIO_0_25
+ >;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+
+ hog_pins_coding: hog@2 {
+ reg = <2>;
+ fsl,pinmux-ids = <
+ MX28_PAD_GPMI_D01__GPIO_0_1
+ MX28_PAD_GPMI_D03__GPIO_0_3
+ MX28_PAD_GPMI_D04__GPIO_0_4
+ MX28_PAD_GPMI_D06__GPIO_0_6
+ MX28_PAD_GPMI_D07__GPIO_0_7
+ >;
+ fsl,voltage = <MXS_VOLTAGE_HIGH>;
+ fsl,pull-up = <MXS_PULL_DISABLE>;
+ };
+};
+
+®_fec_3v3 {
+ gpio = <&gpio0 0 0>;
+};
+
+®_usb_5v {
+ gpio = <&gpio0 2 0>;
+};
+
+&spi2_pins_a {
+ fsl,pinmux-ids = <
+ MX28_PAD_SSP2_SCK__SSP2_SCK
+ MX28_PAD_SSP2_MOSI__SSP2_CMD
+ MX28_PAD_SSP2_MISO__SSP2_D0
+ MX28_PAD_SSP2_SS0__GPIO_2_19
+ >;
+};
diff --git a/src/arm/imx51-digi-connectcore-som.dtsi b/src/arm/imx51-digi-connectcore-som.dtsi
index 16addb3..7d49704 100644
--- a/src/arm/imx51-digi-connectcore-som.dtsi
+++ b/src/arm/imx51-digi-connectcore-som.dtsi
@@ -206,7 +206,7 @@
pinctrl-0 = <&pinctrl_weim>;
status = "okay";
- lan9221: lan9221@5,0 {
+ lan9221: ethernet@5,0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lan9221>;
compatible = "smsc,lan9221", "smsc,lan9115";
diff --git a/src/arm/imx53-ard.dts b/src/arm/imx53-ard.dts
index 9a2e1fd..6208fbb 100644
--- a/src/arm/imx53-ard.dts
+++ b/src/arm/imx53-ard.dts
@@ -24,7 +24,7 @@
reg = <0xf4000000 0x3ff0000>;
ranges;
- lan9220@f4000000 {
+ ethernet@f4000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0xf4000000 0x2000000>;
phy-mode = "mii";
diff --git a/src/arm/imx53-ppd.dts b/src/arm/imx53-ppd.dts
index be040b6..5a5fa61 100644
--- a/src/arm/imx53-ppd.dts
+++ b/src/arm/imx53-ppd.dts
@@ -651,6 +651,7 @@
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
+ fsl,dma-info = <24 20>;
status = "okay";
};
@@ -670,6 +671,7 @@
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
+ fsl,dma-info = <4096 4>;
status = "okay";
};
diff --git a/src/arm/imx6dl-b105pv2.dts b/src/arm/imx6dl-b105pv2.dts
new file mode 100644
index 0000000..411aa72
--- /dev/null
+++ b/src/arm/imx6dl-b105pv2.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B105Pv2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ model = "General Electric B105Pv2";
+ compatible = "ge,imx6dl-b105pv2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g101evn010";
+ };
+};
+
+&i2c3 {
+ touchscreen@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ };
+};
diff --git a/src/arm/imx6dl-b105v2.dts b/src/arm/imx6dl-b105v2.dts
new file mode 100644
index 0000000..d011127
--- /dev/null
+++ b/src/arm/imx6dl-b105v2.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B105v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B105v2";
+ compatible = "ge,imx6dl-b105v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g101evn010";
+ };
+};
+
+&i2c3 {
+ touchscreen@41 {
+ compatible = "ilitek,ili251x";
+ reg = <0x41>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <1280>;
+ touchscreen-size-y = <800>;
+ };
+};
diff --git a/src/arm/imx6dl-b125pv2.dts b/src/arm/imx6dl-b125pv2.dts
new file mode 100644
index 0000000..ca840fa
--- /dev/null
+++ b/src/arm/imx6dl-b125pv2.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B125Pv2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ model = "General Electric B125Pv2";
+ compatible = "ge,imx6dl-b125pv2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g121ean01";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ compatible = "eeti,exc80h60";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/src/arm/imx6dl-b125v2.dts b/src/arm/imx6dl-b125v2.dts
new file mode 100644
index 0000000..81e5a9c
--- /dev/null
+++ b/src/arm/imx6dl-b125v2.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B125v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B125v2";
+ compatible = "ge,imx6dl-b125v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g121ean01";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ compatible = "eeti,exc80h60";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/src/arm/imx6dl-b155v2.dts b/src/arm/imx6dl-b155v2.dts
new file mode 100644
index 0000000..c861937
--- /dev/null
+++ b/src/arm/imx6dl-b155v2.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B155v2
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+/dts-v1/;
+#include "imx6dl-b1x5v2.dtsi"
+
+/ {
+ model = "General Electric B155v2";
+ compatible = "ge,imx6dl-b155v2", "congatec,qmx6", "fsl,imx6dl";
+
+ panel {
+ compatible = "auo,g156xtn01";
+ };
+};
+
+&i2c3 {
+ touchscreen@2a {
+ compatible = "eeti,exc80h84";
+ reg = <0x2a>;
+ pinctrl-names = "default";
+ pinctrl-0 =<&pinctrl_q7_gpio0>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
+ touchscreen-inverted-x;
+ touchscreen-inverted-y;
+ reset-gpios = <&tca6424a 21 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/src/arm/imx6dl-b1x5pv2.dtsi b/src/arm/imx6dl-b1x5pv2.dtsi
new file mode 100644
index 0000000..ec5b664
--- /dev/null
+++ b/src/arm/imx6dl-b1x5pv2.dtsi
@@ -0,0 +1,413 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B1x5Pv2
+// patient monitor series
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+#include <dt-bindings/input/input.h>
+#include "imx6dl-qmx6.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ /* Do not allow frequencies above 800MHz */
+ cpus {
+ cpu@0 {
+ operating-points = <
+ /* kHz uV */
+ 792000 1175000
+ 396000 1150000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 792000 1175000
+ 396000 1175000
+ >;
+ };
+
+ cpu@1 {
+ operating-points = <
+ /* kHz uV */
+ 792000 1175000
+ 396000 1150000
+ >;
+ fsl,soc-operating-points = <
+ /* ARM kHz SOC-PU uV */
+ 792000 1175000
+ 396000 1175000
+ >;
+ };
+ };
+
+ reg_syspwr: regulator-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "SYS_PWR";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ reg_5v_pmc: regulator-5v-pmc {
+ compatible = "regulator-fixed";
+ regulator-name = "5V PMC";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_syspwr>;
+ };
+
+ reg_5v0_audio: regulator-5v0-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "5V0_AUDIO";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ gpio = <&tca6424a 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ /*
+ * This must be always-on for da7212, which has some not
+ * properly documented dependencies for it's speaker supply
+ * pin. The issue manifests as speaker volume being very low.
+ */
+ regulator-always-on;
+ };
+
+
+ reg_3v3_audio: regulator-3v3-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3_AUDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_3v3>;
+ pinctrl-0 = <&pinctrl_q7_hda_reset>;
+ pinctrl-names = "default";
+ gpio = <&gpio6 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_2v5_audio: regulator-2v5-audio {
+ compatible = "regulator-fixed";
+ regulator-name = "2V5_AUDIO";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ vin-supply = <®_3v3_audio>;
+
+ };
+
+ reg_wlan: regulator-wlan {
+ compatible = "regulator-fixed";
+ regulator-name = "WLAN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <®_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_sdio_power>;
+ gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <70000>;
+ };
+
+ reg_bl: regulator-backlight {
+ compatible = "regulator-fixed";
+ regulator-name = "LED_VCC";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <®_syspwr>;
+ pinctrl-0 = <&pinctrl_q7_lcd_power>;
+ pinctrl-names = "default";
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_lcd: regulator-lcd {
+ compatible = "regulator-fixed";
+ regulator-name = "LCD_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ };
+
+ usb_power: regulator-usb-power {
+ compatible = "regulator-fixed";
+ regulator-name = "USB POWER";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <®_5v>;
+ };
+
+ charger: battery-charger {
+ compatible = "gpio-charger"; /* ti,bq24172 */
+ charger-type = "mains";
+ gpios = <&tca6424a 3 GPIO_ACTIVE_LOW>;
+ charge-current-limit-gpios = <&tca6424a 11 GPIO_ACTIVE_HIGH>,
+ <&tca6424a 12 GPIO_ACTIVE_HIGH>;
+ charge-current-limit-mapping = <1300000 0x0>,
+ <700000 0x1>,
+ <0 0x2>;
+ charge-status-gpios = <&tca6424a 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ poweroff {
+ compatible = "gpio-poweroff";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_spi_cs1>;
+ gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
+ };
+
+ power-button-key {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_sleep_button>;
+
+ power-button {
+ label = "power button";
+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ rotary-encoder-key {
+ compatible = "gpio-keys";
+
+ rotary-encoder-press {
+ label = "rotary-encoder press";
+ gpios = <&tca6424a 0 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_ENTER>;
+ linux,can-disable;
+ };
+ };
+
+ rotary-encoder {
+ compatible = "rotary-encoder";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio2 &pinctrl_q7_gpio4>;
+ gpios = <&gpio4 26 GPIO_ACTIVE_LOW>, <&gpio1 0 GPIO_ACTIVE_LOW>;
+ rotary-encoder,relative-axis;
+ rotary-encoder,steps-per-period = <2>;
+ wakeup-source;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>;
+
+ alarm1 {
+ label = "alarm:red";
+ gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm2 {
+ label = "alarm:yellow";
+ gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ alarm3 {
+ label = "alarm:blue";
+ gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_backlight_enable>;
+ power-supply = <®_bl>;
+ pwms = <&pwm4 0 5000000 0>;
+ brightness-levels = <0 255>;
+ num-interpolated-steps = <255>;
+ default-brightness-level = <179>;
+ enable-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel {
+ backlight = <&backlight>;
+ power-supply = <®_lcd>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lvds0_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&dailink_master>;
+ simple-audio-card,frame-master = <&dailink_master>;
+ simple-audio-card,widgets = "Speaker", "Ext Spk";
+ simple-audio-card,audio-routing = "Ext Spk", "LINE";
+
+ simple-audio-card,cpu {
+ sound-dai = <&ssi1>;
+ };
+
+ dailink_master: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
+ clk_ext_audio_codec: clock-codec {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ };
+};
+
+&audmux {
+ status = "okay";
+};
+
+&fec {
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&i2c1 {
+ battery: battery@b {
+ compatible = "ti,bq20z65", "sbs,sbs-battery";
+ reg = <0x0b>;
+ sbs,battery-detect-gpios = <&tca6424a 5 GPIO_ACTIVE_LOW>;
+ sbs,i2c-retry-count = <5>;
+ power-supplies = <&charger>;
+ };
+
+ codec: audio-codec@1a {
+ compatible = "dlg,da7212";
+ reg = <0x1a>;
+ #sound-dai-cells = <0>;
+ VDDA-supply = <®_2v5_audio>;
+ VDDSP-supply = <®_5v0_audio>;
+ VDDMIC-supply = <®_3v3_audio>;
+ VDDIO-supply = <®_3v3_audio>;
+ clocks = <&clk_ext_audio_codec>;
+ clock-names = "mclk";
+ };
+};
+
+&i2c5 {
+ tca6424a: gpio-controller@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ vcc-supply = <®_3v3>;
+ interrupt-parent = <&gpio7>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio6>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-line-names = "GPIO_ROTOR#", "ACM_IO_INT", "TMP_SENSOR_IRQ", "AC_IN",
+ "TF_S", "BATT_T", "LED_INC_CHAR", "ACM1_OCF",
+ "ACM2_OCF", "ACM_IO_RST", "USB1_POWER_EN", "EGPIO_CC_CTL0",
+ "EGPIO_CC_CTL1", "12V_OEMNBP_EN", "CP2105_RST", "",
+ "SPEAKER_PA_EN", "ARM7_UPI_RESET", "ARM7_PWR_RST", "NURSE_CALL",
+ "MARKER_EN", "EGPIO_TOUCH_RST", "PRESSURE_INT1", "PRESSURE_INT2";
+
+ };
+
+ tmp75: temperature-sensor@48 {
+ compatible = "ti,tmp75";
+ reg = <0x48>;
+ vs-supply = <®_3v3>;
+ interrupt-parent = <&tca6424a>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&ldb {
+ status = "okay";
+
+ lvds0: lvds-channel@0 {
+ status = "okay";
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <24>;
+
+ port@4 {
+ reg = <4>;
+
+ lvds0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-slave";
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <&usb_power>;
+ disable-over-current;
+ dr_mode = "host";
+ status = "okay";
+
+ /*
+ * TPS2051BDGN fault-gpio is connected to Q7[86] USB_0_1_OC_N.
+ * On QMX6 this is not connceted to the i.MX6, but to the USB Hub
+ * from &usbh1. This means, that we cannot easily detect and handle
+ * over-current events. Fortunately the regulator limits the current
+ * automatically, so the hardware is still protected.
+ */
+};
+
+&usdhc4 {
+ /* WiFi module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ wakeup-source;
+ keep-power-in-suspend;
+ cap-power-off-card;
+ max-frequency = <25000000>;
+ vmmc-supply = <®_wlan>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ wlcore: wlcore@2 {
+ compatible = "ti,wl1837";
+ reg = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_q7_gpio7>;
+
+ interrupt-parent = <&gpio4>;
+ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+
+ tcxo-clock-frequency = <26000000>;
+ };
+};
diff --git a/src/arm/imx6dl-b1x5v2.dtsi b/src/arm/imx6dl-b1x5v2.dtsi
new file mode 100644
index 0000000..a326a33
--- /dev/null
+++ b/src/arm/imx6dl-b1x5v2.dtsi
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for General Electric B1x5v2
+// patient monitor series
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+
+#include <dt-bindings/input/input.h>
+#include "imx6dl-b1x5pv2.dtsi"
+
+/ {
+ reg_3v3_acm: regulator-3v3-acm {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3 ACM";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <®_3v3>;
+ };
+};
+
+&i2c1 {
+ tca6416: gpio-controller@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ reset-gpios = <&tca6424a 9 GPIO_ACTIVE_LOW>;
+ vcc-supply = <®_3v3_acm>;
+ gpio-line-names = "ACM1_EN", "ACM1_CL0", "ACM1_CL1", "ACM1_CL2",
+ "", "ACM2_EN", "ACM2_CL0", "ACM2_CL1",
+ "ACM2_CL2", "", "", "",
+ "", "", "", "";
+
+ /*
+ * The interrupt pin is connected to &tca6424a pin 1, but the Linux
+ * TCA6424 driver cannot handle low type interrupts at the moment
+ * (and support cannot be added without some ugly hacks). Since this
+ * controller does not have any input type GPIOs, just pretend
+ * that the interrupt pin is unconnected.
+ */
+ };
+};
+
+&i2c5 {
+ mpl3115a2: pressure-sensor@60 {
+ compatible = "fsl,mpl3115";
+ reg = <0x60>;
+ vcc-supply = <®_3v3_acm>;
+
+ /*
+ * The MPL3115 interrupts are connected to pin 22 and 23
+ * of &tca6424a, but the binding does not yet support
+ * interrupts.
+ */
+ };
+};
diff --git a/src/arm/imx6dl-plym2m.dts b/src/arm/imx6dl-plym2m.dts
index 4d0d3d3..60fe5f1 100644
--- a/src/arm/imx6dl-plym2m.dts
+++ b/src/arm/imx6dl-plym2m.dts
@@ -138,8 +138,6 @@
interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>;
pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
- touchscreen-size-x = <800>;
- touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
touchscreen-max-pressure = <4095>;
@@ -147,7 +145,9 @@
ti,vref-delay-usecs = /bits/ 16 <100>;
ti,x-plate-ohms = /bits/ 16 <800>;
ti,y-plate-ohms = /bits/ 16 <300>;
-
+ ti,debounce-max = /bits/ 16 <3>;
+ ti,debounce-tol = /bits/ 16 <70>;
+ ti,debounce-rep = /bits/ 16 <3>;
wakeup-source;
};
};
diff --git a/src/arm/imx6dl-prtvt7.dts b/src/arm/imx6dl-prtvt7.dts
index ae6da24..190d266 100644
--- a/src/arm/imx6dl-prtvt7.dts
+++ b/src/arm/imx6dl-prtvt7.dts
@@ -21,14 +21,11 @@
backlight_lcd: backlight-lcd {
compatible = "pwm-backlight";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_backlight>;
- pwms = <&pwm1 0 500000>;
+ pwms = <&pwm1 0 500000 0>;
brightness-levels = <0 20 81 248 1000>;
default-brightness-level = <20>;
num-interpolated-steps = <21>;
power-supply = <®_bl_12v0>;
- enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
};
keys {
@@ -223,6 +220,24 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
+
+ touchscreen@0 {
+ compatible = "ti,tsc2046";
+ reg = <0>;
+ pinctrl-0 = <&pinctrl_tsc>;
+ pinctrl-names ="default";
+ spi-max-frequency = <100000>;
+ interrupts-extended = <&gpio3 20 IRQ_TYPE_EDGE_FALLING>;
+ pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
+ touchscreen-max-pressure = <4095>;
+ ti,vref-delay-usecs = /bits/ 16 <100>;
+ ti,x-plate-ohms = /bits/ 16 <800>;
+ ti,y-plate-ohms = /bits/ 16 <300>;
+ ti,debounce-max = /bits/ 16 <3>;
+ ti,debounce-tol = /bits/ 16 <70>;
+ ti,debounce-rep = /bits/ 16 <3>;
+ wakeup-source;
+ };
};
&i2c1 {
@@ -261,7 +276,6 @@
};
&pwm1 {
- #pwm-cells = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
@@ -276,8 +290,6 @@
};
&ssi1 {
- #sound-dai-cells = <0>;
- fsl,mode = "ac97-slave";
status = "okay";
};
@@ -285,10 +297,6 @@
status = "disabled";
};
-&vpu {
- status = "disabled";
-};
-
&iomuxc {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
@@ -300,12 +308,6 @@
>;
};
- pinctrl_backlight: backlightgrp {
- fsl,pins = <
- MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b0
- >;
- };
-
pinctrl_can1phy: can1phy {
fsl,pins = <
/* CAN1_SR */
diff --git a/src/arm/imx6dl-qmx6.dtsi b/src/arm/imx6dl-qmx6.dtsi
new file mode 100644
index 0000000..150d698
--- /dev/null
+++ b/src/arm/imx6dl-qmx6.dtsi
@@ -0,0 +1,612 @@
+// SPDX-License-Identifier: GPL-2.0 or MIT
+//
+// Device Tree Source for i.MX6DL based congatec QMX6
+// System on Module
+//
+// Copyright 2018-2021 General Electric Company
+// Copyright 2018-2021 Collabora
+// Copyright 2016 congatec AG
+
+#include "imx6dl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/sound/fsl-imx-audmux.h>
+
+/ {
+ memory@10000000 {
+ reg = <0x10000000 0x40000000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mux-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>;
+ i2c-parent = <&i2c2>;
+
+ i2c5: i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c6: i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux>;
+
+ audmux_ssi1 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>;
+ fsl,port-config = <
+ (IMX_AUDMUX_V2_PTCR_TFSDIR |
+ IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT6) |
+ IMX_AUDMUX_V2_PTCR_TCLKDIR |
+ IMX_AUDMUX_V2_PTCR_TCSEL(MX51_AUDMUX_PORT6) |
+ IMX_AUDMUX_V2_PTCR_SYN)
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT6)
+ >;
+ };
+
+ audmux_aud6 {
+ fsl,audmux-port = <MX51_AUDMUX_PORT6>;
+ fsl,port-config = <
+ IMX_AUDMUX_V2_PTCR_SYN
+ IMX_AUDMUX_V2_PDCR_RXDSEL(MX51_AUDMUX_PORT1_SSI0)
+ >;
+ };
+};
+
+&clks {
+ clocks = <&rtc_sqw>;
+ clock-names = "ckil";
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "sst,sst25vf032b", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "user";
+ reg = <0x0100000 0x2fc000>;
+ };
+
+ partition@3fc000 {
+ label = "reserved";
+ reg = <0x03fc000 0x4000>;
+ read-only;
+ };
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet &pinctrl_phy_reset>;
+ phy-mode = "rgmii-id";
+ phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+ fsl,magic-packet;
+ phy-handle = <&phy0>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: ethernet-phy@6 {
+ reg = <6>;
+ qca,clk-out-frequency = <125000000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ rtc: m41t62@68 {
+ compatible = "st,m41t62";
+ reg = <0x68>;
+
+ rtc_sqw: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
+
+&i2c6 {
+ pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <675000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /*
+ * keep VGEN3, VGEN4 and VGEN5 enabled in order to
+ * maintain backward compatibility with hw-rev. A.0
+ */
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ /* supply voltage for eMMC */
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&pcie {
+ reset-gpio = <&gpio1 20 0>;
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+};
+
+®_arm {
+ vin-supply = <&sw1a_reg>;
+};
+
+®_pu {
+ vin-supply = <&sw1c_reg>;
+};
+
+®_soc {
+ vin-supply = <&sw1c_reg>;
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbh1 {
+ /* Connected to USB-Hub SMSC USB2514, provides P0, P2, P3, P4 on Qseven connector */
+ vbus-supply = <®_5v>;
+ status = "okay";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+};
+
+&usdhc2 {
+ /* MicroSD card slot */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&usdhc3 {
+ /* eMMC module */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ non-removable;
+ bus-width = <8>;
+ no-1-8-v;
+ keep-power-in-suspend;
+ wakeup-source;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ qmx6mux: imx6qdl-qmx6 {
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x110b0 /* Q7[67] HDA_SDO */
+ MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x30b0 /* Q7[59] HDA_SYNC */
+ MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x30b0 /* Q7[65] HDA_SDI */
+ MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x30b0 /* Q7[63] HDA_BITCLK */
+ >;
+ };
+
+ /* PHY is on System on Module, Q7[3-15] have Ethernet lines */
+ pinctrl_enet: enet {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* PCIE_WAKE_B */
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x80000000 /* I2C multiplexer */
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* SD4_CD# */
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* SD4_WP */
+ MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x80000000 /* Camera MCLK */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 /* Q7[66] I2C_CLK */
+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 /* Q7[68] I2C_DAT */
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x1b0b0 /* Q7[66] I2C_CLK */
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b0 /* Q7[68] I2C_DAT */
+ >;
+ };
+
+ pinctrl_i2c2: i2c2 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 /* Q7[152] SDVO_CTRL_CLK */
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 /* Q7[150] SDVO_CTRL_DAT */
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* Q7[152] SDVO_CTRL_CLK */
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* Q7[150] SDVO_CTRL_DAT */
+ >;
+ };
+
+ pinctrl_i2c3: i2c3 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 /* Q7[60] SMB_CLK */
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 /* Q7[62] SMB_DAT */
+ >;
+ };
+
+ pinctrl_i2c3_gpio: i2c3-gpio {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0 /* Q7[60] SMB_CLK */
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 /* Q7[62] SMB_DAT */
+ >;
+ };
+
+ pinctrl_phy_reset: phy-reset {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b0 /* RGMII Phy Reset */
+ >;
+ };
+
+ pinctrl_pwm4: pwm4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 /* Q7[123] LVDS_BLT_CTRL */
+ >;
+ };
+
+ pinctrl_q7_backlight_enable: q7-backlight-enable {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* Q7[112] LVDS_BLEN */
+ >;
+ };
+
+ pinctrl_q7_gpio0: q7-gpio0 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 /* Q7[185] GPIO0 */
+ >;
+ };
+
+ pinctrl_q7_gpio1: q7-gpio1 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* Q7[186] GPIO1 */
+ >;
+ };
+
+ pinctrl_q7_gpio2: q7-gpio2 {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0 /* Q7[187] GPIO2 */
+ >;
+ };
+
+ pinctrl_q7_gpio3: q7-gpio3 {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0 /* Q7[188] GPIO3 */
+ >;
+ };
+
+ pinctrl_q7_gpio4: q7-gpio4 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* Q7[189] GPIO4 */
+ >;
+ };
+
+ pinctrl_q7_gpio5: q7-gpio5 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* Q7[190] GPIO5 */
+ >;
+ };
+
+ pinctrl_q7_gpio6: q7-gpio6 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0 /* Q7[191] GPIO6 */
+ >;
+ };
+
+ pinctrl_q7_gpio7: q7-gpio7 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* Q7[192] GPIO7 */
+ >;
+ };
+
+ pinctrl_q7_hda_reset: q7-hda-reset {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0 /* Q7[61] HDA_RST_N */
+ >;
+ };
+
+ pinctrl_q7_lcd_power: lcd-power {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* Q7[111] LVDS_PPEN */
+ >;
+ };
+
+ pinctrl_q7_sdio_power: q7-sdio-power {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b0 /* Q7[47] SDIO_PWR# */
+ >;
+ };
+
+ pinctrl_q7_sleep_button: q7-sleep-button {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 /* Q7[21] SLP_BTN# */
+ >;
+ };
+
+ pinctrl_q7_spi_cs1: spi-cs1 {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0 /* Q7[202] SPI_CS1# */
+ >;
+ };
+
+ /* SPI1 bus does not leave System on Module */
+ pinctrl_spi1: spi1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
+ >;
+ };
+
+ /* Debug connector on Q7 module */
+ pinctrl_uart2: uart2 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 /* Q7[177] UART0_RX */
+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 /* Q7[171] UART0_TX */
+ >;
+ };
+
+ pinctrl_usbotg: usbotg {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 /* Q7[92] USB_ID */
+ >;
+ };
+
+ /* µSD card slot on Q7 module */
+ pinctrl_usdhc2: usdhc2 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2_CD */
+ >;
+ };
+
+ /* eMMC module on Q7 module */
+ pinctrl_usdhc3: usdhc3 {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc4: usdhc4 {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 /* Q7[45] SDIO_CMD */
+ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x17059 /* Q7[42] SDIO_CLK */
+ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 /* Q7[48] SDIO_DAT1 */
+ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 /* Q7[49] SDIO_DAT0 */
+ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 /* Q7[50] SDIO_DAT3 */
+ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 /* Q7[51] SDIO_DAT2 */
+ >;
+ };
+
+ pinctrl_wdog: wdog {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 /* Watchdog output signal */
+ >;
+ };
+ };
+};
diff --git a/src/arm/imx6dl-riotboard.dts b/src/arm/imx6dl-riotboard.dts
index 065d3ab..e7d9bfb 100644
--- a/src/arm/imx6dl-riotboard.dts
+++ b/src/arm/imx6dl-riotboard.dts
@@ -106,6 +106,8 @@
reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <1000>;
+ qca,smarteee-tw-us-1g = <24>;
+ qca,clk-out-frequency = <125000000>;
};
};
};
diff --git a/src/arm/imx6dl-yapp4-common.dtsi b/src/arm/imx6dl-yapp4-common.dtsi
index 9148a01..cb8b539 100644
--- a/src/arm/imx6dl-yapp4-common.dtsi
+++ b/src/arm/imx6dl-yapp4-common.dtsi
@@ -11,6 +11,8 @@
aliases: aliases {
ethernet1 = ð1;
ethernet2 = ð2;
+ mmc0 = &usdhc3;
+ mmc1 = &usdhc4;
};
backlight: backlight {
@@ -345,6 +347,7 @@
solomon,height = <64>;
solomon,width = <128>;
solomon,page-offset = <0>;
+ solomon,col-offset = <4>;
solomon,prechargep2 = <15>;
reset-gpios = <&gpio_oled 1 GPIO_ACTIVE_LOW>;
vbat-supply = <&sw2_reg>;
diff --git a/src/arm/imx6q-dhcom-som.dtsi b/src/arm/imx6q-dhcom-som.dtsi
index d0768ae..4bf51f3 100644
--- a/src/arm/imx6q-dhcom-som.dtsi
+++ b/src/arm/imx6q-dhcom-som.dtsi
@@ -12,10 +12,20 @@
/ {
aliases {
+ i2c0 = &i2c2;
+ i2c1 = &i2c1;
+ i2c2 = &i2c3;
mmc0 = &usdhc2;
mmc1 = &usdhc3;
mmc2 = &usdhc4;
mmc3 = &usdhc1;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ serial0 = &uart1;
+ serial1 = &uart5;
+ serial2 = &uart4;
+ serial3 = &uart2;
+ serial4 = &uart3;
};
memory@10000000 {
@@ -23,6 +33,19 @@
reg = <0x10000000 0x40000000>;
};
+ reg_eth_vio: regulator-eth-vio {
+ compatible = "regulator-fixed";
+ gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&pinctrl_enet_vio>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_vio";
+ vin-supply = <&sw2_reg>;
+ };
+
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg_vbus";
@@ -96,30 +119,40 @@
reg = <0>;
max-speed = <100>;
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- reset-post-delay-us = <1000>;
+ reset-assert-us = <1000>;
+ reset-deassert-us = <1000>;
+ smsc,disable-energy-detect; /* Make plugin detection reliable */
};
};
};
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_gpio>;
+ scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
ltc3676: pmic@3c {
@@ -203,7 +236,7 @@
pagesize = <16>;
};
- rtc@56 {
+ rtc_i2c: rtc@56 {
compatible = "microcrystal,rv3029";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc_hw300>;
@@ -260,6 +293,11 @@
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0
MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1
+ >;
+ };
+
+ pinctrl_enet_vio: enet-vio-grp {
+ fsl,pins = <
MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x120b0
>;
};
@@ -285,6 +323,13 @@
>;
};
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
@@ -292,6 +337,13 @@
>;
};
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
@@ -299,6 +351,13 @@
>;
};
+ pinctrl_i2c3_gpio: i2c3-gpio-grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ >;
+ };
+
pinctrl_pmic_hw300: pmic-hw300-grp {
fsl,pins = <
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1B0B0
diff --git a/src/arm/imx6q-dmo-edmqmx6.dts b/src/arm/imx6q-dmo-edmqmx6.dts
index fa2307d..c713ac0 100644
--- a/src/arm/imx6q-dmo-edmqmx6.dts
+++ b/src/arm/imx6q-dmo-edmqmx6.dts
@@ -112,7 +112,7 @@
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-supply = <&vgen2_1v2_eth>;
status = "okay";
diff --git a/src/arm/imx6q-ds.dts b/src/arm/imx6q-ds.dts
new file mode 100644
index 0000000..b0a63a1
--- /dev/null
+++ b/src/arm/imx6q-ds.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2021 Dillon Min <dillon.minfei@gmail.com>
+//
+// Based on imx6qdl-sabresd.dtsi which is:
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-ds.dtsi"
+
+/ {
+ model = "DaSheng i.MX6 Quad Com-9xx Board";
+ compatible = "ds,imx6q-sbc", "fsl,imx6q";
+};
diff --git a/src/arm/imx6qdl-ds.dtsi b/src/arm/imx6qdl-ds.dtsi
new file mode 100644
index 0000000..f7e5175
--- /dev/null
+++ b/src/arm/imx6qdl-ds.dtsi
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2021 Dillon Min <dillon.minfei@gmail.com>
+//
+// Based on imx6qdl-sabresd.dtsi which is:
+// Copyright 2012 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ memory@10000000 {
+ device_type = "memory";
+ reg = <0x10000000 0x80000000>;
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usb_h1_vbus: regulator-usb-h1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_h1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led-0 {
+ gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov2659_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+ status = "okay";
+};
+
+&ecspi1 {
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_gpio>;
+ status = "okay";
+
+ m25p80: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,m25p80", "jedec,spi-nor";
+ spi-max-frequency = <20000000>;
+ reg = <0>;
+ };
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rgmii-id";
+ phy-handle = <&phy>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: ethernet-phy@1 {
+ reg = <1>;
+ qca,clk-out-frequency = <125000000>;
+ reset-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ };
+ };
+};
+
+&hdmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_cec>;
+ ddc-i2c-bus = <&i2c3>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pfuze100: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ ov2659: camera@30 {
+ compatible = "ovti,ov2659";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov2659>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xvclk";
+ reg = <0x30>;
+ powerdown-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ port {
+ ov2659_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ link-frequencies = /bits/ 64 <70000000>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+ >;
+ };
+
+ pinctrl_ecspi1_gpio: ecspi1grpgpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet: enetgrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
+ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
+ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ >;
+ };
+
+ pinctrl_hdmi_cec: hdmicecgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
+ >;
+ };
+
+ pinctrl_ov2659: ov2659grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b0
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
+ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg: usbotggrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1grpgpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
+ >;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbh1 {
+ vbus-supply = <®_usb_h1_vbus>;
+ status = "okay";
+};
+
+&usbotg {
+ vbus-supply = <®_usb_otg_vbus>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg>;
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ status = "disabled";
+};
+
+&wdog2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/src/arm/imx6qdl-phytec-pfla02.dtsi b/src/arm/imx6qdl-phytec-pfla02.dtsi
index 7bd658b..f323620 100644
--- a/src/arm/imx6qdl-phytec-pfla02.dtsi
+++ b/src/arm/imx6qdl-phytec-pfla02.dtsi
@@ -322,8 +322,8 @@
fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
- MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1
- MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
>;
};
@@ -410,6 +410,7 @@
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
+ uart-has-rtscts;
status = "disabled";
};
diff --git a/src/arm/imx6qdl-sabresd.dtsi b/src/arm/imx6qdl-sabresd.dtsi
index f824c9a..0c01054 100644
--- a/src/arm/imx6qdl-sabresd.dtsi
+++ b/src/arm/imx6qdl-sabresd.dtsi
@@ -97,8 +97,11 @@
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hp>;
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
+ audio-asrc = <&asrc>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
@@ -545,6 +548,13 @@
>;
};
+ pinctrl_hp: hpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
diff --git a/src/arm/imx6qdl-vicut1.dtsi b/src/arm/imx6qdl-vicut1.dtsi
index eb25d21..b9e3057 100644
--- a/src/arm/imx6qdl-vicut1.dtsi
+++ b/src/arm/imx6qdl-vicut1.dtsi
@@ -40,6 +40,27 @@
};
};
+ counter-0 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter0>;
+ gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+ };
+
+ counter-1 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter1>;
+ gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+ };
+
+ counter-2 {
+ compatible = "interrupt-counter";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_counter2>;
+ gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
autorepeat;
@@ -254,7 +275,7 @@
&gpio2 {
gpio-line-names =
- "", "", "", "", "", "", "", "",
+ "count0", "count1", "count2", "", "", "", "", "",
"REV_ID0", "REV_ID1", "REV_ID2", "REV_ID3", "REV_ID4",
"BOARD_ID0", "BOARD_ID1", "BOARD_ID2",
"", "", "", "", "", "", "", "ON_SWITCH",
@@ -572,6 +593,24 @@
>;
};
+ pinctrl_counter0: counter0grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b000
+ >;
+ };
+
+ pinctrl_counter1: counter1grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b000
+ >;
+ };
+
+ pinctrl_counter2: counter2grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b000
+ >;
+ };
+
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
diff --git a/src/arm/imx6qdl-wandboard-revd1.dtsi b/src/arm/imx6qdl-wandboard-revd1.dtsi
index b9b698f..bf86b63 100644
--- a/src/arm/imx6qdl-wandboard-revd1.dtsi
+++ b/src/arm/imx6qdl-wandboard-revd1.dtsi
@@ -142,7 +142,6 @@
imx6qdl-wandboard {
pinctrl_hog: hoggrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x80000000 /* USB Power Enable */
MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USDHC1 CD */
MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1f0b1 /* RGMII PHY reset */
diff --git a/src/arm/imx6ul-14x14-evk.dtsi b/src/arm/imx6ul-14x14-evk.dtsi
index 5a1e10d..779cc53 100644
--- a/src/arm/imx6ul-14x14-evk.dtsi
+++ b/src/arm/imx6ul-14x14-evk.dtsi
@@ -60,38 +60,26 @@
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
};
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "mx6ul-wm8960";
- simple-audio-card,format = "i2s";
- simple-audio-card,bitclock-master = <&dailink_master>;
- simple-audio-card,frame-master = <&dailink_master>;
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Line", "Line In",
- "Line", "Line Out",
- "Speaker", "Speaker",
- "Headphone", "Headphone Jack";
- simple-audio-card,routing =
+ sound-wm8960 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ audio-cpu = <&sai2>;
+ audio-codec = <&codec>;
+ audio-asrc = <&asrc>;
+ hp-det-gpio = <&gpio5 4 0>;
+ audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
- "Speaker", "SPK_LP",
- "Speaker", "SPK_LN",
- "Speaker", "SPK_RP",
- "Speaker", "SPK_RN",
- "LINPUT1", "Mic Jack",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
- "RINPUT1", "Mic Jack",
- "RINPUT2", "Mic Jack";
-
- simple-audio-card,cpu {
- sound-dai = <&sai2>;
- };
-
- dailink_master: simple-audio-card,codec {
- sound-dai = <&codec>;
- clocks = <&clks IMX6UL_CLK_SAI2>;
- };
+ "RINPUT1", "AMIC",
+ "RINPUT2", "AMIC",
+ "Mic Jack", "MICB",
+ "AMIC", "MICB";
};
spi4 {
@@ -145,6 +133,10 @@
compatible = "wlf,wm8960";
reg = <0x1a>;
wlf,shared-lrclk;
+ wlf,hp-cfg = <3 2 3>;
+ wlf,gpio-cfg = <1 3>;
+ clocks = <&clks IMX6UL_CLK_SAI2>;
+ clock-names = "mclk";
};
camera@3c {
diff --git a/src/arm/imx7d-sdb.dts b/src/arm/imx7d-sdb.dts
index ac0751b..4a0d837 100644
--- a/src/arm/imx7d-sdb.dts
+++ b/src/arm/imx7d-sdb.dts
@@ -164,6 +164,13 @@
"LINPUT1", "AMIC",
"AMIC", "MICB";
};
+
+ sound-hdmi {
+ compatible = "fsl,imx-audio-sii902x";
+ model = "sii902x-audio";
+ audio-cpu = <&sai3>;
+ hdmi-out;
+ };
};
&adc1 {
diff --git a/src/arm/intel-ixp42x-linksys-nslu2.dts b/src/arm/intel-ixp42x-linksys-nslu2.dts
index 8fcd958..5b8dcc1 100644
--- a/src/arm/intel-ixp42x-linksys-nslu2.dts
+++ b/src/arm/intel-ixp42x-linksys-nslu2.dts
@@ -90,20 +90,71 @@
timeout-ms = <5000>;
};
- /* The first 16MB region on the expansion bus */
- flash@50000000 {
- compatible = "intel,ixp4xx-flash", "cfi-flash";
- bank-width = <2>;
- /*
- * 8 MB of Flash in 0x20000 byte blocks
- * mapped in at 0x50000000
- */
- reg = <0x50000000 0x800000>;
+ gpio-beeper {
+ compatible = "gpio-beeper";
+ gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ };
- partitions {
- compatible = "redboot-fis";
- /* Eraseblock at 0x7e0000 */
- fis-index-block = <0x3f>;
+ soc {
+ bus@50000000 {
+ /* The first 16MB region at CS0 on the expansion bus */
+ flash@0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+ * 8 MB of Flash in 0x20000 byte blocks
+ * mapped in at CS0.
+ */
+ reg = <0x00000000 0x800000>;
+
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x7e0000 */
+ fis-index-block = <0x3f>;
+ };
+ };
+ };
+
+ pci@c0000000 {
+ status = "ok";
+
+ /*
+ * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant
+ * We have slots (IDSEL) 1, 2 and 3.
+ */
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+ /* IDSEL 2 */
+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
+ <0x1000 0 0 3 &gpio0 11 3>, /* INT C on slot 2 is irq 11 */
+ <0x1000 0 0 4 &gpio0 8 3>, /* INT D on slot 2 is irq 8 */
+ /* IDSEL 3 */
+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
+ <0x1800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+ <0x1800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+ <0x1800 0 0 4 &gpio0 8 3>; /* INT D on slot 3 is irq 8 */
+ };
+
+ ethernet@c8009000 {
+ status = "ok";
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
};
};
};
diff --git a/src/arm/intel-ixp42x-welltech-epbx100.dts b/src/arm/intel-ixp42x-welltech-epbx100.dts
new file mode 100644
index 0000000..8415850
--- /dev/null
+++ b/src/arm/intel-ixp42x-welltech-epbx100.dts
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Corentin Labbe <clabbe@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "intel-ixp42x.dtsi"
+
+/ {
+ model = "Welltech EPBX100";
+ compatible = "welltech,epbx100", "intel,ixp42x";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory@0 {
+ /* 64 MB SDRAM */
+ device_type = "memory";
+ reg = <0x00000000 0x4000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 root=/dev/ram0 initrd=0x00800000,9M";
+ stdout-path = "uart0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ flash@50000000 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+ * 16 MB of Flash
+ */
+ reg = <0x50000000 0x1000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "RedBoot";
+ reg = <0x00000000 0x00080000>;
+ read-only;
+ };
+ partition@80000 {
+ label = "zImage";
+ reg = <0x00080000 0x00100000>;
+ read-only;
+ };
+ partition@180000 {
+ label = "ramdisk";
+ reg = <0x00180000 0x00300000>;
+ read-only;
+ };
+ partition@480000 {
+ label = "User";
+ reg = <0x00480000 0x00b60000>;
+ read-only;
+ };
+ partition@fe0000 {
+ label = "FIS directory";
+ reg = <0x00fe0000 0x001f000>;
+ read-only;
+ };
+ partition@fff000 {
+ label = "RedBoot config";
+ reg = <0x00fff000 0x0001000>;
+ read-only;
+ };
+ };
+ };
+};
diff --git a/src/arm/intel-ixp42x.dtsi b/src/arm/intel-ixp42x.dtsi
index a9622ca..5fa063e 100644
--- a/src/arm/intel-ixp42x.dtsi
+++ b/src/arm/intel-ixp42x.dtsi
@@ -7,6 +7,10 @@
/ {
soc {
+ pci@c0000000 {
+ compatible = "intel,ixp42x-pci";
+ };
+
interrupt-controller@c8003000 {
compatible = "intel,ixp42x-interrupt";
};
diff --git a/src/arm/intel-ixp43x-gateworks-gw2358.dts b/src/arm/intel-ixp43x-gateworks-gw2358.dts
index ba1163a..60a1228 100644
--- a/src/arm/intel-ixp43x-gateworks-gw2358.dts
+++ b/src/arm/intel-ixp43x-gateworks-gw2358.dts
@@ -76,19 +76,97 @@
};
};
- flash@50000000 {
- compatible = "intel,ixp4xx-flash", "cfi-flash";
- bank-width = <2>;
- /*
- * 32 MB of Flash in 0x20000 byte blocks
- * mapped in at 0x50000000
- */
- reg = <0x50000000 0x2000000>;
+ soc {
+ bus@50000000 {
+ flash@0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
+ /*
+ * 32 MB of Flash in 0x20000 byte blocks
+ * mapped in at CS0.
+ */
+ reg = <0x00000000 0x2000000>;
- partitions {
- compatible = "redboot-fis";
- /* Eraseblock at 0x1fe0000 */
- fis-index-block = <0xff>;
+ partitions {
+ compatible = "redboot-fis";
+ /* Eraseblock at 0x1fe0000 */
+ fis-index-block = <0xff>;
+ };
+ };
+ };
+
+ pci@c0000000 {
+ status = "ok";
+
+ /*
+ * In the boardfile for the Cambria from OpenWRT the interrupts
+ * are assigned one per IDSEL, so all 4 interrupts from IDSEL
+ * 1 are connected to IRQ 11, all 4 interrupts from IDSEL 2
+ * connected to IRQ 10 etc. I find this highly unlikely so I
+ * have instead assumed that they are rotated (swizzled) like
+ * this with 11, 10, 9, 8 for the 4 pins on IDSEL 1 etc.
+ */
+ interrupt-map =
+ /* IDSEL 1 */
+ <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
+ <0x0800 0 0 2 &gpio0 10 3>, /* INT B on slot 1 is irq 10 */
+ <0x0800 0 0 3 &gpio0 9 3>, /* INT C on slot 1 is irq 9 */
+ <0x0800 0 0 4 &gpio0 8 3>, /* INT D on slot 1 is irq 8 */
+ /* IDSEL 2 */
+ <0x1000 0 0 1 &gpio0 10 3>, /* INT A on slot 2 is irq 10 */
+ <0x1000 0 0 2 &gpio0 9 3>, /* INT B on slot 2 is irq 9 */
+ <0x1000 0 0 3 &gpio0 8 3>, /* INT C on slot 2 is irq 8 */
+ <0x1000 0 0 4 &gpio0 11 3>, /* INT D on slot 2 is irq 11 */
+ /* IDSEL 3 */
+ <0x1800 0 0 1 &gpio0 9 3>, /* INT A on slot 3 is irq 9 */
+ <0x1800 0 0 2 &gpio0 8 3>, /* INT B on slot 3 is irq 8 */
+ <0x1800 0 0 3 &gpio0 11 3>, /* INT C on slot 3 is irq 11 */
+ <0x1800 0 0 4 &gpio0 10 3>, /* INT D on slot 3 is irq 10 */
+ /* IDSEL 4 */
+ <0x2000 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
+ <0x2000 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+ <0x2000 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+ <0x2000 0 0 4 &gpio0 9 3>, /* INT D on slot 3 is irq 9 */
+ /* IDSEL 6 */
+ <0x3000 0 0 1 &gpio0 10 3>, /* INT A on slot 3 is irq 10 */
+ <0x3000 0 0 2 &gpio0 9 3>, /* INT B on slot 3 is irq 9 */
+ <0x3000 0 0 3 &gpio0 8 3>, /* INT C on slot 3 is irq 8 */
+ <0x3000 0 0 4 &gpio0 11 3>, /* INT D on slot 3 is irq 11 */
+ /* IDSEL 15 */
+ <0x7800 0 0 1 &gpio0 8 3>, /* INT A on slot 3 is irq 8 */
+ <0x7800 0 0 2 &gpio0 11 3>, /* INT B on slot 3 is irq 11 */
+ <0x7800 0 0 3 &gpio0 10 3>, /* INT C on slot 3 is irq 10 */
+ <0x7800 0 0 4 &gpio0 9 3>; /* INT D on slot 3 is irq 9 */
+ };
+
+ ethernet@c800a000 {
+ status = "ok";
+ queue-rx = <&qmgr 4>;
+ queue-txready = <&qmgr 21>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy1>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ ethernet@c800c000 {
+ status = "ok";
+ queue-rx = <&qmgr 2>;
+ queue-txready = <&qmgr 19>;
+ phy-mode = "rgmii";
+ phy-handle = <&phy2>;
+ intel,npe-handle = <&npe 0>;
};
};
};
diff --git a/src/arm/intel-ixp43x.dtsi b/src/arm/intel-ixp43x.dtsi
index 494fb2f..1d0817c 100644
--- a/src/arm/intel-ixp43x.dtsi
+++ b/src/arm/intel-ixp43x.dtsi
@@ -8,6 +8,10 @@
/ {
soc {
+ pci@c0000000 {
+ compatible = "intel,ixp43x-pci";
+ };
+
interrupt-controller@c8003000 {
compatible = "intel,ixp43x-interrupt";
};
diff --git a/src/arm/intel-ixp45x-ixp46x.dtsi b/src/arm/intel-ixp45x-ixp46x.dtsi
index f8cd506..cce49e8 100644
--- a/src/arm/intel-ixp45x-ixp46x.dtsi
+++ b/src/arm/intel-ixp45x-ixp46x.dtsi
@@ -30,5 +30,38 @@
interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ /* This is known as EthB1 */
+ ethernet@c800d000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800d000 0x1000>;
+ status = "disabled";
+ intel,npe = <1>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
+
+ /* This is known as EthB2 */
+ ethernet@c800e000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800e000 0x1000>;
+ status = "disabled";
+ intel,npe = <2>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
+
+ /* This is known as EthB3 */
+ ethernet@c800f000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800f000 0x1000>;
+ status = "disabled";
+ intel,npe = <3>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
};
};
diff --git a/src/arm/intel-ixp4xx.dtsi b/src/arm/intel-ixp4xx.dtsi
index d4a0958..a50427a 100644
--- a/src/arm/intel-ixp4xx.dtsi
+++ b/src/arm/intel-ixp4xx.dtsi
@@ -14,12 +14,61 @@
compatible = "simple-bus";
interrupt-parent = <&intcon>;
+ /*
+ * The IXP4xx expansion bus is a set of 16 or 32MB
+ * windows in the 256MB space from 0x50000000 to
+ * 0x5fffffff.
+ */
+ bus@50000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x50000000 0x10000000>;
+ dma-ranges = <0x00000000 0x50000000 0x10000000>;
+ };
+
qmgr: queue-manager@60000000 {
compatible = "intel,ixp4xx-ahb-queue-manager";
reg = <0x60000000 0x4000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>;
};
+ pci@c0000000 {
+ /* compatible filled in by per-soc device tree */
+ reg = <0xc0000000 0x1000>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>,
+ <9 IRQ_TYPE_LEVEL_HIGH>,
+ <10 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ status = "disabled";
+
+ ranges =
+ /*
+ * 64MB 32bit non-prefetchable memory 0x48000000-0x4bffffff
+ * done in 4 chunks of 16MB each.
+ */
+ <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
+ /* 64KB I/O space at 0x4c000000 */
+ <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
+
+ /*
+ * This needs to map to the start of physical memory so
+ * PCI devices can see all (hopefully) memory. This is done
+ * using 4 1:1 16MB windows, so the RAM should not be more than
+ * 64 MB for this to work. If your memory is anywhere else
+ * than at 0x0 you need to alter this.
+ */
+ dma-ranges =
+ <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ /* Each unique DTS using PCI must specify the swizzling */
+ };
+
uart0: serial@c8000000 {
compatible = "intel,xscale-uart";
reg = <0xc8000000 0x1000>;
@@ -61,9 +110,50 @@
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
};
- npe@c8006000 {
+ npe: npe@c8006000 {
compatible = "intel,ixp4xx-network-processing-engine";
reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
+
+ /* NPE-C contains a crypto accelerator */
+ crypto {
+ compatible = "intel,ixp4xx-crypto";
+ intel,npe-handle = <&npe 2>;
+ queue-rx = <&qmgr 30>;
+ queue-txready = <&qmgr 29>;
+ };
+ };
+
+ /* This is known as EthB */
+ ethernet@c8009000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc8009000 0x1000>;
+ status = "disabled";
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 3>;
+ queue-txready = <&qmgr 20>;
+ intel,npe-handle = <&npe 1>;
+ };
+
+ /* This is known as EthC */
+ ethernet@c800a000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800a000 0x1000>;
+ status = "disabled";
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ intel,npe-handle = <&npe 2>;
+ };
+
+ /* This is known as EthA */
+ ethernet@c800c000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800c000 0x1000>;
+ status = "disabled";
+ intel,npe = <0>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
};
};
};
diff --git a/src/arm/keystone-k2g-evm.dts b/src/arm/keystone-k2g-evm.dts
index 14e26a4..d800f26 100644
--- a/src/arm/keystone-k2g-evm.dts
+++ b/src/arm/keystone-k2g-evm.dts
@@ -544,20 +544,15 @@
};
};
-&k2g_clks {
- /* on the board 22.5792MHz is connected to AUDOSC_IN */
- assigned-clocks = <&k2g_clks 0x4c 2>;
- assigned-clock-rates = <22579200>;
-};
-
&mcasp2 {
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcasp2_pins>;
- assigned-clocks = <&k2g_clks 0x6 1>;
- assigned-clock-parents = <&k2g_clks 0x6 2>;
+ assigned-clocks = <&k2g_clks 0x4c 2>, <&k2g_clks 0x6 1>;
+ assigned-clock-parents = <0>, <&k2g_clks 0x6 2>;
+ assigned-clock-rates = <22579200>, <0>;
status = "okay";
diff --git a/src/arm/keystone-k2g.dtsi b/src/arm/keystone-k2g.dtsi
index 05a7501..3719829 100644
--- a/src/arm/keystone-k2g.dtsi
+++ b/src/arm/keystone-k2g.dtsi
@@ -242,7 +242,7 @@
status = "disabled";
};
- msgmgr: msgmgr@2a00000 {
+ msgmgr: mailbox@2a00000 {
compatible = "ti,k2g-message-manager";
#mbox-cells = <2>;
reg-names = "queue_proxy_region",
@@ -254,7 +254,7 @@
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
};
- pmmc: pmmc@2921c00 {
+ pmmc: system-controller@2921c00 {
compatible = "ti,k2g-sci";
/*
* In case of rare platforms that does not use k2g as
@@ -272,7 +272,7 @@
#power-domain-cells = <1>;
};
- k2g_clks: clocks {
+ k2g_clks: clock-controller {
compatible = "ti,k2g-sci-clk";
#clock-cells = <2>;
};
diff --git a/src/arm/meson.dtsi b/src/arm/meson.dtsi
index 8bae6ed..bd0e864 100644
--- a/src/arm/meson.dtsi
+++ b/src/arm/meson.dtsi
@@ -50,6 +50,7 @@
compatible = "amlogic,meson6-uart", "amlogic,meson-uart";
reg = <0x84c0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
+ fifo-size = <128>;
status = "disabled";
};
diff --git a/src/arm/mstar-v7.dtsi b/src/arm/mstar-v7.dtsi
index 075d583..2273295 100644
--- a/src/arm/mstar-v7.dtsi
+++ b/src/arm/mstar-v7.dtsi
@@ -60,6 +60,14 @@
clock-frequency = <32768>;
status = "disabled";
};
+
+ xtal_div2: xtal_div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&xtal>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
soc: soc {
@@ -101,6 +109,12 @@
mask = <0x79>;
};
+ watchdog@6000 {
+ compatible = "mstar,msc313e-wdt";
+ reg = <0x6000 0x1f>;
+ clocks = <&xtal_div2>;
+ };
+
intc_fiq: interrupt-controller@201310 {
compatible = "mstar,mst-intc";
reg = <0x201310 0x40>;
diff --git a/src/arm/omap2.dtsi b/src/arm/omap2.dtsi
index f9c2a99..5750ca1 100644
--- a/src/arm/omap2.dtsi
+++ b/src/arm/omap2.dtsi
@@ -120,8 +120,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <56>;
- dmas = <&sdma 27 &sdma 28>;
- dma-names = "tx", "rx";
};
i2c2: i2c@48072000 {
@@ -131,8 +129,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <57>;
- dmas = <&sdma 29 &sdma 30>;
- dma-names = "tx", "rx";
};
mcspi1: spi@48098000 {
diff --git a/src/arm/omap2420.dtsi b/src/arm/omap2420.dtsi
index 494bf69..bb529a2 100644
--- a/src/arm/omap2420.dtsi
+++ b/src/arm/omap2420.dtsi
@@ -192,16 +192,15 @@
compatible = "ti,omap2-mailbox";
reg = <0x48094000 0x200>;
interrupts = <26>, <34>;
- interrupt-names = "dsp", "iva";
ti,hwmods = "mailbox";
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
- mbox_dsp: dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_iva: iva {
+ mbox_iva: mbox-iva {
ti,mbox-tx = <2 1 3>;
ti,mbox-rx = <3 1 3>;
};
diff --git a/src/arm/omap2430.dtsi b/src/arm/omap2430.dtsi
index d19d8ba..23115ba 100644
--- a/src/arm/omap2430.dtsi
+++ b/src/arm/omap2430.dtsi
@@ -284,7 +284,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <6>;
- mbox_dsp: dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
diff --git a/src/arm/omap3-evm-processor-common.dtsi b/src/arm/omap3-evm-processor-common.dtsi
index b4109f4..e6ba30a 100644
--- a/src/arm/omap3-evm-processor-common.dtsi
+++ b/src/arm/omap3-evm-processor-common.dtsi
@@ -195,7 +195,7 @@
* for bus switch SN74CB3Q3384A, level-shifter SN74AVC16T245DGGR, and 1.8V.
*/
&gpio2 {
- en_usb2_port {
+ en-usb2-port-hog {
gpio-hog;
gpios = <29 GPIO_ACTIVE_HIGH>; /* gpio_61 */
output-low;
diff --git a/src/arm/omap3-gta04a5.dts b/src/arm/omap3-gta04a5.dts
index fd84bbf..9ce8d81 100644
--- a/src/arm/omap3-gta04a5.dts
+++ b/src/arm/omap3-gta04a5.dts
@@ -37,7 +37,7 @@
};
&gpio5 {
- irda_en {
+ irda-en-hog {
gpio-hog;
gpios = <(175-160) GPIO_ACTIVE_HIGH>;
output-high; /* activate gpio_175 to disable IrDA receiver */
diff --git a/src/arm/omap3.dtsi b/src/arm/omap3.dtsi
index c5b9da0..64b7e6f 100644
--- a/src/arm/omap3.dtsi
+++ b/src/arm/omap3.dtsi
@@ -403,8 +403,6 @@
compatible = "ti,omap3-i2c";
reg = <0x48070000 0x80>;
interrupts = <56>;
- dmas = <&sdma 27 &sdma 28>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c1";
@@ -414,8 +412,6 @@
compatible = "ti,omap3-i2c";
reg = <0x48072000 0x80>;
interrupts = <57>;
- dmas = <&sdma 29 &sdma 30>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c2";
@@ -425,8 +421,6 @@
compatible = "ti,omap3-i2c";
reg = <0x48060000 0x80>;
interrupts = <61>;
- dmas = <&sdma 25 &sdma 26>;
- dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "i2c3";
@@ -440,7 +434,7 @@
#mbox-cells = <1>;
ti,mbox-num-users = <2>;
ti,mbox-num-fifos = <2>;
- mbox_dsp: dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
diff --git a/src/arm/omap4-l4.dtsi b/src/arm/omap4-l4.dtsi
index 9972167..46b8f9e 100644
--- a/src/arm/omap4-l4.dtsi
+++ b/src/arm/omap4-l4.dtsi
@@ -600,11 +600,11 @@
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
+ mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
diff --git a/src/arm/omap5-board-common.dtsi b/src/arm/omap5-board-common.dtsi
index d8f1362..45435bb 100644
--- a/src/arm/omap5-board-common.dtsi
+++ b/src/arm/omap5-board-common.dtsi
@@ -149,7 +149,7 @@
&gpio8 {
/* TI trees use GPIO instead of msecure, see also muxing */
- p234 {
+ msecure-hog {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
diff --git a/src/arm/omap5-l4.dtsi b/src/arm/omap5-l4.dtsi
index b148b28..06cc3a1 100644
--- a/src/arm/omap5-l4.dtsi
+++ b/src/arm/omap5-l4.dtsi
@@ -616,11 +616,11 @@
#mbox-cells = <1>;
ti,mbox-num-users = <3>;
ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
+ mbox_ipu: mbox-ipu {
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <1 0 0>;
};
- mbox_dsp: mbox_dsp {
+ mbox_dsp: mbox-dsp {
ti,mbox-tx = <3 0 0>;
ti,mbox-rx = <2 0 0>;
};
diff --git a/src/arm/openbmc-flash-layout-64.dtsi b/src/arm/openbmc-flash-layout-64.dtsi
index 9116386..31f59de 100644
--- a/src/arm/openbmc-flash-layout-64.dtsi
+++ b/src/arm/openbmc-flash-layout-64.dtsi
@@ -9,27 +9,27 @@
#size-cells = <1>;
u-boot@0 {
- reg = <0x0 0x60000>; // 384KB
+ reg = <0x0 0xe0000>; // 896KB
label = "u-boot";
};
- u-boot-env@60000 {
- reg = <0x60000 0x20000>; // 128KB
+ u-boot-env@e0000 {
+ reg = <0xe0000 0x20000>; // 128KB
label = "u-boot-env";
};
- kernel@80000 {
- reg = <0x80000 0x500000>; // 5MB
+ kernel@100000 {
+ reg = <0x100000 0x900000>; // 9MB
label = "kernel";
};
- rofs@580000 {
- reg = <0x580000 0x2a80000>; // 42.5MB
+ rofs@a00000 {
+ reg = <0xa00000 0x2000000>; // 32MB
label = "rofs";
};
- rwfs@3000000 {
- reg = <0x3000000 0x1000000>; // 16MB
+ rwfs@6000000 {
+ reg = <0x2a00000 0x1600000>; // 22MB
label = "rwfs";
};
};
diff --git a/src/arm/qcom-ipq8064-rb3011.dts b/src/arm/qcom-ipq8064-rb3011.dts
index 282b89c..f7ea2e5 100644
--- a/src/arm/qcom-ipq8064-rb3011.dts
+++ b/src/arm/qcom-ipq8064-rb3011.dts
@@ -216,6 +216,10 @@
};
};
+&adm_dma {
+ status = "okay";
+};
+
&gmac0 {
status = "okay";
@@ -251,6 +255,39 @@
status = "okay";
};
+&hs_phy_1 {
+ status = "okay";
+};
+
+&nand {
+ status = "okay";
+
+ nandcs@0 {
+ compatible = "qcom,nandcs";
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-bus-width = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boot@0 {
+ label = "RouterBoard NAND 1 Boot";
+ reg = <0x0000000 0x0800000>;
+ };
+
+ main@800000 {
+ label = "RouterBoard NAND 1 Main";
+ reg = <0x0800000 0x7800000>;
+ };
+ };
+ };
+};
+
&qcom_pinmux {
buttons_pins: buttons_pins {
mux {
@@ -305,4 +342,25 @@
input-disable;
};
};
+
+ usb1_pwr_en_pins: usb1_pwr_en_pins {
+ mux {
+ pins = "gpio4";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&ss_phy_1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ pinctrl-0 = <&usb1_pwr_en_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
};
diff --git a/src/arm/qcom-ipq8064.dtsi b/src/arm/qcom-ipq8064.dtsi
index 98995ea..7bcf5ef 100644
--- a/src/arm/qcom-ipq8064.dtsi
+++ b/src/arm/qcom-ipq8064.dtsi
@@ -2,6 +2,8 @@
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/gpio/gpio.h>
@@ -46,6 +48,228 @@
};
};
+ thermal-zones {
+ tsens_tz_sensor0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 0>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 1>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 2>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor3 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 3>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor4 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 4>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor5 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 5>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor6 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 6>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor7 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 7>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor8 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 8>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor9 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 9>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ tsens_tz_sensor10 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 10>;
+
+ trips {
+ cpu-critical {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu-hot {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+ };
+
memory {
device_type = "memory";
reg = <0x0 0x0>;
@@ -185,6 +409,31 @@
bias-pull-up;
};
};
+
+ nand_pins: nand_pins {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39",
+ "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
+ bias-disable;
+ };
+
+ pullups {
+ pins = "gpio39";
+ bias-pull-up;
+ };
+
+ hold {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45",
+ "gpio46", "gpio47";
+ bias-bus-hold;
+ };
+ };
};
intc: interrupt-controller@2000000 {
@@ -226,6 +475,26 @@
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
};
+ adm_dma: dma-controller@18300000 {
+ compatible = "qcom,adm";
+ reg = <0x18300000 0x100000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+ clock-names = "core", "iface";
+
+ resets = <&gcc ADM0_RESET>,
+ <&gcc ADM0_PBUS_RESET>,
+ <&gcc ADM0_C0_RESET>,
+ <&gcc ADM0_C1_RESET>,
+ <&gcc ADM0_C2_RESET>;
+ reset-names = "clk", "pbus", "c0", "c1", "c2";
+ qcom,ee = <0>;
+
+ status = "disabled";
+ };
+
saw0: regulator@2089000 {
compatible = "qcom,saw2";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
@@ -403,6 +672,28 @@
status = "disabled";
};
+ nand: nand-controller@1ac00000 {
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1ac00000 0x800>;
+
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
sata: sata@29000000 {
compatible = "qcom,ipq806x-ahci", "generic-ahci";
reg = <0x29000000 0x180>;
@@ -436,6 +727,12 @@
reg = <0x00700000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+ tsens_calib: calib@400 {
+ reg = <0x400 0xb>;
+ };
+ tsens_calib_backup: calib_backup@410 {
+ reg = <0x410 0xb>;
+ };
};
gcc: clock-controller@900000 {
@@ -443,6 +740,38 @@
reg = <0x00900000 0x4000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ tsens: thermal-sensor@900000 {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ rpm: rpm@108000 {
+ compatible = "qcom,rpm-ipq8064";
+ reg = <0x108000 0x1000>;
+ qcom,ipc = <&l2cc 0x8 2>;
+
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ack", "err", "wakeup";
+
+ clocks = <&gcc RPM_MSG_RAM_H_CLK>;
+ clock-names = "ram";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
};
tcsr: syscon@1a400000 {
@@ -450,6 +779,14 @@
reg = <0x1a400000 0x100>;
};
+ l2cc: clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu_l2_aux";
+ };
+
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
@@ -718,6 +1055,94 @@
status = "disabled";
};
+ hs_phy_0: phy@100f8800 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ss_phy_0: phy@100f8830 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb3_0: usb3@100f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x100f8800 0x8000>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_0_MASTER_RESET>;
+ reset-names = "master";
+
+ status = "disabled";
+
+ dwc3_0: dwc3@10000000 {
+ compatible = "snps,dwc3";
+ reg = <0x10000000 0xcd00>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_0>, <&ss_phy_0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
+ hs_phy_1: phy@110f8800 {
+ compatible = "qcom,ipq806x-usb-phy-hs";
+ reg = <0x110f8800 0x30>;
+ clocks = <&gcc USB30_1_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ ss_phy_1: phy@110f8830 {
+ compatible = "qcom,ipq806x-usb-phy-ss";
+ reg = <0x110f8830 0x30>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+ };
+
+ usb3_1: usb3@110f8800 {
+ compatible = "qcom,dwc3", "syscon";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x110f8800 0x8000>;
+ clocks = <&gcc USB30_1_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ resets = <&gcc USB30_1_MASTER_RESET>;
+ reset-names = "master";
+
+ status = "disabled";
+
+ dwc3_1: dwc3@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0xcd00>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&hs_phy_1>, <&ss_phy_1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ snps,dis_u3_susphy_quirk;
+ };
+ };
+
vsdcc_fixed: vsdcc-regulator {
compatible = "regulator-fixed";
regulator-name = "SDCC Power";
diff --git a/src/arm/qcom-sdx55-t55.dts b/src/arm/qcom-sdx55-t55.dts
index ddcd53a..2ffcd08 100644
--- a/src/arm/qcom-sdx55-t55.dts
+++ b/src/arm/qcom-sdx55-t55.dts
@@ -250,7 +250,7 @@
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* efs2 partition is secured */
- secure-regions = <0x500000 0xb00000>;
+ secure-regions = /bits/ 64 <0x500000 0xb00000>;
};
};
diff --git a/src/arm/qcom-sdx55-telit-fn980-tlb.dts b/src/arm/qcom-sdx55-telit-fn980-tlb.dts
index 3065f84..80c40da 100644
--- a/src/arm/qcom-sdx55-telit-fn980-tlb.dts
+++ b/src/arm/qcom-sdx55-telit-fn980-tlb.dts
@@ -250,8 +250,8 @@
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
/* ico and efs2 partitions are secured */
- secure-regions = <0x500000 0x500000
- 0xa00000 0xb00000>;
+ secure-regions = /bits/ 64 <0x500000 0x500000
+ 0xa00000 0xb00000>;
};
};
diff --git a/src/arm/r8a7742.dtsi b/src/arm/r8a7742.dtsi
index dd1b976..a227968 100644
--- a/src/arm/r8a7742.dtsi
+++ b/src/arm/r8a7742.dtsi
@@ -47,7 +47,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -56,6 +55,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -77,6 +77,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -98,6 +99,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -119,6 +121,7 @@
clock-frequency = <1400000000>;
clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -750,6 +753,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a7743.dtsi b/src/arm/r8a7743.dtsi
index 6e37b8d..7e5e09d 100644
--- a/src/arm/r8a7743.dtsi
+++ b/src/arm/r8a7743.dtsi
@@ -49,7 +49,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -59,6 +58,7 @@
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@
clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -702,6 +703,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a7744.dtsi b/src/arm/r8a7744.dtsi
index ace2086..8419683 100644
--- a/src/arm/r8a7744.dtsi
+++ b/src/arm/r8a7744.dtsi
@@ -49,7 +49,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -59,6 +58,7 @@
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -78,6 +78,7 @@
clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
clock-latency = <300000>; /* 300 us */
power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
/* kHz - uV - OPPs unknown yet */
@@ -702,6 +703,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a7745.dtsi b/src/arm/r8a7745.dtsi
index be33bda..f877c51 100644
--- a/src/arm/r8a7745.dtsi
+++ b/src/arm/r8a7745.dtsi
@@ -64,7 +64,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -73,6 +72,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -83,6 +83,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -645,6 +646,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a77470.dtsi b/src/arm/r8a77470.dtsi
index a1d7f6e..13ef1e9 100644
--- a/src/arm/r8a77470.dtsi
+++ b/src/arm/r8a77470.dtsi
@@ -25,7 +25,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -34,6 +33,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
power-domains = <&sysc R8A77470_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -44,6 +44,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A77470_CLK_Z2>;
power-domains = <&sysc R8A77470_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -537,6 +538,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a7778.dtsi b/src/arm/r8a7778.dtsi
index c9f8735..95efbaf 100644
--- a/src/arm/r8a7778.dtsi
+++ b/src/arm/r8a7778.dtsi
@@ -166,6 +166,7 @@
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
power-domains = <&cpg_clocks>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -177,6 +178,7 @@
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
power-domains = <&cpg_clocks>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -188,6 +190,7 @@
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
power-domains = <&cpg_clocks>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
diff --git a/src/arm/r8a7779-marzen.dts b/src/arm/r8a7779-marzen.dts
index d2240b8..4658453 100644
--- a/src/arm/r8a7779-marzen.dts
+++ b/src/arm/r8a7779-marzen.dts
@@ -145,7 +145,7 @@
status = "okay";
clocks = <&mstp1_clks R8A7779_CLK_DU>, <&x3_clk>;
- clock-names = "du", "dclkin.0";
+ clock-names = "du.0", "dclkin.0";
ports {
port@0 {
diff --git a/src/arm/r8a7779.dtsi b/src/arm/r8a7779.dtsi
index 74d7e90..39fc58f 100644
--- a/src/arm/r8a7779.dtsi
+++ b/src/arm/r8a7779.dtsi
@@ -198,6 +198,7 @@
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -209,6 +210,7 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -220,6 +222,7 @@
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
+ i2c-scl-internal-delay-ns = <5>;
status = "disabled";
};
@@ -463,6 +466,7 @@
reg = <0xfff80000 0x40000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7779_CLK_DU>;
+ clock-names = "du.0";
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
status = "disabled";
diff --git a/src/arm/r8a7790-lager.dts b/src/arm/r8a7790-lager.dts
index 2dad074..fa6d986 100644
--- a/src/arm/r8a7790-lager.dts
+++ b/src/arm/r8a7790-lager.dts
@@ -81,6 +81,9 @@
keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
one {
linux,code = <KEY_1>;
label = "SW2-1";
@@ -659,6 +662,11 @@
groups = "audio_clk_a";
function = "audio_clk";
};
+
+ keyboard_pins: keyboard {
+ pins = "GP_1_14", "GP_1_24", "GP_1_26", "GP_1_28";
+ bias-pull-up;
+ };
};
ðer {
diff --git a/src/arm/r8a7790.dtsi b/src/arm/r8a7790.dtsi
index de29394..ed6dd4f 100644
--- a/src/arm/r8a7790.dtsi
+++ b/src/arm/r8a7790.dtsi
@@ -69,7 +69,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -78,6 +77,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -99,6 +99,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -120,6 +121,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -141,6 +143,7 @@
clock-frequency = <1300000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
capacity-dmips-mhz = <1024>;
voltage-tolerance = <1>; /* 1% */
@@ -162,6 +165,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -173,6 +177,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -184,6 +189,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU2>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -195,6 +201,7 @@
clock-frequency = <780000000>;
clocks = <&cpg CPG_CORE R8A7790_CLK_Z2>;
power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
capacity-dmips-mhz = <539>;
};
@@ -768,6 +775,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a7791-koelsch.dts b/src/arm/r8a7791-koelsch.dts
index 61e881b..2a8b6fd 100644
--- a/src/arm/r8a7791-koelsch.dts
+++ b/src/arm/r8a7791-koelsch.dts
@@ -81,7 +81,7 @@
keyboard {
compatible = "gpio-keys";
- pinctrl-0 = <&sw2_pins>;
+ pinctrl-0 = <&keyboard_pins>;
pinctrl-names = "default";
key-1 {
@@ -622,7 +622,7 @@
function = "audio_clk";
};
- sw2_pins: sw2 {
+ keyboard_pins: keyboard {
pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
bias-pull-up;
};
diff --git a/src/arm/r8a7791.dtsi b/src/arm/r8a7791.dtsi
index 9d8320f..0ccc162 100644
--- a/src/arm/r8a7791.dtsi
+++ b/src/arm/r8a7791.dtsi
@@ -68,7 +68,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -77,6 +76,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@@ -97,6 +97,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@@ -728,6 +729,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a7792-blanche.dts b/src/arm/r8a7792-blanche.dts
index c100ae9..62aa9f6 100644
--- a/src/arm/r8a7792-blanche.dts
+++ b/src/arm/r8a7792-blanche.dts
@@ -112,6 +112,9 @@
keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
key-1 {
linux,code = <KEY_1>;
label = "SW2-1";
@@ -235,6 +238,11 @@
function = "du1";
};
+ keyboard_pins: keyboard {
+ pins = "GP_3_10", "GP_3_11", "GP_3_12", "GP_3_15", "GP_11_02";
+ bias-pull-up;
+ };
+
pmic_irq_pins: pmicirq {
groups = "intc_irq2";
function = "intc";
diff --git a/src/arm/r8a7792.dtsi b/src/arm/r8a7792.dtsi
index 253e8bf..9cdb738 100644
--- a/src/arm/r8a7792.dtsi
+++ b/src/arm/r8a7792.dtsi
@@ -45,7 +45,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -54,6 +53,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
};
@@ -64,6 +64,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA15>;
};
@@ -537,6 +538,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/r8a7793-gose.dts b/src/arm/r8a7793-gose.dts
index 87fa57a..479e0fd 100644
--- a/src/arm/r8a7793-gose.dts
+++ b/src/arm/r8a7793-gose.dts
@@ -64,9 +64,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
- gpio-keys {
+ keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
key-1 {
gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_1>;
@@ -567,6 +570,11 @@
function = "audio_clk";
};
+ keyboard_pins: keyboard {
+ pins = "GP_5_0", "GP_5_1", "GP_5_2", "GP_5_3";
+ bias-pull-up;
+ };
+
vin0_pins: vin0 {
groups = "vin0_data24", "vin0_sync", "vin0_clkenb", "vin0_clk";
function = "vin0";
diff --git a/src/arm/r8a7793.dtsi b/src/arm/r8a7793.dtsi
index 6d74475..dea4b1e 100644
--- a/src/arm/r8a7793.dtsi
+++ b/src/arm/r8a7793.dtsi
@@ -60,7 +60,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +68,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
+ enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
@@ -89,6 +89,7 @@
clock-frequency = <1500000000>;
clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+ enable-method = "renesas,apmu";
voltage-tolerance = <1>; /* 1% */
clock-latency = <300000>; /* 300 us */
diff --git a/src/arm/r8a7794-alt.dts b/src/arm/r8a7794-alt.dts
index f9dba56..f330d79 100644
--- a/src/arm/r8a7794-alt.dts
+++ b/src/arm/r8a7794-alt.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "r8a7794.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Alt";
@@ -94,6 +95,42 @@
#size-cells = <1>;
};
+ keyboard {
+ compatible = "gpio-keys";
+
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
+ one {
+ linux,code = <KEY_1>;
+ label = "SW2-1";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
+ };
+ two {
+ linux,code = <KEY_2>;
+ label = "SW2-2";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 10 GPIO_ACTIVE_LOW>;
+ };
+ three {
+ linux,code = <KEY_3>;
+ label = "SW2-3";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ };
+ four {
+ linux,code = <KEY_4>;
+ label = "SW2-4";
+ wakeup-source;
+ debounce-interval = <20>;
+ gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
vga-encoder {
compatible = "adi,adv7123";
@@ -319,6 +356,11 @@
groups = "usb1";
function = "usb1";
};
+
+ keyboard_pins: keyboard {
+ pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
+ bias-pull-up;
+ };
};
&cmt0 {
diff --git a/src/arm/r8a7794-silk.dts b/src/arm/r8a7794-silk.dts
index eb89a27..cafa304 100644
--- a/src/arm/r8a7794-silk.dts
+++ b/src/arm/r8a7794-silk.dts
@@ -45,9 +45,12 @@
reg = <0 0x40000000 0 0x40000000>;
};
- gpio-keys {
+ keyboard {
compatible = "gpio-keys";
+ pinctrl-0 = <&keyboard_pins>;
+ pinctrl-names = "default";
+
key-3 {
gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
linux,code = <KEY_3>;
@@ -358,6 +361,11 @@
function = "du1";
};
+ keyboard_pins: keyboard {
+ pins = "GP_3_9", "GP_3_10", "GP_3_11", "GP_3_12";
+ bias-pull-up;
+ };
+
ssi_pins: sound {
groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data";
function = "ssi";
diff --git a/src/arm/r8a7794.dtsi b/src/arm/r8a7794.dtsi
index 330dc51..eac9ed8 100644
--- a/src/arm/r8a7794.dtsi
+++ b/src/arm/r8a7794.dtsi
@@ -62,7 +62,6 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
- enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -71,6 +70,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU0>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -81,6 +81,7 @@
clock-frequency = <1000000000>;
clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>;
power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
+ enable-method = "renesas,apmu";
next-level-cache = <&L2_CA7>;
};
@@ -598,6 +599,7 @@
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
diff --git a/src/arm/rk3036-kylin.dts b/src/arm/rk3036-kylin.dts
index 7154b82..e817eba 100644
--- a/src/arm/rk3036-kylin.dts
+++ b/src/arm/rk3036-kylin.dts
@@ -390,7 +390,7 @@
};
};
- sleep {
+ suspend {
global_pwroff: global-pwroff {
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
};
diff --git a/src/arm/rk3036.dtsi b/src/arm/rk3036.dtsi
index e24230d..ffa9bc7 100644
--- a/src/arm/rk3036.dtsi
+++ b/src/arm/rk3036.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3036-cru.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/power/rk3036-power.h>
/ {
#address-cells = <1>;
@@ -111,10 +112,32 @@
assigned-clock-rates = <100000000>;
clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3036_PD_GPU>;
resets = <&cru SRST_GPU>;
status = "disabled";
};
+ vpu: video-codec@10108000 {
+ compatible = "rockchip,rk3036-vpu";
+ reg = <0x10108000 0x800>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdpu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3036_PD_VPU>;
+ };
+
+ vpu_mmu: iommu@10108800 {
+ compatible = "rockchip,iommu";
+ reg = <0x10108800 0x100>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3036_PD_VPU>;
+ #iommu-cells = <0>;
+ };
+
vop: vop@10118000 {
compatible = "rockchip,rk3036-vop";
reg = <0x10118000 0x19c>;
@@ -124,6 +147,7 @@
resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
+ power-domains = <&power RK3036_PD_VIO>;
status = "disabled";
vop_out: port {
@@ -140,13 +164,28 @@
compatible = "rockchip,iommu";
reg = <0x10118300 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3036_PD_VIO>;
#iommu-cells = <0>;
status = "disabled";
};
+ qos_gpu: qos@1012d000 {
+ compatible = "rockchip,rk3036-qos", "syscon";
+ reg = <0x1012d000 0x20>;
+ };
+
+ qos_vpu: qos@1012e000 {
+ compatible = "rockchip,rk3036-qos", "syscon";
+ reg = <0x1012e000 0x20>;
+ };
+
+ qos_vio: qos@1012f000 {
+ compatible = "rockchip,rk3036-qos", "syscon";
+ reg = <0x1012f000 0x20>;
+ };
+
gic: interrupt-controller@10139000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -302,6 +341,37 @@
compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
reg = <0x20008000 0x1000>;
+ power: power-controller {
+ compatible = "rockchip,rk3036-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3036_PD_VIO {
+ reg = <RK3036_PD_VIO>;
+ clocks = <&cru ACLK_LCDC>,
+ <&cru HCLK_LCDC>,
+ <&cru SCLK_LCDC>;
+ pm_qos = <&qos_vio>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3036_PD_VPU {
+ reg = <RK3036_PD_VPU>;
+ clocks = <&cru ACLK_VCODEC>,
+ <&cru HCLK_VCODEC>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3036_PD_GPU {
+ reg = <RK3036_PD_GPU>;
+ clocks = <&cru SCLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+ };
+
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x1d8>;
diff --git a/src/arm/rk3066a-bqcurie2.dts b/src/arm/rk3066a-bqcurie2.dts
index eba7a13..390aa33 100644
--- a/src/arm/rk3066a-bqcurie2.dts
+++ b/src/arm/rk3066a-bqcurie2.dts
@@ -12,6 +12,11 @@
model = "bq Curie 2";
compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
diff --git a/src/arm/rk3066a-marsboard.dts b/src/arm/rk3066a-marsboard.dts
index 6b12165..a66d915 100644
--- a/src/arm/rk3066a-marsboard.dts
+++ b/src/arm/rk3066a-marsboard.dts
@@ -10,6 +10,10 @@
model = "MarsBoard RK3066";
compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
diff --git a/src/arm/rk3066a-mk808.dts b/src/arm/rk3066a-mk808.dts
index eed9e60..9790bc6 100644
--- a/src/arm/rk3066a-mk808.dts
+++ b/src/arm/rk3066a-mk808.dts
@@ -10,6 +10,11 @@
model = "Rikomagic MK808";
compatible = "rikomagic,mk808", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/src/arm/rk3066a-rayeager.dts b/src/arm/rk3066a-rayeager.dts
index 3095184..12b2e59 100644
--- a/src/arm/rk3066a-rayeager.dts
+++ b/src/arm/rk3066a-rayeager.dts
@@ -11,6 +11,12 @@
model = "Rayeager PX2";
compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &emmc;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x40000000>;
@@ -58,7 +64,7 @@
};
/* input for 5V_STDBY is VSYS or DC5V, selectable by jumper J4 */
- vcc_stdby: 5v-stdby-regulator {
+ vcc_stdby: stdby-regulator {
compatible = "regulator-fixed";
regulator-name = "5v_stdby";
regulator-min-microvolt = <5000000>;
diff --git a/src/arm/rk3066a.dtsi b/src/arm/rk3066a.dtsi
index 252750c..f5a665b 100644
--- a/src/arm/rk3066a.dtsi
+++ b/src/arm/rk3066a.dtsi
@@ -217,7 +217,7 @@
<150000000>, <75000000>;
};
- timer@2000e000 {
+ timer2: timer@2000e000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2000e000 0x100>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
@@ -238,7 +238,7 @@
};
};
- timer@20038000 {
+ timer0: timer@20038000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x20038000 0x100>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
@@ -246,7 +246,7 @@
clock-names = "timer", "pclk";
};
- timer@2003a000 {
+ timer1: timer@2003a000 {
compatible = "snps,dw-apb-timer-osc";
reg = <0x2003a000 0x100>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -266,30 +266,6 @@
status = "disabled";
};
- usbphy: phy {
- compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- usbphy0: usb-phy@17c {
- #phy-cells = <0>;
- reg = <0x17c>;
- clocks = <&cru SCLK_OTGPHY0>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
-
- usbphy1: usb-phy@188 {
- #phy-cells = <0>;
- reg = <0x188>;
- clocks = <&cru SCLK_OTGPHY1>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
- };
-
pinctrl: pinctrl {
compatible = "rockchip,rk3066a-pinctrl";
rockchip,grf = <&grf>;
@@ -702,6 +678,34 @@
power-domains = <&power RK3066_PD_GPU>;
};
+&grf {
+ compatible = "rockchip,rk3066-grf", "syscon", "simple-mfd";
+
+ usbphy: usbphy {
+ compatible = "rockchip,rk3066a-usb-phy",
+ "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy@17c {
+ reg = <0x17c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+ usbphy1: usb-phy@188 {
+ reg = <0x188>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
@@ -755,7 +759,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3066_PD_VIO {
+ power-domain@RK3066_PD_VIO {
reg = <RK3066_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
@@ -780,21 +784,24 @@
<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
- pd_video@RK3066_PD_VIDEO {
+ power-domain@RK3066_PD_VIDEO {
reg = <RK3066_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
- pd_gpu@RK3066_PD_GPU {
+ power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -861,6 +868,10 @@
pinctrl-0 = <&uart3_xfer>;
};
+&vpu {
+ power-domains = <&power RK3066_PD_VIDEO>;
+};
+
&wdt {
compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};
diff --git a/src/arm/rk3188-bqedison2qc.dts b/src/arm/rk3188-bqedison2qc.dts
index 66a0ff1..85d3fce 100644
--- a/src/arm/rk3188-bqedison2qc.dts
+++ b/src/arm/rk3188-bqedison2qc.dts
@@ -13,6 +13,12 @@
model = "BQ Edison2 Quad-Core";
compatible = "mundoreader,bq-edison2qc", "rockchip,rk3188";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ mmc2 = &emmc;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
diff --git a/src/arm/rk3188-px3-evb.dts b/src/arm/rk3188-px3-evb.dts
index c32e1d4..39c6042 100644
--- a/src/arm/rk3188-px3-evb.dts
+++ b/src/arm/rk3188-px3-evb.dts
@@ -11,6 +11,11 @@
model = "Rockchip PX3-EVB";
compatible = "rockchip,px3-evb", "rockchip,px3", "rockchip,rk3188";
+ aliases {
+ mmc0 = &mmc0;
+ mmc1 = &emmc;
+ };
+
chosen {
stdout-path = "serial2:115200n8";
};
diff --git a/src/arm/rk3188-radxarock.dts b/src/arm/rk3188-radxarock.dts
index b0fef82..36c0945 100644
--- a/src/arm/rk3188-radxarock.dts
+++ b/src/arm/rk3188-radxarock.dts
@@ -11,6 +11,10 @@
model = "Radxa Rock";
compatible = "radxa,rock", "rockchip,rk3188";
+ aliases {
+ mmc0 = &mmc0;
+ };
+
memory@60000000 {
device_type = "memory";
reg = <0x60000000 0x80000000>;
diff --git a/src/arm/rk3188.dtsi b/src/arm/rk3188.dtsi
index 2298a8d..793a1b9 100644
--- a/src/arm/rk3188.dtsi
+++ b/src/arm/rk3188.dtsi
@@ -150,16 +150,16 @@
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
+ clock-names = "pclk", "timer";
};
timer6: timer@200380a0 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x200380a0 0x20>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
+ clock-names = "pclk", "timer";
};
i2s0: i2s@1011a000 {
@@ -214,30 +214,6 @@
};
};
- usbphy: phy {
- compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
- rockchip,grf = <&grf>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- usbphy0: usb-phy@10c {
- #phy-cells = <0>;
- reg = <0x10c>;
- clocks = <&cru SCLK_OTGPHY0>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
-
- usbphy1: usb-phy@11c {
- #phy-cells = <0>;
- reg = <0x11c>;
- clocks = <&cru SCLK_OTGPHY1>;
- clock-names = "phyclk";
- #clock-cells = <0>;
- };
- };
-
pinctrl: pinctrl {
compatible = "rockchip,rk3188-pinctrl";
rockchip,grf = <&grf>;
@@ -662,6 +638,34 @@
power-domains = <&power RK3188_PD_GPU>;
};
+&grf{
+ compatible = "rockchip,rk3188-grf", "syscon", "simple-mfd";
+
+ usbphy: usbphy {
+ compatible = "rockchip,rk3188-usb-phy",
+ "rockchip,rk3288-usb-phy";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ usbphy0: usb-phy@10c {
+ reg = <0x10c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+
+ usbphy1: usb-phy@11c {
+ reg = <0x11c>;
+ clocks = <&cru SCLK_OTGPHY1>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ };
+ };
+};
+
&i2c0 {
compatible = "rockchip,rk3188-i2c";
pinctrl-names = "default";
@@ -699,7 +703,7 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_vio@RK3188_PD_VIO {
+ power-domain@RK3188_PD_VIO {
reg = <RK3188_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
@@ -719,21 +723,24 @@
<&qos_cif0>,
<&qos_ipp>,
<&qos_rga>;
+ #power-domain-cells = <0>;
};
- pd_video@RK3188_PD_VIDEO {
+ power-domain@RK3188_PD_VIDEO {
reg = <RK3188_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
};
- pd_gpu@RK3188_PD_GPU {
+ power-domain@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -794,6 +801,11 @@
pinctrl-0 = <&uart3_xfer>;
};
+&vpu {
+ compatible = "rockchip,rk3188-vpu", "rockchip,rk3066-vpu";
+ power-domains = <&power RK3188_PD_VIDEO>;
+};
+
&wdt {
compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
};
diff --git a/src/arm/rk322x.dtsi b/src/arm/rk322x.dtsi
index 208f212..75af99c 100644
--- a/src/arm/rk322x.dtsi
+++ b/src/arm/rk322x.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/rk3228-power.h>
/ {
#address-cells = <1>;
@@ -190,7 +191,65 @@
status = "disabled";
};
- u2phy0: usb2-phy@760 {
+ power: power-controller {
+ compatible = "rockchip,rk3228-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RK3228_PD_VIO {
+ reg = <RK3228_PD_VIO>;
+ clocks = <&cru ACLK_HDCP>,
+ <&cru SCLK_HDCP>,
+ <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>,
+ <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>,
+ <&cru SCLK_RGA>;
+ pm_qos = <&qos_hdcp>,
+ <&qos_iep>,
+ <&qos_rga_r>,
+ <&qos_rga_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_VOP {
+ reg = <RK3228_PD_VOP>;
+ clocks =<&cru ACLK_VOP>,
+ <&cru DCLK_VOP>,
+ <&cru HCLK_VOP>;
+ pm_qos = <&qos_vop>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_VPU {
+ reg = <RK3228_PD_VPU>;
+ clocks = <&cru ACLK_VPU>,
+ <&cru HCLK_VPU>;
+ pm_qos = <&qos_vpu>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_RKVDEC {
+ reg = <RK3228_PD_RKVDEC>;
+ clocks = <&cru ACLK_RKVDEC>,
+ <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>,
+ <&cru SCLK_VDEC_CORE>;
+ pm_qos = <&qos_rkvdec_r>,
+ <&qos_rkvdec_w>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RK3228_PD_GPU {
+ reg = <RK3228_PD_GPU>;
+ clocks = <&cru ACLK_GPU>;
+ pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ u2phy0: usb2phy@760 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0760 0x0c>;
clocks = <&cru SCLK_OTGPHY0>;
@@ -217,7 +276,7 @@
};
};
- u2phy1: usb2-phy@800 {
+ u2phy1: usb2phy@800 {
compatible = "rockchip,rk3228-usb2phy";
reg = <0x0800 0x0c>;
clocks = <&cru SCLK_OTGPHY1>;
@@ -379,7 +438,6 @@
reg = <0x110b0000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm0_pin>;
status = "disabled";
@@ -390,7 +448,6 @@
reg = <0x110b0010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm1_pin>;
status = "disabled";
@@ -401,7 +458,6 @@
reg = <0x110b0020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm2_pin>;
status = "disabled";
@@ -412,7 +468,6 @@
reg = <0x110b0030 0x10>;
#pwm-cells = <2>;
clocks = <&cru PCLK_PWM>;
- clock-names = "pwm";
pinctrl-names = "default";
pinctrl-0 = <&pwm3_pin>;
status = "disabled";
@@ -517,7 +572,7 @@
pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_pin>;
- #thermal-sensor-cells = <0>;
+ #thermal-sensor-cells = <1>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
@@ -550,30 +605,54 @@
"ppmmu1";
clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
clock-names = "bus", "core";
+ power-domains = <&power RK3228_PD_GPU>;
resets = <&cru SRST_GPU_A>;
status = "disabled";
};
+ vpu: video-codec@20020000 {
+ compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu";
+ reg = <0x20020000 0x800>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk", "hclk";
+ iommus = <&vpu_mmu>;
+ power-domains = <&power RK3228_PD_VPU>;
+ };
+
vpu_mmu: iommu@20020800 {
compatible = "rockchip,iommu";
reg = <0x20020800 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_VPU>;
+ #iommu-cells = <0>;
+ };
+
+ vdec: video-codec@20030000 {
+ compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec";
+ reg = <0x20030000 0x480>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,
+ <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ clock-names = "axi", "ahb", "cabac", "core";
+ assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>;
+ assigned-clock-rates = <300000000>, <300000000>;
+ iommus = <&vdec_mmu>;
+ power-domains = <&power RK3228_PD_RKVDEC>;
};
vdec_mmu: iommu@20030480 {
compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
- status = "disabled";
+ power-domains = <&power RK3228_PD_RKVDEC>;
+ #iommu-cells = <0>;
};
vop: vop@20050000 {
@@ -585,6 +664,7 @@
resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
+ power-domains = <&power RK3228_PD_VOP>;
status = "disabled";
vop_out: port {
@@ -602,9 +682,9 @@
compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface";
+ power-domains = <&power RK3228_PD_VOP>;
#iommu-cells = <0>;
status = "disabled";
};
@@ -615,6 +695,7 @@
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk", "hclk", "sclk";
+ power-domains = <&power RK3228_PD_VIO>;
resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
reset-names = "core", "axi", "ahb";
};
@@ -623,10 +704,10 @@
compatible = "rockchip,iommu";
reg = <0x20070800 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface";
- iommu-cells = <0>;
+ power-domains = <&power RK3228_PD_VIO>;
+ #iommu-cells = <0>;
status = "disabled";
};
@@ -800,6 +881,51 @@
status = "disabled";
};
+ qos_iep: qos@31030080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030080 0x20>;
+ };
+
+ qos_rga_w: qos@31030100 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030100 0x20>;
+ };
+
+ qos_hdcp: qos@31030180 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030180 0x20>;
+ };
+
+ qos_rga_r: qos@31030200 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31030200 0x20>;
+ };
+
+ qos_vpu: qos@31040000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31040000 0x20>;
+ };
+
+ qos_gpu: qos@31050000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31050000 0x20>;
+ };
+
+ qos_vop: qos@31060000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31060000 0x20>;
+ };
+
+ qos_rkvdec_r: qos@31070000 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070000 0x20>;
+ };
+
+ qos_rkvdec_w: qos@31070080 {
+ compatible = "rockchip,rk3228-qos", "syscon";
+ reg = <0x31070080 0x20>;
+ };
+
gic: interrupt-controller@32010000 {
compatible = "arm,gic-400";
interrupt-controller;
diff --git a/src/arm/rk3288-rock2-som.dtsi b/src/arm/rk3288-rock2-som.dtsi
index 44bb5e6..76363b8 100644
--- a/src/arm/rk3288-rock2-som.dtsi
+++ b/src/arm/rk3288-rock2-som.dtsi
@@ -218,7 +218,7 @@
flash0-supply = <&vcc_flash>;
flash1-supply = <&vccio_pmu>;
gpio30-supply = <&vccio_pmu>;
- gpio1830 = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>;
diff --git a/src/arm/rk3288-vyasa.dts b/src/arm/rk3288-vyasa.dts
index aa50f8e..b156a83 100644
--- a/src/arm/rk3288-vyasa.dts
+++ b/src/arm/rk3288-vyasa.dts
@@ -379,10 +379,10 @@
audio-supply = <&vcc_18>;
bb-supply = <&vcc_io>;
dvp-supply = <&vcc_io>;
- flash0-suuply = <&vcc_18>;
+ flash0-supply = <&vcc_18>;
flash1-supply = <&vcc_lan>;
gpio30-supply = <&vcc_io>;
- gpio1830 = <&vcc_io>;
+ gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>;
diff --git a/src/arm/rk3288.dtsi b/src/arm/rk3288.dtsi
index 05557ad..9c5a779 100644
--- a/src/arm/rk3288.dtsi
+++ b/src/arm/rk3288.dtsi
@@ -196,8 +196,8 @@
compatible = "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&xin24m>, <&cru PCLK_TIMER>;
- clock-names = "timer", "pclk";
+ clocks = <&cru PCLK_TIMER>, <&xin24m>;
+ clock-names = "pclk", "timer";
};
display-subsystem {
@@ -765,7 +765,7 @@
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
- pd_vio@RK3288_PD_VIO {
+ power-domain@RK3288_PD_VIO {
reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
@@ -801,19 +801,21 @@
<&qos_vio2_rga_r>,
<&qos_vio2_rga_w>,
<&qos_vio1_isp_r>;
+ #power-domain-cells = <0>;
};
/*
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
- pd_hevc@RK3288_PD_HEVC {
+ power-domain@RK3288_PD_HEVC {
reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
<&cru SCLK_HEVC_CORE>;
pm_qos = <&qos_hevc_r>,
<&qos_hevc_w>;
+ #power-domain-cells = <0>;
};
/*
@@ -821,22 +823,24 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
- pd_video@RK3288_PD_VIDEO {
+ power-domain@RK3288_PD_VIDEO {
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video>;
+ #power-domain-cells = <0>;
};
/*
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
- pd_gpu@RK3288_PD_GPU {
+ power-domain@RK3288_PD_GPU {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>,
<&qos_gpu_w>;
+ #power-domain-cells = <0>;
};
};
@@ -1582,7 +1586,7 @@
drive-strength = <12>;
};
- sleep {
+ suspend {
global_pwroff: global-pwroff {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
};
diff --git a/src/arm/rk3xxx.dtsi b/src/arm/rk3xxx.dtsi
index 755c946..616a828 100644
--- a/src/arm/rk3xxx.dtsi
+++ b/src/arm/rk3xxx.dtsi
@@ -21,9 +21,6 @@
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
- mshc0 = &emmc;
- mshc1 = &mmc0;
- mshc2 = &mmc1;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -50,6 +47,18 @@
status = "disabled";
};
+ vpu: video-codec@10104000 {
+ compatible = "rockchip,rk3066-vpu";
+ reg = <0x10104000 0x800>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vepu", "vdpu";
+ clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
+ <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
+ clock-names = "aclk_vdpu", "hclk_vdpu",
+ "aclk_vepu", "hclk_vepu";
+ };
+
L2: cache-controller@10138000 {
compatible = "arm,pl310-cache";
reg = <0x10138000 0x1000>;
@@ -256,7 +265,7 @@
};
grf: grf@20008000 {
- compatible = "syscon";
+ compatible = "syscon", "simple-mfd";
reg = <0x20008000 0x200>;
};
diff --git a/src/arm/rv1108.dtsi b/src/arm/rv1108.dtsi
index 884872c..9bd0acf 100644
--- a/src/arm/rv1108.dtsi
+++ b/src/arm/rv1108.dtsi
@@ -265,7 +265,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,rv1108-usb2phy";
reg = <0x100 0x0c>;
clocks = <&cru SCLK_USBPHY>;
diff --git a/src/arm/s5pv210-goni.dts b/src/arm/s5pv210-goni.dts
index 5c1e12d..c6f3914 100644
--- a/src/arm/s5pv210-goni.dts
+++ b/src/arm/s5pv210-goni.dts
@@ -358,15 +358,6 @@
reg = <0x4a>;
interrupt-parent = <&gpj0>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
-
- atmel,x-line = <17>;
- atmel,y-line = <11>;
- atmel,x-size = <800>;
- atmel,y-size = <480>;
- atmel,burst-length = <0x21>;
- atmel,threshold = <0x28>;
- atmel,orientation = <1>;
-
vdd-supply = <&tsp_reg>;
};
};
diff --git a/src/arm/sama5d4.dtsi b/src/arm/sama5d4.dtsi
index 05c5587..f6e3e6f 100644
--- a/src/arm/sama5d4.dtsi
+++ b/src/arm/sama5d4.dtsi
@@ -101,6 +101,13 @@
ranges = <0 0x100000 0x2400>;
};
+ vdec0: vdec@300000 {
+ compatible = "microchip,sama5d4-vdec";
+ reg = <0x00300000 0x100000>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ };
+
usb0: gadget@400000 {
compatible = "atmel,sama5d3-udc";
reg = <0x00400000 0x100000
@@ -787,7 +794,7 @@
0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
- 0x0003ff00 0x8002a800 0x00000000 /* pioD */
+ 0xb003ff00 0x8002a800 0x00000000 /* pioD */
0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
>;
diff --git a/src/arm/sd5203.dts b/src/arm/sd5203.dts
index 3cc9a23..a61a078 100644
--- a/src/arm/sd5203.dts
+++ b/src/arm/sd5203.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2020 Hisilicon Limited.
+ * Copyright (c) 2020 HiSilicon Limited.
*
* DTS file for Hisilicon SD5203 Board
*/
diff --git a/src/arm/ste-ab8500.dtsi b/src/arm/ste-ab8500.dtsi
index a16a00f..d0fe3f9 100644
--- a/src/arm/ste-ab8500.dtsi
+++ b/src/arm/ste-ab8500.dtsi
@@ -34,7 +34,7 @@
#clock-cells = <1>;
};
- ab8500_gpio: ab8500-gpio {
+ ab8500_gpio: ab8500-gpiocontroller {
compatible = "stericsson,ab8500-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -42,15 +42,15 @@
ab8500-rtc {
compatible = "stericsson,ab8500-rtc";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH
- 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "60S", "ALARM";
};
gpadc: ab8500-gpadc {
compatible = "stericsson,ab8500-gpadc";
- interrupts = <32 IRQ_TYPE_LEVEL_HIGH
- 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
+ <39 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "HW_CONV_END", "SW_CONV_END";
vddadc-supply = <&ab8500_ldo_tvout_reg>;
#address-cells = <1>;
@@ -219,13 +219,13 @@
ab8500_usb {
compatible = "stericsson,ab8500-usb";
- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
- 96 IRQ_TYPE_LEVEL_HIGH
- 14 IRQ_TYPE_LEVEL_HIGH
- 15 IRQ_TYPE_LEVEL_HIGH
- 79 IRQ_TYPE_LEVEL_HIGH
- 74 IRQ_TYPE_LEVEL_HIGH
- 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ID_WAKEUP_R",
"ID_WAKEUP_F",
"VBUS_DET_F",
@@ -242,8 +242,8 @@
ab8500-ponkey {
compatible = "stericsson,ab8500-poweron-key";
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH
- 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
};
diff --git a/src/arm/ste-ab8505.dtsi b/src/arm/ste-ab8505.dtsi
index cc045b2..0defc15 100644
--- a/src/arm/ste-ab8505.dtsi
+++ b/src/arm/ste-ab8505.dtsi
@@ -31,7 +31,7 @@
#clock-cells = <1>;
};
- ab8505_gpio: ab8505-gpio {
+ ab8505_gpio: ab8505-gpiocontroller {
compatible = "stericsson,ab8505-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -39,8 +39,8 @@
ab8500-rtc {
compatible = "stericsson,ab8500-rtc";
- interrupts = <17 IRQ_TYPE_LEVEL_HIGH
- 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+ <18 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "60S", "ALARM";
};
@@ -182,13 +182,13 @@
ab8500_usb: ab8500_usb {
compatible = "stericsson,ab8500-usb";
- interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
- 96 IRQ_TYPE_LEVEL_HIGH
- 14 IRQ_TYPE_LEVEL_HIGH
- 15 IRQ_TYPE_LEVEL_HIGH
- 79 IRQ_TYPE_LEVEL_HIGH
- 74 IRQ_TYPE_LEVEL_HIGH
- 75 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <90 IRQ_TYPE_LEVEL_HIGH>,
+ <96 IRQ_TYPE_LEVEL_HIGH>,
+ <14 IRQ_TYPE_LEVEL_HIGH>,
+ <15 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>,
+ <74 IRQ_TYPE_LEVEL_HIGH>,
+ <75 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ID_WAKEUP_R",
"ID_WAKEUP_F",
"VBUS_DET_F",
@@ -205,8 +205,8 @@
ab8500-ponkey {
compatible = "stericsson,ab8500-poweron-key";
- interrupts = <6 IRQ_TYPE_LEVEL_HIGH
- 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>,
+ <7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
};
diff --git a/src/arm/ste-href-ab8500.dtsi b/src/arm/ste-href-ab8500.dtsi
index 4946743..3ccb7b5 100644
--- a/src/arm/ste-href-ab8500.dtsi
+++ b/src/arm/ste-href-ab8500.dtsi
@@ -9,7 +9,7 @@
soc {
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
/* Hog a few default settings */
pinctrl-names = "default";
pinctrl-0 = <&gpio2_default_mode>,
diff --git a/src/arm/ste-href-tvk1281618-r2.dtsi b/src/arm/ste-href-tvk1281618-r2.dtsi
index 8d59202..37e5940 100644
--- a/src/arm/ste-href-tvk1281618-r2.dtsi
+++ b/src/arm/ste-href-tvk1281618-r2.dtsi
@@ -104,6 +104,9 @@
* <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
* <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
*/
+ mount-matrix = "0", "1", "0",
+ "1", "0", "0",
+ "0", "0", "-1";
};
magnetometer@1e {
/* Magnetometer */
@@ -136,6 +139,9 @@
/* INT2 would need to be open drain */
interrupts = <18 IRQ_TYPE_EDGE_RISING>,
<19 IRQ_TYPE_EDGE_RISING>;
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
};
magnetometer@f {
/* Magnetometer */
diff --git a/src/arm/ste-href-tvk1281618-r3.dtsi b/src/arm/ste-href-tvk1281618-r3.dtsi
index 70f0583..00ce9d7 100644
--- a/src/arm/ste-href-tvk1281618-r3.dtsi
+++ b/src/arm/ste-href-tvk1281618-r3.dtsi
@@ -89,10 +89,12 @@
<19 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&accel_tvk_mode>;
+ mount-matrix = "0", "-1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
};
magnetometer@1e {
compatible = "st,lsm303dlm-magn";
- st,drdy-int-pin = <1>;
reg = <0x1e>;
vdd-supply = <&ab8500_ldo_aux1_reg>;
vddio-supply = <&db8500_vsmps2_reg>;
diff --git a/src/arm/ste-href.dtsi b/src/arm/ste-href.dtsi
index 83b1796..c97e8d2 100644
--- a/src/arm/ste-href.dtsi
+++ b/src/arm/ste-href.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
#include "ste-href-family-pinctrl.dtsi"
/ {
@@ -64,17 +65,20 @@
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
linux,default-trigger = "heartbeat";
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
};
lp5521@34 {
@@ -88,16 +92,19 @@
reg = <0>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
chan@1 {
reg = <1>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
chan@2 {
reg = <2>;
led-cur = /bits/ 8 <0x2f>;
max-cur = /bits/ 8 <0x5f>;
+ color = <LED_COLOR_ID_BLUE>;
};
};
bh1780@29 {
@@ -202,7 +209,7 @@
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
};
ab8500_usb {
diff --git a/src/arm/ste-snowball.dts b/src/arm/ste-snowball.dts
index b344b37..40f1d7c 100644
--- a/src/arm/ste-snowball.dts
+++ b/src/arm/ste-snowball.dts
@@ -376,7 +376,7 @@
prcmu@80157000 {
ab8500 {
- ab8500-gpio {
+ ab8500-gpiocontroller {
/*
* AB8500 GPIOs are numbered starting from 1, so the first
* index 0 is what in the datasheet is called "GPIO1", and
diff --git a/src/arm/ste-ux500-samsung-golden.dts b/src/arm/ste-ux500-samsung-golden.dts
index 0d43ee6..40df7c6 100644
--- a/src/arm/ste-ux500-samsung-golden.dts
+++ b/src/arm/ste-ux500-samsung-golden.dts
@@ -121,7 +121,7 @@
#size-cells = <0>;
wifi@1 {
- compatible = "brcm,bcm4329-fmac";
+ compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/* GPIO216 (WLAN_HOST_WAKE) */
@@ -162,6 +162,7 @@
pinctrl-1 = <&u0_a_1_sleep>;
bluetooth {
+ /* BCM4334B0 actually */
compatible = "brcm,bcm4330-bt";
/* GPIO222 (BT_VREG_ON) */
shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
diff --git a/src/arm/ste-ux500-samsung-janice.dts b/src/arm/ste-ux500-samsung-janice.dts
index f243698..25af066 100644
--- a/src/arm/ste-ux500-samsung-janice.dts
+++ b/src/arm/ste-ux500-samsung-janice.dts
@@ -401,8 +401,7 @@
status = "okay";
wifi@1 {
- /* Actually BRCM4330 */
- compatible = "brcm,bcm4329-fmac";
+ compatible = "brcm,bcm4330-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/* GPIO216 WL_HOST_WAKE */
interrupt-parent = <&gpio6>;
@@ -436,6 +435,7 @@
status = "okay";
bluetooth {
+ /* BCM4330B1 actually */
compatible = "brcm,bcm4330-bt";
/* GPIO222 rail BT_VREG_EN to BT_REG_ON */
shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
@@ -583,10 +583,9 @@
accelerometer@08 {
compatible = "bosch,bma222";
reg = <0x08>;
- /* FIXME: no idea about this */
- mount-matrix = "1", "0", "0",
- "0", "1", "0",
- "0", "0", "1";
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "-1";
vddio-supply = <&ab8500_ldo_aux2_reg>; // 1.8V
vdd-supply = <&ab8500_ldo_aux1_reg>; // 3V
};
diff --git a/src/arm/ste-ux500-samsung-skomer.dts b/src/arm/ste-ux500-samsung-skomer.dts
index d28a007..94afd7a 100644
--- a/src/arm/ste-ux500-samsung-skomer.dts
+++ b/src/arm/ste-ux500-samsung-skomer.dts
@@ -211,7 +211,7 @@
#size-cells = <0>;
wifi@1 {
- compatible = "brcm,bcm4329-fmac";
+ compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac";
reg = <1>;
/* GPIO216 WL_HOST_WAKE */
interrupt-parent = <&gpio6>;
@@ -247,6 +247,7 @@
/* FIXME: not quite working yet, probably needs regulators */
bluetooth {
+ /* BCM4334B0 actually */
compatible = "brcm,bcm4330-bt";
shutdown-gpios = <&gpio6 30 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
diff --git a/src/arm/stm32429i-eval.dts b/src/arm/stm32429i-eval.dts
index 7e10ae7..9ac1ffe 100644
--- a/src/arm/stm32429i-eval.dts
+++ b/src/arm/stm32429i-eval.dts
@@ -119,17 +119,15 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 0>;
};
- button@1 {
+ button-1 {
label = "Tamper";
linux,code = <KEY_RESTART>;
gpios = <&gpioc 13 0>;
diff --git a/src/arm/stm32746g-eval.dts b/src/arm/stm32746g-eval.dts
index ca8c192..327613f 100644
--- a/src/arm/stm32746g-eval.dts
+++ b/src/arm/stm32746g-eval.dts
@@ -81,12 +81,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "Wake up";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioc 13 0>;
diff --git a/src/arm/stm32f4-pinctrl.dtsi b/src/arm/stm32f4-pinctrl.dtsi
index 4774163..155d9ff 100644
--- a/src/arm/stm32f4-pinctrl.dtsi
+++ b/src/arm/stm32f4-pinctrl.dtsi
@@ -45,7 +45,7 @@
/ {
soc {
- pinctrl: pin-controller {
+ pinctrl: pin-controller@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
diff --git a/src/arm/stm32f429-disco.dts b/src/arm/stm32f429-disco.dts
index 3dc068b..075ac57 100644
--- a/src/arm/stm32f429-disco.dts
+++ b/src/arm/stm32f429-disco.dts
@@ -81,12 +81,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 0>;
diff --git a/src/arm/stm32f429-pinctrl.dtsi b/src/arm/stm32f429-pinctrl.dtsi
index 3e7a17d..e10d7a1 100644
--- a/src/arm/stm32f429-pinctrl.dtsi
+++ b/src/arm/stm32f429-pinctrl.dtsi
@@ -42,54 +42,50 @@
#include "stm32f4-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller {
- compatible = "st,stm32f429-pinctrl";
+&pinctrl {
+ compatible = "st,stm32f429-pinctrl";
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 16>;
- };
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 0 160 8>;
- };
- };
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 0 160 8>;
};
};
diff --git a/src/arm/stm32f429.dtsi b/src/arm/stm32f429.dtsi
index f6530d7..8748d58 100644
--- a/src/arm/stm32f429.dtsi
+++ b/src/arm/stm32f429.dtsi
@@ -283,8 +283,6 @@
};
timers13: timers@40001c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@@ -299,8 +297,6 @@
};
timers14: timers@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@@ -633,8 +629,6 @@
};
timers10: timers@40014400 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@@ -649,8 +643,6 @@
};
timers11: timers@40014800 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
@@ -709,7 +701,7 @@
status = "disabled";
};
- rcc: rcc@40023810 {
+ rcc: rcc@40023800 {
#reset-cells = <1>;
#clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
diff --git a/src/arm/stm32f469-disco.dts b/src/arm/stm32f469-disco.dts
index 2e1b3bb..8c982ae 100644
--- a/src/arm/stm32f469-disco.dts
+++ b/src/arm/stm32f469-disco.dts
@@ -104,12 +104,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "User";
linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
diff --git a/src/arm/stm32f469-pinctrl.dtsi b/src/arm/stm32f469-pinctrl.dtsi
index fff5426..6bf6026 100644
--- a/src/arm/stm32f469-pinctrl.dtsi
+++ b/src/arm/stm32f469-pinctrl.dtsi
@@ -42,55 +42,51 @@
#include "stm32f4-pinctrl.dtsi"
-/ {
- soc {
- pinctrl: pin-controller {
- compatible = "st,stm32f469-pinctrl";
+&pinctrl {
+ compatible = "st,stm32f469-pinctrl";
- gpioa: gpio@40020000 {
- gpio-ranges = <&pinctrl 0 0 16>;
- };
+ gpioa: gpio@40020000 {
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
- gpiob: gpio@40020400 {
- gpio-ranges = <&pinctrl 0 16 16>;
- };
+ gpiob: gpio@40020400 {
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
- gpioc: gpio@40020800 {
- gpio-ranges = <&pinctrl 0 32 16>;
- };
+ gpioc: gpio@40020800 {
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
- gpiod: gpio@40020c00 {
- gpio-ranges = <&pinctrl 0 48 16>;
- };
+ gpiod: gpio@40020c00 {
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
- gpioe: gpio@40021000 {
- gpio-ranges = <&pinctrl 0 64 16>;
- };
+ gpioe: gpio@40021000 {
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
- gpiof: gpio@40021400 {
- gpio-ranges = <&pinctrl 0 80 16>;
- };
+ gpiof: gpio@40021400 {
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
- gpiog: gpio@40021800 {
- gpio-ranges = <&pinctrl 0 96 16>;
- };
+ gpiog: gpio@40021800 {
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
- gpioh: gpio@40021c00 {
- gpio-ranges = <&pinctrl 0 112 16>;
- };
+ gpioh: gpio@40021c00 {
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
- gpioi: gpio@40022000 {
- gpio-ranges = <&pinctrl 0 128 16>;
- };
+ gpioi: gpio@40022000 {
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
- gpioj: gpio@40022400 {
- gpio-ranges = <&pinctrl 0 144 6>,
- <&pinctrl 12 156 4>;
- };
+ gpioj: gpio@40022400 {
+ gpio-ranges = <&pinctrl 0 144 6>,
+ <&pinctrl 12 156 4>;
+ };
- gpiok: gpio@40022800 {
- gpio-ranges = <&pinctrl 3 163 5>;
- };
- };
+ gpiok: gpio@40022800 {
+ gpio-ranges = <&pinctrl 3 163 5>;
};
};
diff --git a/src/arm/stm32f7-pinctrl.dtsi b/src/arm/stm32f7-pinctrl.dtsi
index fe4cfda..1cf8a23 100644
--- a/src/arm/stm32f7-pinctrl.dtsi
+++ b/src/arm/stm32f7-pinctrl.dtsi
@@ -9,7 +9,7 @@
/ {
soc {
- pinctrl: pin-controller {
+ pinctrl: pin-controller@40020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40020000 0x3000>;
diff --git a/src/arm/stm32f746.dtsi b/src/arm/stm32f746.dtsi
index e1df603..014b416 100644
--- a/src/arm/stm32f746.dtsi
+++ b/src/arm/stm32f746.dtsi
@@ -265,8 +265,6 @@
};
timers13: timers@40001c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@@ -281,8 +279,6 @@
};
timers14: timers@40002000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@@ -364,9 +360,9 @@
status = "disabled";
};
- i2c3: i2c@40005C00 {
+ i2c3: i2c@40005c00 {
compatible = "st,stm32f7-i2c";
- reg = <0x40005C00 0x400>;
+ reg = <0x40005c00 0x400>;
interrupts = <72>,
<73>;
resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
@@ -531,8 +527,6 @@
};
timers10: timers@40014400 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@@ -547,8 +541,6 @@
};
timers11: timers@40014800 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;
diff --git a/src/arm/stm32f769-disco.dts b/src/arm/stm32f769-disco.dts
index 0ce7fbc..be943b7 100644
--- a/src/arm/stm32f769-disco.dts
+++ b/src/arm/stm32f769-disco.dts
@@ -75,12 +75,10 @@
};
};
- gpio_keys {
+ gpio-keys {
compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
autorepeat;
- button@0 {
+ button-0 {
label = "User";
linux,code = <KEY_HOME>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
diff --git a/src/arm/stm32h743.dtsi b/src/arm/stm32h743.dtsi
index 05ecdf9..6e42ca2 100644
--- a/src/arm/stm32h743.dtsi
+++ b/src/arm/stm32h743.dtsi
@@ -485,8 +485,6 @@
};
lptimer4: timer@58002c00 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>;
@@ -501,8 +499,6 @@
};
lptimer5: timer@58003000 {
- #address-cells = <1>;
- #size-cells = <0>;
compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>;
diff --git a/src/arm/stm32mp15-pinctrl.dtsi b/src/arm/stm32mp15-pinctrl.dtsi
index 060baa8..5b60ecb 100644
--- a/src/arm/stm32mp15-pinctrl.dtsi
+++ b/src/arm/stm32mp15-pinctrl.dtsi
@@ -118,6 +118,39 @@
};
};
+ dcmi_pins_b: dcmi-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */
+ bias-disable;
+ };
+ };
+
+ dcmi_sleep_pins_b: dcmi-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */
+ <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
+ <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
+ <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */
+ <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
+ <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
+ <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */
+ <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */
+ <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */
+ <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */
+ <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */
+ };
+ };
+
ethernet0_rgmii_pins_a: rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
diff --git a/src/arm/stm32mp151.dtsi b/src/arm/stm32mp151.dtsi
index fcd3230..bd289bf 100644
--- a/src/arm/stm32mp151.dtsi
+++ b/src/arm/stm32mp151.dtsi
@@ -1369,8 +1369,8 @@
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
reg-names = "qspi", "qspi_mm";
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&mdma1 22 0x2 0x100002 0x0 0x0>,
- <&mdma1 22 0x2 0x100008 0x0 0x0>;
+ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
+ <&mdma1 22 0x2 0x10100008 0x0 0x0>;
dma-names = "tx", "rx";
clocks = <&rcc QSPI_K>;
resets = <&rcc QSPI_R>;
@@ -1416,12 +1416,6 @@
status = "disabled";
};
- stmmac_axi_config_0: stmmac-axi-config {
- snps,wr_osr_lmt = <0x7>;
- snps,rd_osr_lmt = <0x7>;
- snps,blen = <0 0 0 0 16 8 4>;
- };
-
ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>;
@@ -1447,6 +1441,12 @@
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
status = "disabled";
+
+ stmmac_axi_config_0: stmmac-axi-config {
+ snps,wr_osr_lmt = <0x7>;
+ snps,rd_osr_lmt = <0x7>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
};
usbh_ohci: usb@5800c000 {
diff --git a/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
index 674b2d3..5670b23 100644
--- a/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
+++ b/src/arm/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
@@ -89,7 +89,7 @@
};
&pinctrl {
- ltdc_pins: ltdc {
+ ltdc_pins: ltdc-0 {
pins {
pinmux = <STM32_PINMUX('G', 10, AF14)>, /* LTDC_B2 */
<STM32_PINMUX('H', 12, AF14)>, /* LTDC_R6 */
diff --git a/src/arm/stm32mp157a-stinger96.dtsi b/src/arm/stm32mp157a-stinger96.dtsi
index 113c48b..a4b14ef 100644
--- a/src/arm/stm32mp157a-stinger96.dtsi
+++ b/src/arm/stm32mp157a-stinger96.dtsi
@@ -184,8 +184,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -208,7 +206,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -219,13 +216,13 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
diff --git a/src/arm/stm32mp157c-odyssey-som.dtsi b/src/arm/stm32mp157c-odyssey-som.dtsi
index 6cf49a0..2d94610 100644
--- a/src/arm/stm32mp157c-odyssey-som.dtsi
+++ b/src/arm/stm32mp157c-odyssey-som.dtsi
@@ -173,8 +173,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -197,7 +195,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -213,7 +210,7 @@
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -269,7 +266,7 @@
st,neg-edge;
bus-width = <8>;
vmmc-supply = <&v3v3>;
- vqmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
mmc-ddr-3_3v;
status = "okay";
};
diff --git a/src/arm/stm32mp157c-odyssey.dts b/src/arm/stm32mp157c-odyssey.dts
index a7ffec8..be1dd5e 100644
--- a/src/arm/stm32mp157c-odyssey.dts
+++ b/src/arm/stm32mp157c-odyssey.dts
@@ -64,7 +64,7 @@
pinctrl-0 = <&sdmmc1_b4_pins_a>;
pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
- cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+ cd-gpios = <&gpioi 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
disable-wp;
st,neg-edge;
bus-width = <4>;
diff --git a/src/arm/stm32mp15xx-dhcom-pdk2.dtsi b/src/arm/stm32mp15xx-dhcom-pdk2.dtsi
index 5523f41..c5ea08f 100644
--- a/src/arm/stm32mp15xx-dhcom-pdk2.dtsi
+++ b/src/arm/stm32mp15xx-dhcom-pdk2.dtsi
@@ -34,7 +34,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #size-cells = <0>;
poll-interval = <20>;
/*
@@ -60,7 +59,6 @@
gpio-keys {
compatible = "gpio-keys";
- #size-cells = <0>;
button-1 {
label = "TA2-GPIO-B";
@@ -184,12 +182,11 @@
};
- polytouch@38 {
- compatible = "edt,edt-ft5x06";
+ touchscreen@38 {
+ compatible = "edt,edt-ft5406";
reg = <0x38>;
interrupt-parent = <&gpiog>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
- linux,wakeup;
};
};
diff --git a/src/arm/stm32mp15xx-dhcom-som.dtsi b/src/arm/stm32mp15xx-dhcom-som.dtsi
index 272a1a6..2af0a67 100644
--- a/src/arm/stm32mp15xx-dhcom-som.dtsi
+++ b/src/arm/stm32mp15xx-dhcom-som.dtsi
@@ -123,7 +123,6 @@
max-speed = <100>;
phy-handle = <&phy0>;
st,eth-ref-clk-sel;
- phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
mdio0 {
#address-cells = <1>;
@@ -132,6 +131,13 @@
phy0: ethernet-phy@1 {
reg = <1>;
+ /* LAN8710Ai */
+ compatible = "ethernet-phy-id0007.c0f0",
+ "ethernet-phy-ieee802.3-c22";
+ clocks = <&rcc ETHCK_K>;
+ reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <500>;
+ reset-deassert-us = <500>;
interrupt-parent = <&gpioi>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
};
@@ -144,7 +150,7 @@
pinctrl-1 = <&fmc_sleep_pins_b>;
status = "okay";
- ksz8851: ks8851mll@1,0 {
+ ksz8851: ethernet@1,0 {
compatible = "micrel,ks8851-mll";
reg = <1 0x0 0x2>, <1 0x2 0x20000>;
interrupt-parent = <&gpioc>;
@@ -327,8 +333,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -350,7 +354,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -366,7 +369,7 @@
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
@@ -431,7 +434,7 @@
#size-cells = <0>;
status = "okay";
- flash0: mx66l51235l@0 {
+ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
diff --git a/src/arm/stm32mp15xx-dhcor-som.dtsi b/src/arm/stm32mp15xx-dhcor-som.dtsi
index 013ae36..2b0ac60 100644
--- a/src/arm/stm32mp15xx-dhcor-som.dtsi
+++ b/src/arm/stm32mp15xx-dhcor-som.dtsi
@@ -198,7 +198,7 @@
#size-cells = <0>;
status = "okay";
- flash0: spi-flash@0 {
+ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
diff --git a/src/arm/stm32mp15xx-osd32.dtsi b/src/arm/stm32mp15xx-osd32.dtsi
index 713485a..6706d83 100644
--- a/src/arm/stm32mp15xx-osd32.dtsi
+++ b/src/arm/stm32mp15xx-osd32.dtsi
@@ -146,8 +146,6 @@
vdd_usb: ldo4 {
regulator-name = "vdd_usb";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
interrupts = <IT_CURLIM_LDO4 0>;
};
@@ -171,7 +169,6 @@
vref_ddr: vref_ddr {
regulator-name = "vref_ddr";
regulator-always-on;
- regulator-over-current-protection;
};
bst_out: boost {
@@ -182,13 +179,13 @@
vbus_otg: pwr_sw1 {
regulator-name = "vbus_otg";
interrupts = <IT_OCP_OTG 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
vbus_sw: pwr_sw2 {
regulator-name = "vbus_sw";
interrupts = <IT_OCP_SWOUT 0>;
- regulator-active-discharge;
+ regulator-active-discharge = <1>;
};
};
diff --git a/src/arm/sun8i-a33.dtsi b/src/arm/sun8i-a33.dtsi
index 7344c37..2beddbb 100644
--- a/src/arm/sun8i-a33.dtsi
+++ b/src/arm/sun8i-a33.dtsi
@@ -198,7 +198,7 @@
};
link_codec: simple-audio-card,codec {
- sound-dai = <&codec>;
+ sound-dai = <&codec 0>;
};
};
@@ -238,7 +238,7 @@
};
codec: codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x400>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm/sun8i-h3-orangepi-plus.dts b/src/arm/sun8i-h3-orangepi-plus.dts
index 97f4978..d05fa67 100644
--- a/src/arm/sun8i-h3-orangepi-plus.dts
+++ b/src/arm/sun8i-h3-orangepi-plus.dts
@@ -85,7 +85,7 @@
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <®_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
- phy-mode = "rgmii";
+ phy-mode = "rgmii-id";
status = "okay";
};
diff --git a/src/arm/sun8i-r40-feta40i.dtsi b/src/arm/sun8i-r40-feta40i.dtsi
new file mode 100644
index 0000000..265e0fa
--- /dev/null
+++ b/src/arm/sun8i-r40-feta40i.dtsi
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+#include "sun8i-r40.dtsi"
+
+&i2c0 {
+ status = "okay";
+
+ axp22x: pmic@34 {
+ compatible = "x-powers,axp221";
+ reg = <0x34>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+#include "axp22x.dtsi"
+
+&mmc2 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_aldo2>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_out_a_pin>;
+ vcc-pa-supply = <®_dcdc1>;
+ vcc-pc-supply = <®_aldo2>;
+ vcc-pd-supply = <®_dcdc1>;
+ vcc-pf-supply = <®_dldo4>;
+ vcc-pg-supply = <®_dldo1>;
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc-pa";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpu";
+};
+
+®_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi-io";
+};
+
+®_dldo4 {
+ regulator-always-on;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vdd2v5-sata";
+};
+
+®_eldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vdd1v2-sata";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-pe";
+};
diff --git a/src/arm/sun8i-r40-oka40i-c.dts b/src/arm/sun8i-r40-oka40i-c.dts
new file mode 100644
index 0000000..0bd1336
--- /dev/null
+++ b/src/arm/sun8i-r40-oka40i-c.dts
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// Copyright (C) 2021 Ivan Uvarov <i.uvarov@cognitivepilot.com>
+// Based on the sun8i-r40-bananapi-m2-ultra.dts, which is:
+// Copyright (C) 2017 Chen-Yu Tsai <wens@csie.org>
+// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+
+/dts-v1/;
+#include "sun8i-r40-feta40i.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Forlinx OKA40i-C";
+ compatible = "forlinx,oka40i-c", "forlinx,feta40i-c", "allwinner,sun8i-r40";
+
+ aliases {
+ ethernet0 = &gmac;
+ serial0 = &uart0;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5; /* RS485 */
+ serial7 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-5 { /* this is how the leds are labeled on the board */
+ gpios = <&pio 7 26 GPIO_ACTIVE_LOW>; /* PH26 */
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led-6 {
+ gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; // PB10 WIFI_EN
+ clocks = <&ccu CLK_OUTA>;
+ clock-names = "ext_clock";
+ };
+};
+
+&ahci {
+ ahci-supply = <®_dldo4>;
+ phy-supply = <®_eldo2>;
+ status = "okay";
+};
+
+&de {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_rgmii_pins>;
+ phy-handle = <&phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <®_dcdc1>;
+ status = "okay";
+};
+
+&gmac_mdio {
+ phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&mmc0 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 8 11 GPIO_ACTIVE_LOW>; // PI11
+ status = "okay";
+};
+
+&mmc3 {
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_dcdc1>;
+ bus-width = <4>;
+ cd-gpios = <&pio 8 10 GPIO_ACTIVE_LOW>; // PI10
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+®_dc1sw {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-lcd";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&tcon_tv0 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_rts_cts_pi_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_rts_cts_pg_pins>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pg_pins>;
+ status = "okay";
+};
+
+&uart5 { /* RS485 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5_ph_pins>;
+ status = "okay";
+};
+
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7_pi_pins>;
+ status = "okay";
+};
+
+&usbphy {
+ usb1_vbus-supply = <®_vcc5v0>;
+ usb2_vbus-supply = <®_vcc5v0>;
+ status = "okay";
+};
diff --git a/src/arm/sun8i-r40.dtsi b/src/arm/sun8i-r40.dtsi
index d5ad3b9..291f478 100644
--- a/src/arm/sun8i-r40.dtsi
+++ b/src/arm/sun8i-r40.dtsi
@@ -357,6 +357,8 @@
clock-names = "ahb", "mmc";
resets = <&ccu RST_BUS_MMC3>;
reset-names = "ahb";
+ pinctrl-0 = <&mmc3_pins>;
+ pinctrl-names = "default";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
@@ -602,6 +604,15 @@
};
/omit-if-no-ref/
+ mmc3_pins: mmc3-pins {
+ pins = "PI4", "PI5", "PI6",
+ "PI7", "PI8", "PI9";
+ function = "mmc3";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
spi0_pc_pins: spi0-pc-pins {
pins = "PC0", "PC1", "PC2";
function = "spi0";
@@ -631,20 +642,65 @@
function = "spi1";
};
+ /omit-if-no-ref/
uart0_pb_pins: uart0-pb-pins {
pins = "PB22", "PB23";
function = "uart0";
};
+ /omit-if-no-ref/
+ uart2_pi_pins: uart2-pi-pins {
+ pins = "PI18", "PI19";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
+ uart2_rts_cts_pi_pins: uart2-rts-cts-pi-pins{
+ pins = "PI16", "PI17";
+ function = "uart2";
+ };
+
+ /omit-if-no-ref/
uart3_pg_pins: uart3-pg-pins {
pins = "PG6", "PG7";
function = "uart3";
};
+ /omit-if-no-ref/
uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
pins = "PG8", "PG9";
function = "uart3";
};
+
+ /omit-if-no-ref/
+ uart4_pg_pins: uart4-pg-pins {
+ pins = "PG10", "PG11";
+ function = "uart4";
+ };
+
+ /omit-if-no-ref/
+ uart5_ph_pins: uart5-ph-pins {
+ pins = "PH6", "PH7";
+ function = "uart5";
+ };
+
+ /omit-if-no-ref/
+ uart7_pi_pins: uart7-pi-pins {
+ pins = "PI20", "PI21";
+ function = "uart7";
+ };
+ };
+
+ timer@1c20c00 {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x90>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
};
wdt: watchdog@1c20c90 {
diff --git a/src/arm/sun8i-v3.dtsi b/src/arm/sun8i-v3.dtsi
index c279e13..186c30c 100644
--- a/src/arm/sun8i-v3.dtsi
+++ b/src/arm/sun8i-v3.dtsi
@@ -1,14 +1,40 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io>
+ * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*/
#include "sun8i-v3s.dtsi"
+/ {
+ soc {
+ i2s0: i2s@1c22000 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-v3-i2s",
+ "allwinner,sun8i-h3-i2s";
+ reg = <0x01c22000 0x400>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
+ clock-names = "apb", "mod";
+ dmas = <&dma 3>, <&dma 3>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0_pins>;
+ resets = <&ccu RST_BUS_I2S0>;
+ status = "disabled";
+ };
+ };
+};
+
&ccu {
compatible = "allwinner,sun8i-v3-ccu";
};
+&codec_analog {
+ compatible = "allwinner,sun8i-v3-codec-analog",
+ "allwinner,sun8i-h3-codec-analog";
+};
+
&emac {
/delete-property/ phy-handle;
/delete-property/ phy-mode;
@@ -25,6 +51,11 @@
&pio {
compatible = "allwinner,sun8i-v3-pinctrl";
+ i2s0_pins: i2s0-pins {
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "i2s";
+ };
+
uart1_pg_pins: uart1-pg-pins {
pins = "PG6", "PG7";
function = "uart1";
diff --git a/src/arm/sun8i-v3s-licheepi-zero-dock.dts b/src/arm/sun8i-v3s-licheepi-zero-dock.dts
index db5cd0b..752ad05 100644
--- a/src/arm/sun8i-v3s-licheepi-zero-dock.dts
+++ b/src/arm/sun8i-v3s-licheepi-zero-dock.dts
@@ -49,16 +49,18 @@
compatible = "licheepi,licheepi-zero-dock", "licheepi,licheepi-zero",
"allwinner,sun8i-v3s";
+ aliases {
+ ethernet0 = &emac;
+ };
+
leds {
/* The LEDs use PG0~2 pins, which conflict with MMC1 */
status = "disabled";
};
};
-&mmc1 {
- broken-cd;
- bus-width = <4>;
- vmmc-supply = <®_vcc3v3>;
+&emac {
+ allwinner,leds-active-low;
status = "okay";
};
@@ -94,3 +96,10 @@
voltage = <800000>;
};
};
+
+&mmc1 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
diff --git a/src/arm/sun8i-v3s.dtsi b/src/arm/sun8i-v3s.dtsi
index eb4cb63..b30bc1a 100644
--- a/src/arm/sun8i-v3s.dtsi
+++ b/src/arm/sun8i-v3s.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ * Copyright (C) 2021 Tobias Schramm <t.schramm@manjaro.org>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@@ -172,6 +173,15 @@
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
+ dma: dma-controller@1c02000 {
+ compatible = "allwinner,sun8i-v3s-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
tcon0: lcd-controller@1c0c000 {
compatible = "allwinner,sun8i-v3s-tcon";
reg = <0x01c0c000 0x1000>;
@@ -275,6 +285,8 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
clock-names = "ahb", "mod";
+ dmas = <&dma 16>, <&dma 16>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_CE>;
reset-names = "ahb";
};
@@ -422,6 +434,15 @@
clocks = <&osc24M>;
};
+ pwm: pwm@1c21400 {
+ compatible = "allwinner,sun8i-v3s-pwm",
+ "allwinner,sun7i-a20-pwm";
+ reg = <0x01c21400 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
lradc: lradc@1c22800 {
compatible = "allwinner,sun4i-a10-lradc-keys";
reg = <0x01c22800 0x400>;
@@ -429,6 +450,25 @@
status = "disabled";
};
+ codec: codec@1c22c00 {
+ #sound-dai-cells = <0>;
+ compatible = "allwinner,sun8i-v3s-codec";
+ reg = <0x01c22c00 0x400>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
+ clock-names = "apb", "codec";
+ resets = <&ccu RST_BUS_CODEC>;
+ dmas = <&dma 15>, <&dma 15>;
+ dma-names = "rx", "tx";
+ allwinner,codec-analog-controls = <&codec_analog>;
+ status = "disabled";
+ };
+
+ codec_analog: codec-analog@1c23000 {
+ compatible = "allwinner,sun8i-v3s-codec-analog";
+ reg = <0x01c23000 0x4>;
+ };
+
uart0: serial@1c28000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c28000 0x400>;
@@ -436,6 +476,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART0>;
+ dmas = <&dma 6>, <&dma 6>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART0>;
status = "disabled";
};
@@ -447,6 +489,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART1>;
+ dmas = <&dma 7>, <&dma 7>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART1>;
status = "disabled";
};
@@ -458,6 +502,8 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&ccu CLK_BUS_UART2>;
+ dmas = <&dma 8>, <&dma 8>;
+ dma-names = "rx", "tx";
resets = <&ccu RST_BUS_UART2>;
pinctrl-0 = <&uart2_pins>;
pinctrl-names = "default";
@@ -537,6 +583,8 @@
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
resets = <&ccu RST_BUS_SPI0>;
diff --git a/src/arm/tegra124.dtsi b/src/arm/tegra124.dtsi
index 0b678af..8b38f12 100644
--- a/src/arm/tegra124.dtsi
+++ b/src/arm/tegra124.dtsi
@@ -283,7 +283,7 @@
reg = <0x0 0x60007000 0x0 0x1000>;
};
- actmon@6000c800 {
+ actmon: actmon@6000c800 {
compatible = "nvidia,tegra124-actmon";
reg = <0x0 0x6000c800 0x0 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -295,6 +295,7 @@
operating-points-v2 = <&emc_bw_dfs_opp_table>;
interconnects = <&mc TEGRA124_MC_MPCORER &emc>;
interconnect-names = "cpu-read";
+ #cooling-cells = <2>;
};
gpio: gpio@6000d000 {
diff --git a/src/arm/tegra20-acer-a500-picasso.dts b/src/arm/tegra20-acer-a500-picasso.dts
index 2298fc0..1976c38 100644
--- a/src/arm/tegra20-acer-a500-picasso.dts
+++ b/src/arm/tegra20-acer-a500-picasso.dts
@@ -420,11 +420,14 @@
reg = <0x1a>;
interrupt-parent = <&gpio>;
- interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
gpio-controller;
#gpio-cells = <2>;
+ micdet-cfg = <0>;
+ micdet-delay = <100>;
+
gpio-cfg = <
0x0000 /* MIC_LR_OUT# GPIO, output, low */
0x0000 /* FM2018-enable GPIO, output, low */
@@ -759,7 +762,7 @@
mmc-pwrseq = <&brcm_wifi_pwrseq>;
vmmc-supply = <&vdd_3v3_sys>;
- vqmmc-supply = <&vdd_3v3_sys>;
+ vqmmc-supply = <&vdd_1v8_sys>;
/* Azurewave AW-NH611 BCM4329 */
wifi@1 {
@@ -1030,7 +1033,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
nvidia,headset;
@@ -1056,15 +1059,15 @@
trips {
trip0: cpu-alert0 {
- /* start throttling at 50C */
- temperature = <50000>;
+ /* start throttling at 60C */
+ temperature = <60000>;
hysteresis = <200>;
type = "passive";
};
trip1: cpu-crit {
- /* shut down at 60C */
- temperature = <60000>;
+ /* shut down at 70C */
+ temperature = <70000>;
hysteresis = <2000>;
type = "critical";
};
@@ -1085,6 +1088,7 @@
emc-tables@0 {
nvidia,ram-code = <0>; /* elpida-8gb */
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1182,6 +1186,7 @@
emc-tables@1 {
nvidia,ram-code = <1>; /* elpida-4gb */
+ reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1279,6 +1284,7 @@
emc-tables@2 {
nvidia,ram-code = <2>; /* hynix-8gb */
+ reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
@@ -1376,6 +1382,7 @@
emc-tables@3 {
nvidia,ram-code = <3>; /* hynix-4gb */
+ reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/src/arm/tegra20-harmony.dts b/src/arm/tegra20-harmony.dts
index 86494cb..ae4312e 100644
--- a/src/arm/tegra20-harmony.dts
+++ b/src/arm/tegra20-harmony.dts
@@ -748,7 +748,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
diff --git a/src/arm/tegra20-medcom-wide.dts b/src/arm/tegra20-medcom-wide.dts
index a348ca3..b31c9bc 100644
--- a/src/arm/tegra20-medcom-wide.dts
+++ b/src/arm/tegra20-medcom-wide.dts
@@ -84,7 +84,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/src/arm/tegra20-paz00.dts b/src/arm/tegra20-paz00.dts
index 940a9f3..3180bff 100644
--- a/src/arm/tegra20-paz00.dts
+++ b/src/arm/tegra20-paz00.dts
@@ -2,6 +2,8 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
+#include <dt-bindings/thermal/thermal.h>
+
#include "tegra20.dtsi"
#include "tegra20-cpu-opp.dtsi"
#include "tegra20-cpu-opp-microvolt.dtsi"
@@ -318,6 +320,7 @@
nvidia,ram-code = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
+ reg = <0>;
emc-table@166500 {
reg = <166500>;
@@ -497,9 +500,10 @@
};
};
- adt7461@4c {
+ adt7461: temperature-sensor@4c {
compatible = "adi,adt7461";
reg = <0x4c>;
+ #thermal-sensor-cells = <1>;
};
};
@@ -654,11 +658,46 @@
cpu0: cpu@0 {
cpu-supply = <&cpu_vdd_reg>;
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
- cpu@1 {
+ cpu1: cpu@1 {
cpu-supply = <&cpu_vdd_reg>;
operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <500>; /* milliseconds */
+ polling-delay = <1500>; /* milliseconds */
+
+ thermal-sensors = <&adt7461 1>;
+
+ trips {
+ trip0: cpu-alert0 {
+ /* start throttling at 80C */
+ temperature = <80000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+
+ trip1: cpu-crit {
+ /* shut down at 85C */
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip0>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
diff --git a/src/arm/tegra20-plutux.dts b/src/arm/tegra20-plutux.dts
index 378f23b..5811b70 100644
--- a/src/arm/tegra20-plutux.dts
+++ b/src/arm/tegra20-plutux.dts
@@ -52,7 +52,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/src/arm/tegra20-seaboard.dts b/src/arm/tegra20-seaboard.dts
index c24d4a3..92d494b 100644
--- a/src/arm/tegra20-seaboard.dts
+++ b/src/arm/tegra20-seaboard.dts
@@ -911,7 +911,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/src/arm/tegra20-tec.dts b/src/arm/tegra20-tec.dts
index 44ced60..10ff09d 100644
--- a/src/arm/tegra20-tec.dts
+++ b/src/arm/tegra20-tec.dts
@@ -61,7 +61,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
<&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
diff --git a/src/arm/tegra20-ventana.dts b/src/arm/tegra20-ventana.dts
index 99a356c..5a2578b 100644
--- a/src/arm/tegra20-ventana.dts
+++ b/src/arm/tegra20-ventana.dts
@@ -709,7 +709,7 @@
nvidia,audio-codec = <&wm8903>;
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
- nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
+ nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
GPIO_ACTIVE_HIGH>;
nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
diff --git a/src/arm/tegra30-asus-nexus7-grouper-common.dtsi b/src/arm/tegra30-asus-nexus7-grouper-common.dtsi
index dc773b1..ae8300b 100644
--- a/src/arm/tegra30-asus-nexus7-grouper-common.dtsi
+++ b/src/arm/tegra30-asus-nexus7-grouper-common.dtsi
@@ -927,7 +927,6 @@
compatible = "ti,bq27541";
reg = <0x55>;
power-supplies = <&power_supply>;
- monitored-battery = <&battery_cell>;
};
power_supply: charger@6a {
@@ -1252,13 +1251,6 @@
};
thermal-zones {
- skin-thermal {
- polling-delay-passive = <1000>; /* milliseconds */
- polling-delay = <0>; /* milliseconds */
-
- thermal-sensors = <&nct72 0>;
- };
-
cpu-thermal {
polling-delay-passive = <1000>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
@@ -1274,8 +1266,8 @@
};
trip1: cpu-crit {
- /* shut down at 60C */
- temperature = <60000>;
+ /* shut down at 65C */
+ temperature = <65000>;
hysteresis = <2000>;
type = "critical";
};
@@ -1287,7 +1279,9 @@
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
};
};
};
diff --git a/src/arm/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/src/arm/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
index 17b6682..53966fa 100644
--- a/src/arm/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
+++ b/src/arm/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi
@@ -182,4 +182,13 @@
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
+
+ pmc@7000e400 {
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x3c>;
+ nvidia,reg-addr = <0x41>;
+ nvidia,reg-data = <0xe0>;
+ };
+ };
};
diff --git a/src/arm/tegra30-asus-nexus7-grouper-ti-pmic.dtsi b/src/arm/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
index b97da45..9365ae6 100644
--- a/src/arm/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
+++ b/src/arm/tegra30-asus-nexus7-grouper-ti-pmic.dtsi
@@ -144,7 +144,16 @@
};
vdd_3v3_sys: regulator@1 {
- gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
+ gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ pmc@7000e400 {
+ i2c-thermtrip {
+ nvidia,i2c-controller-id = <4>;
+ nvidia,bus-addr = <0x2d>;
+ nvidia,reg-addr = <0x3f>;
+ nvidia,reg-data = <0x80>;
+ };
+ };
};
diff --git a/src/arm/tegra30-cardhu.dtsi b/src/arm/tegra30-cardhu.dtsi
index 2dff14b..d9dd115 100644
--- a/src/arm/tegra30-cardhu.dtsi
+++ b/src/arm/tegra30-cardhu.dtsi
@@ -630,7 +630,7 @@
nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
- GPIO_ACTIVE_HIGH>;
+ GPIO_ACTIVE_LOW>;
clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
<&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
diff --git a/src/arm/tegra30-ouya.dts b/src/arm/tegra30-ouya.dts
index 9a10e0d..ab8744f 100644
--- a/src/arm/tegra30-ouya.dts
+++ b/src/arm/tegra30-ouya.dts
@@ -463,7 +463,9 @@
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&actmon THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
};
};
};
diff --git a/src/arm/tegra30.dtsi b/src/arm/tegra30.dtsi
index 44a6dbb..c577c19 100644
--- a/src/arm/tegra30.dtsi
+++ b/src/arm/tegra30.dtsi
@@ -410,7 +410,7 @@
reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
};
- actmon@6000c800 {
+ actmon: actmon@6000c800 {
compatible = "nvidia,tegra30-actmon";
reg = <0x6000c800 0x400>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -422,6 +422,7 @@
operating-points-v2 = <&emc_bw_dfs_opp_table>;
interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
interconnect-names = "cpu-read";
+ #cooling-cells = <2>;
};
gpio: gpio@6000d000 {
diff --git a/src/arm/vexpress-v2m-rs1.dtsi b/src/arm/vexpress-v2m-rs1.dtsi
index 4f7220b..2ad9fd7 100644
--- a/src/arm/vexpress-v2m-rs1.dtsi
+++ b/src/arm/vexpress-v2m-rs1.dtsi
@@ -144,7 +144,7 @@
compatible = "nxp,usb-isp1761";
reg = <2 0x03000000 0x20000>;
interrupts = <16>;
- port1-otg;
+ dr_mode = "peripheral";
};
iofpga-bus@300000000 {
diff --git a/src/arm/vexpress-v2m.dtsi b/src/arm/vexpress-v2m.dtsi
index 2ac41ed..ec13ceb 100644
--- a/src/arm/vexpress-v2m.dtsi
+++ b/src/arm/vexpress-v2m.dtsi
@@ -62,7 +62,7 @@
compatible = "nxp,usb-isp1761";
reg = <3 0x03000000 0x20000>;
interrupts = <16>;
- port1-otg;
+ dr_mode = "peripheral";
};
iofpga@7,00000000 {
diff --git a/src/arm64/allwinner/sun50i-a64-pinephone.dtsi b/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
index 79adea3..5b44a97 100644
--- a/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
+++ b/src/arm64/allwinner/sun50i-a64-pinephone.dtsi
@@ -25,6 +25,11 @@
/* Backlight configuration differs per PinePhone revision. */
};
+ bt_sco_codec: bt-sco-codec {
+ #sound-dai-cells = <1>;
+ compatible = "linux,bt-sco";
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
@@ -91,6 +96,8 @@
};
&codec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&aif3_pins>;
status = "okay";
};
@@ -426,6 +433,7 @@
&sound {
status = "okay";
+ simple-audio-card,name = "PinePhone";
simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
simple-audio-card,widgets = "Microphone", "Headset Microphone",
"Microphone", "Internal Microphone",
@@ -447,6 +455,23 @@
"MIC1", "Internal Microphone",
"Headset Microphone", "HBIAS",
"MIC2", "Headset Microphone";
+
+ simple-audio-card,dai-link@2 {
+ format = "dsp_a";
+ frame-master = <&link2_codec>;
+ bitclock-master = <&link2_codec>;
+ bitclock-inversion;
+
+ link2_cpu: cpu {
+ sound-dai = <&bt_sco_codec 0>;
+ };
+
+ link2_codec: codec {
+ sound-dai = <&codec 2>;
+ dai-tdm-slot-num = <1>;
+ dai-tdm-slot-width = <32>;
+ };
+ };
};
&uart0 {
diff --git a/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts b/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
index e22b94c..5e66ce1 100644
--- a/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/src/arm64/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -79,7 +79,7 @@
&emac {
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
- phy-mode = "rgmii-id";
+ phy-mode = "rgmii-txid";
phy-handle = <&ext_rgmii_phy>;
phy-supply = <®_dc1sw>;
status = "okay";
diff --git a/src/arm64/allwinner/sun50i-a64.dtsi b/src/arm64/allwinner/sun50i-a64.dtsi
index 5b30e6c..6ddb717 100644
--- a/src/arm64/allwinner/sun50i-a64.dtsi
+++ b/src/arm64/allwinner/sun50i-a64.dtsi
@@ -131,12 +131,10 @@
};
sound: sound {
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "simple-audio-card";
simple-audio-card,name = "sun50i-a64-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&cpudai>;
- simple-audio-card,bitclock-master = <&cpudai>;
- simple-audio-card,mclk-fs = <128>;
simple-audio-card,aux-devs = <&codec_analog>;
simple-audio-card,routing =
"Left DAC", "DACL",
@@ -145,12 +143,19 @@
"ADCR", "Right ADC";
status = "disabled";
- cpudai: simple-audio-card,cpu {
- sound-dai = <&dai>;
- };
+ simple-audio-card,dai-link@0 {
+ format = "i2s";
+ frame-master = <&link0_cpu>;
+ bitclock-master = <&link0_cpu>;
+ mclk-fs = <128>;
- link_codec: simple-audio-card,codec {
- sound-dai = <&codec>;
+ link0_cpu: cpu {
+ sound-dai = <&dai>;
+ };
+
+ link0_codec: codec {
+ sound-dai = <&codec 0>;
+ };
};
};
@@ -659,6 +664,18 @@
interrupt-controller;
#interrupt-cells = <3>;
+ /omit-if-no-ref/
+ aif2_pins: aif2-pins {
+ pins = "PB4", "PB5", "PB6", "PB7";
+ function = "aif2";
+ };
+
+ /omit-if-no-ref/
+ aif3_pins: aif3-pins {
+ pins = "PG10", "PG11", "PG12", "PG13";
+ function = "aif3";
+ };
+
csi_pins: csi-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5", "PE6",
"PE7", "PE8", "PE9", "PE10", "PE11";
@@ -799,6 +816,23 @@
};
};
+ timer@1c20c00 {
+ compatible = "allwinner,sun50i-a64-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x01c20c00 0xa0>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
+ wdt0: watchdog@1c20ca0 {
+ compatible = "allwinner,sun50i-a64-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x01c20ca0 0x20>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
spdif: spdif@1c21000 {
#sound-dai-cells = <0>;
compatible = "allwinner,sun50i-a64-spdif",
@@ -880,7 +914,7 @@
};
codec: codec@1c22e00 {
- #sound-dai-cells = <0>;
+ #sound-dai-cells = <1>;
compatible = "allwinner,sun50i-a64-codec",
"allwinner,sun8i-a33-codec";
reg = <0x01c22e00 0x600>;
@@ -1325,13 +1359,5 @@
#address-cells = <1>;
#size-cells = <0>;
};
-
- wdt0: watchdog@1c20ca0 {
- compatible = "allwinner,sun50i-a64-wdt",
- "allwinner,sun6i-a31-wdt";
- reg = <0x01c20ca0 0x20>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc24M>;
- };
};
};
diff --git a/src/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/src/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts
new file mode 100644
index 0000000..55bcdf8
--- /dev/null
+++ b/src/arm64/allwinner/sun50i-h5-nanopi-r1s-h5.dts
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+#include "sun50i-h5-cpu-opp.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <®_usb0_vbus>;
+ status = "okay";
+};
diff --git a/src/arm64/allwinner/sun50i-h6.dtsi b/src/arm64/allwinner/sun50i-h6.dtsi
index 5081586..30d396e 100644
--- a/src/arm64/allwinner/sun50i-h6.dtsi
+++ b/src/arm64/allwinner/sun50i-h6.dtsi
@@ -271,6 +271,15 @@
};
};
+ timer@3009000 {
+ compatible = "allwinner,sun50i-h6-timer",
+ "allwinner,sun8i-a23-timer";
+ reg = <0x03009000 0xa0>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc24M>;
+ };
+
watchdog: watchdog@30090a0 {
compatible = "allwinner,sun50i-h6-wdt",
"allwinner,sun6i-a31-wdt";
diff --git a/src/arm64/amlogic/meson-axg.dtsi b/src/arm64/amlogic/meson-axg.dtsi
index 895c43c..3f5254e 100644
--- a/src/arm64/amlogic/meson-axg.dtsi
+++ b/src/arm64/amlogic/meson-axg.dtsi
@@ -1871,6 +1871,7 @@
status = "disabled";
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
+ fifo-size = <128>;
};
};
diff --git a/src/arm64/amlogic/meson-g12-common.dtsi b/src/arm64/amlogic/meson-g12-common.dtsi
index 793d48f..00c6f53 100644
--- a/src/arm64/amlogic/meson-g12-common.dtsi
+++ b/src/arm64/amlogic/meson-g12-common.dtsi
@@ -2317,6 +2317,7 @@
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
+ fifo-size = <128>;
};
};
diff --git a/src/arm64/amlogic/meson-gx.dtsi b/src/arm64/amlogic/meson-gx.dtsi
index 3d00404..6b457b2 100644
--- a/src/arm64/amlogic/meson-gx.dtsi
+++ b/src/arm64/amlogic/meson-gx.dtsi
@@ -301,6 +301,7 @@
reg = <0x0 0x84c0 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
+ fifo-size = <128>;
};
uart_B: serial@84dc {
diff --git a/src/arm64/amlogic/meson-khadas-vim3.dtsi b/src/arm64/amlogic/meson-khadas-vim3.dtsi
index 66d6752..3cf4ecb 100644
--- a/src/arm64/amlogic/meson-khadas-vim3.dtsi
+++ b/src/arm64/amlogic/meson-khadas-vim3.dtsi
@@ -171,11 +171,16 @@
sound {
compatible = "amlogic,axg-sound-card";
model = "KHADAS-VIM3";
- audio-aux-devs = <&tdmout_a>;
+ audio-aux-devs = <&tdmin_a>, <&tdmout_a>;
audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
"TDMOUT_A IN 1", "FRDDR_B OUT 0",
"TDMOUT_A IN 2", "FRDDR_C OUT 0",
- "TDM_A Playback", "TDMOUT_A OUT";
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 3", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
assigned-clocks = <&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL0>,
@@ -198,8 +203,20 @@
sound-dai = <&frddr_c>;
};
- /* 8ch hdmi interface */
dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
sound-dai = <&tdmif_a>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-0 = <1 1>;
@@ -214,7 +231,7 @@
};
/* hdmi glue */
- dai-link-4 {
+ dai-link-7 {
sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
codec {
@@ -454,10 +471,26 @@
status = "okay";
};
+&tdmin_a {
+ status = "okay";
+};
+
&tdmout_a {
status = "okay";
};
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
&tohdmitx {
status = "okay";
};
diff --git a/src/arm64/amlogic/meson-sm1-bananapi-m5.dts b/src/arm64/amlogic/meson-sm1-bananapi-m5.dts
new file mode 100644
index 0000000..effaa13
--- /dev/null
+++ b/src/arm64/amlogic/meson-sm1-bananapi-m5.dts
@@ -0,0 +1,646 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/dts-v1/;
+
+#include "meson-sm1.dtsi"
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/gpio/meson-g12a-gpio.h>
+#include <dt-bindings/sound/meson-g12a-toacodec.h>
+#include <dt-bindings/sound/meson-g12a-tohdmitx.h>
+
+/ {
+ compatible = "bananapi,bpi-m5", "amlogic,sm1";
+ model = "Banana Pi BPI-M5";
+
+ adc_keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 2>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ key {
+ label = "SW3";
+ linux,code = <BTN_3>;
+ press-threshold-microvolt = <1700000>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ /* TOFIX: handle CVBS_DET on SARADC channel 0 */
+ cvbs-connector {
+ compatible = "composite-video-connector";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key {
+ label = "SW1";
+ linux,code = <BTN_1>;
+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ };
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+
+ blue {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio_ao GPIOAO_11 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+
+ emmc_1v8: regulator-emmc_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "EMMC_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ vddio_c: regulator-vddio_c {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_C";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_DRAIN>;
+ gpios-states = <1>;
+
+ states = <1800000 0>,
+ <3300000 1>;
+ };
+
+ tflash_vdd: regulator-tflash_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "TFLASH_VDD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ vddao_1v8: regulator-vddao_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_1V8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vddao_3v3>;
+ regulator-always-on;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ vddcpu: regulator-vddcpu {
+ /*
+ * SY8120B1ABC DC/DC Regulator.
+ */
+ compatible = "pwm-regulator";
+
+ regulator-name = "VDDCPU";
+ regulator-min-microvolt = <690000>;
+ regulator-max-microvolt = <1050000>;
+
+ vin-supply = <&dc_in>;
+
+ pwms = <&pwm_AO_cd 1 1250 0>;
+ pwm-dutycycle-range = <100 0>;
+
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* USB Hub Power Enable */
+ vl_pwr_en: regulator-vl_pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "VL_PWR_EN";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_in>;
+
+ gpio = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "BPI-M5";
+ audio-widgets = "Line", "Lineout";
+ audio-aux-devs = <&tdmout_b>, <&tdmout_c>,
+ <&tdmin_a>, <&tdmin_b>, <&tdmin_c>;
+ audio-routing = "TDMOUT_B IN 0", "FRDDR_A OUT 1",
+ "TDMOUT_B IN 1", "FRDDR_B OUT 1",
+ "TDMOUT_B IN 2", "FRDDR_C OUT 1",
+ "TDM_B Playback", "TDMOUT_B OUT",
+ "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 4", "TDM_B Loopback",
+ "TDMIN_B IN 4", "TDM_B Loopback",
+ "TDMIN_C IN 4", "TDM_B Loopback",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "Lineout", "ACODEC LOLP",
+ "Lineout", "ACODEC LORP";
+
+ assigned-clocks = <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <294912000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link-0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link-1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link-2 {
+ sound-dai = <&frddr_c>;
+ };
+
+ dai-link-3 {
+ sound-dai = <&toddr_a>;
+ };
+
+ dai-link-4 {
+ sound-dai = <&toddr_b>;
+ };
+
+ dai-link-5 {
+ sound-dai = <&toddr_c>;
+ };
+
+ /* 8ch hdmi interface */
+ dai-link-6 {
+ sound-dai = <&tdmif_b>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ dai-tdm-slot-tx-mask-1 = <1 1>;
+ dai-tdm-slot-tx-mask-2 = <1 1>;
+ dai-tdm-slot-tx-mask-3 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_B>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_B>;
+ };
+ };
+
+ /* i2s jack output interface */
+ dai-link-7 {
+ sound-dai = <&tdmif_c>;
+ dai-format = "i2s";
+ dai-tdm-slot-tx-mask-0 = <1 1>;
+ mclk-fs = <256>;
+
+ codec-0 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_IN_C>;
+ };
+
+ codec-1 {
+ sound-dai = <&toacodec TOACODEC_IN_C>;
+ };
+ };
+
+ /* hdmi glue */
+ dai-link-8 {
+ sound-dai = <&tohdmitx TOHDMITX_I2S_OUT>;
+
+ codec {
+ sound-dai = <&hdmi_tx>;
+ };
+ };
+
+ /* acodec glue */
+ dai-link-9 {
+ sound-dai = <&toacodec TOACODEC_OUT>;
+
+ codec {
+ sound-dai = <&acodec>;
+ };
+ };
+ };
+};
+
+&acodec {
+ AVDD-supply = <&vddao_1v8>;
+ status = "okay";
+};
+
+&arb {
+ status = "okay";
+};
+
+&clkc_audio {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU1_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu2 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU2_CLK>;
+ clock-latency = <50000>;
+};
+
+&cpu3 {
+ cpu-supply = <&vddcpu>;
+ operating-points-v2 = <&cpu_opp_table>;
+ clocks = <&clkc CLKID_CPU3_CLK>;
+ clock-latency = <50000>;
+};
+
+&cvbs_vdac_port {
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&cvbs_connector_in>;
+ };
+};
+
+&ext_mdio {
+ external_phy: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ max-speed = <1000>;
+
+ interrupt-parent = <&gpio_intc>;
+ /* MAC_INTR on GPIOZ_14 */
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+ðmac {
+ pinctrl-0 = <ð_pins>, <ð_rgmii_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ phy-mode = "rgmii-txid";
+ phy-handle = <&external_phy>;
+};
+
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
+&gpio {
+ gpio-line-names =
+ /* GPIOZ */
+ "ETH_MDIO", /* GPIOZ_0 */
+ "ETH_MDC", /* GPIOZ_1 */
+ "ETH_RXCLK", /* GPIOZ_2 */
+ "ETH_RX_DV", /* GPIOZ_3 */
+ "ETH_RXD0", /* GPIOZ_4 */
+ "ETH_RXD1", /* GPIOZ_5 */
+ "ETH_RXD2", /* GPIOZ_6 */
+ "ETH_RXD3", /* GPIOZ_7 */
+ "ETH_TXCLK", /* GPIOZ_8 */
+ "ETH_TXEN", /* GPIOZ_9 */
+ "ETH_TXD0", /* GPIOZ_10 */
+ "ETH_TXD1", /* GPIOZ_11 */
+ "ETH_TXD2", /* GPIOZ_12 */
+ "ETH_TXD3", /* GPIOZ_13 */
+ "ETH_INTR", /* GPIOZ_14 */
+ "ETH_NRST", /* GPIOZ_15 */
+ /* GPIOH */
+ "HDMI_SDA", /* GPIOH_0 */
+ "HDMI_SCL", /* GPIOH_1 */
+ "HDMI_HPD", /* GPIOH_2 */
+ "HDMI_CEC", /* GPIOH_3 */
+ "VL-RST_N", /* GPIOH_4 */
+ "CON1-P36", /* GPIOH_5 */
+ "VL-PWREN", /* GPIOH_6 */
+ "WiFi_3V3_1V8", /* GPIOH_7 */
+ "TFLASH_VDD_EN", /* GPIOH_8 */
+ /* BOOT */
+ "eMMC_D0", /* BOOT_0 */
+ "eMMC_D1", /* BOOT_1 */
+ "eMMC_D2", /* BOOT_2 */
+ "eMMC_D3", /* BOOT_3 */
+ "eMMC_D4", /* BOOT_4 */
+ "eMMC_D5", /* BOOT_5 */
+ "eMMC_D6", /* BOOT_6 */
+ "eMMC_D7", /* BOOT_7 */
+ "eMMC_CLK", /* BOOT_8 */
+ "",
+ "eMMC_CMD", /* BOOT_10 */
+ "",
+ "eMMC_RST#", /* BOOT_12 */
+ "eMMC_DS", /* BOOT_13 */
+ /* GPIOC */
+ "SD_D0_B", /* GPIOC_0 */
+ "SD_D1_B", /* GPIOC_1 */
+ "SD_D2_B", /* GPIOC_2 */
+ "SD_D3_B", /* GPIOC_3 */
+ "SD_CLK_B", /* GPIOC_4 */
+ "SD_CMD_B", /* GPIOC_5 */
+ "CARD_EN_DET", /* GPIOC_6 */
+ "",
+ /* GPIOA */
+ "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "",
+ "CON1-P27", /* GPIOA_14 */
+ "CON1-P28", /* GPIOA_15 */
+ /* GPIOX */
+ "CON1-P16", /* GPIOX_0 */
+ "CON1-P18", /* GPIOX_1 */
+ "CON1-P22", /* GPIOX_2 */
+ "CON1-P11", /* GPIOX_3 */
+ "CON1-P13", /* GPIOX_4 */
+ "CON1-P07", /* GPIOX_5 */
+ "CON1-P33", /* GPIOX_6 */
+ "CON1-P15", /* GPIOX_7 */
+ "CON1-P19", /* GPIOX_8 */
+ "CON1-P21", /* GPIOX_9 */
+ "CON1-P24", /* GPIOX_10 */
+ "CON1-P23", /* GPIOX_11 */
+ "CON1-P08", /* GPIOX_12 */
+ "CON1-P10", /* GPIOX_13 */
+ "CON1-P29", /* GPIOX_14 */
+ "CON1-P31", /* GPIOX_15 */
+ "CON1-P26", /* GPIOX_16 */
+ "CON1-P03", /* GPIOX_17 */
+ "CON1-P05", /* GPIOX_18 */
+ "CON1-P32"; /* GPIOX_19 */
+
+ /*
+ * WARNING: The USB Hub on the BPI-M5 needs a reset signal
+ * to be turned high in order to be detected by the USB Controller
+ * This signal should be handled by a USB specific power sequence
+ * in order to reset the Hub when USB bus is powered down.
+ */
+ usb-hub {
+ gpio-hog;
+ gpios = <GPIOH_4 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb-hub-reset";
+ };
+};
+
+&gpio_ao {
+ gpio-line-names =
+ /* GPIOAO */
+ "DEBUG TX", /* GPIOAO_0 */
+ "DEBUG RX", /* GPIOAO_1 */
+ "SYS_LED2", /* GPIOAO_2 */
+ "UPDATE_KEY", /* GPIOAO_3 */
+ "CON1-P40", /* GPIOAO_4 */
+ "IR_IN", /* GPIOAO_5 */
+ "TF_3V3N_1V8_EN", /* GPIOAO_6 */
+ "CON1-P35", /* GPIOAO_7 */
+ "CON1-P12", /* GPIOAO_8 */
+ "CON1-P37", /* GPIOAO_9 */
+ "CON1-P38", /* GPIOAO_10 */
+ "SYS_LED", /* GPIOAO_11 */
+ /* GPIOE */
+ "VDDEE_PWM", /* GPIOE_0 */
+ "VDDCPU_PWM", /* GPIOE_1 */
+ "TF_PWR_EN"; /* GPIOE_2 */
+};
+
+&hdmi_tx {
+ status = "okay";
+ pinctrl-0 = <&hdmitx_hpd_pins>, <&hdmitx_ddc_pins>;
+ pinctrl-names = "default";
+ hdmi-supply = <&dc_in>;
+};
+
+&hdmi_tx_tmds_port {
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+&pwm_AO_cd {
+ pinctrl-0 = <&pwm_ao_d_e_pins>;
+ pinctrl-names = "default";
+ clocks = <&xtal>;
+ clock-names = "clkin1";
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddao_1v8>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_c_pins>;
+ pinctrl-1 = <&sdcard_clk_gate_c_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <50000000>;
+ disable-wp;
+
+ /* TOFIX: SD card is barely usable in SDR modes */
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&tflash_vdd>;
+ vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+ pinctrl-1 = <&emmc_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ disable-wp;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&emmc_1v8>;
+};
+
+&tdmif_b {
+ status = "okay";
+};
+
+&tdmif_c {
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmout_b {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&toacodec {
+ status = "okay";
+};
+
+&tohdmitx {
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb2_phy0 {
+ phy-supply = <&dc_in>;
+};
+
+&usb2_phy1 {
+ /* Enable the hub which is connected to this port */
+ phy-supply = <&vl_pwr_en>;
+};
diff --git a/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts b/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
index 06de0b1..f2c0981 100644
--- a/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
+++ b/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts
@@ -32,6 +32,19 @@
regulator-boot-on;
regulator-always-on;
};
+
+ sound {
+ model = "G12B-KHADAS-VIM3L";
+ audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
+ "TDMOUT_A IN 1", "FRDDR_B OUT 0",
+ "TDMOUT_A IN 2", "FRDDR_C OUT 0",
+ "TDM_A Playback", "TDMOUT_A OUT",
+ "TDMIN_A IN 0", "TDM_A Capture",
+ "TDMIN_A IN 13", "TDM_A Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT";
+ };
};
&cpu0 {
diff --git a/src/arm64/amlogic/meson-sm1-odroid-c4.dts b/src/arm64/amlogic/meson-sm1-odroid-c4.dts
index 8c327c0..8c30ce6 100644
--- a/src/arm64/amlogic/meson-sm1-odroid-c4.dts
+++ b/src/arm64/amlogic/meson-sm1-odroid-c4.dts
@@ -23,18 +23,6 @@
};
};
- hub_5v: regulator-hub_5v {
- compatible = "regulator-fixed";
- regulator-name = "HUB_5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- vin-supply = <&vcc_5v>;
-
- /* Connected to the Hub CHIPENABLE, LOW sets low power state */
- gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
sound {
model = "ODROID-C4";
};
@@ -58,8 +46,3 @@
&ir {
linux,rc-map-name = "rc-odroid";
};
-
-&usb2_phy1 {
- /* Enable the hub which is connected to this port */
- phy-supply = <&hub_5v>;
-};
diff --git a/src/arm64/amlogic/meson-sm1-odroid-hc4.dts b/src/arm64/amlogic/meson-sm1-odroid-hc4.dts
index bf15700..f3f9532 100644
--- a/src/arm64/amlogic/meson-sm1-odroid-hc4.dts
+++ b/src/arm64/amlogic/meson-sm1-odroid-hc4.dts
@@ -44,6 +44,32 @@
};
};
+ /* Powers the SATA Disk 0 regulator, which is enabled when a disk load is detected */
+ p12v_0: regulator-p12v_0 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ /* Powers the SATA Disk 1 regulator, which is enabled when a disk load is detected */
+ p12v_1: regulator-p12v_1 {
+ compatible = "regulator-fixed";
+ regulator-name = "P12V_1";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
sound {
model = "ODROID-HC4";
};
@@ -90,7 +116,25 @@
status = "disabled";
};
+&spifc {
+ status = "okay";
+ pinctrl-0 = <&nor_pins>;
+ pinctrl-names = "default";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ };
+};
+
&usb {
- phys = <&usb2_phy0>, <&usb2_phy1>;
- phy-names = "usb2-phy0", "usb2-phy1";
+ phys = <&usb2_phy1>;
+ phy-names = "usb2-phy1";
+};
+
+&usb2_phy0 {
+ status = "disabled";
};
diff --git a/src/arm64/amlogic/meson-sm1-odroid.dtsi b/src/arm64/amlogic/meson-sm1-odroid.dtsi
index d14716b..fd0ad85 100644
--- a/src/arm64/amlogic/meson-sm1-odroid.dtsi
+++ b/src/arm64/amlogic/meson-sm1-odroid.dtsi
@@ -46,8 +46,13 @@
regulator-name = "TF_IO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc_5v>;
- gpios = <&gpio_ao GPIOAO_6 GPIO_ACTIVE_HIGH>;
+ enable-gpio = <&gpio GPIOE_2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+
+ gpios = <&gpio_ao GPIOAO_6 GPIO_OPEN_SOURCE>;
gpios-states = <0>;
states = <3300000 0>,
@@ -78,6 +83,8 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&main_12v>;
+ gpio = <&gpio GPIOH_8 GPIO_OPEN_DRAIN>;
+ enable-active-high;
};
vcc_1v8: regulator-vcc_1v8 {
diff --git a/src/arm64/amlogic/meson-sm1.dtsi b/src/arm64/amlogic/meson-sm1.dtsi
index c309517..3d8b1f4 100644
--- a/src/arm64/amlogic/meson-sm1.dtsi
+++ b/src/arm64/amlogic/meson-sm1.dtsi
@@ -401,6 +401,16 @@
status = "disabled";
};
+ toacodec: audio-controller@740 {
+ compatible = "amlogic,sm1-toacodec",
+ "amlogic,g12a-toacodec";
+ reg = <0x0 0x740 0x0 0x4>;
+ #sound-dai-cells = <1>;
+ sound-name-prefix = "TOACODEC";
+ resets = <&clkc_audio AUD_RESET_TOACODEC>;
+ status = "disabled";
+ };
+
tohdmitx: audio-controller@744 {
compatible = "amlogic,sm1-tohdmitx",
"amlogic,g12a-tohdmitx";
diff --git a/src/arm64/arm/juno-base.dtsi b/src/arm64/arm/juno-base.dtsi
index 1cc7fdc..8e7a669 100644
--- a/src/arm64/arm/juno-base.dtsi
+++ b/src/arm64/arm/juno-base.dtsi
@@ -568,13 +568,13 @@
clocks {
compatible = "arm,scpi-clocks";
- scpi_dvfs: scpi-dvfs {
+ scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>, <2>;
clock-output-names = "atlclk", "aplclk","gpuclk";
};
- scpi_clk: scpi-clk {
+ scpi_clk: clocks-1 {
compatible = "arm,scpi-variable-clocks";
#clock-cells = <1>;
clock-indices = <3>;
@@ -582,7 +582,7 @@
};
};
- scpi_devpd: scpi-power-domains {
+ scpi_devpd: power-controller {
compatible = "arm,scpi-power-domains";
num-domains = <2>;
#power-domain-cells = <1>;
diff --git a/src/arm64/arm/vexpress-v2m-rs1.dtsi b/src/arm64/arm/vexpress-v2m-rs1.dtsi
index 4f7220b..2ad9fd7 100644
--- a/src/arm64/arm/vexpress-v2m-rs1.dtsi
+++ b/src/arm64/arm/vexpress-v2m-rs1.dtsi
@@ -144,7 +144,7 @@
compatible = "nxp,usb-isp1761";
reg = <2 0x03000000 0x20000>;
interrupts = <16>;
- port1-otg;
+ dr_mode = "peripheral";
};
iofpga-bus@300000000 {
diff --git a/src/arm64/broadcom/bcm2711-rpi-400.dts b/src/arm64/broadcom/bcm2711-rpi-400.dts
new file mode 100644
index 0000000..b9000f5
--- /dev/null
+++ b/src/arm64/broadcom/bcm2711-rpi-400.dts
@@ -0,0 +1,2 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "arm/bcm2711-rpi-400.dts"
diff --git a/src/arm64/broadcom/bcm4908/bcm4908.dtsi b/src/arm64/broadcom/bcm4908/bcm4908.dtsi
index 8060178..a5a64d1 100644
--- a/src/arm64/broadcom/bcm4908/bcm4908.dtsi
+++ b/src/arm64/broadcom/bcm4908/bcm4908.dtsi
@@ -306,7 +306,7 @@
interrupt-names = "nand";
status = "okay";
- nandcs: nandcs@0 {
+ nandcs: nand@0 {
compatible = "brcm,nandcs";
reg = <0>;
};
diff --git a/src/arm64/broadcom/stingray/stingray.dtsi b/src/arm64/broadcom/stingray/stingray.dtsi
index 2ffb2c9..7b04dfe 100644
--- a/src/arm64/broadcom/stingray/stingray.dtsi
+++ b/src/arm64/broadcom/stingray/stingray.dtsi
@@ -470,7 +470,7 @@
status = "disabled";
};
- uart0: uart@100000 {
+ uart0: serial@100000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00100000 0x1000>;
@@ -481,7 +481,7 @@
status = "disabled";
};
- uart1: uart@110000 {
+ uart1: serial@110000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00110000 0x1000>;
@@ -492,7 +492,7 @@
status = "disabled";
};
- uart2: uart@120000 {
+ uart2: serial@120000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00120000 0x1000>;
@@ -503,7 +503,7 @@
status = "disabled";
};
- uart3: uart@130000 {
+ uart3: serial@130000 {
device_type = "serial";
compatible = "snps,dw-apb-uart";
reg = <0x00130000 0x1000>;
diff --git a/src/arm64/exynos/exynos5433-tm2-common.dtsi b/src/arm64/exynos/exynos5433-tm2-common.dtsi
index 773d9ab..cbcc01a 100644
--- a/src/arm64/exynos/exynos5433-tm2-common.dtsi
+++ b/src/arm64/exynos/exynos5433-tm2-common.dtsi
@@ -391,6 +391,7 @@
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
reg = <0x66>;
samsung,s2mps11-wrstbi-ground;
+ wakeup-source;
s2mps13_osc: clocks {
compatible = "samsung,s2mps13-clk";
diff --git a/src/arm64/freescale/fsl-ls1012a-frwy.dts b/src/arm64/freescale/fsl-ls1012a-frwy.dts
index 6290e2f..e856258 100644
--- a/src/arm64/freescale/fsl-ls1012a-frwy.dts
+++ b/src/arm64/freescale/fsl-ls1012a-frwy.dts
@@ -24,6 +24,10 @@
status = "okay";
};
+&pcie1 {
+ status = "okay";
+};
+
&qspi {
status = "okay";
diff --git a/src/arm64/freescale/fsl-ls1012a.dtsi b/src/arm64/freescale/fsl-ls1012a.dtsi
index 9058cfa..50a72cd 100644
--- a/src/arm64/freescale/fsl-ls1012a.dtsi
+++ b/src/arm64/freescale/fsl-ls1012a.dtsi
@@ -238,35 +238,35 @@
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
- reg = <0x60000 0x100 0x60e00 0x18>;
+ reg = <0x60000 0x100>, <0x60e00 0x18>;
ranges = <0x0 0x60100 0x500>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x00 0x20 0x100 0x100>;
+ reg = <0x00 0x20>, <0x100 0x100>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x20 0x20 0x200 0x100>;
+ reg = <0x20 0x20>, <0x200 0x100>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x40 0x20 0x300 0x100>;
+ reg = <0x40 0x20>, <0x300 0x100>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v5.4-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
- reg = <0x60 0x20 0x400 0x100>;
+ reg = <0x60 0x20>, <0x400 0x100>;
};
};
};
@@ -522,8 +522,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1012a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
diff --git a/src/arm64/freescale/fsl-ls1028a-rdb.dts b/src/arm64/freescale/fsl-ls1028a-rdb.dts
index 9322c6a..d7b5272 100644
--- a/src/arm64/freescale/fsl-ls1028a-rdb.dts
+++ b/src/arm64/freescale/fsl-ls1028a-rdb.dts
@@ -275,6 +275,10 @@
status = "okay";
};
+&optee {
+ status = "okay";
+};
+
&sai4 {
status = "okay";
};
diff --git a/src/arm64/freescale/fsl-ls1028a.dtsi b/src/arm64/freescale/fsl-ls1028a.dtsi
index a30249e..b2e3e5d 100644
--- a/src/arm64/freescale/fsl-ls1028a.dtsi
+++ b/src/arm64/freescale/fsl-ls1028a.dtsi
@@ -88,7 +88,7 @@
};
firmware {
- optee {
+ optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
status = "disabled";
@@ -617,8 +617,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1028a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
@@ -644,8 +644,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1028a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -990,19 +990,19 @@
msi-map = <0 &its 0x17 0xe>;
iommu-map = <0 &smmu 0x17 0xe>;
/* PF0-6 BAR0 - non-prefetchable memory */
- ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
+ ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000
/* PF0-6 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
+ 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000
/* PF0: VF0-1 BAR0 - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
+ 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000
/* PF0: VF0-1 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
+ 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000
/* PF1: VF0-1 BAR0 - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
+ 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000
/* PF1: VF0-1 BAR2 - prefetchable memory */
- 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
+ 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000
/* BAR4 (PF5) - non-prefetchable memory */
- 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
+ 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>;
enetc_port0: ethernet@0,0 {
compatible = "fsl,enetc";
diff --git a/src/arm64/freescale/fsl-ls1043a.dtsi b/src/arm64/freescale/fsl-ls1043a.dtsi
index 28c51e5..01b01e3 100644
--- a/src/arm64/freescale/fsl-ls1043a.dtsi
+++ b/src/arm64/freescale/fsl-ls1043a.dtsi
@@ -869,8 +869,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 0x4>, /* controller interrupt */
<0 117 0x4>; /* PME interrupt */
@@ -895,8 +895,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 128 0x4>,
<0 127 0x4>;
@@ -921,8 +921,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1043a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 162 0x4>,
<0 161 0x4>;
diff --git a/src/arm64/freescale/fsl-ls1046a.dtsi b/src/arm64/freescale/fsl-ls1046a.dtsi
index 3945830..687fea6 100644
--- a/src/arm64/freescale/fsl-ls1046a.dtsi
+++ b/src/arm64/freescale/fsl-ls1046a.dtsi
@@ -773,8 +773,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -799,8 +799,8 @@
pcie_ep1: pcie_ep@3400000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
- reg = <0x00 0x03400000 0x0 0x00100000
- 0x40 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03400000 0x0 0x00100000>,
+ <0x40 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
@@ -809,8 +809,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -835,8 +835,8 @@
pcie_ep2: pcie_ep@3500000 {
compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
- reg = <0x00 0x03500000 0x0 0x00100000
- 0x48 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03500000 0x0 0x00100000>,
+ <0x48 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
@@ -845,8 +845,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1046a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
@@ -871,8 +871,8 @@
pcie_ep3: pcie_ep@3600000 {
compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03600000 0x0 0x00100000
- 0x50 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03600000 0x0 0x00100000>,
+ <0x50 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
diff --git a/src/arm64/freescale/fsl-ls1088a.dtsi b/src/arm64/freescale/fsl-ls1088a.dtsi
index 8ffbc9f..2fa6cfb 100644
--- a/src/arm64/freescale/fsl-ls1088a.dtsi
+++ b/src/arm64/freescale/fsl-ls1088a.dtsi
@@ -536,8 +536,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -562,8 +562,8 @@
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03400000 0x0 0x00100000
- 0x20 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03400000 0x0 0x00100000>,
+ <0x20 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <24>;
num-ob-windows = <256>;
@@ -573,8 +573,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -599,8 +599,8 @@
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03500000 0x0 0x00100000
- 0x28 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03500000 0x0 0x00100000>,
+ <0x28 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <6>;
@@ -609,8 +609,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,ls1088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "aer";
@@ -635,8 +635,8 @@
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
- reg = <0x00 0x03600000 0x0 0x00100000
- 0x30 0x00000000 0x8 0x00000000>;
+ reg = <0x00 0x03600000 0x0 0x00100000>,
+ <0x30 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <6>;
diff --git a/src/arm64/freescale/fsl-ls2080a.dtsi b/src/arm64/freescale/fsl-ls2080a.dtsi
index 76ab68d..6f6667b 100644
--- a/src/arm64/freescale/fsl-ls2080a.dtsi
+++ b/src/arm64/freescale/fsl-ls2080a.dtsi
@@ -120,32 +120,32 @@
};
&pcie1 {
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x10 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie2 {
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x12 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie3 {
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x14 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
&pcie4 {
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x16 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
diff --git a/src/arm64/freescale/fsl-ls2088a.dtsi b/src/arm64/freescale/fsl-ls2088a.dtsi
index da24dc1..c3dc381 100644
--- a/src/arm64/freescale/fsl-ls2088a.dtsi
+++ b/src/arm64/freescale/fsl-ls2088a.dtsi
@@ -121,8 +121,8 @@
&pcie1 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
@@ -130,8 +130,8 @@
&pcie2 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
@@ -139,8 +139,8 @@
&pcie3 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
@@ -148,8 +148,8 @@
&pcie4 {
compatible = "fsl,ls2088a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x38 0x00000000 0x0 0x00002000>; /* configuration space */
ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
diff --git a/src/arm64/freescale/fsl-ls208xa.dtsi b/src/arm64/freescale/fsl-ls208xa.dtsi
index 135ac82..801ba96 100644
--- a/src/arm64/freescale/fsl-ls208xa.dtsi
+++ b/src/arm64/freescale/fsl-ls208xa.dtsi
@@ -929,7 +929,6 @@
QORIQ_CLK_PLL_DIV(4)>;
clock-names = "dspi";
spi-num-chipselects = <5>;
- bus-num = <0>;
};
esdhc: esdhc@2140000 {
diff --git a/src/arm64/freescale/fsl-lx2160a.dtsi b/src/arm64/freescale/fsl-lx2160a.dtsi
index 0551f6f..c4b1a59 100644
--- a/src/arm64/freescale/fsl-lx2160a.dtsi
+++ b/src/arm64/freescale/fsl-lx2160a.dtsi
@@ -1089,8 +1089,8 @@
pcie1: pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
- 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
+ <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1117,8 +1117,8 @@
pcie2: pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
- 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
+ <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1145,8 +1145,8 @@
pcie3: pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
- 0x90 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
+ <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1173,8 +1173,8 @@
pcie4: pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
- 0x98 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
+ <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1201,8 +1201,8 @@
pcie5: pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
- 0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
+ <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
@@ -1229,8 +1229,8 @@
pcie6: pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
- reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
- 0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
+ <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "csr_axi_slave", "config_axi_slave";
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
diff --git a/src/arm64/freescale/imx8-ss-conn.dtsi b/src/arm64/freescale/imx8-ss-conn.dtsi
index e1e81ca..a79f42a 100644
--- a/src/arm64/freescale/imx8-ss-conn.dtsi
+++ b/src/arm64/freescale/imx8-ss-conn.dtsi
@@ -77,9 +77,12 @@
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
<&enet0_lpcg IMX_LPCG_CLK_2>,
- <&enet0_lpcg IMX_LPCG_CLK_1>,
+ <&enet0_lpcg IMX_LPCG_CLK_3>,
<&enet0_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
@@ -94,9 +97,12 @@
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
<&enet1_lpcg IMX_LPCG_CLK_2>,
- <&enet1_lpcg IMX_LPCG_CLK_1>,
+ <&enet1_lpcg IMX_LPCG_CLK_3>,
<&enet1_lpcg IMX_LPCG_CLK_0>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
+ assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
+ assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;
@@ -152,15 +158,19 @@
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
- <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
- <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
- <IMX_LPCG_CLK_5>;
- clock-output-names = "enet0_ipg_root_clk",
- "enet0_tx_clk",
- "enet0_ahb_clk",
- "enet0_ipg_clk",
- "enet0_ipg_s_clk";
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet0_lpcg_timer_clk",
+ "enet0_lpcg_txc_sampling_clk",
+ "enet0_lpcg_ahb_clk",
+ "enet0_lpcg_rgmii_txc_clk",
+ "enet0_lpcg_ipg_clk",
+ "enet0_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_0>;
};
@@ -170,15 +180,19 @@
#clock-cells = <1>;
clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
<&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
- <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
+ <&conn_axi_clk>,
+ <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
- <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
- <IMX_LPCG_CLK_5>;
- clock-output-names = "enet1_ipg_root_clk",
- "enet1_tx_clk",
- "enet1_ahb_clk",
- "enet1_ipg_clk",
- "enet1_ipg_s_clk";
+ <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
+ clock-output-names = "enet1_lpcg_timer_clk",
+ "enet1_lpcg_txc_sampling_clk",
+ "enet1_lpcg_ahb_clk",
+ "enet1_lpcg_rgmii_txc_clk",
+ "enet1_lpcg_ipg_clk",
+ "enet1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
};
diff --git a/src/arm64/freescale/imx8mm-evk.dtsi b/src/arm64/freescale/imx8mm-evk.dtsi
index 6518f08..e033d02 100644
--- a/src/arm64/freescale/imx8mm-evk.dtsi
+++ b/src/arm64/freescale/imx8mm-evk.dtsi
@@ -314,6 +314,7 @@
srp-disable;
adp-disable;
usb-role-switch;
+ disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
diff --git a/src/arm64/freescale/imx8mm-venice-gw7901.dts b/src/arm64/freescale/imx8mm-venice-gw7901.dts
new file mode 100644
index 0000000..5a1e9df
--- /dev/null
+++ b/src/arm64/freescale/imx8mm-venice-gw7901.dts
@@ -0,0 +1,1019 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2020 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/leds/common.h>
+
+#include "imx8mm.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7901 i.MX8MM board";
+ compatible = "gw,imx8mm-gw7901", "fsl,imx8mm";
+
+ aliases {
+ ethernet0 = &fec1;
+ ethernet1 = &lan1;
+ ethernet2 = &lan2;
+ ethernet3 = &lan3;
+ ethernet4 = &lan4;
+ usb0 = &usbotg1;
+ usb1 = &usbotg2;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user-pb {
+ label = "user_pb";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ user-pb1x {
+ label = "user_pb1x";
+ linux,code = <BTN_1>;
+ interrupt-parent = <&gsc>;
+ interrupts = <0>;
+ };
+
+ key-erased {
+ label = "key_erased";
+ linux,code = <BTN_2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <1>;
+ };
+
+ eeprom-wp {
+ label = "eeprom_wp";
+ linux,code = <BTN_3>;
+ interrupt-parent = <&gsc>;
+ interrupts = <2>;
+ };
+
+ tamper {
+ label = "tamper";
+ linux,code = <BTN_4>;
+ interrupt-parent = <&gsc>;
+ interrupts = <5>;
+ };
+
+ switch-hold {
+ label = "switch_hold";
+ linux,code = <BTN_5>;
+ interrupt-parent = <&gsc>;
+ interrupts = <7>;
+ };
+ };
+
+ led-controller {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led01_red";
+ gpios = <&leds_gpio 0 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led01_grn";
+ gpios = <&leds_gpio 1 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-2 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led02_red";
+ gpios = <&leds_gpio 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-3 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led02_grn";
+ gpios = <&leds_gpio 3 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-4 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led03_red";
+ gpios = <&leds_gpio 4 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-5 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led03_grn";
+ gpios = <&leds_gpio 5 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-6 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led04_red";
+ gpios = <&leds_gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-7 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led04_grn";
+ gpios = <&leds_gpio 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-8 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led05_red";
+ gpios = <&leds_gpio 10 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-9 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led05_grn";
+ gpios = <&leds_gpio 11 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-a {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ label = "led06_red";
+ gpios = <&leds_gpio 12 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led-b {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_GREEN>;
+ label = "led06_grn";
+ gpios = <&leds_gpio 13 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator-ioexp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_ioexp>;
+ compatible = "regulator-fixed";
+ regulator-name = "ioexp";
+ gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator-isouart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_isouart>;
+ compatible = "regulator-fixed";
+ regulator-name = "iso_uart";
+ gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb2_vbus: regulator-usb2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usb2>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_usb2_vbus";
+ gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wifi: regulator-wifi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wl>;
+ compatible = "regulator-fixed";
+ regulator-name = "wifi";
+ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ opp-750M {
+ opp-hz = /bits/ 64 <750000000>;
+ };
+ };
+};
+
+&ecspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ status = "okay";
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ local-mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ gsc: gsc@20 {
+ compatible = "gw,gsc";
+ reg = <0x20>;
+ pinctrl-0 = <&pinctrl_gsc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc {
+ compatible = "gw,gsc-adc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@6 {
+ gw,mode = <0>;
+ reg = <0x06>;
+ label = "temp";
+ };
+
+ channel@8 {
+ gw,mode = <1>;
+ reg = <0x08>;
+ label = "vdd_bat";
+ };
+
+ channel@82 {
+ gw,mode = <2>;
+ reg = <0x82>;
+ label = "vin_aux1";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@84 {
+ gw,mode = <2>;
+ reg = <0x84>;
+ label = "vin_aux2";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@86 {
+ gw,mode = <2>;
+ reg = <0x86>;
+ label = "vdd_vin";
+ gw,voltage-divider-ohms = <22100 1000>;
+ };
+
+ channel@88 {
+ gw,mode = <2>;
+ reg = <0x88>;
+ label = "vdd_3p3";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8c {
+ gw,mode = <2>;
+ reg = <0x8c>;
+ label = "vdd_2p5";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+
+ channel@8e {
+ gw,mode = <2>;
+ reg = <0x8e>;
+ label = "vdd_0p95";
+ };
+
+ channel@90 {
+ gw,mode = <2>;
+ reg = <0x90>;
+ label = "vdd_soc";
+ };
+
+ channel@92 {
+ gw,mode = <2>;
+ reg = <0x92>;
+ label = "vdd_arm";
+ };
+
+ channel@98 {
+ gw,mode = <2>;
+ reg = <0x98>;
+ label = "vdd_1p8";
+ };
+
+ channel@9a {
+ gw,mode = <2>;
+ reg = <0x9a>;
+ label = "vdd_1p2";
+ };
+
+ channel@9c {
+ gw,mode = <2>;
+ reg = <0x9c>;
+ label = "vdd_dram";
+ };
+
+ channel@a2 {
+ gw,mode = <2>;
+ reg = <0xa2>;
+ label = "vdd_gsc";
+ gw,voltage-divider-ohms = <10000 10000>;
+ };
+ };
+ };
+
+ gpio: gpio@23 {
+ compatible = "nxp,pca9555";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&gsc>;
+ interrupts = <4>;
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ eeprom@51 {
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+
+ eeprom@52 {
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
+
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ pagesize = <16>;
+ };
+
+ rtc@68 {
+ compatible = "dallas,ds1672";
+ reg = <0x68>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ /* vdd_soc: 0.805-0.900V (typ=0.8V) */
+ BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ /* vdd_arm: 0.805-1.0V (typ=0.9V) */
+ BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
+ BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_3p3 */
+ BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_1p8 */
+ BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_dram */
+ BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* nvcc_snvs_1p8 */
+ LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdd_snvs_0p8 */
+ LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ /* vdda_1p8 */
+ LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ leds_gpio: gpio@20 {
+ compatible = "nxp,pca9555";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ switch: switch@5f {
+ compatible = "microchip,ksz9897";
+ reg = <0x5f>;
+ pinctrl-0 = <&pinctrl_ksz>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ phy-mode = "rgmii-id";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lan1: port@0 {
+ reg = <0>;
+ label = "lan1";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan2: port@1 {
+ reg = <1>;
+ label = "lan2";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan3: port@2 {
+ reg = <2>;
+ label = "lan3";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ lan4: port@3 {
+ reg = <3>;
+ label = "lan4";
+ local-mac-address = [00 00 00 00 00 00];
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&fec1>;
+ phy-mode = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+
+ crypto@60 {
+ compatible = "atmel,atecc508a";
+ reg = <0x60>;
+ };
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
+ rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+ dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+/* console */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
+ cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
+ cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ vbus-supply = <®_usb2_vbus>;
+ status = "okay";
+};
+
+/* SDIO WiFi */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <4>;
+ non-removable;
+ vmmc-supply = <®_wifi>;
+ status = "okay";
+};
+
+/* microSD */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ vmmc-supply = <®_3p3v>;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* DIG2_OUT */
+ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* DIG2_IN */
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* DIG1_IN */
+ MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIG1_OUT */
+ MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
+ MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
+ MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* IRQ# */
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* RST# */
+ >;
+ };
+
+ pinctrl_gsc: gscgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x159
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_ksz: kszgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x41
+ MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x41 /* RST# */
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41
+ >;
+ };
+
+ pinctrl_reg_isouart: regisouartgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041
+ >;
+ };
+
+ pinctrl_reg_ioexp: regioexpgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041
+ >;
+ };
+
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000041
+ >;
+ };
+
+ pinctrl_reg_usb2: regusb1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x41
+ MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x41
+ >;
+ };
+
+ pinctrl_spi1: spi1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
+ MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
+ MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
+ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x140
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
+ MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
+ MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
+ MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140
+ MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x140
+ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x140
+ MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x140
+ >;
+ };
+
+ pinctrl_uart1_gpio: uart1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
+ MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140
+ MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140
+ >;
+ };
+
+ pinctrl_uart3_gpio: uart3gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000041 /* RS485# */
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
+ MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
+ MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x140
+ MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x140
+ >;
+ };
+
+ pinctrl_uart4_gpio: uart4gpiogrp {
+ fsl,pins = <
+
+ MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
+
+&cpu_alert0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+};
+
+&cpu_crit0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+};
diff --git a/src/arm64/freescale/imx8mm.dtsi b/src/arm64/freescale/imx8mm.dtsi
index a27e02b..e7648c3 100644
--- a/src/arm64/freescale/imx8mm.dtsi
+++ b/src/arm64/freescale/imx8mm.dtsi
@@ -261,6 +261,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mm_uid>;
nvmem-cell-names = "soc_unique_id";
@@ -271,117 +272,125 @@
#size-cells = <1>;
ranges = <0x30000000 0x30000000 0x400000>;
- sai1: sai@30010000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30010000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
- <&clk IMX8MM_CLK_SAI1_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ spba2: spba-bus@30000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30000000 0x100000>;
+ ranges;
- sai2: sai@30020000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30020000 0x10000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
- <&clk IMX8MM_CLK_SAI2_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai1: sai@30010000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30010000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
+ <&clk IMX8MM_CLK_SAI1_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai3: sai@30030000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30030000 0x10000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
- <&clk IMX8MM_CLK_SAI3_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai2: sai@30020000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30020000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
+ <&clk IMX8MM_CLK_SAI2_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai5: sai@30050000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30050000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
- <&clk IMX8MM_CLK_SAI5_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai3: sai@30030000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30030000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
+ <&clk IMX8MM_CLK_SAI3_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai6: sai@30060000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
- reg = <0x30060000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
- <&clk IMX8MM_CLK_SAI6_ROOT>,
- <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ sai5: sai@30050000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30050000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
+ <&clk IMX8MM_CLK_SAI5_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- micfil: audio-controller@30080000 {
- compatible = "fsl,imx8mm-micfil";
- reg = <0x30080000 0x10000>;
- interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_PDM_IPG>,
- <&clk IMX8MM_CLK_PDM_ROOT>,
- <&clk IMX8MM_AUDIO_PLL1_OUT>,
- <&clk IMX8MM_AUDIO_PLL2_OUT>,
- <&clk IMX8MM_CLK_EXT3>;
- clock-names = "ipg_clk", "ipg_clk_app",
- "pll8k", "pll11k", "clkext3";
- dmas = <&sdma2 24 25 0x80000000>;
- dma-names = "rx";
- status = "disabled";
- };
+ sai6: sai@30060000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
+ reg = <0x30060000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
+ <&clk IMX8MM_CLK_SAI6_ROOT>,
+ <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
+ clock-names = "bus", "mclk1", "mclk2", "mclk3";
+ dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- spdif1: spdif@30090000 {
- compatible = "fsl,imx35-spdif";
- reg = <0x30090000 0x10000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
- <&clk IMX8MM_CLK_24M>, /* rxtx0 */
- <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
- <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
- <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
- <&clk IMX8MM_CLK_DUMMY>; /* spba */
- clock-names = "core", "rxtx0",
- "rxtx1", "rxtx2",
- "rxtx3", "rxtx4",
- "rxtx5", "rxtx6",
- "rxtx7", "spba";
- dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
- dma-names = "rx", "tx";
- status = "disabled";
+ micfil: audio-controller@30080000 {
+ compatible = "fsl,imx8mm-micfil";
+ reg = <0x30080000 0x10000>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_PDM_IPG>,
+ <&clk IMX8MM_CLK_PDM_ROOT>,
+ <&clk IMX8MM_AUDIO_PLL1_OUT>,
+ <&clk IMX8MM_AUDIO_PLL2_OUT>,
+ <&clk IMX8MM_CLK_EXT3>;
+ clock-names = "ipg_clk", "ipg_clk_app",
+ "pll8k", "pll11k", "clkext3";
+ dmas = <&sdma2 24 25 0x80000000>;
+ dma-names = "rx";
+ status = "disabled";
+ };
+
+ spdif1: spdif@30090000 {
+ compatible = "fsl,imx35-spdif";
+ reg = <0x30090000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
+ <&clk IMX8MM_CLK_24M>, /* rxtx0 */
+ <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
+ <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
+ <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
+ <&clk IMX8MM_CLK_DUMMY>; /* spba */
+ clock-names = "core", "rxtx0",
+ "rxtx1", "rxtx2",
+ "rxtx3", "rxtx4",
+ "rxtx5", "rxtx6",
+ "rxtx7", "spba";
+ dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
};
gpio1: gpio@30200000 {
@@ -670,80 +679,88 @@
ranges = <0x30800000 0x30800000 0x400000>,
<0x8000000 0x8000000 0x10000000>;
- ecspi1: spi@30820000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ spba1: spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
- <&clk IMX8MM_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
- ecspi2: spi@30830000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
- <&clk IMX8MM_CLK_ECSPI2_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi1: spi@30820000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- ecspi3: spi@30840000 {
- compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
- <&clk IMX8MM_CLK_ECSPI3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi2: spi@30830000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
- <&clk IMX8MM_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi3: spi@30840000 {
+ compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MM_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
- <&clk IMX8MM_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
+ <&clk IMX8MM_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
- <&clk IMX8MM_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
+ <&clk IMX8MM_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
+ <&clk IMX8MM_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
};
crypto: crypto@30900000 {
diff --git a/src/arm64/freescale/imx8mn-beacon-som.dtsi b/src/arm64/freescale/imx8mn-beacon-som.dtsi
index c35eeaf..54eaf3d 100644
--- a/src/arm64/freescale/imx8mn-beacon-som.dtsi
+++ b/src/arm64/freescale/imx8mn-beacon-som.dtsi
@@ -120,6 +120,9 @@
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
diff --git a/src/arm64/freescale/imx8mn-evk.dtsi b/src/arm64/freescale/imx8mn-evk.dtsi
index a0dddba..85e65f8 100644
--- a/src/arm64/freescale/imx8mn-evk.dtsi
+++ b/src/arm64/freescale/imx8mn-evk.dtsi
@@ -193,6 +193,7 @@
srp-disable;
adp-disable;
usb-role-switch;
+ disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
diff --git a/src/arm64/freescale/imx8mn.dtsi b/src/arm64/freescale/imx8mn.dtsi
index 4dac4da..d4231e0 100644
--- a/src/arm64/freescale/imx8mn.dtsi
+++ b/src/arm64/freescale/imx8mn.dtsi
@@ -245,6 +245,7 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mn_uid>;
nvmem-cell-names = "soc_unique_id";
@@ -255,7 +256,7 @@
#size-cells = <1>;
ranges;
- spba: spba-bus@30000000 {
+ spba2: spba-bus@30000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -681,80 +682,88 @@
#size-cells = <1>;
ranges;
- ecspi1: spi@30820000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ spba1: spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
- <&clk IMX8MN_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
- ecspi2: spi@30830000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
- <&clk IMX8MN_CLK_ECSPI2_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi1: spi@30820000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- ecspi3: spi@30840000 {
- compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
- <&clk IMX8MN_CLK_ECSPI3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi2: spi@30830000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI2_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
- <&clk IMX8MN_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ ecspi3: spi@30840000 {
+ compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
+ <&clk IMX8MN_CLK_ECSPI3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
- <&clk IMX8MN_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
+ <&clk IMX8MN_CLK_UART1_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
- <&clk IMX8MN_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
+ uart3: serial@30880000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
+ <&clk IMX8MN_CLK_UART3_ROOT>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ uart2: serial@30890000 {
+ compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
+ <&clk IMX8MN_CLK_UART2_ROOT>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
};
crypto: crypto@30900000 {
diff --git a/src/arm64/freescale/imx8mp-evk.dts b/src/arm64/freescale/imx8mp-evk.dts
index 2c28e58..7b99fad 100644
--- a/src/arm64/freescale/imx8mp-evk.dts
+++ b/src/arm64/freescale/imx8mp-evk.dts
@@ -81,6 +81,26 @@
status = "disabled";/* can2 pin conflict with pdm */
};
+&eqos {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eqos>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ eee-broken-1000t;
+ };
+ };
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
@@ -104,6 +124,92 @@
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9450c";
+ reg = <0x25>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1025000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ nxp,dvs-run-voltage = <950000>;
+ nxp,dvs-standby-voltage = <850000>;
+ };
+
+ BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <1045000>;
+ regulator-max-microvolt = <1155000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -177,6 +283,26 @@
};
&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
+ MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
+ MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
+ MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
+ MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
+ MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
+ MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
+ MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
+ MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
+ MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
+ MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
+ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
+ MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
+ MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
+ MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
+ >;
+ };
+
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
@@ -229,6 +355,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
+ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
@@ -236,6 +369,12 @@
>;
};
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
diff --git a/src/arm64/freescale/imx8mp-phycore-som.dtsi b/src/arm64/freescale/imx8mp-phycore-som.dtsi
index f3965ec..aa78e0d 100644
--- a/src/arm64/freescale/imx8mp-phycore-som.dtsi
+++ b/src/arm64/freescale/imx8mp-phycore-som.dtsi
@@ -65,6 +65,20 @@
};
};
+&flexspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi0>;
+ status = "okay";
+
+ som_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
@@ -217,6 +231,17 @@
>;
};
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
+ MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
+ MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
+ MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
+ MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
+ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
+ >;
+ };
+
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
diff --git a/src/arm64/freescale/imx8mp.dtsi b/src/arm64/freescale/imx8mp.dtsi
index c2d51a4..9f7c7f5 100644
--- a/src/arm64/freescale/imx8mp.dtsi
+++ b/src/arm64/freescale/imx8mp.dtsi
@@ -37,6 +37,7 @@
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
+ spi0 = &flexspi;
};
cpus {
@@ -407,7 +408,6 @@
<&clk IMX8MP_CLK_GIC>,
<&clk IMX8MP_CLK_AUDIO_AHB>,
<&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
- <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
<&clk IMX8MP_AUDIO_PLL1>,
<&clk IMX8MP_AUDIO_PLL2>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
@@ -423,7 +423,6 @@
<500000000>,
<400000000>,
<800000000>,
- <400000000>,
<393216000>,
<361267200>;
};
@@ -761,6 +760,21 @@
status = "disabled";
};
+ flexspi: spi@30bb0000 {
+ compatible = "nxp,imx8mp-fspi";
+ reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
+ <&clk IMX8MP_CLK_QSPI_ROOT>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clock-rates = <80000000>;
+ assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;
diff --git a/src/arm64/freescale/imx8mq-evk.dts b/src/arm64/freescale/imx8mq-evk.dts
index 85b0452..4d2035e 100644
--- a/src/arm64/freescale/imx8mq-evk.dts
+++ b/src/arm64/freescale/imx8mq-evk.dts
@@ -318,6 +318,7 @@
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ vph-supply = <&vgen5_reg>;
status = "okay";
};
diff --git a/src/arm64/freescale/imx8mq-nitrogen.dts b/src/arm64/freescale/imx8mq-nitrogen.dts
index 81d2692..f70fb32 100644
--- a/src/arm64/freescale/imx8mq-nitrogen.dts
+++ b/src/arm64/freescale/imx8mq-nitrogen.dts
@@ -34,6 +34,30 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ ddc-i2c-bus = <&ddc_i2c_bus>;
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <<8912_out>;
+ };
+ };
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
@@ -70,6 +94,9 @@
};
};
+&dphy {
+ status = "okay";
+};
&fec1 {
pinctrl-names = "default";
@@ -91,6 +118,15 @@
};
};
+/* Release reset of the USB Host HUB */
+&gpio1 {
+ usb-host-reset-hog {
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-high;
+ };
+};
+
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -174,6 +210,98 @@
};
};
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pca9546: i2cmux@70 {
+ compatible = "nxp,pca9546";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c4@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+
+ hdmi-bridge@48 {
+ compatible = "lontium,lt8912b";
+ reg = <0x48> ;
+ reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_out_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ remote-endpoint = <&mipi_dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lt8912_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+ };
+
+ ddc_i2c_bus: i2c4@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ };
+
+ i2c4@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+
+ max7323: gpio-expander@68 {
+ compatible = "maxim,max7323";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max7323>;
+ gpio-controller;
+ reg = <0x68>;
+ #gpio-cells = <2>;
+ };
+ };
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&mipi_dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mipi_dsi_out: endpoint {
+ remote-endpoint = <&hdmi_out_in>;
+ };
+ };
+ };
+};
+
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -190,6 +318,29 @@
status = "okay";
};
+&usb_dwc3_0 {
+ dr_mode = "otg";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_0>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ vbus-supply = <®_usb_otg_vbus>;
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb3_phy1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_1>;
+ status = "okay";
+};
+
&usdhc1 {
assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
@@ -321,6 +472,19 @@
>;
};
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_max7323: max7323grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
+ >;
+ };
+
pinctrl_reg_arm_dram: reg-arm-dramgrp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
@@ -339,6 +503,12 @@
>;
};
+ pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
@@ -353,6 +523,18 @@
>;
};
+ pinctrl_usb3_0: usb3-0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
+ >;
+ };
+
+ pinctrl_usb3_1: usb3-1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
diff --git a/src/arm64/freescale/imx8mq.dtsi b/src/arm64/freescale/imx8mq.dtsi
index 17c449e..91df9c5 100644
--- a/src/arm64/freescale/imx8mq.dtsi
+++ b/src/arm64/freescale/imx8mq.dtsi
@@ -1383,6 +1383,14 @@
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
@@ -1413,6 +1421,14 @@
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
status = "disabled";
};
diff --git a/src/arm64/hisilicon/hi3660-coresight.dtsi b/src/arm64/hisilicon/hi3660-coresight.dtsi
index d607f2f..79a55a0 100644
--- a/src/arm64/hisilicon/hi3660-coresight.dtsi
+++ b/src/arm64/hisilicon/hi3660-coresight.dtsi
@@ -3,7 +3,7 @@
/*
* dtsi for Hisilicon Hi3660 Coresight
*
- * Copyright (C) 2016-2018 Hisilicon Ltd.
+ * Copyright (C) 2016-2018 HiSilicon Ltd.
*
* Author: Wanglai Shi <shiwanglai@hisilicon.com>
*
diff --git a/src/arm64/hisilicon/hi3660-hikey960.dts b/src/arm64/hisilicon/hi3660-hikey960.dts
index 963300e..f68580d 100644
--- a/src/arm64/hisilicon/hi3660-hikey960.dts
+++ b/src/arm64/hisilicon/hi3660-hikey960.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey960 Development Board
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
*
*/
diff --git a/src/arm64/hisilicon/hi3660.dtsi b/src/arm64/hisilicon/hi3660.dtsi
index cab89dc..f1ec87c 100644
--- a/src/arm64/hisilicon/hi3660.dtsi
+++ b/src/arm64/hisilicon/hi3660.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi3660 SoC
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/src/arm64/hisilicon/hi3670-hikey970.dts b/src/arm64/hisilicon/hi3670-hikey970.dts
index 7f9f988..d8abf44 100644
--- a/src/arm64/hisilicon/hi3670-hikey970.dts
+++ b/src/arm64/hisilicon/hi3670-hikey970.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey970 Development Board
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*
*/
diff --git a/src/arm64/hisilicon/hi3670.dtsi b/src/arm64/hisilicon/hi3670.dtsi
index 8830795..20698cf 100644
--- a/src/arm64/hisilicon/hi3670.dtsi
+++ b/src/arm64/hisilicon/hi3670.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi3670 SoC
*
- * Copyright (C) 2016, Hisilicon Ltd.
+ * Copyright (C) 2016, HiSilicon Ltd.
* Copyright (C) 2018, Linaro Ltd.
*/
diff --git a/src/arm64/hisilicon/hi6220-coresight.dtsi b/src/arm64/hisilicon/hi6220-coresight.dtsi
index 7b3010f..3f387f4 100644
--- a/src/arm64/hisilicon/hi6220-coresight.dtsi
+++ b/src/arm64/hisilicon/hi6220-coresight.dtsi
@@ -2,7 +2,7 @@
/*
* dtsi file for Hisilicon Hi6220 coresight
*
- * Copyright (C) 2017 Hisilicon Ltd.
+ * Copyright (C) 2017 HiSilicon Ltd.
*
* Author: Pengcheng Li <lipengcheng8@huawei.com>
* Leo Yan <leo.yan@linaro.org>
diff --git a/src/arm64/hisilicon/hi6220-hikey.dts b/src/arm64/hisilicon/hi6220-hikey.dts
index 91d0867..3df2afb 100644
--- a/src/arm64/hisilicon/hi6220-hikey.dts
+++ b/src/arm64/hisilicon/hi6220-hikey.dts
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon HiKey Development Board
*
- * Copyright (C) 2015, Hisilicon Ltd.
+ * Copyright (C) 2015, HiSilicon Ltd.
*
*/
diff --git a/src/arm64/hisilicon/hi6220.dtsi b/src/arm64/hisilicon/hi6220.dtsi
index d426c6c..dde9371 100644
--- a/src/arm64/hisilicon/hi6220.dtsi
+++ b/src/arm64/hisilicon/hi6220.dtsi
@@ -2,7 +2,7 @@
/*
* dts file for Hisilicon Hi6220 SoC
*
- * Copyright (C) 2015, Hisilicon Ltd.
+ * Copyright (C) 2015, HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/src/arm64/hisilicon/hip05-d02.dts b/src/arm64/hisilicon/hip05-d02.dts
index 369b69b..40f3e00 100644
--- a/src/arm64/hisilicon/hip05-d02.dts
+++ b/src/arm64/hisilicon/hip05-d02.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D02 Development Board
*
- * Copyright (C) 2014,2015 Hisilicon Ltd.
+ * Copyright (C) 2014,2015 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/src/arm64/hisilicon/hip05.dtsi b/src/arm64/hisilicon/hip05.dtsi
index 4aed8d4..7b2abd1 100644
--- a/src/arm64/hisilicon/hip05.dtsi
+++ b/src/arm64/hisilicon/hip05.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D02 Development Board
*
- * Copyright (C) 2014,2015 Hisilicon Ltd.
+ * Copyright (C) 2014,2015 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/src/arm64/hisilicon/hip06-d03.dts b/src/arm64/hisilicon/hip06-d03.dts
index 9f4a930..35af5d3 100644
--- a/src/arm64/hisilicon/hip06-d03.dts
+++ b/src/arm64/hisilicon/hip06-d03.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D03 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/src/arm64/hisilicon/hip06.dtsi b/src/arm64/hisilicon/hip06.dtsi
index 7deca5f..70d7732 100644
--- a/src/arm64/hisilicon/hip06.dtsi
+++ b/src/arm64/hisilicon/hip06.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D03 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/src/arm64/hisilicon/hip07-d05.dts b/src/arm64/hisilicon/hip07-d05.dts
index 81a2312..c3df678 100644
--- a/src/arm64/hisilicon/hip07-d05.dts
+++ b/src/arm64/hisilicon/hip07-d05.dts
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D05 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
/dts-v1/;
diff --git a/src/arm64/hisilicon/hip07.dtsi b/src/arm64/hisilicon/hip07.dtsi
index 2172d80..6baf6a6 100644
--- a/src/arm64/hisilicon/hip07.dtsi
+++ b/src/arm64/hisilicon/hip07.dtsi
@@ -2,7 +2,7 @@
/**
* dts file for Hisilicon D05 Development Board
*
- * Copyright (C) 2016 Hisilicon Ltd.
+ * Copyright (C) 2016 HiSilicon Ltd.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/src/arm64/marvell/armada-3720-turris-mox.dts b/src/arm64/marvell/armada-3720-turris-mox.dts
index 53e817c..ce2bcdd 100644
--- a/src/arm64/marvell/armada-3720-turris-mox.dts
+++ b/src/arm64/marvell/armada-3720-turris-mox.dts
@@ -109,10 +109,8 @@
};
firmware {
- turris-mox-rwtm {
- compatible = "cznic,turris-mox-rwtm";
- mboxes = <&rwtm 0>;
- status = "okay";
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
};
};
};
diff --git a/src/arm64/marvell/armada-37xx.dtsi b/src/arm64/marvell/armada-37xx.dtsi
index 456dcd4..5db81a4 100644
--- a/src/arm64/marvell/armada-37xx.dtsi
+++ b/src/arm64/marvell/armada-37xx.dtsi
@@ -134,7 +134,7 @@
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
- reg = <0x12000 0x200>;
+ reg = <0x12000 0x18>;
clocks = <&xtalclk>;
interrupts =
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
@@ -504,4 +504,12 @@
};
};
};
+
+ firmware {
+ armada-3700-rwtm {
+ compatible = "marvell,armada-3700-rwtm-firmware";
+ mboxes = <&rwtm 0>;
+ status = "okay";
+ };
+ };
};
diff --git a/src/arm64/marvell/armada-ap807.dtsi b/src/arm64/marvell/armada-ap807.dtsi
index d9bbbfa..4a23f65 100644
--- a/src/arm64/marvell/armada-ap807.dtsi
+++ b/src/arm64/marvell/armada-ap807.dtsi
@@ -29,6 +29,7 @@
};
&ap_sdhci0 {
- compatible = "marvell,armada-ap807-sdhci";
+ compatible = "marvell,armada-ap807-sdhci",
+ "marvell,armada-ap806-sdhci"; /* Backward compatibility */
};
diff --git a/src/arm64/marvell/cn9130-db.dts b/src/arm64/marvell/cn9130-db.dts
index 2c2af00..9758609 100644
--- a/src/arm64/marvell/cn9130-db.dts
+++ b/src/arm64/marvell/cn9130-db.dts
@@ -260,7 +260,7 @@
};
partition@200000 {
label = "Linux";
- reg = <0x200000 0xd00000>;
+ reg = <0x200000 0xe00000>;
};
partition@1000000 {
label = "Filesystem";
diff --git a/src/arm64/mediatek/mt8167.dtsi b/src/arm64/mediatek/mt8167.dtsi
index 1c5639e..9029051 100644
--- a/src/arm64/mediatek/mt8167.dtsi
+++ b/src/arm64/mediatek/mt8167.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/mt8167-clk.h>
#include <dt-bindings/memory/mt8167-larb-port.h>
+#include <dt-bindings/power/mt8167-power.h>
#include "mt8167-pinfunc.h"
@@ -34,6 +35,73 @@
#clock-cells = <1>;
};
+ scpsys: syscon@10006000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+ #power-domain-cells = <1>;
+
+ spm: power-controller {
+ compatible = "mediatek,mt8167-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domains of the SoC */
+ power-domain@MT8167_POWER_DOMAIN_MM {
+ reg = <MT8167_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_VDEC {
+ reg = <MT8167_POWER_DOMAIN_VDEC>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>,
+ <&topckgen CLK_TOP_RG_VDEC>;
+ clock-names = "mm", "vdec";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_ISP {
+ reg = <MT8167_POWER_DOMAIN_ISP>;
+ clocks = <&topckgen CLK_TOP_SMI_MM>;
+ clock-names = "mm";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_MFG_ASYNC {
+ reg = <MT8167_POWER_DOMAIN_MFG_ASYNC>;
+ clocks = <&topckgen CLK_TOP_RG_AXI_MFG>,
+ <&topckgen CLK_TOP_RG_SLOW_MFG>;
+ clock-names = "axi_mfg", "mfg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+ mediatek,infracfg = <&infracfg>;
+
+ power-domain@MT8167_POWER_DOMAIN_MFG_2D {
+ reg = <MT8167_POWER_DOMAIN_MFG_2D>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8167_POWER_DOMAIN_MFG {
+ reg = <MT8167_POWER_DOMAIN_MFG>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+
+ power-domain@MT8167_POWER_DOMAIN_CONN {
+ reg = <MT8167_POWER_DOMAIN_CONN>;
+ #power-domain-cells = <0>;
+ mediatek,infracfg = <&infracfg>;
+ };
+ };
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt8167-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -57,5 +125,58 @@
#interrupt-cells = <2>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ mmsys: mmsys@14000000 {
+ compatible = "mediatek,mt8167-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ smi_common: smi@14017000 {
+ compatible = "mediatek,mt8167-smi-common";
+ reg = <0 0x14017000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_COMMON>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
+ larb0: larb@14016000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x14016000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
+ larb1: larb@15001000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB1_SMI>,
+ <&imgsys CLK_IMG_LARB1_SMI>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
+ };
+
+ larb2: larb@16010000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x16010000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_CKEN>,
+ <&vdecsys CLK_VDEC_LARB1_CKEN>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
+ };
+
+ iommu: m4u@10203000 {
+ compatible = "mediatek,mt8167-m4u";
+ reg = <0 0x10203000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb1 &larb2>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+ #iommu-cells = <1>;
+ };
};
};
diff --git a/src/arm64/mediatek/mt8173.dtsi b/src/arm64/mediatek/mt8173.dtsi
index 003a565..22f271b 100644
--- a/src/arm64/mediatek/mt8173.dtsi
+++ b/src/arm64/mediatek/mt8173.dtsi
@@ -1459,14 +1459,11 @@
clock-names = "apb", "smi";
};
- vcodec_enc: vcodec@18002000 {
+ vcodec_enc_avc: vcodec@18002000 {
compatible = "mediatek,mt8173-vcodec-enc";
- reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */
- <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
- interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
- mediatek,larb = <&larb3>,
- <&larb5>;
+ reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ mediatek,larb = <&larb3>;
iommus = <&iommu M4U_PORT_VENC_RCPU>,
<&iommu M4U_PORT_VENC_REC>,
<&iommu M4U_PORT_VENC_BSDMA>,
@@ -1477,29 +1474,12 @@
<&iommu M4U_PORT_VENC_REF_LUMA>,
<&iommu M4U_PORT_VENC_REF_CHROMA>,
<&iommu M4U_PORT_VENC_NBM_RDMA>,
- <&iommu M4U_PORT_VENC_NBM_WDMA>,
- <&iommu M4U_PORT_VENC_RCPU_SET2>,
- <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
- <&iommu M4U_PORT_VENC_BSDMA_SET2>,
- <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
- <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
- <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
- <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ <&iommu M4U_PORT_VENC_NBM_WDMA>;
mediatek,vpu = <&vpu>;
- clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
- <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_UNIVPLL1_D2>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- clock-names = "venc_sel_src",
- "venc_sel",
- "venc_lt_sel_src",
- "venc_lt_sel";
- assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>,
- <&topckgen CLK_TOP_VENC_LT_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>,
- <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ clock-names = "venc_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
};
jpegdec: jpegdec@18004000 {
@@ -1531,5 +1511,27 @@
<&vencltsys CLK_VENCLT_CKE0>;
clock-names = "apb", "smi";
};
+
+ vcodec_enc_vp8: vcodec@19002000 {
+ compatible = "mediatek,mt8173-vcodec-enc-vp8";
+ reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
+ <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
+ <&iommu M4U_PORT_VENC_BSDMA_SET2>,
+ <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
+ <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
+ <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
+ mediatek,larb = <&larb5>;
+ mediatek,vpu = <&vpu>;
+ clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ clock-names = "venc_lt_sel";
+ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
+ assigned-clock-parents =
+ <&topckgen CLK_TOP_VCODECPLL_370P5>;
+ };
};
};
diff --git a/src/arm64/mediatek/mt8183-evb.dts b/src/arm64/mediatek/mt8183-evb.dts
index edff1e0..7bc0a6a 100644
--- a/src/arm64/mediatek/mt8183-evb.dts
+++ b/src/arm64/mediatek/mt8183-evb.dts
@@ -42,6 +42,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts
new file mode 100644
index 0000000..a8d6f32
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-burnet.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+/ {
+ model = "Google burnet board";
+ compatible = "google,burnet", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&i2c0 {
+ touchscreen@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+ interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
+
+ post-power-on-delay-ms = <200>;
+ hid-descr-addr = <0x0020>;
+ };
+};
+
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
new file mode 100644
index 0000000..ef6257c
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel sku1 board";
+ compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183";
+
+ pwmleds {
+ compatible = "pwm-leds";
+ keyboard_backlight: keyboard-backlight {
+ label = "cros_ec::kbd_backlight";
+ pwms = <&cros_ec_pwm 0>;
+ max-brightness = <1023>;
+ };
+ };
+};
+
+&cros_ec_pwm {
+ status = "okay";
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL";
+};
+
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
new file mode 100644
index 0000000..899c2e4
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel sku6 board";
+ compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183";
+};
+
+&touchscreen {
+ status = "okay";
+
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+ interrupt-parent = <&pio>;
+ interrupts = <155 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touchscreen_pins>;
+
+ post-power-on-delay-ms = <10>;
+ hid-descr-addr = <0x0001>;
+};
+
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL";
+};
+
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
new file mode 100644
index 0000000..bbe6c33
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
+
+&i2c2 {
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
+
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
new file mode 100644
index 0000000..e8c41f6
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel14.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-fennel.dtsi"
+
+/ {
+ model = "Google fennel14 sku0 board";
+ compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183";
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_FENNEL14";
+};
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts
new file mode 100644
index 0000000..b3f46c1
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-kappa.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+/ {
+ model = "Google kappa board";
+ compatible = "google,kappa", "mediatek,mt8183";
+};
+
+&mt6358codec {
+ mediatek,dmic-mode = <1>; /* one-wire */
+};
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
new file mode 100644
index 0000000..6f1aa69
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-juniper.dtsi"
+
+/ {
+ model = "Google kenzo sku17 board";
+ compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
+};
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
new file mode 100644
index 0000000..281265f
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-willow.dtsi"
+
+/ {
+ model = "Google willow board sku0";
+ compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183";
+};
+
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
new file mode 100644
index 0000000..22e56bd
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi-willow.dtsi"
+
+/ {
+ model = "Google willow board sku1";
+ compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183";
+};
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi b/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
new file mode 100644
index 0000000..76d3354
--- /dev/null
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2021 Google LLC
+ */
+
+/dts-v1/;
+#include "mt8183-kukui-jacuzzi.dtsi"
+
+&i2c2 {
+ trackpad@2c {
+ compatible = "hid-over-i2c";
+ reg = <0x2c>;
+ hid-descr-addr = <0x20>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&trackpad_pins>;
+
+ interrupts-extended = <&pio 7 IRQ_TYPE_LEVEL_LOW>;
+
+ wakeup-source;
+ };
+};
+
+&qca_wifi {
+ qcom,ath10k-calibration-variant = "GO_JUNIPER";
+};
diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi b/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
index 4049dff..d8826c8 100644
--- a/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
+++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi.dtsi
@@ -92,6 +92,14 @@
};
};
+&cros_ec {
+ cros_ec_pwm: ec-pwm {
+ compatible = "google,cros-ec-pwm";
+ #pwm-cells = <1>;
+ status = "disabled";
+ };
+};
+
&dsi0 {
status = "okay";
/delete-node/panel@0;
diff --git a/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi b/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
index b442e38..28966a6 100644
--- a/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
+++ b/src/arm64/mediatek/mt8183-kukui-kakadu.dtsi
@@ -88,11 +88,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcama2_reg>;
};
};
@@ -101,11 +103,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/src/arm64/mediatek/mt8183-kukui-kodama.dtsi b/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
index 2f5234a..3aa7940 100644
--- a/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
+++ b/src/arm64/mediatek/mt8183-kukui-kodama.dtsi
@@ -62,11 +62,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c64";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcamio_reg>;
};
};
@@ -75,11 +77,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c64";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/src/arm64/mediatek/mt8183-kukui-krane.dtsi b/src/arm64/mediatek/mt8183-kukui-krane.dtsi
index fbc471c..30c183c 100644
--- a/src/arm64/mediatek/mt8183-kukui-krane.dtsi
+++ b/src/arm64/mediatek/mt8183-kukui-krane.dtsi
@@ -71,11 +71,13 @@
pinctrl-0 = <&i2c2_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcamio_reg>;
eeprom@58 {
compatible = "atmel,24c32";
reg = <0x58>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcama2_reg>;
};
};
@@ -84,11 +86,13 @@
pinctrl-0 = <&i2c4_pins>;
status = "okay";
clock-frequency = <400000>;
+ vbus-supply = <&mt6358_vcn18_reg>;
eeprom@54 {
compatible = "atmel,24c32";
reg = <0x54>;
pagesize = <32>;
+ vcc-supply = <&mt6358_vcn18_reg>;
};
};
diff --git a/src/arm64/mediatek/mt8183-kukui.dtsi b/src/arm64/mediatek/mt8183-kukui.dtsi
index ff56bcf..ae549d5 100644
--- a/src/arm64/mediatek/mt8183-kukui.dtsi
+++ b/src/arm64/mediatek/mt8183-kukui.dtsi
@@ -279,6 +279,11 @@
};
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
@@ -816,6 +821,10 @@
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
};
+
+ cbas {
+ compatible = "google,cros-cbas";
+ };
};
};
@@ -847,6 +856,20 @@
status = "okay";
};
+&thermal_zones {
+ tboard1 {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&tboard_thermistor1>;
+ };
+
+ tboard2 {
+ polling-delay = <1000>; /* milliseconds */
+ polling-delay-passive = <0>; /* milliseconds */
+ thermal-sensors = <&tboard_thermistor2>;
+ };
+};
+
&u3phy {
status = "okay";
};
diff --git a/src/arm64/mediatek/mt8183-pumpkin.dts b/src/arm64/mediatek/mt8183-pumpkin.dts
index 0aff5eb..ee91282 100644
--- a/src/arm64/mediatek/mt8183-pumpkin.dts
+++ b/src/arm64/mediatek/mt8183-pumpkin.dts
@@ -68,6 +68,11 @@
status = "okay";
};
+&gpu {
+ mali-supply = <&mt6358_vgpu_reg>;
+ sram-supply = <&mt6358_vsram_gpu_reg>;
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c_pins_0>;
diff --git a/src/arm64/mediatek/mt8183.dtsi b/src/arm64/mediatek/mt8183.dtsi
index c5e822b..f90df64 100644
--- a/src/arm64/mediatek/mt8183.dtsi
+++ b/src/arm64/mediatek/mt8183.dtsi
@@ -197,6 +197,91 @@
};
};
+ gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <625000>, <850000>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ opp-microvolt = <631250>, <850000>;
+ };
+
+ opp-340000000 {
+ opp-hz = /bits/ 64 <340000000>;
+ opp-microvolt = <637500>, <850000>;
+ };
+
+ opp-360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ opp-microvolt = <643750>, <850000>;
+ };
+
+ opp-380000000 {
+ opp-hz = /bits/ 64 <380000000>;
+ opp-microvolt = <650000>, <850000>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <656250>, <850000>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <662500>, <850000>;
+ };
+
+ opp-460000000 {
+ opp-hz = /bits/ 64 <460000000>;
+ opp-microvolt = <675000>, <850000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <687500>, <850000>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <700000>, <850000>;
+ };
+
+ opp-580000000 {
+ opp-hz = /bits/ 64 <580000000>;
+ opp-microvolt = <712500>, <850000>;
+ };
+
+ opp-620000000 {
+ opp-hz = /bits/ 64 <620000000>;
+ opp-microvolt = <725000>, <850000>;
+ };
+
+ opp-653000000 {
+ opp-hz = /bits/ 64 <653000000>;
+ opp-microvolt = <743750>, <850000>;
+ };
+
+ opp-698000000 {
+ opp-hz = /bits/ 64 <698000000>;
+ opp-microvolt = <768750>, <868750>;
+ };
+
+ opp-743000000 {
+ opp-hz = /bits/ 64 <743000000>;
+ opp-microvolt = <793750>, <893750>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <825000>, <925000>;
+ };
+ };
+
pmu-a53 {
compatible = "arm,cortex-a53-pmu";
interrupt-parent = <&gic>;
@@ -673,7 +758,7 @@
nvmem-cell-names = "calibration-data";
};
- thermal-zones {
+ thermal_zones: thermal-zones {
cpu_thermal: cpu_thermal {
polling-delay-passive = <100>;
polling-delay = <500>;
@@ -1118,6 +1203,26 @@
#clock-cells = <1>;
};
+ gpu: gpu@13040000 {
+ compatible = "mediatek,mt8183-mali", "arm,mali-bifrost";
+ reg = <0 0x13040000 0 0x4000>;
+ interrupts =
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "job", "mmu", "gpu";
+
+ clocks = <&topckgen CLK_TOP_MFGPLL_CK>;
+
+ power-domains =
+ <&spm MT8183_POWER_DOMAIN_MFG_CORE0>,
+ <&spm MT8183_POWER_DOMAIN_MFG_CORE1>,
+ <&spm MT8183_POWER_DOMAIN_MFG_2D>;
+ power-domain-names = "core0", "core1", "core2";
+
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
@@ -1263,13 +1368,14 @@
};
smi_common: smi@14019000 {
- compatible = "mediatek,mt8183-smi-common", "syscon";
+ compatible = "mediatek,mt8183-smi-common";
reg = <0 0x14019000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_GALS_COMM0>,
<&mmsys CLK_MM_GALS_COMM1>;
clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
imgsys: syscon@15020000 {
diff --git a/src/arm64/microchip/sparx5.dtsi b/src/arm64/microchip/sparx5.dtsi
index d64621d..ad07fff 100644
--- a/src/arm64/microchip/sparx5.dtsi
+++ b/src/arm64/microchip/sparx5.dtsi
@@ -135,9 +135,12 @@
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
+ reset: reset-controller@611010008 {
+ compatible = "microchip,sparx5-switch-reset";
reg = <0x6 0x11010008 0x4>;
+ reg-names = "gcb";
+ #reset-cells = <1>;
+ cpu-syscon = <&cpu_ctrl>;
};
uart0: serial@600100000 {
@@ -275,6 +278,21 @@
"GPIO_46", "GPIO_47";
function = "emmc";
};
+
+ miim1_pins: miim1-pins {
+ pins = "GPIO_56", "GPIO_57";
+ function = "miim";
+ };
+
+ miim2_pins: miim2-pins {
+ pins = "GPIO_58", "GPIO_59";
+ function = "miim";
+ };
+
+ miim3_pins: miim3-pins {
+ pins = "GPIO_52", "GPIO_53";
+ function = "miim";
+ };
};
sgpio0: gpio@61101036c {
@@ -285,6 +303,8 @@
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio0_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x1101036c 0x100>;
sgpio_in0: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -292,6 +312,9 @@
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out0: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -310,6 +333,8 @@
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio1_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x11010484 0x100>;
sgpio_in1: gpio@0 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -317,6 +342,9 @@
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out1: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -335,6 +363,8 @@
clocks = <&sys_clk>;
pinctrl-0 = <&sgpio2_pins>;
pinctrl-names = "default";
+ resets = <&reset 0>;
+ reset-names = "switch";
reg = <0x6 0x1101059c 0x100>;
sgpio_in2: gpio@0 {
reg = <0>;
@@ -342,6 +372,9 @@
gpio-controller;
#gpio-cells = <3>;
ngpios = <96>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
};
sgpio_out2: gpio@1 {
compatible = "microchip,sparx5-sgpio-bank";
@@ -386,5 +419,62 @@
#thermal-sensor-cells = <0>;
clocks = <&ahb_clk>;
};
+
+ mdio0: mdio@6110102b0 {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x110102b0 0x24>;
+ };
+
+ mdio1: mdio@6110102d4 {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ pinctrl-0 = <&miim1_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x110102d4 0x24>;
+ };
+
+ mdio2: mdio@6110102f8 {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ pinctrl-0 = <&miim2_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x110102d4 0x24>;
+ };
+
+ mdio3: mdio@61101031c {
+ compatible = "mscc,ocelot-miim";
+ status = "disabled";
+ pinctrl-0 = <&miim3_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x6 0x1101031c 0x24>;
+ };
+
+ serdes: serdes@10808000 {
+ compatible = "microchip,sparx5-serdes";
+ #phy-cells = <1>;
+ clocks = <&sys_clk>;
+ reg = <0x6 0x10808000 0x5d0000>;
+ };
+
+ switch: switch@0x600000000 {
+ compatible = "microchip,sparx5-switch";
+ reg = <0x6 0 0x401000>,
+ <0x6 0x10004000 0x7fc000>,
+ <0x6 0x11010000 0xaf0000>;
+ reg-names = "cpu", "dev", "gcb";
+ interrupt-names = "xtr";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&reset 0>;
+ reset-names = "switch";
+ };
};
};
diff --git a/src/arm64/microchip/sparx5_pcb134_board.dtsi b/src/arm64/microchip/sparx5_pcb134_board.dtsi
index f0c9151..33faf1f 100644
--- a/src/arm64/microchip/sparx5_pcb134_board.dtsi
+++ b/src/arm64/microchip/sparx5_pcb134_board.dtsi
@@ -7,30 +7,6 @@
#include "sparx5_pcb_common.dtsi"
/{
- aliases {
- i2c0 = &i2c0;
- i2c100 = &i2c100;
- i2c101 = &i2c101;
- i2c102 = &i2c102;
- i2c103 = &i2c103;
- i2c104 = &i2c104;
- i2c105 = &i2c105;
- i2c106 = &i2c106;
- i2c107 = &i2c107;
- i2c108 = &i2c108;
- i2c109 = &i2c109;
- i2c110 = &i2c110;
- i2c111 = &i2c111;
- i2c112 = &i2c112;
- i2c113 = &i2c113;
- i2c114 = &i2c114;
- i2c115 = &i2c115;
- i2c116 = &i2c116;
- i2c117 = &i2c117;
- i2c118 = &i2c118;
- i2c119 = &i2c119;
- };
-
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
@@ -298,17 +274,10 @@
&spi0 {
status = "okay";
- spi@0 {
- compatible = "spi-mux";
- mux-controls = <&mux>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>; /* CS0 */
- spi-flash@9 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <8000000>;
- reg = <0x9>; /* SPI */
- };
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0>;
};
};
@@ -328,6 +297,33 @@
};
};
+&sgpio0 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <8 15>;
+ gpio@0 {
+ ngpios = <64>;
+ };
+ gpio@1 {
+ ngpios = <64>;
+ };
+};
+
+&sgpio1 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <24 31>;
+ gpio@0 {
+ ngpios = <64>;
+ };
+ gpio@1 {
+ ngpios = <64>;
+ };
+};
+
+&sgpio2 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <0 0>, <11 31>;
+};
+
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
@@ -415,9 +411,9 @@
&i2c0_imux {
pinctrl-names =
- "i2c100", "i2c101", "i2c102", "i2c103",
- "i2c104", "i2c105", "i2c106", "i2c107",
- "i2c108", "i2c109", "i2c110", "i2c111", "idle";
+ "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
+ "i2c_sfp5", "i2c_sfp6", "i2c_sfp7", "i2c_sfp8",
+ "i2c_sfp9", "i2c_sfp10", "i2c_sfp11", "i2c_sfp12", "idle";
pinctrl-0 = <&i2cmux_0>;
pinctrl-1 = <&i2cmux_1>;
pinctrl-2 = <&i2cmux_2>;
@@ -431,62 +427,62 @@
pinctrl-10 = <&i2cmux_10>;
pinctrl-11 = <&i2cmux_11>;
pinctrl-12 = <&i2cmux_pins_i>;
- i2c100: i2c_sfp1 {
+ i2c_sfp1: i2c_sfp1 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c101: i2c_sfp2 {
+ i2c_sfp2: i2c_sfp2 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c102: i2c_sfp3 {
+ i2c_sfp3: i2c_sfp3 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c103: i2c_sfp4 {
+ i2c_sfp4: i2c_sfp4 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c104: i2c_sfp5 {
+ i2c_sfp5: i2c_sfp5 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c105: i2c_sfp6 {
+ i2c_sfp6: i2c_sfp6 {
reg = <0x5>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c106: i2c_sfp7 {
+ i2c_sfp7: i2c_sfp7 {
reg = <0x6>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c107: i2c_sfp8 {
+ i2c_sfp8: i2c_sfp8 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c108: i2c_sfp9 {
+ i2c_sfp9: i2c_sfp9 {
reg = <0x8>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c109: i2c_sfp10 {
+ i2c_sfp10: i2c_sfp10 {
reg = <0x9>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c110: i2c_sfp11 {
+ i2c_sfp11: i2c_sfp11 {
reg = <0xa>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c111: i2c_sfp12 {
+ i2c_sfp12: i2c_sfp12 {
reg = <0xb>;
#address-cells = <1>;
#size-cells = <0>;
@@ -499,44 +495,413 @@
&gpio 61 GPIO_ACTIVE_HIGH
&gpio 54 GPIO_ACTIVE_HIGH>;
idle-state = <0x8>;
- i2c112: i2c_sfp13 {
+ i2c_sfp13: i2c_sfp13 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c113: i2c_sfp14 {
+ i2c_sfp14: i2c_sfp14 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c114: i2c_sfp15 {
+ i2c_sfp15: i2c_sfp15 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c115: i2c_sfp16 {
+ i2c_sfp16: i2c_sfp16 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c116: i2c_sfp17 {
+ i2c_sfp17: i2c_sfp17 {
reg = <0x4>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c117: i2c_sfp18 {
+ i2c_sfp18: i2c_sfp18 {
reg = <0x5>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c118: i2c_sfp19 {
+ i2c_sfp19: i2c_sfp19 {
reg = <0x6>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c119: i2c_sfp20 {
+ i2c_sfp20: i2c_sfp20 {
reg = <0x7>;
#address-cells = <1>;
#size-cells = <0>;
};
};
+
+&mdio3 {
+ status = "ok";
+ phy64: ethernet-phy@64 {
+ reg = <28>;
+ };
+};
+
+&axi {
+ sfp_eth12: sfp-eth12 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out2 11 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 11 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 11 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 12 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth13: sfp-eth13 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out2 12 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 12 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 12 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 13 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth14: sfp-eth14 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out2 13 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 13 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 13 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 14 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth15: sfp-eth15 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp4>;
+ tx-disable-gpios = <&sgpio_out2 14 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 14 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 14 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 15 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth48: sfp-eth48 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp5>;
+ tx-disable-gpios = <&sgpio_out2 15 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 15 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 15 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 16 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth49: sfp-eth49 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp6>;
+ tx-disable-gpios = <&sgpio_out2 16 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 16 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 16 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 17 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth50: sfp-eth50 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp7>;
+ tx-disable-gpios = <&sgpio_out2 17 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 17 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 17 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 18 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth51: sfp-eth51 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp8>;
+ tx-disable-gpios = <&sgpio_out2 18 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 18 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 18 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 19 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth52: sfp-eth52 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp9>;
+ tx-disable-gpios = <&sgpio_out2 19 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 19 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 19 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 20 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth53: sfp-eth53 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp10>;
+ tx-disable-gpios = <&sgpio_out2 20 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 20 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 20 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 21 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth54: sfp-eth54 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp11>;
+ tx-disable-gpios = <&sgpio_out2 21 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 21 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 21 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 22 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth55: sfp-eth55 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp12>;
+ tx-disable-gpios = <&sgpio_out2 22 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 22 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 22 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 23 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth56: sfp-eth56 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp13>;
+ tx-disable-gpios = <&sgpio_out2 23 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 23 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 23 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 24 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth57: sfp-eth57 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp14>;
+ tx-disable-gpios = <&sgpio_out2 24 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 24 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 24 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 25 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth58: sfp-eth58 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp15>;
+ tx-disable-gpios = <&sgpio_out2 25 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 25 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 25 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 26 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth59: sfp-eth59 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp16>;
+ tx-disable-gpios = <&sgpio_out2 26 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 26 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 26 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 27 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth60: sfp-eth60 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp17>;
+ tx-disable-gpios = <&sgpio_out2 27 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 27 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 27 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth61: sfp-eth61 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp18>;
+ tx-disable-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth62: sfp-eth62 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp19>;
+ tx-disable-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth63: sfp-eth63 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp20>;
+ tx-disable-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_LOW>;
+ los-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 10G SFPs */
+ port12: port@12 {
+ reg = <12>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 13>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth12>;
+ microchip,sd-sgpio = <301>;
+ managed = "in-band-status";
+ };
+ port13: port@13 {
+ reg = <13>;
+ /* Example: CU SFP, 1G speed */
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 14>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth13>;
+ microchip,sd-sgpio = <305>;
+ managed = "in-band-status";
+ };
+ port14: port@14 {
+ reg = <14>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 15>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth14>;
+ microchip,sd-sgpio = <309>;
+ managed = "in-band-status";
+ };
+ port15: port@15 {
+ reg = <15>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 16>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth15>;
+ microchip,sd-sgpio = <313>;
+ managed = "in-band-status";
+ };
+ port48: port@48 {
+ reg = <48>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 17>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth48>;
+ microchip,sd-sgpio = <317>;
+ managed = "in-band-status";
+ };
+ port49: port@49 {
+ reg = <49>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 18>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth49>;
+ microchip,sd-sgpio = <321>;
+ managed = "in-band-status";
+ };
+ port50: port@50 {
+ reg = <50>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 19>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth50>;
+ microchip,sd-sgpio = <325>;
+ managed = "in-band-status";
+ };
+ port51: port@51 {
+ reg = <51>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 20>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth51>;
+ microchip,sd-sgpio = <329>;
+ managed = "in-band-status";
+ };
+ port52: port@52 {
+ reg = <52>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 21>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth52>;
+ microchip,sd-sgpio = <333>;
+ managed = "in-band-status";
+ };
+ port53: port@53 {
+ reg = <53>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 22>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth53>;
+ microchip,sd-sgpio = <337>;
+ managed = "in-band-status";
+ };
+ port54: port@54 {
+ reg = <54>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 23>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth54>;
+ microchip,sd-sgpio = <341>;
+ managed = "in-band-status";
+ };
+ port55: port@55 {
+ reg = <55>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 24>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth55>;
+ microchip,sd-sgpio = <345>;
+ managed = "in-band-status";
+ };
+ /* 25G SFPs */
+ port56: port@56 {
+ reg = <56>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 25>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth56>;
+ microchip,sd-sgpio = <349>;
+ managed = "in-band-status";
+ };
+ port57: port@57 {
+ reg = <57>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 26>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth57>;
+ microchip,sd-sgpio = <353>;
+ managed = "in-band-status";
+ };
+ port58: port@58 {
+ reg = <58>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 27>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth58>;
+ microchip,sd-sgpio = <357>;
+ managed = "in-band-status";
+ };
+ port59: port@59 {
+ reg = <59>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 28>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth59>;
+ microchip,sd-sgpio = <361>;
+ managed = "in-band-status";
+ };
+ port60: port@60 {
+ reg = <60>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 29>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth60>;
+ microchip,sd-sgpio = <365>;
+ managed = "in-band-status";
+ };
+ port61: port@61 {
+ reg = <61>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 30>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth61>;
+ microchip,sd-sgpio = <369>;
+ managed = "in-band-status";
+ };
+ port62: port@62 {
+ reg = <62>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 31>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth62>;
+ microchip,sd-sgpio = <373>;
+ managed = "in-band-status";
+ };
+ port63: port@63 {
+ reg = <63>;
+ microchip,bandwidth = <10000>;
+ phys = <&serdes 32>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth63>;
+ microchip,sd-sgpio = <377>;
+ managed = "in-band-status";
+ };
+ /* Finally the Management interface */
+ port64: port@64 {
+ reg = <64>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 0>;
+ phy-handle = <&phy64>;
+ phy-mode = "sgmii";
+ };
+ };
+};
diff --git a/src/arm64/microchip/sparx5_pcb135_board.dtsi b/src/arm64/microchip/sparx5_pcb135_board.dtsi
index e28c6dd..ef96e6d 100644
--- a/src/arm64/microchip/sparx5_pcb135_board.dtsi
+++ b/src/arm64/microchip/sparx5_pcb135_board.dtsi
@@ -7,14 +7,6 @@
#include "sparx5_pcb_common.dtsi"
/{
- aliases {
- i2c0 = &i2c0;
- i2c152 = &i2c152;
- i2c153 = &i2c153;
- i2c154 = &i2c154;
- i2c155 = &i2c155;
- };
-
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
@@ -97,17 +89,10 @@
&spi0 {
status = "okay";
- spi@0 {
- compatible = "spi-mux";
- mux-controls = <&mux>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>; /* CS0 */
- spi-flash@9 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <8000000>;
- reg = <0x9>; /* SPI */
- };
+ spi-flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0>;
};
};
@@ -138,6 +123,11 @@
};
};
+&sgpio2 {
+ status = "okay";
+ microchip,sgpio-port-ranges = <0 0>, <16 18>, <28 31>;
+};
+
&axi {
i2c0_imux: i2c0-imux@0 {
compatible = "i2c-mux-pinctrl";
@@ -149,31 +139,614 @@
&i2c0_imux {
pinctrl-names =
- "i2c152", "i2c153", "i2c154", "i2c155",
+ "i2c_sfp1", "i2c_sfp2", "i2c_sfp3", "i2c_sfp4",
"idle";
pinctrl-0 = <&i2cmux_s29>;
pinctrl-1 = <&i2cmux_s30>;
pinctrl-2 = <&i2cmux_s31>;
pinctrl-3 = <&i2cmux_s32>;
pinctrl-4 = <&i2cmux_pins_i>;
- i2c152: i2c_sfp1 {
+ i2c_sfp1: i2c_sfp1 {
reg = <0x0>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c153: i2c_sfp2 {
+ i2c_sfp2: i2c_sfp2 {
reg = <0x1>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c154: i2c_sfp3 {
+ i2c_sfp3: i2c_sfp3 {
reg = <0x2>;
#address-cells = <1>;
#size-cells = <0>;
};
- i2c155: i2c_sfp4 {
+ i2c_sfp4: i2c_sfp4 {
reg = <0x3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
+
+&axi {
+ sfp_eth60: sfp-eth60 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ tx-disable-gpios = <&sgpio_out2 28 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 28 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 28 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 28 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 28 2 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth61: sfp-eth61 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp2>;
+ tx-disable-gpios = <&sgpio_out2 29 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 29 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 29 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 29 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 29 2 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth62: sfp-eth62 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp3>;
+ tx-disable-gpios = <&sgpio_out2 30 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 30 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 30 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 30 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 30 2 GPIO_ACTIVE_HIGH>;
+ };
+ sfp_eth63: sfp-eth63 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp4>;
+ tx-disable-gpios = <&sgpio_out2 31 0 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&sgpio_out2 31 1 GPIO_ACTIVE_HIGH>;
+ los-gpios = <&sgpio_in2 31 0 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&sgpio_in2 31 1 GPIO_ACTIVE_LOW>;
+ tx-fault-gpios = <&sgpio_in2 31 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&mdio0 {
+ status = "ok";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+ phy2: ethernet-phy@2 {
+ reg = <2>;
+ };
+ phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ phy4: ethernet-phy@4 {
+ reg = <4>;
+ };
+ phy5: ethernet-phy@5 {
+ reg = <5>;
+ };
+ phy6: ethernet-phy@6 {
+ reg = <6>;
+ };
+ phy7: ethernet-phy@7 {
+ reg = <7>;
+ };
+ phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+ phy10: ethernet-phy@10 {
+ reg = <10>;
+ };
+ phy11: ethernet-phy@11 {
+ reg = <11>;
+ };
+ phy12: ethernet-phy@12 {
+ reg = <12>;
+ };
+ phy13: ethernet-phy@13 {
+ reg = <13>;
+ };
+ phy14: ethernet-phy@14 {
+ reg = <14>;
+ };
+ phy15: ethernet-phy@15 {
+ reg = <15>;
+ };
+ phy16: ethernet-phy@16 {
+ reg = <16>;
+ };
+ phy17: ethernet-phy@17 {
+ reg = <17>;
+ };
+ phy18: ethernet-phy@18 {
+ reg = <18>;
+ };
+ phy19: ethernet-phy@19 {
+ reg = <19>;
+ };
+ phy20: ethernet-phy@20 {
+ reg = <20>;
+ };
+ phy21: ethernet-phy@21 {
+ reg = <21>;
+ };
+ phy22: ethernet-phy@22 {
+ reg = <22>;
+ };
+ phy23: ethernet-phy@23 {
+ reg = <23>;
+ };
+};
+
+&mdio1 {
+ status = "ok";
+ phy24: ethernet-phy@24 {
+ reg = <0>;
+ };
+ phy25: ethernet-phy@25 {
+ reg = <1>;
+ };
+ phy26: ethernet-phy@26 {
+ reg = <2>;
+ };
+ phy27: ethernet-phy@27 {
+ reg = <3>;
+ };
+ phy28: ethernet-phy@28 {
+ reg = <4>;
+ };
+ phy29: ethernet-phy@29 {
+ reg = <5>;
+ };
+ phy30: ethernet-phy@30 {
+ reg = <6>;
+ };
+ phy31: ethernet-phy@31 {
+ reg = <7>;
+ };
+ phy32: ethernet-phy@32 {
+ reg = <8>;
+ };
+ phy33: ethernet-phy@33 {
+ reg = <9>;
+ };
+ phy34: ethernet-phy@34 {
+ reg = <10>;
+ };
+ phy35: ethernet-phy@35 {
+ reg = <11>;
+ };
+ phy36: ethernet-phy@36 {
+ reg = <12>;
+ };
+ phy37: ethernet-phy@37 {
+ reg = <13>;
+ };
+ phy38: ethernet-phy@38 {
+ reg = <14>;
+ };
+ phy39: ethernet-phy@39 {
+ reg = <15>;
+ };
+ phy40: ethernet-phy@40 {
+ reg = <16>;
+ };
+ phy41: ethernet-phy@41 {
+ reg = <17>;
+ };
+ phy42: ethernet-phy@42 {
+ reg = <18>;
+ };
+ phy43: ethernet-phy@43 {
+ reg = <19>;
+ };
+ phy44: ethernet-phy@44 {
+ reg = <20>;
+ };
+ phy45: ethernet-phy@45 {
+ reg = <21>;
+ };
+ phy46: ethernet-phy@46 {
+ reg = <22>;
+ };
+ phy47: ethernet-phy@47 {
+ reg = <23>;
+ };
+};
+
+&mdio3 {
+ status = "ok";
+ phy64: ethernet-phy@64 {
+ reg = <28>;
+ };
+};
+
+&switch {
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy0>;
+ phy-mode = "qsgmii";
+ };
+ port1: port@1 {
+ reg = <1>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy1>;
+ phy-mode = "qsgmii";
+ };
+ port2: port@2 {
+ reg = <2>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy2>;
+ phy-mode = "qsgmii";
+ };
+ port3: port@3 {
+ reg = <3>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 13>;
+ phy-handle = <&phy3>;
+ phy-mode = "qsgmii";
+ };
+ port4: port@4 {
+ reg = <4>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy4>;
+ phy-mode = "qsgmii";
+ };
+ port5: port@5 {
+ reg = <5>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy5>;
+ phy-mode = "qsgmii";
+ };
+ port6: port@6 {
+ reg = <6>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy6>;
+ phy-mode = "qsgmii";
+ };
+ port7: port@7 {
+ reg = <7>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 14>;
+ phy-handle = <&phy7>;
+ phy-mode = "qsgmii";
+ };
+ port8: port@8 {
+ reg = <8>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy8>;
+ phy-mode = "qsgmii";
+ };
+ port9: port@9 {
+ reg = <9>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy9>;
+ phy-mode = "qsgmii";
+ };
+ port10: port@10 {
+ reg = <10>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy10>;
+ phy-mode = "qsgmii";
+ };
+ port11: port@11 {
+ reg = <11>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 15>;
+ phy-handle = <&phy11>;
+ phy-mode = "qsgmii";
+ };
+ port12: port@12 {
+ reg = <12>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy12>;
+ phy-mode = "qsgmii";
+ };
+ port13: port@13 {
+ reg = <13>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy13>;
+ phy-mode = "qsgmii";
+ };
+ port14: port@14 {
+ reg = <14>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy14>;
+ phy-mode = "qsgmii";
+ };
+ port15: port@15 {
+ reg = <15>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 16>;
+ phy-handle = <&phy15>;
+ phy-mode = "qsgmii";
+ };
+ port16: port@16 {
+ reg = <16>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy16>;
+ phy-mode = "qsgmii";
+ };
+ port17: port@17 {
+ reg = <17>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy17>;
+ phy-mode = "qsgmii";
+ };
+ port18: port@18 {
+ reg = <18>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy18>;
+ phy-mode = "qsgmii";
+ };
+ port19: port@19 {
+ reg = <19>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 17>;
+ phy-handle = <&phy19>;
+ phy-mode = "qsgmii";
+ };
+ port20: port@20 {
+ reg = <20>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy20>;
+ phy-mode = "qsgmii";
+ };
+ port21: port@21 {
+ reg = <21>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy21>;
+ phy-mode = "qsgmii";
+ };
+ port22: port@22 {
+ reg = <22>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy22>;
+ phy-mode = "qsgmii";
+ };
+ port23: port@23 {
+ reg = <23>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 18>;
+ phy-handle = <&phy23>;
+ phy-mode = "qsgmii";
+ };
+ port24: port@24 {
+ reg = <24>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy24>;
+ phy-mode = "qsgmii";
+ };
+ port25: port@25 {
+ reg = <25>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy25>;
+ phy-mode = "qsgmii";
+ };
+ port26: port@26 {
+ reg = <26>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy26>;
+ phy-mode = "qsgmii";
+ };
+ port27: port@27 {
+ reg = <27>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 19>;
+ phy-handle = <&phy27>;
+ phy-mode = "qsgmii";
+ };
+ port28: port@28 {
+ reg = <28>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy28>;
+ phy-mode = "qsgmii";
+ };
+ port29: port@29 {
+ reg = <29>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy29>;
+ phy-mode = "qsgmii";
+ };
+ port30: port@30 {
+ reg = <30>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy30>;
+ phy-mode = "qsgmii";
+ };
+ port31: port@31 {
+ reg = <31>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 20>;
+ phy-handle = <&phy31>;
+ phy-mode = "qsgmii";
+ };
+ port32: port@32 {
+ reg = <32>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy32>;
+ phy-mode = "qsgmii";
+ };
+ port33: port@33 {
+ reg = <33>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy33>;
+ phy-mode = "qsgmii";
+ };
+ port34: port@34 {
+ reg = <34>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy34>;
+ phy-mode = "qsgmii";
+ };
+ port35: port@35 {
+ reg = <35>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 21>;
+ phy-handle = <&phy35>;
+ phy-mode = "qsgmii";
+ };
+ port36: port@36 {
+ reg = <36>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy36>;
+ phy-mode = "qsgmii";
+ };
+ port37: port@37 {
+ reg = <37>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy37>;
+ phy-mode = "qsgmii";
+ };
+ port38: port@38 {
+ reg = <38>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy38>;
+ phy-mode = "qsgmii";
+ };
+ port39: port@39 {
+ reg = <39>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 22>;
+ phy-handle = <&phy39>;
+ phy-mode = "qsgmii";
+ };
+ port40: port@40 {
+ reg = <40>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy40>;
+ phy-mode = "qsgmii";
+ };
+ port41: port@41 {
+ reg = <41>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy41>;
+ phy-mode = "qsgmii";
+ };
+ port42: port@42 {
+ reg = <42>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy42>;
+ phy-mode = "qsgmii";
+ };
+ port43: port@43 {
+ reg = <43>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 23>;
+ phy-handle = <&phy43>;
+ phy-mode = "qsgmii";
+ };
+ port44: port@44 {
+ reg = <44>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy44>;
+ phy-mode = "qsgmii";
+ };
+ port45: port@45 {
+ reg = <45>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy45>;
+ phy-mode = "qsgmii";
+ };
+ port46: port@46 {
+ reg = <46>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy46>;
+ phy-mode = "qsgmii";
+ };
+ port47: port@47 {
+ reg = <47>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 24>;
+ phy-handle = <&phy47>;
+ phy-mode = "qsgmii";
+ };
+ /* Then the 25G interfaces */
+ port60: port@60 {
+ reg = <60>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 29>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth60>;
+ managed = "in-band-status";
+ };
+ port61: port@61 {
+ reg = <61>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 30>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth61>;
+ managed = "in-band-status";
+ };
+ port62: port@62 {
+ reg = <62>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 31>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth62>;
+ managed = "in-band-status";
+ };
+ port63: port@63 {
+ reg = <63>;
+ microchip,bandwidth = <25000>;
+ phys = <&serdes 32>;
+ phy-mode = "10gbase-r";
+ sfp = <&sfp_eth63>;
+ managed = "in-band-status";
+ };
+ /* Finally the Management interface */
+ port64: port@64 {
+ reg = <64>;
+ microchip,bandwidth = <1000>;
+ phys = <&serdes 0>;
+ phy-handle = <&phy64>;
+ phy-mode = "sgmii";
+ };
+ };
+};
diff --git a/src/arm64/nvidia/tegra186-p2771-0000.dts b/src/arm64/nvidia/tegra186-p2771-0000.dts
index 683743f..74c1a5d 100644
--- a/src/arm64/nvidia/tegra186-p2771-0000.dts
+++ b/src/arm64/nvidia/tegra186-p2771-0000.dts
@@ -817,7 +817,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-tx2-hda";
+ nvidia,model = "NVIDIA Jetson TX2 HDA";
status = "okay";
};
@@ -1109,6 +1109,6 @@
<&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>,
<&dmic3_port>, <&dspk1_port>, <&dspk2_port>;
- label = "jetson-tx2-ape";
+ label = "NVIDIA Jetson TX2 APE";
};
};
diff --git a/src/arm64/nvidia/tegra186.dtsi b/src/arm64/nvidia/tegra186.dtsi
index 9f75bbf..d02f6bf 100644
--- a/src/arm64/nvidia/tegra186.dtsi
+++ b/src/arm64/nvidia/tegra186.dtsi
@@ -1082,7 +1082,7 @@
};
smmu: iommu@12000000 {
- compatible = "arm,mmu-500";
+ compatible = "nvidia,tegra186-smmu", "nvidia,smmu-500";
reg = <0 0x12000000 0 0x800000>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
@@ -1152,6 +1152,8 @@
stream-match-mask = <0x7f80>;
#global-interrupts = <1>;
#iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
};
host1x@13e00000 {
diff --git a/src/arm64/nvidia/tegra194-p2972-0000.dts b/src/arm64/nvidia/tegra194-p2972-0000.dts
index d618f19..96bd01c 100644
--- a/src/arm64/nvidia/tegra194-p2972-0000.dts
+++ b/src/arm64/nvidia/tegra194-p2972-0000.dts
@@ -554,7 +554,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-xavier-hda";
+ nvidia,model = "NVIDIA Jetson AGX Xavier HDA";
status = "okay";
};
@@ -831,7 +831,7 @@
<&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>,
<&dmic3_port>;
- label = "jetson-xavier-ape";
+ label = "NVIDIA Jetson AGX Xavier APE";
widgets =
"Microphone", "CVB-RT MIC Jack",
diff --git a/src/arm64/nvidia/tegra194-p3509-0000.dtsi b/src/arm64/nvidia/tegra194-p3509-0000.dtsi
index d1d7722..836a7e0 100644
--- a/src/arm64/nvidia/tegra194-p3509-0000.dtsi
+++ b/src/arm64/nvidia/tegra194-p3509-0000.dtsi
@@ -15,6 +15,577 @@
interrupt-controller@2a40000 {
status = "okay";
};
+
+ ahub@2900800 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0x0>;
+
+ xbar_admaif0_ep: endpoint {
+ remote-endpoint = <&admaif0_ep>;
+ };
+ };
+
+ port@1 {
+ reg = <0x1>;
+
+ xbar_admaif1_ep: endpoint {
+ remote-endpoint = <&admaif1_ep>;
+ };
+ };
+
+ port@2 {
+ reg = <0x2>;
+
+ xbar_admaif2_ep: endpoint {
+ remote-endpoint = <&admaif2_ep>;
+ };
+ };
+
+ port@3 {
+ reg = <0x3>;
+
+ xbar_admaif3_ep: endpoint {
+ remote-endpoint = <&admaif3_ep>;
+ };
+ };
+
+ port@4 {
+ reg = <0x4>;
+
+ xbar_admaif4_ep: endpoint {
+ remote-endpoint = <&admaif4_ep>;
+ };
+ };
+
+ port@5 {
+ reg = <0x5>;
+
+ xbar_admaif5_ep: endpoint {
+ remote-endpoint = <&admaif5_ep>;
+ };
+ };
+
+ port@6 {
+ reg = <0x6>;
+
+ xbar_admaif6_ep: endpoint {
+ remote-endpoint = <&admaif6_ep>;
+ };
+ };
+
+ port@7 {
+ reg = <0x7>;
+
+ xbar_admaif7_ep: endpoint {
+ remote-endpoint = <&admaif7_ep>;
+ };
+ };
+
+ port@8 {
+ reg = <0x8>;
+
+ xbar_admaif8_ep: endpoint {
+ remote-endpoint = <&admaif8_ep>;
+ };
+ };
+
+ port@9 {
+ reg = <0x9>;
+
+ xbar_admaif9_ep: endpoint {
+ remote-endpoint = <&admaif9_ep>;
+ };
+ };
+
+ port@a {
+ reg = <0xa>;
+
+ xbar_admaif10_ep: endpoint {
+ remote-endpoint = <&admaif10_ep>;
+ };
+ };
+
+ port@b {
+ reg = <0xb>;
+
+ xbar_admaif11_ep: endpoint {
+ remote-endpoint = <&admaif11_ep>;
+ };
+ };
+
+ port@c {
+ reg = <0xc>;
+
+ xbar_admaif12_ep: endpoint {
+ remote-endpoint = <&admaif12_ep>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ xbar_admaif13_ep: endpoint {
+ remote-endpoint = <&admaif13_ep>;
+ };
+ };
+
+ port@e {
+ reg = <0xe>;
+
+ xbar_admaif14_ep: endpoint {
+ remote-endpoint = <&admaif14_ep>;
+ };
+ };
+
+ port@f {
+ reg = <0xf>;
+
+ xbar_admaif15_ep: endpoint {
+ remote-endpoint = <&admaif15_ep>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ xbar_admaif16_ep: endpoint {
+ remote-endpoint = <&admaif16_ep>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ xbar_admaif17_ep: endpoint {
+ remote-endpoint = <&admaif17_ep>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ xbar_admaif18_ep: endpoint {
+ remote-endpoint = <&admaif18_ep>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ xbar_admaif19_ep: endpoint {
+ remote-endpoint = <&admaif19_ep>;
+ };
+ };
+
+ xbar_i2s3_port: port@16 {
+ reg = <0x16>;
+
+ xbar_i2s3_ep: endpoint {
+ remote-endpoint = <&i2s3_cif_ep>;
+ };
+ };
+
+ xbar_i2s5_port: port@18 {
+ reg = <0x18>;
+
+ xbar_i2s5_ep: endpoint {
+ remote-endpoint = <&i2s5_cif_ep>;
+ };
+ };
+
+ xbar_dmic1_port: port@1a {
+ reg = <0x1a>;
+
+ xbar_dmic1_ep: endpoint {
+ remote-endpoint = <&dmic1_cif_ep>;
+ };
+ };
+
+ xbar_dmic2_port: port@1b {
+ reg = <0x1b>;
+
+ xbar_dmic2_ep: endpoint {
+ remote-endpoint = <&dmic2_cif_ep>;
+ };
+ };
+
+ xbar_dmic4_port: port@1d {
+ reg = <0x1d>;
+
+ xbar_dmic4_ep: endpoint {
+ remote-endpoint = <&dmic4_cif_ep>;
+ };
+ };
+
+ xbar_dspk1_port: port@1e {
+ reg = <0x1e>;
+
+ xbar_dspk1_ep: endpoint {
+ remote-endpoint = <&dspk1_cif_ep>;
+ };
+ };
+
+ xbar_dspk2_port: port@1f {
+ reg = <0x1f>;
+
+ xbar_dspk2_ep: endpoint {
+ remote-endpoint = <&dspk2_cif_ep>;
+ };
+ };
+ };
+
+ admaif@290f000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ admaif0_port: port@0 {
+ reg = <0x0>;
+
+ admaif0_ep: endpoint {
+ remote-endpoint = <&xbar_admaif0_ep>;
+ };
+ };
+
+ admaif1_port: port@1 {
+ reg = <0x1>;
+
+ admaif1_ep: endpoint {
+ remote-endpoint = <&xbar_admaif1_ep>;
+ };
+ };
+
+ admaif2_port: port@2 {
+ reg = <0x2>;
+
+ admaif2_ep: endpoint {
+ remote-endpoint = <&xbar_admaif2_ep>;
+ };
+ };
+
+ admaif3_port: port@3 {
+ reg = <0x3>;
+
+ admaif3_ep: endpoint {
+ remote-endpoint = <&xbar_admaif3_ep>;
+ };
+ };
+
+ admaif4_port: port@4 {
+ reg = <0x4>;
+
+ admaif4_ep: endpoint {
+ remote-endpoint = <&xbar_admaif4_ep>;
+ };
+ };
+
+ admaif5_port: port@5 {
+ reg = <0x5>;
+
+ admaif5_ep: endpoint {
+ remote-endpoint = <&xbar_admaif5_ep>;
+ };
+ };
+
+ admaif6_port: port@6 {
+ reg = <0x6>;
+
+ admaif6_ep: endpoint {
+ remote-endpoint = <&xbar_admaif6_ep>;
+ };
+ };
+
+ admaif7_port: port@7 {
+ reg = <0x7>;
+
+ admaif7_ep: endpoint {
+ remote-endpoint = <&xbar_admaif7_ep>;
+ };
+ };
+
+ admaif8_port: port@8 {
+ reg = <0x8>;
+
+ admaif8_ep: endpoint {
+ remote-endpoint = <&xbar_admaif8_ep>;
+ };
+ };
+
+ admaif9_port: port@9 {
+ reg = <0x9>;
+
+ admaif9_ep: endpoint {
+ remote-endpoint = <&xbar_admaif9_ep>;
+ };
+ };
+
+ admaif10_port: port@a {
+ reg = <0xa>;
+
+ admaif10_ep: endpoint {
+ remote-endpoint = <&xbar_admaif10_ep>;
+ };
+ };
+
+ admaif11_port: port@b {
+ reg = <0xb>;
+
+ admaif11_ep: endpoint {
+ remote-endpoint = <&xbar_admaif11_ep>;
+ };
+ };
+
+ admaif12_port: port@c {
+ reg = <0xc>;
+
+ admaif12_ep: endpoint {
+ remote-endpoint = <&xbar_admaif12_ep>;
+ };
+ };
+
+ admaif13_port: port@d {
+ reg = <0xd>;
+
+ admaif13_ep: endpoint {
+ remote-endpoint = <&xbar_admaif13_ep>;
+ };
+ };
+
+ admaif14_port: port@e {
+ reg = <0xe>;
+
+ admaif14_ep: endpoint {
+ remote-endpoint = <&xbar_admaif14_ep>;
+ };
+ };
+
+ admaif15_port: port@f {
+ reg = <0xf>;
+
+ admaif15_ep: endpoint {
+ remote-endpoint = <&xbar_admaif15_ep>;
+ };
+ };
+
+ admaif16_port: port@10 {
+ reg = <0x10>;
+
+ admaif16_ep: endpoint {
+ remote-endpoint = <&xbar_admaif16_ep>;
+ };
+ };
+
+ admaif17_port: port@11 {
+ reg = <0x11>;
+
+ admaif17_ep: endpoint {
+ remote-endpoint = <&xbar_admaif17_ep>;
+ };
+ };
+
+ admaif18_port: port@12 {
+ reg = <0x12>;
+
+ admaif18_ep: endpoint {
+ remote-endpoint = <&xbar_admaif18_ep>;
+ };
+ };
+
+ admaif19_port: port@13 {
+ reg = <0x13>;
+
+ admaif19_ep: endpoint {
+ remote-endpoint = <&xbar_admaif19_ep>;
+ };
+ };
+ };
+ };
+
+ i2s@2901200 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s3_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s3_ep>;
+ };
+ };
+
+ i2s3_port: port@1 {
+ reg = <1>;
+
+ i2s3_dap_ep: endpoint {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ i2s@2901400 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ i2s5_cif_ep: endpoint {
+ remote-endpoint = <&xbar_i2s5_ep>;
+ };
+ };
+
+ i2s5_port: port@1 {
+ reg = <1>;
+
+ i2s5_dap_ep: endpoint@0 {
+ dai-format = "i2s";
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic1_ep>;
+ };
+ };
+
+ dmic1_port: port@1 {
+ reg = <1>;
+
+ dmic1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic2_ep>;
+ };
+ };
+
+ dmic2_port: port@1 {
+ reg = <1>;
+
+ dmic2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dmic@2904300 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dmic4_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dmic4_ep>;
+ };
+ };
+
+ dmic4_port: port@1 {
+ reg = <1>;
+
+ dmic4_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905000 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk1_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk1_ep>;
+ };
+ };
+
+ dspk1_port: port@1 {
+ reg = <1>;
+
+ dspk1_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+
+ dspk@2905100 {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dspk2_cif_ep: endpoint {
+ remote-endpoint = <&xbar_dspk2_ep>;
+ };
+ };
+
+ dspk2_port: port@1 {
+ reg = <1>;
+
+ dspk2_dap_ep: endpoint {
+ /* Place holder for external Codec */
+ };
+ };
+ };
+ };
+ };
};
ddc: i2c@3190000 {
@@ -36,7 +607,7 @@
};
hda@3510000 {
- nvidia,model = "jetson-xavier-nx-hda";
+ nvidia,model = "NVIDIA Jetson Xavier NX HDA";
status = "okay";
};
@@ -265,6 +836,28 @@
regulator-boot-on;
};
+ sound {
+ compatible = "nvidia,tegra186-audio-graph-card";
+ status = "okay";
+
+ dais = /* ADMAIF (FE) Ports */
+ <&admaif0_port>, <&admaif1_port>, <&admaif2_port>, <&admaif3_port>,
+ <&admaif4_port>, <&admaif5_port>, <&admaif6_port>, <&admaif7_port>,
+ <&admaif8_port>, <&admaif9_port>, <&admaif10_port>, <&admaif11_port>,
+ <&admaif12_port>, <&admaif13_port>, <&admaif14_port>, <&admaif15_port>,
+ <&admaif16_port>, <&admaif17_port>, <&admaif18_port>, <&admaif19_port>,
+ /* XBAR Ports */
+ <&xbar_i2s3_port>, <&xbar_i2s5_port>,
+ <&xbar_dmic1_port>, <&xbar_dmic2_port>, <&xbar_dmic4_port>,
+ <&xbar_dspk1_port>, <&xbar_dspk2_port>,
+ /* BE I/O Ports */
+ <&i2s3_port>, <&i2s5_port>,
+ <&dmic1_port>, <&dmic2_port>, <&dmic4_port>,
+ <&dspk1_port>, <&dspk2_port>;
+
+ label = "NVIDIA Jetson Xavier NX APE";
+ };
+
thermal-zones {
cpu {
polling-delay = <0>;
diff --git a/src/arm64/nvidia/tegra194.dtsi b/src/arm64/nvidia/tegra194.dtsi
index 9449156..b7d5328 100644
--- a/src/arm64/nvidia/tegra194.dtsi
+++ b/src/arm64/nvidia/tegra194.dtsi
@@ -62,6 +62,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_EQOSR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_EQOSW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_EQOS>;
status = "disabled";
snps,write-requests = <1>;
@@ -733,6 +734,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWA &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC1>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout =
<0x07>;
nvidia,pad-autocal-pull-down-offset-3v3-timeout =
@@ -759,6 +761,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC3>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
@@ -790,6 +793,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRAB &emc>,
<&mc TEGRA194_MEMORY_CLIENT_SDMMCWAB &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_SDMMC4>;
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -821,6 +825,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HDAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_HDAW &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_HDA>;
status = "disabled";
};
@@ -1300,6 +1305,84 @@
interrupt-controller;
};
+ smmu: iommu@12000000 {
+ compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
+ reg = <0x12000000 0x800000>,
+ <0x11000000 0x800000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ stream-match-mask = <0x7f80>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
+ status = "okay";
+ };
+
host1x@13e00000 {
compatible = "nvidia,tegra194-host1x";
reg = <0x13e00000 0x10000>,
@@ -1319,6 +1402,7 @@
ranges = <0x15000000 0x15000000 0x01000000>;
interconnects = <&mc TEGRA194_MEMORY_CLIENT_HOST1XDMAR &emc>;
interconnect-names = "dma-mem";
+ iommus = <&smmu TEGRA194_SID_HOST1X>;
display-hub@15200000 {
compatible = "nvidia,tegra194-display";
@@ -1430,6 +1514,7 @@
interconnects = <&mc TEGRA194_MEMORY_CLIENT_VICSRD &emc>,
<&mc TEGRA194_MEMORY_CLIENT_VICSWR &emc>;
interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_VIC>;
};
dpaux0: dpaux@155c0000 {
@@ -2136,6 +2221,7 @@
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAR &emc>,
<&mc TEGRA194_MEMORY_CLIENT_BPMPDMAW &emc>;
interconnect-names = "read", "write", "dma-mem", "dma-write";
+ iommus = <&smmu TEGRA194_SID_BPMP>;
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
@@ -2345,6 +2431,20 @@
};
};
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0_0 &cpu0_1 &cpu1_0 &cpu1_1
+ &cpu2_0 &cpu2_1 &cpu3_0 &cpu3_1>;
+ };
+
psci {
compatible = "arm,psci-1.0";
status = "okay";
diff --git a/src/arm64/nvidia/tegra210-p2371-2180.dts b/src/arm64/nvidia/tegra210-p2371-2180.dts
index 497635a..7d3e363 100644
--- a/src/arm64/nvidia/tegra210-p2371-2180.dts
+++ b/src/arm64/nvidia/tegra210-p2371-2180.dts
@@ -424,6 +424,6 @@
<&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>,
<&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic3_port>;
- label = "jetson-tx1-ape";
+ label = "NVIDIA Jetson TX1 APE";
};
};
diff --git a/src/arm64/nvidia/tegra210-p2597.dtsi b/src/arm64/nvidia/tegra210-p2597.dtsi
index a9caaf7..d8409c1 100644
--- a/src/arm64/nvidia/tegra210-p2597.dtsi
+++ b/src/arm64/nvidia/tegra210-p2597.dtsi
@@ -1345,7 +1345,7 @@
};
hda@70030000 {
- nvidia,model = "jetson-tx1-hda";
+ nvidia,model = "NVIDIA Jetson TX1 HDA";
status = "okay";
};
diff --git a/src/arm64/nvidia/tegra210-p3450-0000.dts b/src/arm64/nvidia/tegra210-p3450-0000.dts
index 14c128a..7dbb13f 100644
--- a/src/arm64/nvidia/tegra210-p3450-0000.dts
+++ b/src/arm64/nvidia/tegra210-p3450-0000.dts
@@ -441,7 +441,7 @@
};
hda@70030000 {
- nvidia,model = "jetson-nano-hda";
+ nvidia,model = "NVIDIA Jetson Nano HDA";
status = "okay";
};
@@ -1043,6 +1043,6 @@
<&i2s3_port>, <&i2s4_port>,
<&dmic1_port>, <&dmic2_port>;
- label = "jetson-nano-ape";
+ label = "NVIDIA Jetson Nano APE";
};
};
diff --git a/src/arm64/qcom/apq8096-db820c.dtsi b/src/arm64/qcom/apq8096-db820c.dtsi
index defcbd1..0686923 100644
--- a/src/arm64/qcom/apq8096-db820c.dtsi
+++ b/src/arm64/qcom/apq8096-db820c.dtsi
@@ -41,14 +41,14 @@
/ {
aliases {
- serial0 = &blsp2_uart1;
- serial1 = &blsp2_uart2;
- serial2 = &blsp1_uart1;
- i2c0 = &blsp1_i2c2;
+ serial0 = &blsp2_uart2;
+ serial1 = &blsp2_uart3;
+ serial2 = &blsp1_uart2;
+ i2c0 = &blsp1_i2c3;
i2c1 = &blsp2_i2c1;
- i2c2 = &blsp2_i2c0;
- spi0 = &blsp1_spi0;
- spi1 = &blsp2_spi5;
+ i2c2 = &blsp2_i2c1;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp2_spi6;
};
chosen {
@@ -133,24 +133,24 @@
};
};
-&blsp1_i2c2 {
+&blsp1_i2c3 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
-&blsp1_spi0 {
+&blsp1_spi1 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
-&blsp1_uart1 {
+&blsp1_uart2 {
label = "BT-UART";
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_uart1_default>;
- pinctrl-1 = <&blsp1_uart1_sleep>;
+ pinctrl-0 = <&blsp1_uart2_default>;
+ pinctrl-1 = <&blsp1_uart2_sleep>;
bluetooth {
compatible = "qcom,qca6174-bt";
@@ -162,7 +162,11 @@
};
};
-&blsp2_i2c0 {
+&adsp_pil {
+ status = "okay";
+};
+
+&blsp2_i2c1 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
@@ -174,32 +178,36 @@
status = "okay";
};
-&blsp2_spi5 {
+&blsp2_spi6 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
-&blsp2_uart1 {
+&blsp2_uart2 {
label = "LS-UART1";
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart1_2pins_default>;
- pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+ pinctrl-0 = <&blsp2_uart2_2pins_default>;
+ pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
};
-&blsp2_uart2 {
+&blsp2_uart3 {
label = "LS-UART0";
status = "disabled";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart2_4pins_default>;
- pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
+ pinctrl-0 = <&blsp2_uart3_4pins_default>;
+ pinctrl-1 = <&blsp2_uart3_4pins_sleep>;
};
&camss {
vdda-supply = <&vreg_l2a_1p25>;
};
+&gpu {
+ status = "okay";
+};
+
&hdmi {
status = "okay";
@@ -245,7 +253,12 @@
vdd-gfx-supply = <&vdd_gfx>;
};
-&msmgpio {
+&pm8994_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&tlmm {
gpio-line-names =
"[SPI0_DOUT]", /* GPIO_0, BLSP1_SPI_MOSI, LSEC pin 14 */
"[SPI0_DIN]", /* GPIO_1, BLSP1_SPI_MISO, LSEC pin 10 */
@@ -424,7 +437,7 @@
};
};
- blsp1_uart1_default: blsp1_uart1_default {
+ blsp1_uart2_default: blsp1_uart2_default {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "blsp_uart2";
@@ -437,7 +450,7 @@
};
};
- blsp1_uart1_sleep: blsp1_uart1_sleep {
+ blsp1_uart2_sleep: blsp1_uart2_sleep {
mux {
pins = "gpio41", "gpio42", "gpio43", "gpio44";
function = "gpio";
@@ -505,20 +518,20 @@
&pcie0 {
status = "okay";
- perst-gpio = <&msmgpio 35 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&wlan_en>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie1 {
status = "okay";
- perst-gpio = <&msmgpio 130 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 130 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
&pcie2 {
status = "okay";
- perst-gpio = <&msmgpio 114 GPIO_ACTIVE_LOW>;
+ perst-gpio = <&tlmm 114 GPIO_ACTIVE_LOW>;
vdda-supply = <&vreg_l28a_0p925>;
};
@@ -929,9 +942,9 @@
&sdhc2 {
/* External SD card */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
- pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
- cd-gpios = <&msmgpio 38 0x1>;
+ pinctrl-0 = <&sdc2_state_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_state_off &sdc2_cd_off>;
+ cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
status = "okay";
@@ -1026,20 +1039,6 @@
};
};
-&spmi_bus {
- pmic@0 {
- pon@800 {
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
- };
- };
-};
-
&ufsphy {
status = "okay";
@@ -1064,7 +1063,7 @@
status = "okay";
extcon = <&usb2_id>;
- dwc3@7600000 {
+ usb@7600000 {
extcon = <&usb2_id>;
dr_mode = "otg";
maximum-speed = "high-speed";
@@ -1075,7 +1074,7 @@
status = "okay";
extcon = <&usb3_id>;
- dwc3@6a00000 {
+ usb@6a00000 {
extcon = <&usb3_id>;
dr_mode = "otg";
};
@@ -1089,6 +1088,10 @@
};
+&venus {
+ status = "okay";
+};
+
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
diff --git a/src/arm64/qcom/apq8096-ifc6640.dts b/src/arm64/qcom/apq8096-ifc6640.dts
index f6ddf17..8c7a27e 100644
--- a/src/arm64/qcom/apq8096-ifc6640.dts
+++ b/src/arm64/qcom/apq8096-ifc6640.dts
@@ -17,7 +17,7 @@
qcom,board-id = <0x00010018 0>;
aliases {
- serial0 = &blsp2_uart1;
+ serial0 = &blsp2_uart2;
};
chosen {
@@ -81,14 +81,22 @@
};
};
-&blsp2_uart1 {
+&blsp2_uart2 {
status = "okay";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_uart1_2pins_default>;
- pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
+ pinctrl-0 = <&blsp2_uart2_2pins_default>;
+ pinctrl-1 = <&blsp2_uart2_2pins_sleep>;
};
-&msmgpio {
+&gpu {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
+&tlmm {
sdc2_pins_default: sdc2-pins-default {
clk {
pins = "sdc2_clk";
@@ -352,7 +360,7 @@
bus-width = <4>;
- cd-gpios = <&msmgpio 38 0x1>;
+ cd-gpios = <&tlmm 38 0x1>;
vmmc-supply = <&vreg_l21a_2p95>;
vqmmc-supply = <&vreg_l13a_2p95>;
@@ -383,3 +391,7 @@
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
};
+
+&venus {
+ status = "okay";
+};
diff --git a/src/arm64/qcom/ipq8074-hk10-c1.dts b/src/arm64/qcom/ipq8074-hk10-c1.dts
new file mode 100644
index 0000000..2bfcf42
--- /dev/null
+++ b/src/arm64/qcom/ipq8074-hk10-c1.dts
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074-hk10.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C1";
+ compatible = "qcom,ipq8074-hk10-c1", "qcom,ipq8074";
+};
diff --git a/src/arm64/qcom/ipq8074-hk10-c2.dts b/src/arm64/qcom/ipq8074-hk10-c2.dts
new file mode 100644
index 0000000..7da39f1
--- /dev/null
+++ b/src/arm64/qcom/ipq8074-hk10-c2.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+/* Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ */
+#include "ipq8074-hk10.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8074/AP-HK10-C2";
+ compatible = "qcom,ipq8074-hk10-c2", "qcom,ipq8074";
+};
diff --git a/src/arm64/qcom/ipq8074-hk10.dtsi b/src/arm64/qcom/ipq8074-hk10.dtsi
new file mode 100644
index 0000000..07e6708
--- /dev/null
+++ b/src/arm64/qcom/ipq8074-hk10.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+
+/ {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x0 0x20000000>;
+ };
+};
+
+&blsp1_spi1 {
+ status = "ok";
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&blsp1_uart5 {
+ status = "ok";
+};
+
+&pcie0 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+};
+
+&pcie1 {
+ status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
+};
+
+&pcie_phy0 {
+ status = "ok";
+};
+
+&pcie_phy1 {
+ status = "ok";
+};
+
+&qpic_bam {
+ status = "ok";
+};
+
+&qpic_nand {
+ status = "ok";
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+};
diff --git a/src/arm64/qcom/ipq8074.dtsi b/src/arm64/qcom/ipq8074.dtsi
index a32e5e7..95d6cb8 100644
--- a/src/arm64/qcom/ipq8074.dtsi
+++ b/src/arm64/qcom/ipq8074.dtsi
@@ -165,6 +165,7 @@
clock-names = "cfg_ahb", "ref";
resets = <&gcc GCC_QUSB2_0_PHY_BCR>;
+ status = "disabled";
};
pcie_phy0: phy@86000 {
@@ -372,6 +373,21 @@
status = "disabled";
};
+ blsp1_i2c6: i2c@78ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x078ba000 0x600>;
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ clock-frequency = <100000>;
+ dmas = <&blsp_dma 23>, <&blsp_dma 22>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
qpic_bam: dma-controller@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07984000 0x1a000>;
@@ -427,7 +443,7 @@
resets = <&gcc GCC_USB0_BCR>;
status = "disabled";
- dwc_0: dwc3@8a00000 {
+ dwc_0: usb@8a00000 {
compatible = "snps,dwc3";
reg = <0x8a00000 0xcd00>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
@@ -468,7 +484,7 @@
resets = <&gcc GCC_USB1_BCR>;
status = "disabled";
- dwc_1: dwc3@8c00000 {
+ dwc_1: usb@8c00000 {
compatible = "snps,dwc3";
reg = <0x8c00000 0xcd00>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm64/qcom/msm8916-alcatel-idol347.dts b/src/arm64/qcom/msm8916-alcatel-idol347.dts
index 540b1fa..670bd1b 100644
--- a/src/arm64/qcom/msm8916-alcatel-idol347.dts
+++ b/src/arm64/qcom/msm8916-alcatel-idol347.dts
@@ -45,6 +45,24 @@
status = "okay";
};
+&blsp_i2c4 {
+ status = "okay";
+
+ touchscreen@26 {
+ compatible = "mstar,msg2638";
+ reg = <0x26>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&msmgpio 100 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_reset_default>;
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l5>;
+ touchscreen-size-x = <2048>;
+ touchscreen-size-y = <2048>;
+ };
+};
+
&blsp_i2c5 {
status = "okay";
@@ -281,6 +299,14 @@
bias-pull-up;
};
+ ts_int_reset_default: ts-int-reset-default {
+ pins = "gpio13", "gpio100";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
usb_id_default: usb-id-default {
pins = "gpio69";
function = "gpio";
diff --git a/src/arm64/qcom/msm8916-huawei-g7.dts b/src/arm64/qcom/msm8916-huawei-g7.dts
new file mode 100644
index 0000000..e0075b5
--- /dev/null
+++ b/src/arm64/qcom/msm8916-huawei-g7.dts
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright (C) 2021 Stephan Gerhold
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/leds/common.h>
+
+/*
+ * Note: The original firmware from Huawei can only boot 32-bit kernels.
+ * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware
+ * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei
+ * forgot to set up (firmware) secure boot for some reason.
+ *
+ * Also note that Huawei no longer provides bootloader unlock codes.
+ * This can be bypassed by patching the bootloader from a custom HYP firmware,
+ * making it think the bootloader is unlocked.
+ *
+ * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7)
+ */
+
+/ {
+ model = "Huawei Ascend G7";
+ compatible = "huawei,g7", "qcom,msm8916";
+
+ aliases {
+ serial0 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_default>;
+
+ label = "GPIO Buttons";
+
+ volume-up {
+ label = "Volume Up";
+ gpios = <&msmgpio 107 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_leds_default>;
+
+ led-0 {
+ gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led-1 {
+ gpios = <&msmgpio 9 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led-2 {
+ gpios = <&msmgpio 10 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_INDICATOR;
+ };
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpio = <&msmgpio 117 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_id_default>;
+ };
+};
+
+&blsp_i2c2 {
+ status = "okay";
+
+ magnetometer@c {
+ compatible = "asahi-kasei,ak09911";
+ reg = <0x0c>;
+
+ vdd-supply = <&pm8916_l17>;
+ vid-supply = <&pm8916_l6>;
+
+ reset-gpios = <&msmgpio 36 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&mag_reset_default>;
+ };
+
+ accelerometer@1e {
+ compatible = "kionix,kx023-1025";
+ reg = <0x1e>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <115 IRQ_TYPE_EDGE_RISING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&accel_irq_default>;
+
+ mount-matrix = "-1", "0", "0",
+ "0", "1", "0",
+ "0", "0", "1";
+ };
+
+ proximity@39 {
+ compatible = "avago,apds9930";
+ reg = <0x39>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <113 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
+
+ led-max-microamp = <100000>;
+ amstaos,proximity-diodes = <1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&prox_irq_default>;
+ };
+
+ regulator@3e {
+ compatible = "ti,tps65132";
+ reg = <0x3e>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <®_lcd_en_default>;
+
+ reg_lcd_pos: outp {
+ regulator-name = "outp";
+ regulator-min-microvolt = <5400000>;
+ regulator-max-microvolt = <5400000>;
+ enable-gpios = <&msmgpio 97 GPIO_ACTIVE_HIGH>;
+ regulator-active-discharge = <1>;
+ };
+
+ reg_lcd_neg: outn {
+ regulator-name = "outn";
+ regulator-min-microvolt = <5400000>;
+ regulator-max-microvolt = <5400000>;
+ enable-gpios = <&msmgpio 32 GPIO_ACTIVE_HIGH>;
+ regulator-active-discharge = <1>;
+ };
+ };
+};
+
+&blsp_i2c5 {
+ status = "okay";
+
+ rmi4@70 {
+ compatible = "syna,rmi4-i2c";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+
+ vdd-supply = <&pm8916_l17>;
+ vio-supply = <&pm8916_l16>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_irq_default>;
+
+ syna,startup-delay-ms = <100>;
+
+ rmi4-f01@1 {
+ reg = <0x1>;
+ syna,nosleep-mode = <1>; /* Allow sleeping */
+ };
+
+ rmi4-f11@11 {
+ reg = <0x11>;
+ syna,sensor-type = <1>; /* Touchscreen */
+ };
+ };
+};
+
+&blsp_i2c6 {
+ status = "okay";
+
+ nfc@28 {
+ compatible = "nxp,pn547", "nxp,nxp-nci-i2c";
+ reg = <0x28>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ enable-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
+ firmware-gpios = <&msmgpio 2 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_default>;
+ };
+};
+
+&blsp1_uart2 {
+ status = "okay";
+};
+
+&pm8916_resin {
+ status = "okay";
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&pm8916_vib {
+ status = "okay";
+};
+
+&pronto {
+ status = "okay";
+};
+
+&sdhc_1 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdhc2_cd_default>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdhc2_cd_default>;
+
+ /*
+ * The Huawei device tree sets cd-gpios = <&msmgpio 38 GPIO_ACTIVE_HIGH>.
+ * However, gpio38 does not change its state when inserting/removing the
+ * SD card, it's just low all the time. The Huawei kernel seems to use
+ * polling for SD card detection instead.
+ *
+ * However, looking closer at the GPIO debug output it turns out that
+ * gpio56 switches its state when inserting/removing the SD card.
+ * It behaves just like gpio38 normally does. Usually GPIO56 is used as
+ * "UIM2_PRESENT", i.e. to check if a second SIM card is inserted.
+ * Maybe Huawei decided to replace the second SIM card slot with the
+ * SD card slot and forgot to re-route to gpio38.
+ */
+ cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>;
+};
+
+&usb {
+ status = "okay";
+ extcon = <&usb_id>, <&usb_id>;
+};
+
+&usb_hs_phy {
+ extcon = <&usb_id>;
+};
+
+&smd_rpm_regulators {
+ vdd_l1_l2_l3-supply = <&pm8916_s3>;
+ vdd_l4_l5_l6-supply = <&pm8916_s4>;
+ vdd_l7-supply = <&pm8916_s4>;
+
+ s3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ s4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ l1 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1225000>;
+ };
+
+ l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ l4 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l8 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ l9 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l10 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ l11 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ regulator-allow-set-load;
+ regulator-system-load = <200000>;
+ };
+
+ l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ };
+
+ l13 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ };
+
+ l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ l17 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ };
+
+ l18 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2700000>;
+ };
+};
+
+&msmgpio {
+ accel_irq_default: accel-irq-default {
+ pins = "gpio115";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ gpio_keys_default: gpio-keys-default {
+ pins = "gpio107";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ gpio_leds_default: gpio-leds-default {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ nfc_default: nfc-default {
+ pins = "gpio2", "gpio20", "gpio21";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ mag_reset_default: mag-reset-default {
+ pins = "gpio36";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ prox_irq_default: prox-irq-default {
+ pins = "gpio113";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ reg_lcd_en_default: reg-lcd-en-default {
+ pins = "gpio32", "gpio97";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ sdhc2_cd_default: sdhc2-cd-default {
+ pins = "gpio56";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ ts_irq_default: ts-irq-default {
+ pins = "gpio13";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ usb_id_default: usb-id-default {
+ pins = "gpio117";
+ function = "gpio";
+
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+};
diff --git a/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi b/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
index 230ba3c..9b4b7de 100644
--- a/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/src/arm64/qcom/msm8916-samsung-a2015-common.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
/ {
aliases {
@@ -95,6 +96,63 @@
pinctrl-0 = <&muic_int_default>;
};
};
+
+ i2c-tkey {
+ compatible = "i2c-gpio";
+ sda-gpios = <&msmgpio 16 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&msmgpio 17 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_i2c_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ touchkey: touchkey@20 {
+ /* Note: Actually an ABOV MCU that implements same interface */
+ compatible = "coreriver,tc360-touchkey";
+ reg = <0x20>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <98 IRQ_TYPE_EDGE_FALLING>;
+
+ /* vcc/vdd-supply are board-specific */
+ vddio-supply = <&pm8916_l6>;
+
+ linux,keycodes = <KEY_APPSELECT KEY_BACK>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_default>;
+ };
+ };
+
+ i2c-nfc {
+ compatible = "i2c-gpio";
+ sda-gpios = <&msmgpio 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&msmgpio 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_i2c_default>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nfc@27 {
+ compatible = "samsung,s3fwrn5-i2c";
+ reg = <0x27>;
+
+ interrupt-parent = <&msmgpio>;
+ interrupts = <21 IRQ_TYPE_EDGE_RISING>;
+
+ en-gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
+ wake-gpios = <&msmgpio 49 GPIO_ACTIVE_HIGH>;
+
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nfc_default &nfc_clk_req>;
+ };
+ };
};
&blsp_i2c2 {
@@ -122,6 +180,20 @@
};
};
+&blsp_i2c4 {
+ status = "okay";
+
+ battery@35 {
+ compatible = "richtek,rt5033-battery";
+ reg = <0x35>;
+ interrupt-parent = <&msmgpio>;
+ interrupts = <121 IRQ_TYPE_EDGE_BOTH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&fg_alert_default>;
+ };
+};
+
&blsp1_uart2 {
status = "okay";
};
@@ -284,6 +356,14 @@
bias-disable;
};
+ fg_alert_default: fg-alert-default {
+ pins = "gpio121";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
gpio_keys_default: gpio-keys-default {
pins = "gpio107", "gpio109";
function = "gpio";
@@ -333,6 +413,46 @@
bias-disable;
};
+ nfc_default: nfc-default {
+ pins = "gpio20", "gpio49";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+
+ irq {
+ pins = "gpio21";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ nfc_i2c_default: nfc-i2c-default {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_default: tkey-default {
+ pins = "gpio98";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_i2c_default: tkey-i2c-default {
+ pins = "gpio16", "gpio17";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
tsp_en_default: tsp-en-default {
pins = "gpio73";
function = "gpio";
@@ -341,3 +461,14 @@
bias-disable;
};
};
+
+&pm8916_gpios {
+ nfc_clk_req: nfc-clk-req {
+ pins = "gpio2";
+ function = "func1";
+
+ input-enable;
+ bias-disable;
+ power-source = <PM8916_GPIO_L2>;
+ };
+};
diff --git a/src/arm64/qcom/msm8916-samsung-a3u-eur.dts b/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
index 661f41a..6cc2eae 100644
--- a/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
+++ b/src/arm64/qcom/msm8916-samsung-a3u-eur.dts
@@ -20,6 +20,37 @@
pinctrl-names = "default";
pinctrl-0 = <&panel_vdd3_default>;
};
+
+ reg_touch_key: regulator-touch-key {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_key";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+
+ gpio = <&msmgpio 86 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_en_default>;
+ };
+
+ reg_key_led: regulator-key-led {
+ compatible = "regulator-fixed";
+ regulator-name = "key_led";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&msmgpio 60 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_led_en_default>;
+ };
+};
+
+&touchkey {
+ vcc-supply = <®_touch_key>;
+ vdd-supply = <®_key_led>;
};
&accelerometer {
@@ -81,6 +112,22 @@
bias-disable;
};
+ tkey_en_default: tkey-en-default {
+ pins = "gpio86";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ tkey_led_en_default: tkey-led-en-default {
+ pins = "gpio60";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
ts_int_default: ts-int-default {
pins = "gpio13";
function = "gpio";
diff --git a/src/arm64/qcom/msm8916-samsung-a5u-eur.dts b/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
index dd35c33..c2eff5a 100644
--- a/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
+++ b/src/arm64/qcom/msm8916-samsung-a5u-eur.dts
@@ -7,6 +7,19 @@
/ {
model = "Samsung Galaxy A5U (EUR)";
compatible = "samsung,a5u-eur", "qcom,msm8916";
+
+ reg_touch_key: regulator-touch-key {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_key";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&msmgpio 97 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&tkey_en_default>;
+ };
};
&accelerometer {
@@ -42,7 +55,20 @@
};
};
+&touchkey {
+ vcc-supply = <®_touch_key>;
+ vdd-supply = <®_touch_key>;
+};
+
&msmgpio {
+ tkey_en_default: tkey-en-default {
+ pins = "gpio97";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ };
+
ts_int_default: ts-int-default {
pins = "gpio13";
function = "gpio";
diff --git a/src/arm64/qcom/msm8994-angler-rev-101.dts b/src/arm64/qcom/msm8994-angler-rev-101.dts
index baa5564..ffe1a9b 100644
--- a/src/arm64/qcom/msm8994-angler-rev-101.dts
+++ b/src/arm64/qcom/msm8994-angler-rev-101.dts
@@ -32,3 +32,7 @@
};
};
};
+
+&tlmm {
+ gpio-reserved-ranges = <85 4>;
+};
diff --git a/src/arm64/qcom/msm8996-mtp.dtsi b/src/arm64/qcom/msm8996-mtp.dtsi
index 5f46a14..1e1514e 100644
--- a/src/arm64/qcom/msm8996-mtp.dtsi
+++ b/src/arm64/qcom/msm8996-mtp.dtsi
@@ -7,7 +7,7 @@
/ {
aliases {
- serial0 = &blsp2_uart1;
+ serial0 = &blsp2_uart2;
};
chosen {
diff --git a/src/arm64/qcom/msm8996-pins.dtsi b/src/arm64/qcom/msm8996-pins.dtsi
deleted file mode 100644
index ac1ede5..0000000
--- a/src/arm64/qcom/msm8996-pins.dtsi
+++ /dev/null
@@ -1,653 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
- */
-
-&msmgpio {
-
- wcd9xxx_intr {
- wcd_intr_default: wcd_intr_default{
- mux {
- pins = "gpio54";
- function = "gpio";
- };
-
- config {
- pins = "gpio54";
- drive-strength = <2>; /* 2 mA */
- bias-pull-down; /* pull down */
- input-enable;
- };
- };
- };
-
- cdc_reset_ctrl {
- cdc_reset_sleep: cdc_reset_sleep {
- mux {
- pins = "gpio64";
- function = "gpio";
- };
- config {
- pins = "gpio64";
- drive-strength = <16>;
- bias-disable;
- output-low;
- };
- };
- cdc_reset_active:cdc_reset_active {
- mux {
- pins = "gpio64";
- function = "gpio";
- };
- config {
- pins = "gpio64";
- drive-strength = <16>;
- bias-pull-down;
- output-high;
- };
- };
- };
-
- blsp1_spi0_default: blsp1_spi0_default {
- pinmux {
- function = "blsp_spi1";
- pins = "gpio0", "gpio1", "gpio3";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio2";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio3";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio2";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
- };
-
- blsp1_spi0_sleep: blsp1_spi0_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- };
- pinconf {
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- blsp1_i2c2_default: blsp1_i2c2_default {
- pinmux {
- function = "blsp_i2c3";
- pins = "gpio47", "gpio48";
- };
- pinconf {
- pins = "gpio47", "gpio48";
- drive-strength = <16>;
- bias-disable = <0>;
- };
- };
-
- blsp1_i2c2_sleep: blsp1_i2c2_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio47", "gpio48";
- };
- pinconf {
- pins = "gpio47", "gpio48";
- drive-strength = <2>;
- bias-disable = <0>;
- };
- };
-
- blsp2_i2c0_default: blsp2_i2c0 {
- pinmux {
- function = "blsp_i2c7";
- pins = "gpio55", "gpio56";
- };
- pinconf {
- pins = "gpio55", "gpio56";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_i2c0_sleep: blsp2_i2c0_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio55", "gpio56";
- };
- pinconf {
- pins = "gpio55", "gpio56";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart1_2pins_default: blsp2_uart1_2pins {
- pinmux {
- function = "blsp_uart8";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart1_2pins_sleep: blsp2_uart1_2pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5";
- };
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart1_4pins_default: blsp2_uart1_4pins {
- pinmux {
- function = "blsp_uart8";
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- };
-
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart1_4pins_sleep: blsp2_uart1_4pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- };
-
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_i2c1_default: blsp2_i2c1 {
- pinmux {
- function = "blsp_i2c8";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_i2c1_sleep: blsp2_i2c1_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio6", "gpio7";
- };
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart2_2pins_default: blsp2_uart2_2pins {
- pinmux {
- function = "blsp_uart9";
- pins = "gpio49", "gpio50";
- };
- pinconf {
- pins = "gpio49", "gpio50";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart2_2pins_sleep: blsp2_uart2_2pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio49", "gpio50";
- };
- pinconf {
- pins = "gpio49", "gpio50";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_uart2_4pins_default: blsp2_uart2_4pins {
- pinmux {
- function = "blsp_uart9";
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- };
-
- pinconf {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- blsp2_uart2_4pins_sleep: blsp2_uart2_4pins_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- };
-
- pinconf {
- pins = "gpio49", "gpio50", "gpio51", "gpio52";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- blsp2_spi5_default: blsp2_spi5_default {
- pinmux {
- function = "blsp_spi12";
- pins = "gpio85", "gpio86", "gpio88";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio87";
- };
- pinconf {
- pins = "gpio85", "gpio86", "gpio88";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio87";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
- };
-
- blsp2_spi5_sleep: blsp2_spi5_sleep {
- pinmux {
- function = "gpio";
- pins = "gpio85", "gpio86", "gpio87", "gpio88";
- };
- pinconf {
- pins = "gpio85", "gpio86", "gpio87", "gpio88";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- sdc2_clk_on: sdc2_clk_on {
- config {
- pins = "sdc2_clk";
- bias-disable; /* NO pull */
- drive-strength = <16>; /* 16 MA */
- };
- };
-
- sdc2_clk_off: sdc2_clk_off {
- config {
- pins = "sdc2_clk";
- bias-disable; /* NO pull */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- sdc2_cmd_on: sdc2_cmd_on {
- config {
- pins = "sdc2_cmd";
- bias-pull-up; /* pull up */
- drive-strength = <10>; /* 10 MA */
- };
- };
-
- sdc2_cmd_off: sdc2_cmd_off {
- config {
- pins = "sdc2_cmd";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- sdc2_data_on: sdc2_data_on {
- config {
- pins = "sdc2_data";
- bias-pull-up; /* pull up */
- drive-strength = <10>; /* 10 MA */
- };
- };
-
- sdc2_data_off: sdc2_data_off {
- config {
- pins = "sdc2_data";
- bias-pull-up; /* pull up */
- drive-strength = <2>; /* 2 MA */
- };
- };
-
- pcie0_clkreq_default: pcie0_clkreq_default {
- mux {
- pins = "gpio36";
- function = "pci_e0";
- };
-
- config {
- pins = "gpio36";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie0_perst_default: pcie0_perst_default {
- mux {
- pins = "gpio35";
- function = "gpio";
- };
-
- config {
- pins = "gpio35";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie0_wake_default: pcie0_wake_default {
- mux {
- pins = "gpio37";
- function = "gpio";
- };
-
- config {
- pins = "gpio37";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie0_clkreq_sleep: pcie0_clkreq_sleep {
- mux {
- pins = "gpio36";
- function = "gpio";
- };
-
- config {
- pins = "gpio36";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie0_wake_sleep: pcie0_wake_sleep {
- mux {
- pins = "gpio37";
- function = "gpio";
- };
-
- config {
- pins = "gpio37";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie1_clkreq_default: pcie1_clkreq_default {
- mux {
- pins = "gpio131";
- function = "pci_e1";
- };
-
- config {
- pins = "gpio131";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie1_perst_default: pcie1_perst_default {
- mux {
- pins = "gpio130";
- function = "gpio";
- };
-
- config {
- pins = "gpio130";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie1_wake_default: pcie1_wake_default {
- mux {
- pins = "gpio132";
- function = "gpio";
- };
-
- config {
- pins = "gpio132";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie1_clkreq_sleep: pcie1_clkreq_sleep {
- mux {
- pins = "gpio131";
- function = "gpio";
- };
-
- config {
- pins = "gpio131";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie1_wake_sleep: pcie1_wake_sleep {
- mux {
- pins = "gpio132";
- function = "gpio";
- };
-
- config {
- pins = "gpio132";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie2_clkreq_default: pcie2_clkreq_default {
- mux {
- pins = "gpio115";
- function = "pci_e2";
- };
-
- config {
- pins = "gpio115";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie2_perst_default: pcie2_perst_default {
- mux {
- pins = "gpio114";
- function = "gpio";
- };
-
- config {
- pins = "gpio114";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie2_wake_default: pcie2_wake_default {
- mux {
- pins = "gpio116";
- function = "gpio";
- };
-
- config {
- pins = "gpio116";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- pcie2_clkreq_sleep: pcie2_clkreq_sleep {
- mux {
- pins = "gpio115";
- function = "gpio";
- };
-
- config {
- pins = "gpio115";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- pcie2_wake_sleep: pcie2_wake_sleep {
- mux {
- pins = "gpio116";
- function = "gpio";
- };
-
- config {
- pins = "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
- };
-
- cci0_default: cci0_default {
- pinmux {
- function = "cci_i2c";
- pins = "gpio17", "gpio18";
- };
- pinconf {
- pins = "gpio17", "gpio18";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- cci1_default: cci1_default {
- pinmux {
- function = "cci_i2c";
- pins = "gpio19", "gpio20";
- };
- pinconf {
- pins = "gpio19", "gpio20";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_board_default: camera_board_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio98";
- };
- config_pwdn {
- pins = "gpio98";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio104";
- };
- config_rst {
- pins = "gpio104";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk1 {
- function = "cam_mclk";
- pins = "gpio14";
- };
- config_mclk1 {
- pins = "gpio14";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_front_default: camera_front_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio133";
- };
- config_pwdn {
- pins = "gpio133";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio23";
- };
- config_rst {
- pins = "gpio23";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk2 {
- function = "cam_mclk";
- pins = "gpio15";
- };
- config_mclk2 {
- pins = "gpio15";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- camera_rear_default: camera_rear_default {
- mux_pwdn {
- function = "gpio";
- pins = "gpio26";
- };
- config_pwdn {
- pins = "gpio26";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_rst {
- function = "gpio";
- pins = "gpio25";
- };
- config_rst {
- pins = "gpio25";
- drive-strength = <16>;
- bias-disable;
- };
-
- mux_mclk0 {
- function = "cam_mclk";
- pins = "gpio13";
- };
- config_mclk0 {
- pins = "gpio13";
- drive-strength = <16>;
- bias-disable;
- };
- };
-};
diff --git a/src/arm64/qcom/msm8996.dtsi b/src/arm64/qcom/msm8996.dtsi
index ce430ba..0e1bc46 100644
--- a/src/arm64/qcom/msm8996.dtsi
+++ b/src/arm64/qcom/msm8996.dtsi
@@ -6,7 +6,9 @@
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,apr.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -43,6 +45,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -57,6 +62,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 0>;
+ operating-points-v2 = <&cluster0_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_0>;
};
@@ -67,6 +75,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
@@ -81,6 +92,9 @@
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
+ clocks = <&kryocc 1>;
+ operating-points-v2 = <&cluster1_opp>;
+ #cooling-cells = <2>;
next-level-cache = <&L2_1>;
};
@@ -120,6 +134,227 @@
};
};
+ cluster0_opp: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ /* Nominal fmax for now */
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-422400000 {
+ opp-hz = /bits/ 64 <422400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1228800000 {
+ opp-hz = /bits/ 64 <1228800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1593600000 {
+ opp-hz = /bits/ 64 <1593600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
+ cluster1_opp: opp_table1 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+ opp-shared;
+
+ /* Nominal fmax for now */
+ opp-307200000 {
+ opp-hz = /bits/ 64 <307200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-556800000 {
+ opp-hz = /bits/ 64 <556800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-652800000 {
+ opp-hz = /bits/ 64 <652800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-729600000 {
+ opp-hz = /bits/ 64 <729600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-883200000 {
+ opp-hz = /bits/ 64 <883200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-940800000 {
+ opp-hz = /bits/ 64 <940800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1113600000 {
+ opp-hz = /bits/ 64 <1113600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1478400000 {
+ opp-hz = /bits/ 64 <1478400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1632000000 {
+ opp-hz = /bits/ 64 <1632000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1824000000 {
+ opp-hz = /bits/ 64 <1824000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1920000000 {
+ opp-hz = /bits/ 64 <1920000000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ opp-supported-hw = <0x77>;
+ clock-latency-ns = <200000>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-msm8996";
@@ -424,7 +659,7 @@
bits = <1 4>;
};
- gpu_speed_bin: gpu_speed_bin@133 {
+ speedbin_efuse: speedbin@133 {
reg = <0x133 0x1>;
bits = <5 3>;
};
@@ -472,7 +707,7 @@
tcsr_mutex_regs: syscon@740000 {
compatible = "syscon";
- reg = <0x00740000 0x20000>;
+ reg = <0x00740000 0x40000>;
};
tcsr: syscon@7a0000 {
@@ -521,6 +756,8 @@
#size-cells = <1>;
ranges;
+ status = "disabled";
+
mdp: mdp@901000 {
compatible = "qcom,mdp5";
reg = <0x00901000 0x90000>;
@@ -542,6 +779,11 @@
iommus = <&mdp_smmu 0>;
+ assigned-clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <300000000>,
+ <19200000>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -552,9 +794,82 @@
remote-endpoint = <&hdmi_in>;
};
};
+
+ port@1 {
+ reg = <1>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
};
};
+ dsi0: dsi@994000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0x00994000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>;
+ clock-names = "mdp_core",
+ "byte",
+ "iface",
+ "bus",
+ "core_mmss",
+ "pixel",
+ "core";
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ dsi0_phy: dsi-phy@994400 {
+ compatible = "qcom,dsi-phy-14nm";
+ reg = <0x00994400 0x100>,
+ <0x00994500 0x300>,
+ <0x00994800 0x188>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
+ clock-names = "iface", "ref";
+ status = "disabled";
+ };
+
hdmi: hdmi-tx@9a0000 {
compatible = "qcom,hdmi-tx-8996";
reg = <0x009a0000 0x50c>,
@@ -618,7 +933,8 @@
"ref";
};
};
- gpu@b00000 {
+
+ gpu: gpu@b00000 {
compatible = "qcom,adreno-530.2", "qcom,adreno";
#stream-id-cells = <16>;
@@ -642,7 +958,7 @@
power-domains = <&mmcc GPU_GX_GDSC>;
iommus = <&adreno_smmu 0>;
- nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cells = <&speedbin_efuse>;
nvmem-cell-names = "speed_bin";
qcom,gpu-quirk-two-pass-use-wfi;
@@ -650,6 +966,8 @@
operating-points-v2 = <&gpu_opp_table>;
+ status = "disabled";
+
gpu_opp_table: opp-table {
compatible ="operating-points-v2";
@@ -693,15 +1011,482 @@
};
};
- msmgpio: pinctrl@1010000 {
+ tlmm: pinctrl@1010000 {
compatible = "qcom,msm8996-pinctrl";
reg = <0x01010000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&msmgpio 0 0 150>;
+ gpio-ranges = <&tlmm 0 0 150>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+ blsp1_spi1_default: blsp1-spi1-default {
+ spi {
+ pins = "gpio0", "gpio1", "gpio3";
+ function = "blsp_spi1";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs {
+ pins = "gpio2";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp1_spi1_sleep: blsp1-spi1-sleep {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_uart2_2pins_default: blsp2-uart1-2pins {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart8";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_default: blsp2-i2c2 {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c8";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c2_sleep: blsp2-i2c2-sleep {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cci0_default: cci0-default {
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ camera0_state_on:
+ camera_rear_default: camera-rear-default {
+ mclk0 {
+ pins = "gpio13";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio25";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ cci1_default: cci1-default {
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ camera1_state_on:
+ camera_board_default: camera-board-default {
+ mclk1 {
+ pins = "gpio14";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio98";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio104";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ camera2_state_on:
+ camera_front_default: camera-front-default {
+ mclk2 {
+ pins = "gpio15";
+ function = "cam_mclk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ rst {
+ pins = "gpio23";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ pwdn {
+ pins = "gpio133";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ pcie0_state_on: pcie0-state-on {
+ perst {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio36";
+ function = "pci_e0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_state_off: pcie0-state-off {
+ perst {
+ pins = "gpio35";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio36";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio37";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_i2c3_default: blsp1-i2c2-default {
+ pins = "gpio47", "gpio48";
+ function = "blsp_i2c3";
+ drive-strength = <16>;
+ bias-disable = <0>;
+ };
+
+ blsp1_i2c3_sleep: blsp1-i2c2-sleep {
+ pins = "gpio47", "gpio48";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+
+ blsp2_uart3_4pins_default: blsp2-uart2-4pins {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "blsp_uart9";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep {
+ pins = "gpio49", "gpio50", "gpio51", "gpio52";
+ function = "blsp_uart9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wcd_intr_default: wcd-intr-default{
+ pins = "gpio54";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+
+ blsp2_i2c1_default: blsp2-i2c1 {
+ pins = "gpio55", "gpio56";
+ function = "blsp_i2c7";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c1_sleep: blsp2-i2c0-sleep {
+ pins = "gpio55", "gpio56";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ blsp2_i2c5_default: blsp2-i2c5 {
+ pins = "gpio60", "gpio61";
+ function = "blsp_i2c11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ /* Sleep state for BLSP2_I2C5 is missing.. */
+
+ cdc_reset_active: cdc-reset-active {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-pull-down;
+ output-high;
+ };
+
+ cdc_reset_sleep: cdc-reset-sleep {
+ pins = "gpio64";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+
+ blsp2_spi6_default: blsp2-spi5-default {
+ spi {
+ pins = "gpio85", "gpio86", "gpio88";
+ function = "blsp_spi12";
+ drive-strength = <12>;
+ bias-disable;
+ };
+
+ cs {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ blsp2_spi6_sleep: blsp2-spi5-sleep {
+ pins = "gpio85", "gpio86", "gpio87", "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ blsp2_i2c6_default: blsp2-i2c6 {
+ pins = "gpio87", "gpio88";
+ function = "blsp_i2c12";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ blsp2_i2c6_sleep: blsp2-i2c6-sleep {
+ pins = "gpio87", "gpio88";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie1_state_on: pcie1-state-on {
+ perst {
+ pins = "gpio130";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio131";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio132";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie1_state_off: pcie1-state-off {
+ /* Perst is missing? */
+ clkreq {
+ pins = "gpio131";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio132";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pcie2_state_on: pcie2-state-on {
+ perst {
+ pins = "gpio114";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio115";
+ function = "pci_e2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio116";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie2_state_off: pcie2-state-off {
+ /* Perst is missing? */
+ clkreq {
+ pins = "gpio115";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ wake {
+ pins = "gpio116";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ sdc1_state_on: sdc1-state-on {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_state_off: sdc1-state-off {
+ clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_state_on: sdc2-clk-on {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+ };
+
+ sdc2_state_off: sdc2-clk-off {
+ clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
spmi_bus: qcom,spmi@400f000 {
@@ -762,8 +1547,8 @@
<0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
- pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
+ pinctrl-0 = <&pcie0_state_on>;
+ pinctrl-1 = <&pcie0_state_off>;
linux,pci-domain = <0>;
@@ -816,8 +1601,8 @@
<0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
- pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
+ pinctrl-0 = <&pcie1_state_on>;
+ pinctrl-1 = <&pcie1_state_off>;
linux,pci-domain = <1>;
@@ -867,8 +1652,8 @@
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
- pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
+ pinctrl-0 = <&pcie2_state_on>;
+ pinctrl-1 = <&pcie2_state_off>;
linux,pci-domain = <2>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
@@ -1136,7 +1921,7 @@
};
adreno_smmu: iommu@b40000 {
- compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
+ compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
reg = <0x00b40000 0x10000>;
#global-interrupts = <1>;
@@ -1152,7 +1937,7 @@
power-domains = <&mmcc GPU_GDSC>;
};
- video-codec@c00000 {
+ venus: video-codec@c00000 {
compatible = "qcom,msm8996-venus";
reg = <0x00c00000 0xff000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
@@ -1183,7 +1968,7 @@
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_region>;
- status = "okay";
+ status = "disabled";
video-decoder {
compatible = "venus-decoder";
@@ -1745,9 +2530,14 @@
};
};
};
+
kryocc: clock-controller@6400000 {
- compatible = "qcom,apcc-msm8996";
+ compatible = "qcom,msm8996-apcc";
reg = <0x06400000 0x90000>;
+
+ clock-names = "xo";
+ clocks = <&xo_board>;
+
#clock-cells = <1>;
};
@@ -1758,6 +2548,10 @@
#size-cells = <1>;
ranges;
+ interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq";
+
clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
<&gcc GCC_USB30_MASTER_CLK>,
<&gcc GCC_AGGRE2_USB3_AXI_CLK>,
@@ -1772,7 +2566,7 @@
power-domains = <&gcc USB30_GDSC>;
status = "disabled";
- dwc3@6a00000 {
+ usb@6a00000 {
compatible = "snps,dwc3";
reg = <0x06a00000 0xcc00>;
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
@@ -1841,34 +2635,75 @@
status = "disabled";
};
+ sdhc1: sdhci@7464900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x07464900 0x11c>, <0x07464000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clock-names = "iface", "core", "xo";
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&xo_board>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc1_state_on>;
+ pinctrl-1 = <&sdc1_state_off>;
+
+ bus-width = <8>;
+ non-removable;
+ status = "disabled";
+ };
+
sdhc2: sdhci@74a4900 {
- status = "disabled";
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
- reg-names = "hc_mem", "core_mem";
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
+ reg-names = "hc_mem", "core_mem";
- interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 221 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
- clock-names = "iface", "core", "xo";
- clocks = <&gcc GCC_SDCC2_AHB_CLK>,
- <&gcc GCC_SDCC2_APPS_CLK>,
- <&xo_board>;
- bus-width = <4>;
+ clock-names = "iface", "core", "xo";
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&xo_board>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_state_on>;
+ pinctrl-1 = <&sdc2_state_off>;
+
+ bus-width = <4>;
+ status = "disabled";
};
- blsp1_uart1: serial@7570000 {
+ blsp1_dma: dma@7544000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07544000 0x2b000>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "bam_clk";
+ qcom,controlled-remotely;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp1_uart2: serial@7570000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x07570000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
+ dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
- blsp1_spi0: spi@7575000 {
+ blsp1_spi1: spi@7575000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07575000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -1876,14 +2711,16 @@
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_spi0_default>;
- pinctrl-1 = <&blsp1_spi0_sleep>;
+ pinctrl-0 = <&blsp1_spi1_default>;
+ pinctrl-1 = <&blsp1_spi1_sleep>;
+ dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp1_i2c2: i2c@7577000 {
+ blsp1_i2c3: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -1891,14 +2728,27 @@
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp1_i2c2_default>;
- pinctrl-1 = <&blsp1_i2c2_sleep>;
+ pinctrl-0 = <&blsp1_i2c3_default>;
+ pinctrl-1 = <&blsp1_i2c3_sleep>;
+ dmas = <&blsp1_dma 16>, <&blsp1_dma 17>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_uart1: serial@75b0000 {
+ blsp2_dma: dma@7584000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x07584000 0x2b000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ qcom,controlled-remotely;
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ blsp2_uart2: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b0000 0x1000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
@@ -1908,7 +2758,7 @@
status = "disabled";
};
- blsp2_uart2: serial@75b1000 {
+ blsp2_uart3: serial@75b1000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x075b1000 0x1000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
@@ -1918,7 +2768,7 @@
status = "disabled";
};
- blsp2_i2c0: i2c@75b5000 {
+ blsp2_i2c1: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
@@ -1926,14 +2776,16 @@
<&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c0_default>;
- pinctrl-1 = <&blsp2_i2c0_sleep>;
+ pinctrl-0 = <&blsp2_i2c1_default>;
+ pinctrl-1 = <&blsp2_i2c1_sleep>;
+ dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_i2c1: i2c@75b6000 {
+ blsp2_i2c2: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
@@ -1941,14 +2793,49 @@
<&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_i2c1_default>;
- pinctrl-1 = <&blsp2_i2c1_sleep>;
+ pinctrl-0 = <&blsp2_i2c2_default>;
+ pinctrl-1 = <&blsp2_i2c2_sleep>;
+ dmas = <&blsp2_dma 14>, <&blsp2_dma 15>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
- blsp2_spi5: spi@75ba000{
+ blsp2_i2c5: i2c@75b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x75b9000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default";
+ pinctrl-0 = <&blsp2_i2c5_default>;
+ dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_i2c6: i2c@75ba000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x75ba000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp2_i2c6_default>;
+ pinctrl-1 = <&blsp2_i2c6_sleep>;
+ dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ blsp2_spi6: spi@75ba000{
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x075ba000 0x600>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
@@ -1956,8 +2843,10 @@
<&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
- pinctrl-0 = <&blsp2_spi5_default>;
- pinctrl-1 = <&blsp2_spi5_sleep>;
+ pinctrl-0 = <&blsp2_spi6_default>;
+ pinctrl-1 = <&blsp2_spi6_sleep>;
+ dmas = <&blsp2_dma 22>, <&blsp2_dma 23>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1981,14 +2870,16 @@
assigned-clock-rates = <19200000>, <60000000>;
power-domains = <&gcc USB30_GDSC>;
+ qcom,select-utmi-as-pipe-clk;
status = "disabled";
- dwc3@7600000 {
+ usb@7600000 {
compatible = "snps,dwc3";
reg = <0x07600000 0xcc00>;
interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy2>;
phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
};
@@ -2032,13 +2923,13 @@
compatible = "slim217,1a0";
reg = <1 0>;
- interrupt-parent = <&msmgpio>;
+ interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
- reset-gpios = <&msmgpio 64 0>;
+ reset-gpios = <&tlmm 64 0>;
slim-ifc-dev = <&tasha_ifd>;
@@ -2067,6 +2958,11 @@
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
+ power-domains = <&rpmpd MSM8996_VDDCX>;
+ power-domain-names = "cx";
+
+ status = "disabled";
+
smd-edge {
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
@@ -2458,4 +3354,3 @@
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};
-#include "msm8996-pins.dtsi"
diff --git a/src/arm64/qcom/msm8998.dtsi b/src/arm64/qcom/msm8998.dtsi
index e9d3ce2..6f294f9 100644
--- a/src/arm64/qcom/msm8998.dtsi
+++ b/src/arm64/qcom/msm8998.dtsi
@@ -1964,7 +1964,7 @@
resets = <&gcc GCC_USB_30_BCR>;
- usb3_dwc3: dwc3@a800000 {
+ usb3_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0x0a800000 0xcd00>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm64/qcom/pm6150.dtsi b/src/arm64/qcom/pm6150.dtsi
index 8ab4f1f..8a4972e 100644
--- a/src/arm64/qcom/pm6150.dtsi
+++ b/src/arm64/qcom/pm6150.dtsi
@@ -7,6 +7,30 @@
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/thermal/thermal.h>
+/ {
+ thermal-zones {
+ pm6150_thermal: pm6150-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm6150_temp>;
+
+ trips {
+ pm6150_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm6150_crit: crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
&spmi_bus {
pm6150_lsid0: pmic@0 {
compatible = "qcom,pm6150", "qcom,spmi-pmic";
diff --git a/src/arm64/qcom/pm7325.dtsi b/src/arm64/qcom/pm7325.dtsi
new file mode 100644
index 0000000..e7f64a9
--- /dev/null
+++ b/src/arm64/qcom/pm7325.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: BSD-3-Clause
+// Copyright (c) 2021, The Linux Foundation. All rights reserved.
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ pm7325: pmic@1 {
+ compatible = "qcom,pm7325", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm7325_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm7325_gpios: gpios@8800 {
+ compatible = "qcom,pm7325-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pm7325_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+&thermal_zones {
+ pm7325_thermal: pm7325-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm7325_temp_alarm>;
+
+ trips {
+ pm7325_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm7325_crit: pm7325-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/src/arm64/qcom/pm8150.dtsi b/src/arm64/qcom/pm8150.dtsi
index fa4ea7d..c566a64 100644
--- a/src/arm64/qcom/pm8150.dtsi
+++ b/src/arm64/qcom/pm8150.dtsi
@@ -50,7 +50,8 @@
pon: power-on@800 {
compatible = "qcom,pm8916-pon";
reg = <0x0800>;
- pwrkey {
+
+ pon_pwrkey: pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
@@ -59,6 +60,15 @@
status = "disabled";
};
+
+ pon_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+
+ status = "disabled";
+ };
};
pm8150_temp: temp-alarm@2400 {
diff --git a/src/arm64/qcom/pm8350c.dtsi b/src/arm64/qcom/pm8350c.dtsi
index 2b9b75e..e1b75ae 100644
--- a/src/arm64/qcom/pm8350c.dtsi
+++ b/src/arm64/qcom/pm8350c.dtsi
@@ -13,13 +13,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ pm8350c_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pm8350c_gpios: gpio@8800 {
- compatible = "qcom,pm8350c-gpio";
+ compatible = "qcom,pm8350c-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
+ gpio-ranges = <&pm8350c_gpios 0 0 9>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
+
+&thermal_zones {
+ pm8350c_thermal: pm8350c-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8350c_temp_alarm>;
+
+ trips {
+ pm8350c_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8350c_crit: pm8350c-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/src/arm64/qcom/pm8994.dtsi b/src/arm64/qcom/pm8994.dtsi
index c3876c8..ad19016 100644
--- a/src/arm64/qcom/pm8994.dtsi
+++ b/src/arm64/qcom/pm8994.dtsi
@@ -45,7 +45,6 @@
pm8994_pon: pon@800 {
compatible = "qcom,pm8916-pon";
-
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
@@ -58,6 +57,13 @@
linux,code = <KEY_POWER>;
};
+ pm8994_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
};
pm8994_temp: temp-alarm@2400 {
diff --git a/src/arm64/qcom/pmi8994.dtsi b/src/arm64/qcom/pmi8994.dtsi
index e5ed28a..b4ac900 100644
--- a/src/arm64/qcom/pmi8994.dtsi
+++ b/src/arm64/qcom/pmi8994.dtsi
@@ -32,5 +32,18 @@
#address-cells = <1>;
#size-cells = <1>;
};
+
+ pmi8994_wled: wled@d800 {
+ compatible = "qcom,pmi8994-wled";
+ reg = <0xd800 0xd900>;
+ interrupts = <3 0xd8 0x02 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "short";
+ qcom,num-strings = <3>;
+ /* Yes, all four strings *have to* be defined or things won't work. */
+ qcom,enabled-strings = <0 1 2 3>;
+ qcom,cabc;
+ qcom,eternal-pfet;
+ status = "disabled";
+ };
};
};
diff --git a/src/arm64/qcom/pmk8350.dtsi b/src/arm64/qcom/pmk8350.dtsi
index 1530b8f..04fc263 100644
--- a/src/arm64/qcom/pmk8350.dtsi
+++ b/src/arm64/qcom/pmk8350.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2021, Linaro Limited
*/
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
@@ -13,10 +15,57 @@
#address-cells = <1>;
#size-cells = <0>;
+ pmk8350_pon: pon@1300 {
+ compatible = "qcom,pm8998-pon";
+ reg = <0x1300>;
+
+ pwrkey {
+ compatible = "qcom,pmk8350-pwrkey";
+ interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_POWER>;
+ };
+
+ resin {
+ compatible = "qcom,pmk8350-resin";
+ interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ pmk8350_vadc: adc@3100 {
+ compatible = "qcom,spmi-adc7";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ };
+
+ pmk8350_adc_tm: adc-tm@3400 {
+ compatible = "qcom,adc-tm7";
+ reg = <0x3400>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "threshold";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ status = "disabled";
+ };
+
+ pmk8350_rtc: rtc@6100 {
+ compatible = "qcom,pmk8350-rtc";
+ reg = <0x6100>, <0x6200>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
pmk8350_gpios: gpio@b000 {
- compatible = "qcom,pmk8350-gpio";
+ compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio";
reg = <0xb000>;
gpio-controller;
+ gpio-ranges = <&pmk8350_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
diff --git a/src/arm64/qcom/pmm8155au_1.dtsi b/src/arm64/qcom/pmm8155au_1.dtsi
new file mode 100644
index 0000000..7072e5a
--- /dev/null
+++ b/src/arm64/qcom/pmm8155au_1.dtsi
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+/ {
+ thermal-zones {
+ pmm8155au-1-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmm8155au_1_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@0 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pon: power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_POWER>;
+
+ status = "disabled";
+ };
+ };
+
+ pmm8155au_1_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmm8155au_1_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmm8155au_1_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ pmm8155au_1_adc_tm: adc-tm@3500 {
+ compatible = "qcom,spmi-adc-tm5";
+ reg = <0x3500>;
+ interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pmm8155au_1_rtc: rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+
+ status = "disabled";
+ };
+
+ pmm8155au_1_gpios: gpio@c000 {
+ compatible = "qcom,pmm8155au-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm8155au_1_gpios 0 0 10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@1 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/src/arm64/qcom/pmm8155au_2.dtsi b/src/arm64/qcom/pmm8155au_2.dtsi
new file mode 100644
index 0000000..7207596
--- /dev/null
+++ b/src/arm64/qcom/pmm8155au_2.dtsi
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+/ {
+ thermal-zones {
+ pmm8155au-2-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pmm8155au_2_temp>;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "hot";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+&spmi_bus {
+ pmic@4 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-on@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x0800>;
+
+ status = "disabled";
+ };
+
+ pmm8155au_2_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pmm8155au_2_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmm8155au_2_adc: adc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+
+ ref-gnd@0 {
+ reg = <ADC5_REF_GND>;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ vref-1p25@1 {
+ reg = <ADC5_1P25VREF>;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ die-temp@6 {
+ reg = <ADC5_DIE_TEMP>;
+ qcom,pre-scaling = <1 1>;
+ label = "die_temp";
+ };
+ };
+
+ pmm8155au_2_gpios: gpio@c000 {
+ compatible = "qcom,pmm8155au-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pmm8155au_2_gpios 0 0 10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ pmic@5 {
+ compatible = "qcom,pmm8155au", "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/src/arm64/qcom/pmr735a.dtsi b/src/arm64/qcom/pmr735a.dtsi
index 1c675af..b4b6ba2 100644
--- a/src/arm64/qcom/pmr735a.dtsi
+++ b/src/arm64/qcom/pmr735a.dtsi
@@ -13,13 +13,43 @@
#address-cells = <1>;
#size-cells = <0>;
+ pmr735a_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
pmr735a_gpios: gpio@8800 {
- compatible = "qcom,pmr735a-gpio";
+ compatible = "qcom,pmr735a-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
+ gpio-ranges = <&pmr735a_gpios 0 0 4>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
+
+&thermal_zones {
+ pmr735a_thermal: pmr735a-thermal {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmr735a_temp_alarm>;
+
+ trips {
+ pmr735a_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pmr735a_crit: pmr735a-crit {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/src/arm64/qcom/qcs404-evb.dtsi b/src/arm64/qcom/qcs404-evb.dtsi
index a80c578..f8a5530 100644
--- a/src/arm64/qcom/qcs404-evb.dtsi
+++ b/src/arm64/qcom/qcs404-evb.dtsi
@@ -337,7 +337,7 @@
&usb3 {
status = "okay";
- dwc3@7580000 {
+ usb@7580000 {
dr_mode = "host";
};
};
diff --git a/src/arm64/qcom/qcs404.dtsi b/src/arm64/qcom/qcs404.dtsi
index 339790b..9c4be02 100644
--- a/src/arm64/qcom/qcs404.dtsi
+++ b/src/arm64/qcom/qcs404.dtsi
@@ -544,7 +544,7 @@
assigned-clock-rates = <19200000>, <200000000>;
status = "disabled";
- dwc3@7580000 {
+ usb@7580000 {
compatible = "snps,dwc3";
reg = <0x07580000 0xcd00>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -573,7 +573,7 @@
assigned-clock-rates = <19200000>, <133333333>;
status = "disabled";
- dwc3@78c0000 {
+ usb@78c0000 {
compatible = "snps,dwc3";
reg = <0x078c0000 0xcc00>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm64/qcom/qrb5165-rb5.dts b/src/arm64/qcom/qrb5165-rb5.dts
index 5f41de2..8ac96f8 100644
--- a/src/arm64/qcom/qrb5165-rb5.dts
+++ b/src/arm64/qcom/qrb5165-rb5.dts
@@ -5,7 +5,6 @@
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
@@ -552,7 +551,13 @@
vdds-supply = <&vreg_l5a_0p88>;
};
+&gmu {
+ status = "okay";
+};
+
&gpu {
+ status = "okay";
+
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
@@ -664,10 +669,6 @@
&pcie0 {
status = "okay";
- perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_default_state>;
};
&pcie0_phy {
@@ -678,10 +679,6 @@
&pcie1 {
status = "okay";
- perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_default_state>;
};
&pcie1_phy {
@@ -692,10 +689,6 @@
&pcie2 {
status = "okay";
- perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie2_default_state>;
};
&pcie2_phy {
@@ -1173,81 +1166,6 @@
bias-disable;
};
- pcie0_default_state: pcie0-default {
- clkreq {
- pins = "gpio80";
- function = "pci_e0";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio79";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio81";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie1_default_state: pcie1-default {
- clkreq {
- pins = "gpio83";
- function = "pci_e1";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio82";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio84";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- pcie2_default_state: pcie2-default {
- clkreq {
- pins = "gpio86";
- function = "pci_e2";
- bias-pull-up;
- };
-
- reset-n {
- pins = "gpio85";
- function = "gpio";
-
- drive-strength = <2>;
- output-low;
- bias-pull-down;
- };
-
- wake-n {
- pins = "gpio87";
- function = "gpio";
-
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
sdc2_default_state: sdc2-default {
clk {
pins = "sdc2_clk";
@@ -1352,6 +1270,10 @@
qcom,dmic-sample-rate = <600000>;
};
+&venus {
+ status = "okay";
+};
+
/* PINCTRL - additions to nodes defined in sm8250.dtsi */
&qup_spi0_cs_gpio {
drive-strength = <6>;
diff --git a/src/arm64/qcom/sa8155p-adp.dts b/src/arm64/qcom/sa8155p-adp.dts
new file mode 100644
index 0000000..0da7a3b
--- /dev/null
+++ b/src/arm64/qcom/sa8155p-adp.dts
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Linaro Limited
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "sm8150.dtsi"
+#include "pmm8155au_1.dtsi"
+#include "pmm8155au_2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SA8155P ADP";
+ compatible = "qcom,sa8155p-adp", "qcom,sa8155p";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vreg_3p3: vreg_3p3_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ /*
+ * S4A is always on and not controllable through RPMh.
+ * So model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: smps4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-allow-set-load;
+
+ vin-supply = <&vreg_3p3>;
+ };
+};
+
+&apps_rsc {
+ pmm8155au-1-rpmh-regulators {
+ compatible = "qcom,pmm8155au-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vreg_3p3>;
+ vdd-s2-supply = <&vreg_3p3>;
+ vdd-s3-supply = <&vreg_3p3>;
+ vdd-s4-supply = <&vreg_3p3>;
+ vdd-s5-supply = <&vreg_3p3>;
+ vdd-s6-supply = <&vreg_3p3>;
+ vdd-s7-supply = <&vreg_3p3>;
+ vdd-s8-supply = <&vreg_3p3>;
+ vdd-s9-supply = <&vreg_3p3>;
+ vdd-s10-supply = <&vreg_3p3>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p92>;
+ vdd-l2-l10-supply = <&vreg_3p3>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p92>;
+ vdd-l6-l9-supply = <&vreg_s6a_0p92>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
+ vdd-l13-l16-l17-supply = <&vreg_3p3>;
+
+ vreg_s5a_2p04: smps5 {
+ regulator-name = "vreg_s5a_2p04";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p92: smps6 {
+ regulator-name = "vreg_s6a_0p92";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_l1a_0p752: ldo1 {
+ regulator-name = "vreg_l1a_0p752";
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_usb_hs_3p1:
+ vreg_l2a_3p072: ldo2 {
+ regulator-name = "vreg_l2a_3p072";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-name = "vreg_l3a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_usb_hs_core:
+ vdda_usb_ss_dp_core_1:
+ vreg_l5a_0p88: ldo5 {
+ regulator-name = "vreg_l5a_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p96: ldo10 {
+ regulator-name = "vreg_l10a_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-name = "vreg_l11a_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_usb_hs_1p8:
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p7: ldo13 {
+ regulator-name = "vreg_l13a_2p7";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-name = "vreg_l15a_1p7";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-name = "vreg_l16a_2p7";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_2p96: ldo17 {
+ regulator-name = "vreg_l17a_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pmm8155au-2-rpmh-regulators {
+ compatible = "qcom,pmm8155au-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vreg_3p3>;
+ vdd-s2-supply = <&vreg_3p3>;
+ vdd-s3-supply = <&vreg_3p3>;
+ vdd-s4-supply = <&vreg_3p3>;
+ vdd-s5-supply = <&vreg_3p3>;
+ vdd-s6-supply = <&vreg_3p3>;
+ vdd-s7-supply = <&vreg_3p3>;
+ vdd-s8-supply = <&vreg_3p3>;
+ vdd-s9-supply = <&vreg_3p3>;
+ vdd-s10-supply = <&vreg_3p3>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s4c_1p352>;
+ vdd-l2-l10-supply = <&vreg_3p3>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s4c_1p352>;
+ vdd-l6-l9-supply = <&vreg_s6c_1p128>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5c_2p04>;
+ vdd-l13-l16-l17-supply = <&vreg_3p3>;
+
+ vreg_s4c_1p352: smps4 {
+ regulator-name = "vreg_s4c_1p352";
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_s5c_2p04: smps5 {
+ regulator-name = "vreg_s5c_2p04";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6c_1p128: smps6 {
+ regulator-name = "vreg_s6c_1p128";
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_l1c_1p304: ldo1 {
+ regulator-name = "vreg_l1c_1p304";
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p808: ldo2 {
+ regulator-name = "vreg_l2c_1p808";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p2: ldo5 {
+ regulator-name = "vreg_l5c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_1p8: ldo7 {
+ regulator-name = "vreg_l7c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p2: ldo8 {
+ regulator-name = "vreg_l8c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-name = "vreg_l10c_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_0p8: ldo11 {
+ regulator-name = "vreg_l11c_0p8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12c_1p808: ldo12 {
+ regulator-name = "vreg_l12c_1p808";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13c_2p96: ldo13 {
+ regulator-name = "vreg_l13c_2p96";
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15c_1p9: ldo15 {
+ regulator-name = "vreg_l15c_1p9";
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16c_3p008: ldo16 {
+ regulator-name = "vreg_l16c_3p008";
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18c_0p88: ldo18 {
+ regulator-name = "vreg_l18c_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <0 4>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l10a_2p96>;
+ vcc-max-microamp = <750000>;
+ vccq-supply = <&vreg_l5c_1p2>;
+ vccq-max-microamp = <700000>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vccq2-max-microamp = <750000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l8c_1p2>;
+ vdda-max-microamp = <87100>;
+ vdda-pll-supply = <&vreg_l5a_0p88>;
+ vdda-pll-max-microamp = <18300>;
+};
+
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vdd_usb_hs_core>;
+ vdda33-supply = <&vdda_usb_hs_3p1>;
+ vdda18-supply = <&vdda_usb_hs_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l8c_1p2>;
+ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
diff --git a/src/arm64/qcom/sc7180-idp.dts b/src/arm64/qcom/sc7180-idp.dts
index e77a792..acdb36f 100644
--- a/src/arm64/qcom/sc7180-idp.dts
+++ b/src/arm64/qcom/sc7180-idp.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include "sc7180.dtsi"
#include "pm6150.dtsi"
#include "pm6150l.dtsi"
@@ -45,7 +46,7 @@
/* Increase the size from 2MB to 8MB */
&rmtfs_mem {
- reg = <0x0 0x84400000 0x0 0x800000>;
+ reg = <0x0 0x94600000 0x0 0x800000>;
};
/ {
@@ -288,6 +289,57 @@
};
};
+&dsi0 {
+ status = "okay";
+
+ vdda-supply = <&vreg_l3c_1p2>;
+
+ panel@0 {
+ compatible = "visionox,rm69299-1080p-display";
+ reg = <0>;
+
+ vdda-supply = <&vreg_l8c_1p8>;
+ vdd3p3-supply = <&vreg_l18a_2p8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_pins>;
+
+ reset-gpios = <&pm6150l_gpio 3 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ panel0_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&panel0_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dsi_phy {
+ status = "okay";
+};
+
+&mdp {
+ status = "okay";
+};
+
+&mdss {
+ status = "okay";
+};
+
&qfprom {
vcc-supply = <&vreg_l11a_1p8>;
};
@@ -414,6 +466,19 @@
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
+&pm6150l_gpio {
+ disp_pins: disp-pins {
+ pinconf {
+ pins = "gpio3";
+ function = PMIC_GPIO_FUNC_FUNC1;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
&qspi_clk {
pinconf {
pins = "gpio63";
@@ -598,4 +663,106 @@
bias-pull-up;
};
};
+
+ sdc1_on: sdc1-on {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_off: sdc1-off {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_on: sdc2-on {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_off: sdc2-off {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
diff --git a/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts b/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts
index 533c048..82dc00c 100644
--- a/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts
+++ b/src/arm64/qcom/sc7180-trogdor-coachz-r1-lte.dts
@@ -9,8 +9,8 @@
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google CoachZ (rev1) with LTE";
- compatible = "google,coachz-rev1-sku0", "qcom,sc7180";
+ model = "Google CoachZ (rev1 - 2) with LTE";
+ compatible = "google,coachz-rev1-sku0", "google,coachz-rev2-sku0", "qcom,sc7180";
};
&cros_ec_proximity {
diff --git a/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts b/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts
index 1b1dbdb..21b516e 100644
--- a/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts
+++ b/src/arm64/qcom/sc7180-trogdor-coachz-r1.dts
@@ -10,8 +10,26 @@
#include "sc7180-trogdor-coachz.dtsi"
/ {
- model = "Google CoachZ (rev1)";
- compatible = "google,coachz-rev1", "qcom,sc7180";
+ model = "Google CoachZ (rev1 - 2)";
+ compatible = "google,coachz-rev1", "google,coachz-rev2", "qcom,sc7180";
+};
+
+/*
+ * CoachZ rev1 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
+/*
+ * CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature,
+ * which currently is not supported by the PM6150 ADC driver. Disable the
+ * skin temperature thermal zone to avoid using bogus temperature values.
+ */
+&skin_temp_thermal {
+ status = "disabled";
};
&tlmm {
diff --git a/src/arm64/qcom/sc7180-trogdor-coachz-r2-lte.dts b/src/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts
similarity index 69%
rename from src/arm64/qcom/sc7180-trogdor-coachz-r2-lte.dts
rename to src/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts
index 6e77458..d234090 100644
--- a/src/arm64/qcom/sc7180-trogdor-coachz-r2-lte.dts
+++ b/src/arm64/qcom/sc7180-trogdor-coachz-r3-lte.dts
@@ -2,14 +2,14 @@
/*
* Google CoachZ board device tree source
*
- * Copyright 2020 Google LLC.
+ * Copyright 2021 Google LLC.
*/
-#include "sc7180-trogdor-coachz-r2.dts"
+#include "sc7180-trogdor-coachz-r3.dts"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google CoachZ (rev2+) with LTE";
+ model = "Google CoachZ (rev3+) with LTE";
compatible = "google,coachz-sku0", "qcom,sc7180";
};
diff --git a/src/arm64/qcom/sc7180-trogdor-coachz-r2.dts b/src/arm64/qcom/sc7180-trogdor-coachz-r3.dts
similarity index 75%
rename from src/arm64/qcom/sc7180-trogdor-coachz-r2.dts
rename to src/arm64/qcom/sc7180-trogdor-coachz-r3.dts
index 4f69b6b..a02d2d5 100644
--- a/src/arm64/qcom/sc7180-trogdor-coachz-r2.dts
+++ b/src/arm64/qcom/sc7180-trogdor-coachz-r3.dts
@@ -2,7 +2,7 @@
/*
* Google CoachZ board device tree source
*
- * Copyright 2020 Google LLC.
+ * Copyright 2021 Google LLC.
*/
/dts-v1/;
@@ -10,6 +10,6 @@
#include "sc7180-trogdor-coachz.dtsi"
/ {
- model = "Google CoachZ (rev2+)";
+ model = "Google CoachZ (rev3+)";
compatible = "google,coachz", "qcom,sc7180";
};
diff --git a/src/arm64/qcom/sc7180-trogdor-coachz.dtsi b/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
index 4c6e433..6f9c071 100644
--- a/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
+++ b/src/arm64/qcom/sc7180-trogdor-coachz.dtsi
@@ -23,8 +23,53 @@
adau7002: audio-codec-1 {
compatible = "adi,adau7002";
IOVDD-supply = <&pp1800_l15a>;
+ wakeup-delay-ms = <15>;
#sound-dai-cells = <0>;
};
+
+ thermal-zones {
+ skin_temp_thermal: skin-temp-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&pm6150_adc_tm 1>;
+ sustainable-power = <814>;
+
+ trips {
+ skin_temp_alert0: trip-point0 {
+ temperature = <42000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin_temp_alert1: trip-point1 {
+ temperature = <45000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ skin-temp-crit {
+ temperature = <60000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&skin_temp_alert0>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+
+ map1 {
+ trip = <&skin_temp_alert1>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
};
&ap_spi_fp {
@@ -77,6 +122,25 @@
compatible = "boe,nv110wtm-n61";
};
+&pm6150_adc {
+ skin-temp-thermistor@4e {
+ reg = <ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm6150_adc_tm {
+ status = "okay";
+
+ skin-temp-thermistor@1 {
+ reg = <1>;
+ io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time-us = <200>;
+ };
+};
+
&pp3300_dx_edp {
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};
diff --git a/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts b/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts
index 5c997cd..30e3e76 100644
--- a/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts
+++ b/src/arm64/qcom/sc7180-trogdor-lazor-r0.dts
@@ -14,15 +14,6 @@
compatible = "google,lazor-rev0", "qcom,sc7180";
};
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
-
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts b/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts
index d9fbcc7..c2ef063 100644
--- a/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts
+++ b/src/arm64/qcom/sc7180-trogdor-lazor-r1.dts
@@ -14,15 +14,6 @@
compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180";
};
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
-
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts b/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts
index ea8c2ee..b474df4 100644
--- a/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts
+++ b/src/arm64/qcom/sc7180-trogdor-lazor-r3.dts
@@ -14,12 +14,3 @@
model = "Google Lazor (rev3+)";
compatible = "google,lazor", "qcom,sc7180";
};
-
-/*
- * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
- * not supported by the PM6150 ADC driver. Disable the charger thermal zone
- * to avoid using bogus temperature values.
- */
-&charger_thermal {
- status = "disabled";
-};
diff --git a/src/arm64/qcom/sc7180-trogdor-lazor.dtsi b/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
index 6b10b96..00535aa 100644
--- a/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
+++ b/src/arm64/qcom/sc7180-trogdor-lazor.dtsi
@@ -21,6 +21,15 @@
semtech,avg-pos-strength = <64>;
};
+/*
+ * Lazor is stuffed with a 47k NTC as charger thermistor which currently is
+ * not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;
diff --git a/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts b/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts
index e720e7b..e122a6b 100644
--- a/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts
+++ b/src/arm64/qcom/sc7180-trogdor-pompom-r1.dts
@@ -9,11 +9,23 @@
#include "sc7180-trogdor-pompom.dtsi"
+/delete-node/ &keyboard_controller;
+#include <arm/cros-ec-keyboard.dtsi>
+
/ {
model = "Google Pompom (rev1)";
compatible = "google,pompom-rev1", "qcom,sc7180";
};
+/*
+ * Pompom rev1 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
+};
+
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
diff --git a/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts b/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts
index 791d496..00e187c 100644
--- a/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts
+++ b/src/arm64/qcom/sc7180-trogdor-pompom-r2-lte.dts
@@ -9,6 +9,6 @@
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
- model = "Google Pompom (rev2+) with LTE";
- compatible = "google,pompom-sku0", "qcom,sc7180";
+ model = "Google Pompom (rev2) with LTE";
+ compatible = "google,pompom-rev2-sku0", "qcom,sc7180";
};
diff --git a/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts b/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts
index 984d733..4f32e67 100644
--- a/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts
+++ b/src/arm64/qcom/sc7180-trogdor-pompom-r2.dts
@@ -10,35 +10,15 @@
#include "sc7180-trogdor-pompom.dtsi"
/ {
- model = "Google Pompom (rev2+)";
- compatible = "google,pompom", "qcom,sc7180";
+ model = "Google Pompom (rev2)";
+ compatible = "google,pompom-rev2", "qcom,sc7180";
};
-&keyboard_controller {
- function-row-physmap = <
- MATRIX_KEY(0x00, 0x02, 0) /* T1 */
- MATRIX_KEY(0x03, 0x02, 0) /* T2 */
- MATRIX_KEY(0x02, 0x02, 0) /* T3 */
- MATRIX_KEY(0x01, 0x02, 0) /* T4 */
- MATRIX_KEY(0x03, 0x04, 0) /* T5 */
- MATRIX_KEY(0x02, 0x04, 0) /* T6 */
- MATRIX_KEY(0x01, 0x04, 0) /* T7 */
- MATRIX_KEY(0x02, 0x09, 0) /* T8 */
- MATRIX_KEY(0x01, 0x09, 0) /* T9 */
- MATRIX_KEY(0x00, 0x04, 0) /* T10 */
- >;
- linux,keymap = <
- MATRIX_KEY(0x00, 0x02, KEY_BACK)
- MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
- MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
- MATRIX_KEY(0x01, 0x02, KEY_SCALE)
- MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
- MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
- MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
- MATRIX_KEY(0x02, 0x09, KEY_MUTE)
- MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
- MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
-
- CROS_STD_MAIN_KEYMAP
- >;
+/*
+ * Pompom rev2 is stuffed with a 47k NTC as charger thermistor which currently
+ * is not supported by the PM6150 ADC driver. Disable the charger thermal zone
+ * to avoid using bogus temperature values.
+ */
+&charger_thermal {
+ status = "disabled";
};
diff --git a/src/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts b/src/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts
new file mode 100644
index 0000000..e90b73c
--- /dev/null
+++ b/src/arm64/qcom/sc7180-trogdor-pompom-r3-lte.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pompom board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+#include "sc7180-trogdor-pompom-r3.dts"
+#include "sc7180-trogdor-lte-sku.dtsi"
+
+/ {
+ model = "Google Pompom (rev3+) with LTE";
+ compatible = "google,pompom-sku0", "qcom,sc7180";
+};
diff --git a/src/arm64/qcom/sc7180-trogdor-pompom-r3.dts b/src/arm64/qcom/sc7180-trogdor-pompom-r3.dts
new file mode 100644
index 0000000..f8aac63
--- /dev/null
+++ b/src/arm64/qcom/sc7180-trogdor-pompom-r3.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Google Pompom board device tree source
+ *
+ * Copyright 2021 Google LLC.
+ */
+
+/dts-v1/;
+
+#include "sc7180-trogdor-pompom.dtsi"
+
+/ {
+ model = "Google Pompom (rev3+)";
+ compatible = "google,pompom", "qcom,sc7180";
+};
diff --git a/src/arm64/qcom/sc7180-trogdor-pompom.dtsi b/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
index 622b5f1..a246dbd 100644
--- a/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
+++ b/src/arm64/qcom/sc7180-trogdor-pompom.dtsi
@@ -107,6 +107,35 @@
};
};
+&keyboard_controller {
+ function-row-physmap = <
+ MATRIX_KEY(0x00, 0x02, 0) /* T1 */
+ MATRIX_KEY(0x03, 0x02, 0) /* T2 */
+ MATRIX_KEY(0x02, 0x02, 0) /* T3 */
+ MATRIX_KEY(0x01, 0x02, 0) /* T4 */
+ MATRIX_KEY(0x03, 0x04, 0) /* T5 */
+ MATRIX_KEY(0x02, 0x04, 0) /* T6 */
+ MATRIX_KEY(0x01, 0x04, 0) /* T7 */
+ MATRIX_KEY(0x02, 0x09, 0) /* T8 */
+ MATRIX_KEY(0x01, 0x09, 0) /* T9 */
+ MATRIX_KEY(0x00, 0x04, 0) /* T10 */
+ >;
+ linux,keymap = <
+ MATRIX_KEY(0x00, 0x02, KEY_BACK)
+ MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
+ MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
+ MATRIX_KEY(0x01, 0x02, KEY_SCALE)
+ MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
+ MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
+ MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
+ MATRIX_KEY(0x02, 0x09, KEY_MUTE)
+ MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
+ MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
+
+ CROS_STD_MAIN_KEYMAP
+ >;
+};
+
&panel {
compatible = "kingdisplay,kd116n21-30nv-a010";
};
diff --git a/src/arm64/qcom/sc7180-trogdor.dtsi b/src/arm64/qcom/sc7180-trogdor.dtsi
index 24d293e..77ae756 100644
--- a/src/arm64/qcom/sc7180-trogdor.dtsi
+++ b/src/arm64/qcom/sc7180-trogdor.dtsi
@@ -64,11 +64,6 @@
no-map;
};
- camera_mem: memory@8ec00000 {
- reg = <0x0 0x8ec00000 0x0 0x500000>;
- no-map;
- };
-
venus_mem: memory@8f600000 {
reg = <0 0x8f600000 0 0x500000>;
no-map;
@@ -335,8 +330,7 @@
compatible = "jedec,spi-nor";
reg = <0>;
- /* TODO: Increase frequency after testing */
- spi-max-frequency = <25000000>;
+ spi-max-frequency = <37500000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
@@ -564,10 +558,6 @@
#size-cells = <0>;
};
- pdupdate {
- compatible = "google,cros-ec-pd-update";
- };
-
typec {
compatible = "google,cros-ec-typec";
#address-cells = <1>;
@@ -655,6 +645,8 @@
clocks = <&rpmhcc RPMH_LN_BB_CLK3>;
clock-names = "refclk";
+ no-hpd;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -772,7 +764,7 @@
qcom,capture-sd-lines = <0>;
};
- mi2s@1 {
+ secondary_mi2s: mi2s@1 {
reg = <MI2S_SECONDARY>;
qcom,playback-sd-lines = <0>;
};
@@ -805,7 +797,7 @@
};
};
-&pm6150_pwrkey {
+&pm6150_pon {
status = "disabled";
};
@@ -981,6 +973,7 @@
&qspi_clk {
pinconf {
pins = "gpio63";
+ drive-strength = <8>;
bias-disable;
};
};
@@ -1494,4 +1487,106 @@
drive-strength = <2>;
};
};
+
+ sdc1_on: sdc1-on {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc1_off: sdc1-off {
+ pinconf-clk {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-rclk {
+ pins = "sdc1_rclk";
+ bias-pull-down;
+ };
+ };
+
+ sdc2_on: sdc2-on {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ sdc2_off: sdc2-off {
+ pinconf-clk {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ pinconf-cmd {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-data {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ pinconf-sd-cd {
+ pins = "gpio69";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
};
diff --git a/src/arm64/qcom/sc7180.dtsi b/src/arm64/qcom/sc7180.dtsi
index 6228ba2..a5d58eb 100644
--- a/src/arm64/qcom/sc7180.dtsi
+++ b/src/arm64/qcom/sc7180.dtsi
@@ -701,8 +701,9 @@
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_APPS_CLK>,
- <&gcc GCC_SDCC1_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC1_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
interconnect-names = "sdhc-ddr","cpu-sdhc";
@@ -726,15 +727,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <100000 100000>;
- opp-avg-kBps = <100000 50000>;
+ opp-peak-kBps = <1800000 600000>;
+ opp-avg-kBps = <100000 0>;
};
opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- opp-peak-kBps = <600000 900000>;
- opp-avg-kBps = <261438 300000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <390000 0>;
};
};
};
@@ -768,8 +769,6 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
- interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
- interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
@@ -1059,8 +1058,6 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
- interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
- interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
@@ -1871,108 +1868,6 @@
function = "lpass_ext";
};
};
-
- sdc1_on: sdc1-on {
- pinconf-clk {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- pinconf-cmd {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-data {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-rclk {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
- };
-
- sdc1_off: sdc1-off {
- pinconf-clk {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- pinconf-cmd {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-data {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-rclk {
- pins = "sdc1_rclk";
- bias-pull-down;
- };
- };
-
- sdc2_on: sdc2-on {
- pinconf-clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <16>;
- };
-
- pinconf-cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <10>;
- };
-
- pinconf-sd-cd {
- pins = "gpio69";
- bias-pull-up;
- drive-strength = <2>;
- };
- };
-
- sdc2_off: sdc2-off {
- pinconf-clk {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <2>;
- };
-
- pinconf-cmd {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-data {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <2>;
- };
-
- pinconf-sd-cd {
- pins = "gpio69";
- bias-disable;
- drive-strength = <2>;
- };
- };
};
remoteproc_mpss: remoteproc@4080000 {
@@ -2670,8 +2565,9 @@
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC2_APPS_CLK>,
- <&gcc GCC_SDCC2_AHB_CLK>;
- clock-names = "core", "iface";
+ <&gcc GCC_SDCC2_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "core", "iface", "xo";
interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
@@ -2689,15 +2585,15 @@
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
- opp-peak-kBps = <160000 100000>;
- opp-avg-kBps = <80000 50000>;
+ opp-peak-kBps = <1800000 600000>;
+ opp-avg-kBps = <100000 0>;
};
opp-202000000 {
opp-hz = /bits/ 64 <202000000>;
- required-opps = <&rpmhpd_opp_svs_l1>;
- opp-peak-kBps = <200000 120000>;
- opp-avg-kBps = <100000 60000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5400000 1600000>;
+ opp-avg-kBps = <200000 0>;
};
};
};
@@ -2754,8 +2650,8 @@
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x38>,
- <0 0x088ea000 0 0x40>;
+ <0 0x088e8000 0 0x3c>,
+ <0 0x088ea000 0 0x18c>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
@@ -2860,7 +2756,7 @@
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xe000>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm64/qcom/sc7280-idp.dts b/src/arm64/qcom/sc7280-idp.dts
index 54d2cb3..3900cfc 100644
--- a/src/arm64/qcom/sc7280-idp.dts
+++ b/src/arm64/qcom/sc7280-idp.dts
@@ -7,11 +7,19 @@
/dts-v1/;
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmr735b.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include "sc7280.dtsi"
+#include "pm7325.dtsi"
+#include "pmr735a.dtsi"
+#include "pm8350c.dtsi"
+#include "pmk8350.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
- compatible = "qcom,sc7280-idp", "qcom,sc7280";
+ compatible = "qcom,sc7280-idp", "google,senor", "qcom,sc7280";
aliases {
serial0 = &uart5;
@@ -234,6 +242,32 @@
};
};
+&pmk8350_vadc {
+ pm8350_die_temp {
+ reg = <PM8350_ADC7_DIE_TEMP>;
+ label = "pm8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmk8350_die_temp {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "pmk8350_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmr735a_die_temp {
+ reg = <PMR735A_ADC7_DIE_TEMP>;
+ label = "pmr735a_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pmr735b_die_temp {
+ reg = <PMR735B_ADC7_DIE_TEMP>;
+ label = "pmr735b_die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
diff --git a/src/arm64/qcom/sc7280.dtsi b/src/arm64/qcom/sc7280.dtsi
index 2cc4785..a8c274a 100644
--- a/src/arm64/qcom/sc7280.dtsi
+++ b/src/arm64/qcom/sc7280.dtsi
@@ -11,7 +11,10 @@
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/reset/qcom,sdm845-aoss.h>
+#include <dt-bindings/reset/qcom,sdm845-pdc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -51,6 +54,11 @@
no-map;
};
+ smem_mem: memory@80900000 {
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ no-map;
+ };
+
cpucp_mem: memory@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
@@ -70,6 +78,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -88,6 +98,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -103,6 +115,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -118,6 +132,8 @@
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -133,6 +149,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -148,6 +166,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -163,6 +183,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -178,6 +200,8 @@
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@@ -251,6 +275,125 @@
};
};
+ clk_virt: interconnect {
+ compatible = "qcom,sc7280-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-wpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_WPSS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <13>;
+
+ wpss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wpss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -316,6 +459,93 @@
};
};
+ cnoc2: interconnect@1500000 {
+ reg = <0 0x01500000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc2";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ cnoc3: interconnect@1502000 {
+ reg = <0 0x01502000 0 0x1000>;
+ compatible = "qcom,sc7280-cnoc3";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect@1580000 {
+ reg = <0 0x01580000 0 0x4>;
+ compatible = "qcom,sc7280-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1680000 {
+ reg = <0 0x01680000 0 0x15480>;
+ compatible = "qcom,sc7280-system-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre1_noc: interconnect@16e0000 {
+ compatible = "qcom,sc7280-aggre1-noc";
+ reg = <0 0x016e0000 0 0x1c080>;
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ aggre2_noc: interconnect@1700000 {
+ reg = <0 0x01700000 0 0x2b080>;
+ compatible = "qcom,sc7280-aggre2-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mmss_noc: interconnect@1740000 {
+ reg = <0 0x01740000 0 0x1e080>;
+ compatible = "qcom,sc7280-mmss-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex", "syscon";
+ reg = <0 0x01f40000 0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ lpasscc: lpasscc@3000000 {
+ compatible = "qcom,sc7280-lpasscc";
+ reg = <0 0x03000000 0 0x40>,
+ <0 0x03c04000 0 0x4>,
+ <0 0x03389000 0 0x24>;
+ reg-names = "qdsp6ss", "top_cc", "cc";
+ clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
+ clock-names = "iface";
+ #clock-cells = <1>;
+ };
+
+ lpass_ag_noc: interconnect@3c40000 {
+ reg = <0 0x03c40000 0 0xf080>;
+ compatible = "qcom,sc7280-lpass-ag-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gpucc: clock-controller@3d90000 {
+ compatible = "qcom,sc7280-gpucc";
+ reg = <0 0x03d90000 0 0x9000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ clock-names = "bi_tcxo",
+ "gcc_gpu_gpll0_clk_src",
+ "gcc_gpu_gpll0_div_clk_src";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
stm@6002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0 0x06002000 0 0x1000>,
@@ -805,6 +1035,20 @@
};
};
+ dc_noc: interconnect@90e0000 {
+ reg = <0 0x090e0000 0 0x5080>;
+ compatible = "qcom,sc7280-dc-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@9100000 {
+ reg = <0 0x9100000 0 0xe2200>;
+ compatible = "qcom,sc7280-gem-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
system-cache-controller@9200000 {
compatible = "qcom,sc7280-llcc";
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
@@ -812,6 +1056,42 @@
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
+ nsp_noc: interconnect@a0c0000 {
+ reg = <0 0x0a0c0000 0 0x10000>;
+ compatible = "qcom,sc7280-nsp-noc";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ videocc: clock-controller@aaf0000 {
+ compatible = "qcom,sc7280-videocc";
+ reg = <0 0xaaf0000 0 0x10000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,sc7280-dispcc";
+ reg = <0 0xaf00000 0 0x20000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_GPLL0_CLK_SRC>,
+ <0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
+ "dsi0_phy_pll_out_byteclk",
+ "dsi0_phy_pll_out_dsiclk",
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk",
+ "edp_phy_pll_link_clk",
+ "edp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
@@ -825,6 +1105,40 @@
interrupt-controller;
};
+ pdc_reset: reset-controller@b5e0000 {
+ compatible = "qcom,sc7280-pdc-global";
+ reg = <0 0x0b5e0000 0 0x20000>;
+ #reset-cells = <1>;
+ };
+
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <15>;
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x1ff>; /* SROT */
+ #qcom,sensors = <12>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow","critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ aoss_reset: reset-controller@c2a0000 {
+ compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
+ reg = <0 0x0c2a0000 0 0x31000>;
+ #reset-cells = <1>;
+ };
+
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc7280-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
@@ -1063,6 +1377,10 @@
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ apps_bcm_voter: bcm-voter {
+ compatible = "qcom,bcm-voter";
+ };
+
rpmhpd: power-controller {
compatible = "qcom,sc7280-rpmhpd";
#power-domain-cells = <1>;
@@ -1116,6 +1434,859 @@
#clock-cells = <1>;
};
};
+
+ cpufreq_hw: cpufreq@18591000 {
+ compatible = "qcom,cpufreq-epss";
+ reg = <0 0x18591000 0 0x1000>,
+ <0 0x18592000 0 0x1000>,
+ <0 0x18593000 0 0x1000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ #freq-domain-cells = <1>;
+ };
+ };
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ cpu0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu0_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ cpu1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu1_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ cpu2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu2_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ cpu3_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert0>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu3_alert1>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ cpu4_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu4_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ cpu5_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu5_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ cpu6_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu6_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ cpu7_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu7_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu8-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ cpu8_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu8_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu8_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu8_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu8_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu9-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ cpu9_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu9_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu9_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu9_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu9_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu10-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ cpu10_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu10_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu10_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu10_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu10_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu11-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 14>;
+
+ trips {
+ cpu11_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu11_alert1: trip-point1 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu11_crit: cpu-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu11_alert0>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ map1 {
+ trip = <&cpu11_alert1>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ aoss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ aoss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss0_crit: aoss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ aoss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 0>;
+
+ trips {
+ aoss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ aoss1_crit: aoss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ cpuss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpuss0_crit: cluster0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ cpuss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ cpuss1_crit: cluster0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 1>;
+
+ trips {
+ gpuss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss0_crit: gpuss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 2>;
+
+ trips {
+ gpuss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ gpuss1_crit: gpuss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 3>;
+
+ trips {
+ nspss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nspss0_crit: nspss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nspss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 4>;
+
+ trips {
+ nspss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ nspss1_crit: nspss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 5>;
+
+ trips {
+ video_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ video_crit: video-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 6>;
+
+ trips {
+ ddr_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ ddr_crit: ddr-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 7>;
+
+ trips {
+ mdmss0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss0_crit: mdmss0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 8>;
+
+ trips {
+ mdmss1_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss1_crit: mdmss1-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss2-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 9>;
+
+ trips {
+ mdmss2_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss2_crit: mdmss2-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss3-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 10>;
+
+ trips {
+ mdmss3_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ mdmss3_crit: mdmss3-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera0-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens1 11>;
+
+ trips {
+ camera0_alert0: trip-point0 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ camera0_crit: camera0-crit {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
};
timer {
diff --git a/src/arm64/qcom/sdm845-cheza.dtsi b/src/arm64/qcom/sdm845-cheza.dtsi
index 216a74f..dfd1b42 100644
--- a/src/arm64/qcom/sdm845-cheza.dtsi
+++ b/src/arm64/qcom/sdm845-cheza.dtsi
@@ -714,10 +714,6 @@
#address-cells = <1>;
#size-cells = <0>;
};
-
- pdupdate {
- compatible = "google,cros-ec-pd-update";
- };
};
};
diff --git a/src/arm64/qcom/sdm845-mtp.dts b/src/arm64/qcom/sdm845-mtp.dts
index 1372fe8..91ede92 100644
--- a/src/arm64/qcom/sdm845-mtp.dts
+++ b/src/arm64/qcom/sdm845-mtp.dts
@@ -448,6 +448,11 @@
clock-frequency = <400000>;
};
+&ipa {
+ status = "okay";
+ memory-region = <&ipa_fw_mem>;
+};
+
&mdss {
status = "okay";
};
diff --git a/src/arm64/qcom/sdm845-oneplus-common.dtsi b/src/arm64/qcom/sdm845-oneplus-common.dtsi
index 8f617f7..4d052e3 100644
--- a/src/arm64/qcom/sdm845-oneplus-common.dtsi
+++ b/src/arm64/qcom/sdm845-oneplus-common.dtsi
@@ -46,6 +46,14 @@
};
reserved-memory {
+ /* The rmtfs_mem needs to be guarded due to "XPU limitations"
+ * it is otherwise possible for an allocation adjacent to the
+ * rmtfs_mem region to trigger an XPU violation, causing a crash.
+ */
+ rmtfs_lower_guard: memory@f5b00000 {
+ no-map;
+ reg = <0 0xf5b00000 0 0x1000>;
+ };
/*
* The rmtfs memory region in downstream is 'dynamically allocated'
* but given the same address every time. Hard code it as this address is
@@ -59,6 +67,10 @@
qcom,client-id = <1>;
qcom,vmid = <15>;
};
+ rmtfs_upper_guard: memory@f5d01000 {
+ no-map;
+ reg = <0 0xf5d01000 0 0x2000>;
+ };
/*
* It seems like reserving the old rmtfs_mem region is also needed to prevent
@@ -387,6 +399,12 @@
};
};
+&ipa {
+ status = "okay";
+
+ memory-region = <&ipa_fw_mem>;
+};
+
&mdss {
status = "okay";
};
diff --git a/src/arm64/qcom/sdm845-xiaomi-beryllium.dts b/src/arm64/qcom/sdm845-xiaomi-beryllium.dts
index 7d02942..c60c8c6 100644
--- a/src/arm64/qcom/sdm845-xiaomi-beryllium.dts
+++ b/src/arm64/qcom/sdm845-xiaomi-beryllium.dts
@@ -5,6 +5,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/sound/qcom,q6afe.h>
+#include <dt-bindings/sound/qcom,q6asm.h>
#include "sdm845.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
@@ -311,6 +313,28 @@
};
};
+/* QUAT I2S Uses 1 I2S SD Line for audio on TAS2559/60 amplifiers */
+&q6afedai {
+ qi2s@22 {
+ reg = <22>;
+ qcom,sd-lines = <0>;
+ };
+};
+
+&q6asmdai {
+ dai@0 {
+ reg = <0>;
+ };
+
+ dai@1 {
+ reg = <1>;
+ };
+
+ dai@2 {
+ reg = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -328,6 +352,70 @@
cd-gpios = <&tlmm 126 GPIO_ACTIVE_HIGH>;
};
+&sound {
+ compatible = "qcom,db845c-sndcard";
+ pinctrl-0 = <&quat_mi2s_active
+ &quat_mi2s_sd0_active>;
+ pinctrl-names = "default";
+ model = "Xiaomi Poco F1";
+ audio-routing =
+ "RX_BIAS", "MCLK",
+ "AMIC1", "MIC BIAS1",
+ "AMIC2", "MIC BIAS2",
+ "AMIC3", "MIC BIAS3";
+
+ mm1-dai-link {
+ link-name = "MultiMedia1";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
+ };
+ };
+
+ mm2-dai-link {
+ link-name = "MultiMedia2";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
+ };
+ };
+
+ mm3-dai-link {
+ link-name = "MultiMedia3";
+ cpu {
+ sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
+ };
+ };
+
+ slim-dai-link {
+ link-name = "SLIM Playback";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_RX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9340 0>;
+ };
+ };
+
+ slimcap-dai-link {
+ link-name = "SLIM Capture";
+ cpu {
+ sound-dai = <&q6afedai SLIMBUS_0_TX>;
+ };
+
+ platform {
+ sound-dai = <&q6routing>;
+ };
+
+ codec {
+ sound-dai = <&wcd9340 1>;
+ };
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
@@ -356,6 +444,15 @@
function = "gpio";
bias-pull-up;
};
+
+ wcd_intr_default: wcd_intr_default {
+ pins = <54>;
+ function = "gpio";
+
+ input-enable;
+ bias-pull-down;
+ drive-strength = <2>;
+ };
};
&uart6 {
@@ -416,6 +513,23 @@
vdda-pll-supply = <&vreg_l1a_0p875>;
};
+&wcd9340{
+ pinctrl-0 = <&wcd_intr_default>;
+ pinctrl-names = "default";
+ clock-names = "extclk";
+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
+ reset-gpios = <&tlmm 64 0>;
+ vdd-buck-supply = <&vreg_s4a_1p8>;
+ vdd-buck-sido-supply = <&vreg_s4a_1p8>;
+ vdd-tx-supply = <&vreg_s4a_1p8>;
+ vdd-rx-supply = <&vreg_s4a_1p8>;
+ vdd-io-supply = <&vreg_s4a_1p8>;
+ qcom,micbias1-microvolt = <2700000>;
+ qcom,micbias2-microvolt = <1800000>;
+ qcom,micbias3-microvolt = <2700000>;
+ qcom,micbias4-microvolt = <2700000>;
+};
+
&wifi {
status = "okay";
diff --git a/src/arm64/qcom/sdm845.dtsi b/src/arm64/qcom/sdm845.dtsi
index 0a86fe7..1796ae8 100644
--- a/src/arm64/qcom/sdm845.dtsi
+++ b/src/arm64/qcom/sdm845.dtsi
@@ -3781,7 +3781,7 @@
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
@@ -3829,7 +3829,7 @@
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
interconnect-names = "usb-ddr", "apps-usb";
- usb_2_dwc3: dwc3@a800000 {
+ usb_2_dwc3: usb@a800000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts b/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
index 140db2d..c2a709a 100644
--- a/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
+++ b/src/arm64/qcom/sdm850-lenovo-yoga-c630.dts
@@ -376,6 +376,8 @@
clocks = <&sn65dsi86_refclk>;
clock-names = "refclk";
+ no-hpd;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/src/arm64/qcom/sm8150-hdk.dts b/src/arm64/qcom/sm8150-hdk.dts
index fb2cf3d..335aa07 100644
--- a/src/arm64/qcom/sm8150-hdk.dts
+++ b/src/arm64/qcom/sm8150-hdk.dts
@@ -354,22 +354,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&remoteproc_adsp {
diff --git a/src/arm64/qcom/sm8150-microsoft-surface-duo.dts b/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
new file mode 100644
index 0000000..736da9a
--- /dev/null
+++ b/src/arm64/qcom/sm8150-microsoft-surface-duo.dts
@@ -0,0 +1,543 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (C) 2021, Microsoft Corporation
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "sm8150.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+
+/ {
+ model = "Microsoft Surface Duo";
+ compatible = "microsoft,surface-duo", "qcom,sm8150";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8150 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8150-s4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ vol_up {
+ label = "Volume Up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_VOLUMEUP>;
+ };
+ };
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p3>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p0>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ vreg_s5a_2p0: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vdda_wcss_pll:
+ vreg_l1a_0p75: ldo1 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_pdphy:
+ vdda_usb_hs_3p1:
+ vreg_l2a_3p1: ldo2 {
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_usb_hs_core:
+ vdda_csi_0_0p9:
+ vdda_csi_1_0p9:
+ vdda_csi_2_0p9:
+ vdda_csi_3_0p9:
+ vdda_dsi_0_0p9:
+ vdda_dsi_1_0p9:
+ vdda_dsi_0_pll_0p9:
+ vdda_dsi_1_pll_0p9:
+ vdda_pcie_1ln_core:
+ vdda_pcie_2ln_core:
+ vdda_pll_hv_cc_ebi01:
+ vdda_pll_hv_cc_ebi23:
+ vdda_qrefs_0p875_5:
+ vdda_sp_sensor:
+ vdda_ufs_2ln_core_1:
+ vdda_ufs_2ln_core_2:
+ vdda_usb_ss_dp_core_1:
+ vdda_usb_ss_dp_core_2:
+ vdda_qlink_lv:
+ vdda_qlink_lv_ck:
+ vreg_l5a_0p875: ldo5 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_10:
+ vreg_l9a_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p5: ldo10 {
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdd_qfprom:
+ vdd_qfprom_sp:
+ vdda_apc_cs_1p8:
+ vdda_gfx_cs_1p8:
+ vdda_usb_hs_1p8:
+ vdda_qrefs_vref_1p8:
+ vddpx_10_a:
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l13a_2p7: ldo13 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p3>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+ vdd-flash-supply = <&vreg_bob>;
+ vdd-rgb-supply = <&vreg_bob>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_wcss_adcdac_1:
+ vdda_wcss_adcdac_22:
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vdda_hv_ebi0:
+ vdda_hv_ebi1:
+ vdda_hv_ebi2:
+ vdda_hv_ebi3:
+ vdda_hv_refgen0:
+ vdda_qlink_hv_ck:
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_5:
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_6:
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vddpx_2:
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8009-rpmh-regulators {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+
+ vdd-l2-supply = <&vreg_s8c_1p3>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+
+ vreg_l2f_1p2: ldo2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5f_2p85: ldo5 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p85: ldo6 {
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <2856000>;
+ };
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ bq27742@55 {
+ compatible = "ti,bq27742";
+ reg = <0x55>;
+ };
+
+ da7280@4a {
+ compatible = "dlg,da7280";
+ reg = <0x4a>;
+ interrupts-extended = <&tlmm 42 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "da7280_default";
+ pinctrl-0 = <&da7280_intr_default>;
+
+ dlg,actuator-type = "LRA";
+ dlg,dlg,const-op-mode = <1>;
+ dlg,dlg,periodic-op-mode = <1>;
+ dlg,nom-microvolt = <2000000>;
+ dlg,abs-max-microvolt = <2000000>;
+ dlg,imax-microamp = <129000>;
+ dlg,resonant-freq-hz = <180>;
+ dlg,impd-micro-ohms = <14300000>;
+ dlg,freq-track-enable;
+ dlg,bemf-sens-enable;
+ dlg,mem-array = <
+ 0x06 0x08 0x10 0x11 0x12 0x13 0x14 0x15 0x1c 0x2a
+ 0x33 0x3c 0x42 0x4b 0x4c 0x4e 0x17 0x19 0x27 0x29
+ 0x17 0x19 0x03 0x84 0x5e 0x04 0x08 0x84 0x5d 0x01
+ 0x84 0x5e 0x02 0x00 0xa4 0x5d 0x03 0x84 0x5e 0x06
+ 0x08 0x84 0x5d 0x05 0x84 0x5d 0x06 0x84 0x5e 0x08
+ 0x84 0x5e 0x05 0x8c 0x5e 0x24 0x84 0x5f 0x10 0x84
+ 0x5e 0x05 0x84 0x5e 0x08 0x84 0x5f 0x01 0x8c 0x5e
+ 0x04 0x84 0x5e 0x08 0x84 0x5f 0x11 0x19 0x88 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ >;
+ };
+
+ /* SMB1381 @ 0x44 */
+ /* MAX34417 @ 0x1c */
+};
+
+&i2c4 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* SMB1355 @ 0x0c */
+ /* SMB1390 @ 0x10 */
+};
+
+&i2c17 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ bq27742@55 {
+ compatible = "ti,bq27742";
+ reg = <0x55>;
+ };
+};
+
+&i2c19 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* MAX34417 @ 0x12 */
+ /* MAX34417 @ 0x1a */
+ /* MAX34417 @ 0x1e */
+};
+
+&pon {
+ pwrkey {
+ status = "okay";
+ };
+
+ resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&remoteproc_adsp {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/adsp.mdt";
+};
+
+&remoteproc_cdsp {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/cdsp.mdt";
+};
+
+&remoteproc_mpss {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/modem.mdt";
+};
+
+&remoteproc_slpi {
+ status = "okay";
+ firmware-name = "qcom/sm8150/microsoft/slpi.mdt";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <126 4>;
+
+ da7280_intr_default: da7280-intr-default {
+ pins = "gpio42";
+ function = "gpio";
+ bias-pull-up;
+ input-enable;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ status = "okay";
+
+ reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l10a_2p5>;
+ vcc-max-microamp = <750000>;
+ vccq-supply = <&vreg_l9a_1p2>;
+ vccq-max-microamp = <700000>;
+ vccq2-supply = <&vreg_s4a_1p8>;
+ vccq2-max-microamp = <750000>;
+};
+
+&ufs_mem_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
+ vdda-max-microamp = <90200>;
+ vdda-pll-supply = <&vreg_l3c_1p2>;
+ vdda-pll-max-microamp = <19000>;
+};
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vdd_usb_hs_core>;
+ vdda33-supply = <&vdda_usb_hs_3p1>;
+ vdda18-supply = <&vdda_usb_hs_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&wifi {
+ status = "okay";
+
+ vdd-0.8-cx-mx-supply = <&vdda_wcss_pll>;
+ vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
+ vdd-1.3-rfa-supply = <&vdda_wcss_adcdac_1>;
+ vdd-3.3-ch0-supply = <&vreg_l11c_3p3>;
+};
diff --git a/src/arm64/qcom/sm8150-mtp.dts b/src/arm64/qcom/sm8150-mtp.dts
index 3774f8e..53edf75 100644
--- a/src/arm64/qcom/sm8150-mtp.dts
+++ b/src/arm64/qcom/sm8150-mtp.dts
@@ -349,22 +349,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&remoteproc_adsp {
diff --git a/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts b/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts
new file mode 100644
index 0000000..3b55fdd
--- /dev/null
+++ b/src/arm64/qcom/sm8150-sony-xperia-kumano-bahamut.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8150-sony-xperia-kumano.dtsi"
+
+/ {
+ model = "Sony Xperia 5";
+ compatible = "sony,bahamut-generic", "qcom,sm8150";
+};
+
+&framebuffer {
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+};
diff --git a/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts b/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts
new file mode 100644
index 0000000..6f490ec
--- /dev/null
+++ b/src/arm64/qcom/sm8150-sony-xperia-kumano-griffin.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8150-sony-xperia-kumano.dtsi"
+
+/ {
+ model = "Sony Xperia 1";
+ compatible = "sony,griffin-generic", "qcom,sm8150";
+};
diff --git a/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi b/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
new file mode 100644
index 0000000..014fe3a
--- /dev/null
+++ b/src/arm64/qcom/sm8150-sony-xperia-kumano.dtsi
@@ -0,0 +1,452 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8150.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+
+/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &ipa_gsi_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &slpi_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &venus_mem;
+
+/ {
+ qcom,msm-id = <339 0x20000>; /* SM8150 v2 */
+ qcom,board-id = <8 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9c000000 0 0x2300000>;
+ width = <1644>;
+ height = <3840>;
+ stride = <(1644 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's (going to be) a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet (& no dispcc either)..
+ */
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /*
+ * Apparently RPMh does not provide support for PM8150 S4 because it
+ * is always-on; model it as a fixed regulator.
+ */
+ vreg_s4a_1p8: pm8150-s4 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s4a_1p8";
+
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ mpss_mem: memory@8dc00000 {
+ reg = <0x0 0x8dc00000 0x0 0x9600000>;
+ no-map;
+ };
+
+ venus_mem: memory@97200000 {
+ reg = <0x0 0x97200000 0x0 0x500000>;
+ no-map;
+ };
+
+ slpi_mem: memory@97700000 {
+ reg = <0x0 0x97700000 0x0 0x1400000>;
+ no-map;
+ };
+
+ ipa_fw_mem: memory@98b00000 {
+ reg = <0x0 0x98b00000 0x0 0x10000>;
+ no-map;
+ };
+
+ ipa_gsi_mem: memory@98b10000 {
+ reg = <0x0 0x98b10000 0x0 0x5000>;
+ no-map;
+ };
+
+ gpu_mem: memory@98b15000 {
+ reg = <0x0 0x98b15000 0x0 0x2000>;
+ no-map;
+ };
+
+ spss_mem: memory@98c00000 {
+ reg = <0x0 0x98c00000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_mem: memory@98d00000 {
+ reg = <0x0 0x98d00000 0x0 0x1400000>;
+ no-map;
+ };
+
+ cont_splash_mem: memory@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x2400000>;
+ no-map;
+ };
+
+ cdsp_sec_mem: memory@a4c00000 {
+ reg = <0x0 0xa4c00000 0x0 0x3c00000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ msg-size = <0x20000 0x20000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+};
+
+&adsp_mem {
+ reg = <0x0 0x8be00000 0x0 0x1e00000>;
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p9>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p3>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ vreg_s2a_0p6: smps2 {
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <600000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a_1p9: smps5 {
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1a_0p75: ldo1 {
+ regulator-min-microvolt = <752000>;
+ regulator-max-microvolt = <752000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2a_3p1: ldo2 {
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p8: ldo3 {
+ regulator-min-microvolt = <480000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5a_0p875: ldo5 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9a_1p2: ldo9 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10a_2p5: ldo10 {
+ regulator-min-microvolt = <2504000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11a_0p8: ldo11 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L13 is unused. */
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15a_1p7: ldo15 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1704000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l16a_2p7: ldo16 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_0p8: ldo18 {
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <912000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p3>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+
+ vdd-bob-supply = <&vph_pwr>;
+ vdd-flash-supply = <&vreg_bob>;
+ vdd-rgb-supply = <&vreg_bob>;
+
+ vreg_bob: bob {
+ regulator-min-microvolt = <3350000>;
+ regulator-max-microvolt = <4000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ regulator-allow-bypass;
+ };
+
+ vreg_s1c_1p1: smps1 {
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_1p3: smps8 {
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_1p3: ldo2 {
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_1p2: ldo3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_1p8: ldo4 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <2928000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_3p0: ldo7 {
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p3: ldo11 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ /* PM8009 is not present on these boards, even if downstream sources suggest so. */
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* Qcom SMB1355 @ c */
+ /* Qcom SMB1390 @ 10 */
+ /* NXP PN553 NFC @ 28 */
+ /* Qcom FSA4480 USB-C audio switch @ 43 */
+};
+
+&i2c7 {
+ status = "okay";
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c10 {
+ status = "okay";
+
+ /* Samsung touchscreen @ 48 */
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <126 4>;
+};
+
+&uart2 {
+ status = "okay";
+};
+
+/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
+&ufs_mem_hc { status = "disabled"; };
+&ufs_mem_phy { status = "disabled"; };
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vreg_l5a_0p875>;
+ vdda33-supply = <&vreg_l2a_3p1>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l18a_0p8>;
+};
diff --git a/src/arm64/qcom/sm8150.dtsi b/src/arm64/qcom/sm8150.dtsi
index 51235a9..612dda0 100644
--- a/src/arm64/qcom/sm8150.dtsi
+++ b/src/arm64/qcom/sm8150.dtsi
@@ -4,6 +4,7 @@
* Copyright (c) 2019, Linaro Limited
*/
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@@ -577,6 +578,29 @@
<&sleep_clk>;
};
+ gpi_dma0: dma-controller@800000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0x800000 0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x00d6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -695,6 +719,29 @@
};
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0xa00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x0616 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -795,6 +842,29 @@
};
};
+ gpi_dma2: dma-controller@c00000 {
+ compatible = "qcom,sm8150-gpi-dma";
+ reg = <0 0xc00000 0 0x60000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <13>;
+ dma-channel-mask = <0xfa>;
+ iommus = <&apps_smmu 0x07b6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@cc0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00cc0000 0x0 0x6000>;
@@ -1082,6 +1152,8 @@
qcom,gmu = <&gmu>;
+ status = "disabled";
+
zap-shader {
memory-region = <&gpu_mem>;
};
@@ -1149,6 +1221,8 @@
operating-points-v2 = <&gmu_opp_table>;
+ status = "disabled";
+
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -1496,6 +1570,8 @@
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
+ status = "disabled";
+
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
@@ -2268,7 +2344,7 @@
resets = <&gcc GCC_USB30_PRIM_BCR>;
- usb_1_dwc3: dwc3@a600000 {
+ usb_1_dwc3: usb@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/src/arm64/qcom/sm8250-hdk.dts b/src/arm64/qcom/sm8250-hdk.dts
index c3a2c5a..4774281 100644
--- a/src/arm64/qcom/sm8250-hdk.dts
+++ b/src/arm64/qcom/sm8250-hdk.dts
@@ -6,7 +6,6 @@
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include <dt-bindings/gpio/gpio.h>
#include "sm8250.dtsi"
#include "pm8150.dtsi"
#include "pm8150b.dtsi"
@@ -365,22 +364,26 @@
};
};
-&qupv3_id_1 {
+&gmu {
status = "okay";
};
-&pon {
- pwrkey {
- status = "okay";
- };
+&gpu {
+ status = "okay";
+};
- resin {
- compatible = "qcom,pm8941-resin";
- interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
- debounce = <15625>;
- bias-pull-up;
- linux,code = <KEY_VOLUMEDOWN>;
- };
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEDOWN>;
+};
+
+&qupv3_id_1 {
+ status = "okay";
};
&tlmm {
@@ -452,3 +455,7 @@
&usb_2_dwc3 {
dr_mode = "host";
};
+
+&venus {
+ status = "okay";
+};
diff --git a/src/arm64/qcom/sm8250-mtp.dts b/src/arm64/qcom/sm8250-mtp.dts
index cfc4d1f..062b944 100644
--- a/src/arm64/qcom/sm8250-mtp.dts
+++ b/src/arm64/qcom/sm8250-mtp.dts
@@ -465,7 +465,13 @@
firmware-name = "qcom/sm8250/cdsp.mbn";
};
+&gmu {
+ status = "okay";
+};
+
&gpu {
+ status = "okay";
+
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sm8250/a650_zap.mbn";
@@ -691,3 +697,7 @@
vdda-phy-supply = <&vreg_l9a_1p2>;
vdda-pll-supply = <&vreg_l18a_0p9>;
};
+
+&venus {
+ status = "okay";
+};
diff --git a/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts b/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts
new file mode 100644
index 0000000..79afeb0
--- /dev/null
+++ b/src/arm64/qcom/sm8250-sony-xperia-edo-pdx203.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8250-sony-xperia-edo.dtsi"
+
+/ {
+ model = "Sony Xperia 1 II";
+ compatible = "sony,pdx203-generic", "qcom,sm8250";
+};
+
+/delete-node/ &vreg_l7f_1p8;
diff --git a/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts b/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts
new file mode 100644
index 0000000..16c96e8
--- /dev/null
+++ b/src/arm64/qcom/sm8250-sony-xperia-edo-pdx206.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+/dts-v1/;
+
+#include "sm8250-sony-xperia-edo.dtsi"
+
+/ {
+ model = "Sony Xperia 5 II";
+ compatible = "sony,pdx206-generic", "qcom,sm8250";
+};
+
+&framebuffer {
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+};
+
+&gpio_keys {
+ g-assist-key {
+ label = "Google Assistant Key";
+ linux,code = <KEY_LEFTMETA>;
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+};
+
+&vreg_l2f_1p3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+};
diff --git a/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi b/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
new file mode 100644
index 0000000..d63f7a9
--- /dev/null
+++ b/src/arm64/qcom/sm8250-sony-xperia-edo.dtsi
@@ -0,0 +1,636 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "sm8250.dtsi"
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+#include "pm8009.dtsi"
+
+/delete-node/ &adsp_mem;
+/delete-node/ &spss_mem;
+/delete-node/ &cdsp_secure_heap;
+
+/ {
+ qcom,msm-id = <356 0x20001>; /* SM8250 v2.1 */
+ qcom,board-id = <0x10008 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@9c000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x9c000000 0 0x2300000>;
+ width = <1644>;
+ height = <3840>;
+ stride = <(1644 * 4)>;
+ format = "a8r8g8b8";
+ /*
+ * That's a lot of clocks, but it's necessary due
+ * to unused clk cleanup & no panel driver yet..
+ */
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ power-domains = <&dispcc MDSS_GDSC>;
+ };
+ };
+
+ gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+
+ /*
+ * Camera focus (light press) and camera snapshot (full press)
+ * seem not to work properly.. Adding the former one stalls the CPU
+ * and the latter kills the volume down key for whatever reason. In any
+ * case, they are both on &pm8150b_gpios: camera focus(2), camera snapshot(1).
+ */
+
+ vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ /* S6c is really ebi.lvl but it's there for supply map completeness sake. */
+ vreg_s6c_0p88: smpc6-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_s6c_0p88";
+
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-always-on;
+ vin-supply = <&vph_pwr>;
+ };
+
+ reserved-memory {
+ adsp_mem: memory@8a100000 {
+ reg = <0x0 0x8a100000 0x0 0x2500000>;
+ no-map;
+ };
+
+ spss_mem: memory@8c600000 {
+ reg = <0x0 0x8c600000 0x0 0x100000>;
+ no-map;
+ };
+
+ cdsp_secure_heap: memory@8c700000 {
+ reg = <0x0 0x8c700000 0x0 0x4600000>;
+ no-map;
+ };
+
+ cont_splash_mem: memory@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x2300000>;
+ no-map;
+ };
+
+ ramoops@ffc00000 {
+ compatible = "ramoops";
+ reg = <0x0 0xffc00000 0x0 0x100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ msg-size = <0x20000 0x20000>;
+ ecc-size = <16>;
+ no-map;
+ };
+ };
+};
+
+&adsp {
+ status = "okay";
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l1-l8-l11-supply = <&vreg_s6c_0p88>;
+ vdd-l2-l10-supply = <&vreg_bob>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s6a_0p6>;
+ vdd-l6-l9-supply = <&vreg_s8c_1p2>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p9>;
+ vdd-l13-l16-l17-supply = <&vreg_bob>;
+
+ /* (S1+S2+S3) - cx.lvl (ARC) */
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5a_1p9: smps5 {
+ regulator-name = "vreg_s5a_1p9";
+ regulator-min-microvolt = <1824000>;
+ regulator-max-microvolt = <2040000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6a_0p6: smps6 {
+ regulator-name = "vreg_s6a_0p6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1128000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2a_3p1: ldo2 {
+ regulator-name = "vreg_l2a_3p1";
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3a_0p9: ldo3 {
+ regulator-name = "vreg_l3a_0p9";
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <932000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L4 - lmx.lvl (ARC) */
+
+ vreg_l5a_0p88: ldo5 {
+ regulator-name = "vreg_l5a_0p88";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6a_1p2: ldo6 {
+ regulator-name = "vreg_l6a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L7 is unused. */
+
+ vreg_l9a_1p2: ldo9 {
+ regulator-name = "vreg_l9a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L10 is unused, L11 - lcx.lvl (ARC) */
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L13 is unused. */
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L15 & L16 are unused. */
+
+ vreg_l17a_3p0: ldo17 {
+ regulator-name = "vreg_l17a_3p0";
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3008000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18a_0p9: ldo18 {
+ regulator-name = "vreg_l18a_0p9";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ /*
+ * Remaining regulators that are not yet supported:
+ * OLEDB: 4925000-8100000
+ * ab: 4600000-6100000
+ * ibb: 800000-5400000
+ */
+ pm8150l-rpmh-regulators {
+ compatible = "qcom,pm8150l-rpmh-regulators";
+ qcom,pmic-id = "c";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-l1-l8-supply = <&vreg_s4a_1p8>;
+ vdd-l2-l3-supply = <&vreg_s8c_1p2>;
+ vdd-l4-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-l11-supply = <&vreg_bob>;
+ vdd-l9-l10-supply = <&vreg_bob>;
+ vdd-bob-supply = <&vph_pwr>;
+
+ vreg_bob: bob {
+ regulator-name = "vreg_bob";
+ regulator-min-microvolt = <3350000>;
+ regulator-max-microvolt = <3960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ /*
+ * S1-S6 are ARCs:
+ * (S1+S2) - gfx.lvl,
+ * S3 - mx.lvl,
+ * (S4+S5) - mmcx.lvl,
+ * S6 - ebi.lvl
+ */
+
+ vreg_s7c_0p35: smps7 {
+ regulator-name = "vreg_s7c_0p35";
+ regulator-min-microvolt = <348000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_1p2: smps8 {
+ regulator-name = "vreg_s8c_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1c_1p8: ldo1 {
+ regulator-name = "vreg_l1c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L2-4 are unused. */
+
+ vreg_l5c_1p8: ldo5 {
+ regulator-name = "vreg_l5c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6c_2p9: ldo6 {
+ regulator-name = "vreg_l6c_2p9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l7c_2p85: ldo7 {
+ regulator-name = "vreg_l7c_2p85";
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8c_1p8: ldo8 {
+ regulator-name = "vreg_l8c_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9c_2p9: ldo9 {
+ regulator-name = "vreg_l9c_2p9";
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ };
+
+ vreg_l10c_3p3: ldo10 {
+ regulator-name = "vreg_l10c_3p3";
+ regulator-min-microvolt = <3296000>;
+ regulator-max-microvolt = <3296000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11c_3p0: ldo11 {
+ regulator-name = "vreg_l11c_3p0";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ pm8009-rpmh-regulators {
+ compatible = "qcom,pm8009-rpmh-regulators";
+ qcom,pmic-id = "f";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vreg_bob>;
+ vdd-l2-supply = <&vreg_s8c_1p2>;
+ vdd-l5-l6-supply = <&vreg_bob>;
+ vdd-l7-supply = <&vreg_s4a_1p8>;
+
+ vreg_s1f_1p2: smps1 {
+ regulator-name = "vreg_s1f_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s2f_0p5: smps2 {
+ regulator-name = "vreg_s2f_0p5";
+ regulator-min-microvolt = <512000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L1 is unused. */
+
+ vreg_l2f_1p3: ldo2 {
+ regulator-name = "vreg_l2f_1p3";
+ regulator-min-microvolt = <1304000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ /* L3 & L4 are unused. */
+
+ vreg_l5f_2p8: ldo5 {
+ regulator-name = "vreg_l5f_2p85";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l6f_2p8: ldo6 {
+ regulator-name = "vreg_l6f_2p8";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7f_1p8: ldo7 {
+ regulator-name = "vreg_l7f_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
+
+&cdsp {
+ status = "okay";
+};
+
+&gpi_dma0 {
+ status = "okay";
+};
+
+&gpi_dma1 {
+ status = "okay";
+};
+
+&gpi_dma2 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* NXP PN553 NFC @ 28 */
+};
+
+&i2c2 {
+ status = "okay";
+ clock-frequency = <1000000>;
+
+ /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */
+};
+
+&i2c5 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Dialog SLG51000 CMIC @ 75 */
+};
+
+&i2c9 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* AMS TCS3490 RGB+IR color sensor @ 72 */
+};
+
+&i2c13 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ touchscreen@48 {
+ compatible = "samsung,s6sy761";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ /* It's "vddio" downstream but it works anyway! */
+ vdd-supply = <&vreg_l1c_1p8>;
+ avdd-supply = <&vreg_l10c_3p3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&ts_int_default>;
+ };
+};
+
+&i2c15 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Qcom SMB1390 @ 10 */
+ /* Silicon Labs SI4704 FM Radio Receiver @ 11 */
+ /* Qcom SMB1390_slave @ 18 */
+ /* HALO HL6111R Qi charger @ 25 */
+ /* Richwave RTC6226 FM Radio Receiver @ 64 */
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie0_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+};
+
+&pcie2 {
+ status = "okay";
+
+ pinctrl-0 = <&pcie2_default_state &mdm2ap_default &ap2mdm_default>;
+};
+
+&pcie2_phy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l5a_0p88>;
+ vdda-pll-supply = <&vreg_l9a_1p2>;
+};
+
+&pon_pwrkey {
+ status = "okay";
+};
+
+&pon_resin {
+ status = "okay";
+
+ linux,code = <KEY_VOLUMEUP>;
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&qupv3_id_1 {
+ status = "okay";
+};
+
+&qupv3_id_2 {
+ status = "okay";
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sdc2_default_state &sdc2_card_det_n>;
+ pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_n>;
+ vmmc-supply = <&vreg_l9c_2p9>;
+ vqmmc-supply = <&vreg_l6c_2p9>;
+ bus-width = <4>;
+ no-sdio;
+ no-emmc;
+};
+
+&slpi {
+ status = "okay";
+};
+
+&tlmm {
+ gpio-reserved-ranges = <40 4>, <52 4>;
+
+ sdc2_default_state: sdc2-default {
+ clk {
+ pins = "sdc2_clk";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ data {
+ pins = "sdc2_data";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ mdm2ap_default: mdm2ap-default {
+ pins = "gpio1", "gpio3";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ ts_int_default: ts-int-default {
+ pins = "gpio39";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disabled;
+ input-enable;
+ };
+
+ ap2mdm_default: ap2mdm-default {
+ pins = "gpio56", "gpio57";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
+
+ sdc2_card_det_n: sd-card-det-n {
+ pins = "gpio77";
+ function = "gpio";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+};
+
+&uart12 {
+ status = "okay";
+};
+
+/* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */
+&ufs_mem_hc { status = "disabled"; };
+&ufs_mem_phy { status = "disabled"; };
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+
+ vdda-pll-supply = <&vreg_l5a_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l2a_3p1>;
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+
+ vdda-phy-supply = <&vreg_l9a_1p2>;
+ vdda-pll-supply = <&vreg_l18a_0p9>;
+};
diff --git a/src/arm64/qcom/sm8250.dtsi b/src/arm64/qcom/sm8250.dtsi
index 4c0de12..4798368 100644
--- a/src/arm64/qcom/sm8250.dtsi
+++ b/src/arm64/qcom/sm8250.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
#include <dt-bindings/clock/qcom,gpucc-sm8250.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8250.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -519,6 +521,26 @@
};
};
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00800000 0 0x70000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x76 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -714,6 +736,29 @@
};
};
+ gpi_dma0: dma-controller@900000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00900000 0 0x70000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <15>;
+ dma-channel-mask = <0x7ff>;
+ iommus = <&apps_smmu 0x5b6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
@@ -961,6 +1006,26 @@
};
};
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8250-gpi-dma";
+ reg = <0 0x00a00000 0 0x70000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <10>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x56 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
@@ -1249,6 +1314,12 @@
phys = <&pcie0_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_default_state>;
+
status = "disabled";
};
@@ -1347,6 +1418,12 @@
phys = <&pcie1_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_default_state>;
+
status = "disabled";
};
@@ -1447,6 +1524,12 @@
phys = <&pcie2_lane>;
phy-names = "pciephy";
+ perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
+ enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_default_state>;
+
status = "disabled";
};
@@ -1470,7 +1553,7 @@
status = "disabled";
- pcie2_lane: lanes@1c0e200 {
+ pcie2_lane: lanes@1c16200 {
reg = <0 0x1c16200 0 0x170>, /* tx0 */
<0 0x1c16400 0 0x200>, /* rx0 */
<0 0x1c16a00 0 0x1f0>, /* pcs */
@@ -1746,6 +1829,8 @@
qcom,gmu = <&gmu>;
+ status = "disabled";
+
zap-shader {
memory-region = <&gpu_mem>;
};
@@ -1819,6 +1904,8 @@
operating-points-v2 = <&gmu_opp_table>;
+ status = "disabled";
+
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
@@ -2323,6 +2410,8 @@
<&videocc VIDEO_CC_MVS0C_CLK_ARES>;
reset-names = "bus", "core";
+ status = "disabled";
+
video-decoder {
compatible = "venus-decoder";
};
@@ -2370,7 +2459,7 @@
};
mdss: mdss@ae00000 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
@@ -2402,7 +2491,7 @@
ranges;
mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2424,8 +2513,6 @@
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
-
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2499,6 +2586,9 @@
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -2566,6 +2656,9 @@
status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -3395,6 +3488,95 @@
output-high;
};
};
+
+ sdc2_sleep_state: sdc2-sleep {
+ clk {
+ pins = "sdc2_clk";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ cmd {
+ pins = "sdc2_cmd";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ data {
+ pins = "sdc2_data";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_default_state: pcie0-default {
+ perst {
+ pins = "gpio79";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio80";
+ function = "pci_e0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio81";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_default_state: pcie1-default {
+ perst {
+ pins = "gpio82";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio83";
+ function = "pci_e1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio84";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie2_default_state: pcie2-default {
+ perst {
+ pins = "gpio85";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ clkreq {
+ pins = "gpio86";
+ function = "pci_e2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ wake {
+ pins = "gpio87";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
apps_smmu: iommu@15000000 {
diff --git a/src/arm64/qcom/sm8350-mtp.dts b/src/arm64/qcom/sm8350-mtp.dts
index 6ca638b..9374044 100644
--- a/src/arm64/qcom/sm8350-mtp.dts
+++ b/src/arm64/qcom/sm8350-mtp.dts
@@ -364,3 +364,9 @@
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l5b_0p88>;
};
+
+&ipa {
+ status = "okay";
+
+ memory-region = <&pil_ipa_fw_mem>;
+};
diff --git a/src/arm64/qcom/sm8350.dtsi b/src/arm64/qcom/sm8350.dtsi
index ed0b51b..0d16392 100644
--- a/src/arm64/qcom/sm8350.dtsi
+++ b/src/arm64/qcom/sm8350.dtsi
@@ -6,11 +6,13 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/interconnect/qcom,sm8350.h>
/ {
interrupt-parent = <&intc>;
@@ -391,6 +393,17 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ ipa_smp2p_out: ipa-ap-to-modem {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ ipa_smp2p_in: ipa-modem-to-ap {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
smp2p-slpi {
@@ -629,6 +642,45 @@
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ipa: ipa@1e40000 {
+ compatible = "qcom,sm8350-ipa";
+
+ iommus = <&apps_smmu 0x5c0 0x0>,
+ <&apps_smmu 0x5c2 0x0>;
+ reg = <0 0x1e40000 0 0x8000>,
+ <0 0x1e50000 0 0x4b20>,
+ <0 0x1e04000 0 0x23000>;
+ reg-names = "ipa-reg",
+ "ipa-shared",
+ "gsi";
+
+ interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
+ <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ipa",
+ "gsi",
+ "ipa-clock-query",
+ "ipa-setup-ready";
+
+ clocks = <&rpmhcc RPMH_IPA_CLK>;
+ clock-names = "core";
+
+ interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
+ <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
+ interconnect-names = "ipa_to_llcc",
+ "llcc_to_ebi1",
+ "appss_to_ipa";
+
+ qcom,smem-states = <&ipa_smp2p_out 0>,
+ <&ipa_smp2p_out 1>;
+ qcom,smem-state-names = "ipa-clock-enabled-valid",
+ "ipa-clock-enabled";
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -656,7 +708,7 @@
<&rpmhpd 12>;
power-domain-names = "load_state", "cx", "mss";
- interconnects = <&mc_virt 0 &mc_virt 1>;
+ interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_modem_mem>;
@@ -689,7 +741,7 @@
interrupt-controller;
};
- tsens0: thermal-sensor@c222000 {
+ tsens0: thermal-sensor@c263000 {
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
reg = <0 0x0c263000 0 0x1ff>, /* TM */
<0 0x0c222000 0 0x8>; /* SROT */
@@ -700,7 +752,7 @@
#thermal-sensor-cells = <1>;
};
- tsens1: thermal-sensor@c223000 {
+ tsens1: thermal-sensor@c265000 {
compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
reg = <0 0x0c265000 0 0x1ff>, /* TM */
<0 0x0c223000 0 0x8>; /* SROT */
@@ -1063,7 +1115,7 @@
<&rpmhpd 10>;
power-domain-names = "load_state", "cx", "mxc";
- interconnects = <&compute_noc 1 &mc_virt 1>;
+ interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>;
memory-region = <&pil_cdsp_mem>;
@@ -1176,7 +1228,7 @@
};
};
- dc_noc: interconnect@90e0000 {
+ dc_noc: interconnect@90c0000 {
compatible = "qcom,sm8350-dc-noc";
reg = <0 0x090c0000 0 0x4200>;
#interconnect-cells = <1>;
@@ -1317,7 +1369,7 @@
};
};
- thermal-zones {
+ thermal_zones: thermal-zones {
cpu0-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
diff --git a/src/arm64/renesas/beacon-renesom-baseboard.dtsi b/src/arm64/renesas/beacon-renesom-baseboard.dtsi
index d8046fe..e3c8b2f 100644
--- a/src/arm64/renesas/beacon-renesom-baseboard.dtsi
+++ b/src/arm64/renesas/beacon-renesom-baseboard.dtsi
@@ -271,12 +271,12 @@
&ehci0 {
dr_mode = "otg";
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&ehci1 {
status = "okay";
- clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, <&usb2_clksel>, <&versaclock5 3>;
};
&hdmi0 {
diff --git a/src/arm64/renesas/beacon-renesom-som.dtsi b/src/arm64/renesas/beacon-renesom-som.dtsi
index 8d3a4d6..090dc9c 100644
--- a/src/arm64/renesas/beacon-renesom-som.dtsi
+++ b/src/arm64/renesas/beacon-renesom-som.dtsi
@@ -53,6 +53,8 @@
phy-handle = <&phy0>;
rx-internal-delay-ps = <1800>;
tx-internal-delay-ps = <2000>;
+ clocks = <&cpg CPG_MOD 812>, <&versaclock5 4>;
+ clock-names = "fck", "refclk";
status = "okay";
phy0: ethernet-phy@0 {
@@ -319,8 +321,10 @@
status = "okay";
};
-&usb_extal_clk {
- clock-frequency = <50000000>;
+&usb2_clksel {
+ clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>,
+ <&versaclock5 3>, <&usb3s0_clk>;
+ status = "okay";
};
&usb3s0_clk {
diff --git a/src/arm64/renesas/r8a774a1.dtsi b/src/arm64/renesas/r8a774a1.dtsi
index 46f8dbf..78c121a 100644
--- a/src/arm64/renesas/r8a774a1.dtsi
+++ b/src/arm64/renesas/r8a774a1.dtsi
@@ -76,6 +76,7 @@
opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <820000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
};
@@ -1127,6 +1128,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a774b1.dtsi b/src/arm64/renesas/r8a774b1.dtsi
index d16a4be..28c612c 100644
--- a/src/arm64/renesas/r8a774b1.dtsi
+++ b/src/arm64/renesas/r8a774b1.dtsi
@@ -1001,6 +1001,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a774c0.dtsi b/src/arm64/renesas/r8a774c0.dtsi
index 1aef344..a5d4dce 100644
--- a/src/arm64/renesas/r8a774c0.dtsi
+++ b/src/arm64/renesas/r8a774c0.dtsi
@@ -957,6 +957,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a774e1.dtsi b/src/arm64/renesas/r8a774e1.dtsi
index 1f51237..379a130 100644
--- a/src/arm64/renesas/r8a774e1.dtsi
+++ b/src/arm64/renesas/r8a774e1.dtsi
@@ -1230,6 +1230,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77951.dtsi b/src/arm64/renesas/r8a77951.dtsi
index 85d66d1..2e4c18b 100644
--- a/src/arm64/renesas/r8a77951.dtsi
+++ b/src/arm64/renesas/r8a77951.dtsi
@@ -1312,6 +1312,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77960.dtsi b/src/arm64/renesas/r8a77960.dtsi
index 12476e3..2bd8169 100644
--- a/src/arm64/renesas/r8a77960.dtsi
+++ b/src/arm64/renesas/r8a77960.dtsi
@@ -63,18 +63,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@@ -1188,6 +1189,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77961.dtsi b/src/arm64/renesas/r8a77961.dtsi
index d980476..91b501e 100644
--- a/src/arm64/renesas/r8a77961.dtsi
+++ b/src/arm64/renesas/r8a77961.dtsi
@@ -52,18 +52,19 @@
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <820000>;
+ opp-microvolt = <830000>;
clock-latency-ns = <300000>;
+ opp-suspend;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
@@ -559,10 +560,19 @@
};
intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77961", "renesas,irqc";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0 0xe61c0000 0 0x200>;
- /* placeholder */
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
};
tmu0: timer@e61e0000 {
@@ -1144,6 +1154,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77965.dtsi b/src/arm64/renesas/r8a77965.dtsi
index dcb9df8..ad69da3 100644
--- a/src/arm64/renesas/r8a77965.dtsi
+++ b/src/arm64/renesas/r8a77965.dtsi
@@ -1050,6 +1050,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77970-eagle.dts b/src/arm64/renesas/r8a77970-eagle.dts
index 874a7fc..5c84681 100644
--- a/src/arm64/renesas/r8a77970-eagle.dts
+++ b/src/arm64/renesas/r8a77970-eagle.dts
@@ -73,6 +73,12 @@
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x38000000>;
};
+
+ x1_clk: x1-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <148500000>;
+ };
};
&avb {
@@ -104,6 +110,8 @@
};
&du {
+ clocks = <&cpg CPG_MOD 724>, <&x1_clk>;
+ clock-names = "du.0", "dclkin.0";
status = "okay";
};
diff --git a/src/arm64/renesas/r8a77970-v3msk.dts b/src/arm64/renesas/r8a77970-v3msk.dts
index 7417cf5..2426e53 100644
--- a/src/arm64/renesas/r8a77970-v3msk.dts
+++ b/src/arm64/renesas/r8a77970-v3msk.dts
@@ -59,7 +59,7 @@
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
- reg = <0x0 0x48000000 0x0 0x38000000>;
+ reg = <0x0 0x48000000 0x0 0x78000000>;
};
osc5_clk: osc5-clock {
diff --git a/src/arm64/renesas/r8a77970.dtsi b/src/arm64/renesas/r8a77970.dtsi
index e8f6352..517892c 100644
--- a/src/arm64/renesas/r8a77970.dtsi
+++ b/src/arm64/renesas/r8a77970.dtsi
@@ -612,6 +612,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77980-condor.dts b/src/arm64/renesas/r8a77980-condor.dts
index 04d47c0..7bde0a5 100644
--- a/src/arm64/renesas/r8a77980-condor.dts
+++ b/src/arm64/renesas/r8a77980-condor.dts
@@ -210,7 +210,7 @@
&mmc0 {
pinctrl-0 = <&mmc_pins>;
- pinctrl-1 = <&mmc_pins_uhs>;
+ pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
@@ -255,12 +255,6 @@
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
- power-source = <3300>;
- };
-
- mmc_pins_uhs: mmc_uhs {
- groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
- function = "mmc";
power-source = <1800>;
};
diff --git a/src/arm64/renesas/r8a77980.dtsi b/src/arm64/renesas/r8a77980.dtsi
index 7b51d46..6347d15 100644
--- a/src/arm64/renesas/r8a77980.dtsi
+++ b/src/arm64/renesas/r8a77980.dtsi
@@ -664,6 +664,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77990.dtsi b/src/arm64/renesas/r8a77990.dtsi
index 0eaea58..4d0304b 100644
--- a/src/arm64/renesas/r8a77990.dtsi
+++ b/src/arm64/renesas/r8a77990.dtsi
@@ -1000,6 +1000,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a77995.dtsi b/src/arm64/renesas/r8a77995.dtsi
index 2319271..84dba37 100644
--- a/src/arm64/renesas/r8a77995.dtsi
+++ b/src/arm64/renesas/r8a77995.dtsi
@@ -760,6 +760,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 812>;
+ clock-names = "fck";
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
resets = <&cpg 812>;
phy-mode = "rgmii";
diff --git a/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi b/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi
index 14d3db5..f791c76 100644
--- a/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi
+++ b/src/arm64/renesas/r8a779a0-falcon-csi-dsi.dtsi
@@ -6,6 +6,27 @@
*/
&i2c0 {
+ pca9654_a: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_b: gpio@22 {
+ compatible = "onnn,pca9654";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_c: gpio@23 {
+ compatible = "onnn,pca9654";
+ reg = <0x23>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
diff --git a/src/arm64/renesas/r8a779a0.dtsi b/src/arm64/renesas/r8a779a0.dtsi
index 70b3604..78ca75f 100644
--- a/src/arm64/renesas/r8a779a0.dtsi
+++ b/src/arm64/renesas/r8a779a0.dtsi
@@ -618,6 +618,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 211>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 211>;
phy-mode = "rgmii";
@@ -665,6 +666,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 212>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 212>;
phy-mode = "rgmii";
@@ -712,6 +714,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 213>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 213>;
phy-mode = "rgmii";
@@ -759,6 +762,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 214>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 214>;
phy-mode = "rgmii";
@@ -806,6 +810,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 215>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 215>;
phy-mode = "rgmii";
@@ -853,6 +858,7 @@
"ch20", "ch21", "ch22", "ch23",
"ch24";
clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 216>;
phy-mode = "rgmii";
@@ -1096,7 +1102,6 @@
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
};
fcpvd0: fcp@fea10000 {
diff --git a/src/arm64/renesas/r9a07g044.dtsi b/src/arm64/renesas/r9a07g044.dtsi
new file mode 100644
index 0000000..734c8ad
--- /dev/null
+++ b/src/arm64/renesas/r9a07g044.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a07g044-cpg.h>
+
+/ {
+ compatible = "renesas,r9a07g044";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x40000>;
+ };
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@1004b800 {
+ compatible = "renesas,scif-r9a07g044";
+ reg = <0 0x1004b800 0 0x400>;
+ interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A07G044_CLK_SCIF0>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_CLK_SCIF0>;
+ status = "disabled";
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a07g044-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a07g044-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@11900000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0x11900000 0 0x40000>,
+ <0x0 0x11940000 0 0x60000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/src/arm64/renesas/r9a07g044l1.dtsi b/src/arm64/renesas/r9a07g044l1.dtsi
new file mode 100644
index 0000000..9d89d45
--- /dev/null
+++ b/src/arm64/renesas/r9a07g044l1.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L R9A07G044L1 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044l1", "renesas,r9a07g044";
+
+ cpus {
+ /delete-node/ cpu-map;
+ /delete-node/ cpu@100;
+ };
+
+ timer {
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/src/arm64/renesas/r9a07g044l2-smarc.dts b/src/arm64/renesas/r9a07g044l2-smarc.dts
new file mode 100644
index 0000000..d3f72ec
--- /dev/null
+++ b/src/arm64/renesas/r9a07g044l2-smarc.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK board
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044l2.dtsi"
+#include "rzg2l-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g044l2";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g044l2", "renesas,r9a07g044";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
diff --git a/src/arm64/renesas/r9a07g044l2.dtsi b/src/arm64/renesas/r9a07g044l2.dtsi
new file mode 100644
index 0000000..91dc10b
--- /dev/null
+++ b/src/arm64/renesas/r9a07g044l2.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L R9A07G044L2 SoC specific parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a07g044.dtsi"
+
+/ {
+ compatible = "renesas,r9a07g044l2", "renesas,r9a07g044";
+};
diff --git a/src/arm64/renesas/rzg2l-smarc.dtsi b/src/arm64/renesas/rzg2l-smarc.dtsi
new file mode 100644
index 0000000..adcd4f5
--- /dev/null
+++ b/src/arm64/renesas/rzg2l-smarc.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L SMARC EVK common parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
+
+&scif0 {
+ status = "okay";
+};
diff --git a/src/arm64/rockchip/px30.dtsi b/src/arm64/rockchip/px30.dtsi
index 09baa8a..248ebb6 100644
--- a/src/arm64/rockchip/px30.dtsi
+++ b/src/arm64/rockchip/px30.dtsi
@@ -244,28 +244,31 @@
#size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */
- pd_usb@PX30_PD_USB {
+ power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
+ #power-domain-cells = <0>;
};
- pd_sdcard@PX30_PD_SDCARD {
+ power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@PX30_PD_GMAC {
+ power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>,
<&cru SCLK_MAC_REF>,
<&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_mmc_nand@PX30_PD_MMC_NAND {
+ power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
@@ -277,15 +280,17 @@
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
+ #power-domain-cells = <0>;
};
- pd_vpu@PX30_PD_VPU {
+ power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
+ #power-domain-cells = <0>;
};
- pd_vo@PX30_PD_VO {
+ power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>,
@@ -300,8 +305,9 @@
<&cru SCLK_VOPB_PWM>;
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>;
+ #power-domain-cells = <0>;
};
- pd_vi@PX30_PD_VI {
+ power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>,
@@ -311,11 +317,13 @@
pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
<&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>;
+ #power-domain-cells = <0>;
};
- pd_gpu@PX30_PD_GPU {
+ power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
};
};
@@ -814,7 +822,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,px30-usb2phy";
reg = <0x100 0x20>;
clocks = <&pmucru SCLK_USBPHY_REF>;
@@ -1087,7 +1095,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff460f00 0x0 0x100>;
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopb_mmu";
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
@@ -1128,7 +1135,6 @@
compatible = "rockchip,iommu";
reg = <0x0 0xff470f00 0x0 0x100>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vopl_mmu";
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
clock-names = "aclk", "iface";
power-domains = <&power PX30_PD_VO>;
diff --git a/src/arm64/rockchip/rk3308-roc-cc.dts b/src/arm64/rockchip/rk3308-roc-cc.dts
index 3dddd47..665b2e6 100644
--- a/src/arm64/rockchip/rk3308-roc-cc.dts
+++ b/src/arm64/rockchip/rk3308-roc-cc.dts
@@ -84,8 +84,8 @@
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x0
- 3300000 0x1>;
+ states = <1800000 0x0>,
+ <3300000 0x1>;
vin-supply = <&vcc5v0_sys>;
};
diff --git a/src/arm64/rockchip/rk3308.dtsi b/src/arm64/rockchip/rk3308.dtsi
index 0c5fa98..a185901 100644
--- a/src/arm64/rockchip/rk3308.dtsi
+++ b/src/arm64/rockchip/rk3308.dtsi
@@ -164,7 +164,7 @@
grf: grf@ff000000 {
compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
- reg = <0x0 0xff000000 0x0 0x10000>;
+ reg = <0x0 0xff000000 0x0 0x08000>;
reboot-mode {
compatible = "syscon-reboot-mode";
@@ -177,6 +177,42 @@
};
};
+ usb2phy_grf: syscon@ff008000 {
+ compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff008000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u2phy: usb2phy@100 {
+ compatible = "rockchip,rk3308-usb2phy";
+ reg = <0x100 0x10>;
+ assigned-clocks = <&cru USB480M>;
+ assigned-clock-parents = <&u2phy>;
+ clocks = <&cru SCLK_USBPHY_REF>;
+ clock-names = "phyclk";
+ clock-output-names = "usb480m_phy";
+ #clock-cells = <0>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
detect_grf: syscon@ff00b000 {
compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
reg = <0x0 0xff00b000 0x0 0x1000>;
@@ -579,6 +615,42 @@
status = "disabled";
};
+ usb20_otg: usb@ff400000 {
+ compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb",
+ "snps,dwc2";
+ reg = <0x0 0xff400000 0x0 0x40000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_OTG>;
+ clock-names = "otg";
+ dr_mode = "otg";
+ g-np-tx-fifo-size = <16>;
+ g-rx-fifo-size = <280>;
+ g-tx-fifo-size = <256 128 128 64 32 16>;
+ phys = <&u2phy_otg>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host_ehci: usb@ff440000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff440000 0x0 0x10000>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ usb_host_ohci: usb@ff450000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff450000 0x0 0x10000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>;
+ phys = <&u2phy_host>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
sdmmc: mmc@ff480000 {
compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xff480000 0x0 0x4000>;
@@ -637,6 +709,28 @@
status = "disabled";
};
+ gmac: ethernet@ff4e0000 {
+ compatible = "rockchip,rk3308-gmac";
+ reg = <0x0 0xff4e0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>,
+ <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>,
+ <&cru SCLK_MAC>, <&cru ACLK_MAC>,
+ <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "clk_mac_refout", "aclk_mac",
+ "pclk_mac", "clk_mac_speed";
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
+ resets = <&cru SRST_MAC_A>;
+ reset-names = "stmmaceth";
+ rockchip,grf = <&grf>;
+ status = "disabled";
+ };
+
cru: clock-controller@ff500000 {
compatible = "rockchip,rk3308-cru";
reg = <0x0 0xff500000 0x0 0x1000>;
diff --git a/src/arm64/rockchip/rk3326-odroid-go2.dts b/src/arm64/rockchip/rk3326-odroid-go2.dts
index 49c97f7..7fc674a 100644
--- a/src/arm64/rockchip/rk3326-odroid-go2.dts
+++ b/src/arm64/rockchip/rk3326-odroid-go2.dts
@@ -165,6 +165,31 @@
};
};
+ rk817-sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "Analog";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Headphone", "Headphones",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MICL", "Mic Jack",
+ "Headphones", "HPOL",
+ "Headphones", "HPOR",
+ "Speaker", "SPKO";
+
+ simple-audio-card,codec {
+ sound-dai = <&rk817>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&i2s1_2ch>;
+ };
+ };
+
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vcc3v8_sys";
@@ -239,6 +264,7 @@
backlight = <&backlight>;
iovcc-supply = <&vcc_lcd>;
reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ rotation = <270>;
vdd-supply = <&vcc_lcd>;
port {
@@ -269,11 +295,14 @@
reg = <0x20>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "xin32k";
+ clock-names = "mclk";
+ clocks = <&cru SCLK_I2S1_OUT>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
wakeup-source;
#clock-cells = <1>;
- clock-output-names = "rk808-clkout1", "xin32k";
+ #sound-dai-cells = <0>;
vcc1-supply = <&vccsys>;
vcc2-supply = <&vccsys>;
@@ -432,6 +461,10 @@
};
};
};
+
+ rk817_codec: codec {
+ rockchip,mic-in-differential;
+ };
};
};
diff --git a/src/arm64/rockchip/rk3328-nanopi-r2s.dts b/src/arm64/rockchip/rk3328-nanopi-r2s.dts
index f807bc0..3857d48 100644
--- a/src/arm64/rockchip/rk3328-nanopi-r2s.dts
+++ b/src/arm64/rockchip/rk3328-nanopi-r2s.dts
@@ -14,6 +14,7 @@
compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
aliases {
+ ethernet1 = &rtl8153;
mmc0 = &sdmmc;
};
@@ -76,8 +77,8 @@
regulator-settling-time-us = <5000>;
regulator-type = "voltage";
startup-delay-us = <2000>;
- states = <1800000 0x1
- 3300000 0x0>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
vin-supply = <&vcc_io_33>;
};
@@ -101,6 +102,18 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
+
+ vdd_5v_lan: vdd-5v-lan {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&lan_vdd_pin>;
+ pinctrl-names = "default";
+ regulator-name = "vdd_5v_lan";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vdd_5v>;
+ };
};
&cpu0 {
@@ -309,6 +322,12 @@
};
};
+ lan {
+ lan_vdd_pin: lan-vdd-pin {
+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -368,6 +387,19 @@
dr_mode = "host";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Second port is for USB 3.0 */
+ rtl8153: device@2 {
+ compatible = "usbbda,8153";
+ reg = <2>;
+ };
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/src/arm64/rockchip/rk3328-roc-cc.dts b/src/arm64/rockchip/rk3328-roc-cc.dts
index a05732b..aa22a0c 100644
--- a/src/arm64/rockchip/rk3328-roc-cc.dts
+++ b/src/arm64/rockchip/rk3328-roc-cc.dts
@@ -50,8 +50,8 @@
vcc_sdio: sdmmcio-regulator {
compatible = "regulator-gpio";
gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1
- 3300000 0x0>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
regulator-name = "vcc_sdio";
regulator-type = "voltage";
regulator-min-microvolt = <1800000>;
@@ -363,6 +363,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/src/arm64/rockchip/rk3328-rock-pi-e.dts b/src/arm64/rockchip/rk3328-rock-pi-e.dts
index c7e31ef..018a3a5 100644
--- a/src/arm64/rockchip/rk3328-rock-pi-e.dts
+++ b/src/arm64/rockchip/rk3328-rock-pi-e.dts
@@ -177,8 +177,6 @@
};
&gmac2phy {
- pinctrl-names = "default";
- pinctrl-0 = <&fephyled_linkm1>, <&fephyled_rxm1>;
status = "okay";
};
@@ -382,6 +380,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/src/arm64/rockchip/rk3328-rock64.dts b/src/arm64/rockchip/rk3328-rock64.dts
index 3bef1f3..1b0f7e4 100644
--- a/src/arm64/rockchip/rk3328-rock64.dts
+++ b/src/arm64/rockchip/rk3328-rock64.dts
@@ -381,6 +381,11 @@
status = "okay";
};
+&usbdrd3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&usb_host0_ehci {
status = "okay";
};
diff --git a/src/arm64/rockchip/rk3328.dtsi b/src/arm64/rockchip/rk3328.dtsi
index 3ed69ec..8c821ac 100644
--- a/src/arm64/rockchip/rk3328.dtsi
+++ b/src/arm64/rockchip/rk3328.dtsi
@@ -288,7 +288,7 @@
status = "disabled";
};
- grf_gpio: grf-gpio {
+ grf_gpio: gpio {
compatible = "rockchip,rk3328-grf-gpio";
gpio-controller;
#gpio-cells = <2>;
@@ -300,15 +300,18 @@
#address-cells = <1>;
#size-cells = <0>;
- pd_hevc@RK3328_PD_HEVC {
+ power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>;
+ #power-domain-cells = <0>;
};
- pd_video@RK3328_PD_VIDEO {
+ power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>;
+ #power-domain-cells = <0>;
};
- pd_vpu@RK3328_PD_VPU {
+ power-domain@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ #power-domain-cells = <0>;
};
};
@@ -816,7 +819,7 @@
#address-cells = <1>;
#size-cells = <1>;
- u2phy: usb2-phy@100 {
+ u2phy: usb2phy@100 {
compatible = "rockchip,rk3328-usb2phy";
reg = <0x100 0x10>;
clocks = <&xin24m>;
diff --git a/src/arm64/rockchip/rk3368.dtsi b/src/arm64/rockchip/rk3368.dtsi
index dfc6376..4c64fbe 100644
--- a/src/arm64/rockchip/rk3368.dtsi
+++ b/src/arm64/rockchip/rk3368.dtsi
@@ -664,6 +664,8 @@
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
+ clock-names = "pclk", "timer";
};
spdif: spdif@ff880000 {
diff --git a/src/arm64/rockchip/rk3399-firefly.dts b/src/arm64/rockchip/rk3399-firefly.dts
index 45254be..c4dd2a6 100644
--- a/src/arm64/rockchip/rk3399-firefly.dts
+++ b/src/arm64/rockchip/rk3399-firefly.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/usb/pd.h>
#include "rk3399.dtsi"
#include "rk3399-opp.dtsi"
@@ -94,6 +95,13 @@
};
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&ir_int>;
+ pinctrl-names = "default";
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -151,6 +159,23 @@
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
};
+ sound-dit {
+ compatible = "audio-graph-card";
+ label = "SPDIF";
+ dais = <&spdif_p0>;
+ };
+
+ spdif-dit {
+ compatible = "linux,spdif-dit";
+ #sound-dai-cells = <0>;
+
+ port {
+ dit_p0_0: endpoint {
+ remote-endpoint = <&spdif_p0_0>;
+ };
+ };
+ };
+
/* switched by pmic_sleep */
vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 {
compatible = "regulator-fixed";
@@ -196,6 +221,17 @@
vin-supply = <&vcc_sys>;
};
+ vcc5v0_typec: vcc5v0-typec-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec_en>;
+ regulator-name = "vcc5v0_typec";
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
@@ -521,6 +557,53 @@
i2c-scl-falling-time-ns = <20>;
status = "okay";
+ fusb0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fusb0_int>;
+ vbus-supply = <&vcc5v0_typec>;
+ status = "okay";
+
+ connector {
+ compatible = "usb-c-connector";
+ data-role = "host";
+ label = "USB-C";
+ op-sink-microwatt = <1000000>;
+ power-role = "dual";
+ sink-pdos =
+ <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 1400, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usbc_hs: endpoint {
+ remote-endpoint =
+ <&u2phy0_typec_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usbc_ss: endpoint {
+ remote-endpoint =
+ <&tcphy0_typec_ss>;
+ };
+ };
+ };
+ };
+ };
+
accelerometer@68 {
compatible = "invensense,mpu6500";
reg = <0x68>;
@@ -578,12 +661,34 @@
};
};
+ fusb302x {
+ fusb0_int: fusb0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
lcd-panel {
lcd_panel_reset: lcd-panel-reset {
rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
+ leds {
+ work_led_pin: work-led-pin {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_pin: diy-led-pin {
+ rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pcie {
pcie_pwr_en: pcie-pwr-en {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
@@ -595,6 +700,10 @@
};
pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
vsel1_pin: vsel1-pin {
rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
};
@@ -604,21 +713,21 @@
};
};
- sdio-pwrseq {
- wifi_enable_h: wifi-enable-h {
- rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-
rt5640 {
rt5640_hpcon: rt5640-hpcon {
rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb-typec {
+ vcc5v0_typec_en: vcc5v0_typec_en {
+ rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
@@ -633,16 +742,6 @@
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
-
- leds {
- work_led_pin: work-led-pin {
- rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
- };
-
- diy_led_pin: diy-led-pin {
- rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
};
&pwm0 {
@@ -710,10 +809,29 @@
status = "okay";
};
+&spdif {
+ pinctrl-0 = <&spdif_bus_1>;
+ status = "okay";
+
+ spdif_p0: port {
+ spdif_p0_0: endpoint {
+ remote-endpoint = <&dit_p0_0>;
+ };
+ };
+};
+
&tcphy0 {
status = "okay";
};
+&tcphy0_usb3 {
+ port {
+ tcphy0_typec_ss: endpoint {
+ remote-endpoint = <&usbc_ss>;
+ };
+ };
+};
+
&tcphy1 {
status = "okay";
};
@@ -737,6 +855,12 @@
phy-supply = <&vcc5v0_host>;
status = "okay";
};
+
+ port {
+ u2phy0_typec_hs: endpoint {
+ remote-endpoint = <&usbc_hs>;
+ };
+ };
};
&u2phy1 {
diff --git a/src/arm64/rockchip/rk3399-gru-scarlet.dtsi b/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
index beee5fb..5d7a9d9 100644
--- a/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
+++ b/src/arm64/rockchip/rk3399-gru-scarlet.dtsi
@@ -245,7 +245,7 @@
};
&ppvar_sd_card_io {
- states = <1800000 0x0 3300000 0x1>;
+ states = <1800000 0x0>, <3300000 0x1>;
regulator-max-microvolt = <3300000>;
};
diff --git a/src/arm64/rockchip/rk3399-gru.dtsi b/src/arm64/rockchip/rk3399-gru.dtsi
index 4002742..c1bcc8c 100644
--- a/src/arm64/rockchip/rk3399-gru.dtsi
+++ b/src/arm64/rockchip/rk3399-gru.dtsi
@@ -252,8 +252,8 @@
enable-active-high;
enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
- states = <1800000 0x1
- 3000000 0x0>;
+ states = <1800000 0x1>,
+ <3000000 0x0>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
diff --git a/src/arm64/rockchip/rk3399-kobol-helios64.dts b/src/arm64/rockchip/rk3399-kobol-helios64.dts
index 19485b5..738cfd2 100644
--- a/src/arm64/rockchip/rk3399-kobol-helios64.dts
+++ b/src/arm64/rockchip/rk3399-kobol-helios64.dts
@@ -23,6 +23,16 @@
mmc1 = &sdhci;
};
+ avdd_0v9_s0: avdd-0v9-s0 {
+ compatible = "regulator-fixed";
+ regulator-name = "avdd_0v9_s0";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc1v8_sys_s3>;
+ };
+
avdd_1v8_s0: avdd-1v8-s0 {
compatible = "regulator-fixed";
regulator-name = "avdd_1v8_s0";
@@ -40,6 +50,20 @@
#clock-cells = <0>;
};
+ fan1 {
+ /* fan connected to P7 */
+ compatible = "pwm-fan";
+ pwms = <&pwm0 0 40000 0>;
+ cooling-levels = <0 80 170 255>;
+ };
+
+ fan2 {
+ /* fan connected to P6 */
+ compatible = "pwm-fan";
+ pwms = <&pwm1 0 40000 0>;
+ cooling-levels = <0 80 170 255>;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -58,6 +82,18 @@
};
};
+ pcie_power: pcie-power {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&pcie_pwr>;
+ pinctrl-names = "default";
+ regulator-boot-on;
+ regulator-name = "pcie_power";
+ startup-delay-us = <10000>;
+ vin-supply = <&vcc5v0_perdev>;
+ };
+
vcc1v8_sys_s0: vcc1v8-sys-s0 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8_sys_s0";
@@ -95,6 +131,16 @@
};
};
+ vcc5v0_perdev: vcc5v0-perdev {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_perdev";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin_bkup>;
+ };
+
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
@@ -109,6 +155,20 @@
};
};
+ vcc5v0_usb: vcc5v0-usb {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_en>;
+ regulator-name = "vcc5v0_usb";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_perdev>;
+ };
+
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
@@ -317,6 +377,20 @@
status = "okay";
};
+&pcie_phy {
+ status = "okay";
+};
+
+&pcie0 {
+ num-lanes = <2>;
+ status = "okay";
+
+ vpcie12v-supply = <&vcc12v_dcin>;
+ vpcie3v3-supply = <&pcie_power>;
+ vpcie1v8-supply = <&avdd_1v8_s0>;
+ vpcie0v9-supply = <&avdd_0v9_s0>;
+};
+
&pinctrl {
gmac {
gphy_reset: gphy-reset {
@@ -334,12 +408,25 @@
};
};
+ pcie {
+ pcie_pwr: pcie-pwr {
+ rockchip,pins =
+ <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
+ power {
+ vcc5v0_usb_en: vcc5v0-usb-en {
+ rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
vcc3v0-sd {
sdmmc0_pwr_h: sdmmc0-pwr-h {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -352,6 +439,16 @@
status = "okay";
};
+&pwm0 {
+ /* pwm-fan on P7 */
+ status = "okay";
+};
+
+&pwm1 {
+ /* pwm-fan on P6 */
+ status = "okay";
+};
+
&sdhci {
bus-width = <8>;
mmc-hs200-1_8v;
@@ -372,6 +469,30 @@
status = "okay";
};
+&tcphy1 {
+ /* phy for &usbdrd_dwc3_1 */
+ status = "okay";
+};
+
+&u2phy1 {
+ status = "okay";
+
+ otg-port {
+ /* phy for &usbdrd_dwc3_1 */
+ phy-supply = <&vcc5v0_usb>;
+ status = "okay";
+ };
+};
+
&uart2 {
status = "okay";
};
+
+&usbdrd3_1 {
+ status = "okay";
+
+ usb@fe900000 {
+ dr_mode = "host";
+ status = "okay";
+ };
+};
diff --git a/src/arm64/rockchip/rk3399-nanopi-r4s.dts b/src/arm64/rockchip/rk3399-nanopi-r4s.dts
index fa58098..cef4d18 100644
--- a/src/arm64/rockchip/rk3399-nanopi-r4s.dts
+++ b/src/arm64/rockchip/rk3399-nanopi-r4s.dts
@@ -33,7 +33,7 @@
sys_led: led-sys {
gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
- label = "red:sys";
+ label = "red:power";
default-state = "on";
};
diff --git a/src/arm64/rockchip/rk3399-nanopi4.dtsi b/src/arm64/rockchip/rk3399-nanopi4.dtsi
index 16fd58c..8c0ff6c 100644
--- a/src/arm64/rockchip/rk3399-nanopi4.dtsi
+++ b/src/arm64/rockchip/rk3399-nanopi4.dtsi
@@ -510,7 +510,6 @@
};
&pcie0 {
- max-link-speed = <2>;
num-lanes = <2>;
vpcie0v9-supply = <&vcca0v9_s3>;
vpcie1v8-supply = <&vcca1v8_s3>;
diff --git a/src/arm64/rockchip/rk3399-roc-pc.dtsi b/src/arm64/rockchip/rk3399-roc-pc.dtsi
index c172f5a..d1aaf8e 100644
--- a/src/arm64/rockchip/rk3399-roc-pc.dtsi
+++ b/src/arm64/rockchip/rk3399-roc-pc.dtsi
@@ -63,6 +63,13 @@
};
};
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -389,6 +396,7 @@
vcc_sdio: LDO_REG4 {
regulator-name = "vcc_sdio";
+ regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
@@ -493,6 +501,8 @@
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <1000>;
+ regulator-always-on;
+ regulator-boot-on;
vin-supply = <&vcc3v3_sys>;
regulator-state-mem {
@@ -601,6 +611,12 @@
};
};
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
lcd-panel {
lcd_panel_reset: lcd-panel-reset {
rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/src/arm64/rockchip/rk3399-rock-pi-4.dtsi b/src/arm64/rockchip/rk3399-rock-pi-4.dtsi
index 7d0a7c6..b28888e 100644
--- a/src/arm64/rockchip/rk3399-rock-pi-4.dtsi
+++ b/src/arm64/rockchip/rk3399-rock-pi-4.dtsi
@@ -474,7 +474,6 @@
&pcie0 {
ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
- max-link-speed = <2>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
diff --git a/src/arm64/rockchip/rk3399.dtsi b/src/arm64/rockchip/rk3399.dtsi
index 634a91a..3871c7f 100644
--- a/src/arm64/rockchip/rk3399.dtsi
+++ b/src/arm64/rockchip/rk3399.dtsi
@@ -227,7 +227,7 @@
<&pcie_phy 2>, <&pcie_phy 3>;
phy-names = "pcie-phy-0", "pcie-phy-1",
"pcie-phy-2", "pcie-phy-3";
- ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
+ ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
<0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
@@ -968,126 +968,146 @@
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
- pd_iep@RK3399_PD_IEP {
+ power-domain@RK3399_PD_IEP {
reg = <RK3399_PD_IEP>;
clocks = <&cru ACLK_IEP>,
<&cru HCLK_IEP>;
pm_qos = <&qos_iep>;
+ #power-domain-cells = <0>;
};
- pd_rga@RK3399_PD_RGA {
+ power-domain@RK3399_PD_RGA {
reg = <RK3399_PD_RGA>;
clocks = <&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_rga_r>,
<&qos_rga_w>;
+ #power-domain-cells = <0>;
};
- pd_vcodec@RK3399_PD_VCODEC {
+ power-domain@RK3399_PD_VCODEC {
reg = <RK3399_PD_VCODEC>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video_m0>;
+ #power-domain-cells = <0>;
};
- pd_vdu@RK3399_PD_VDU {
+ power-domain@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
+ #power-domain-cells = <0>;
};
/* These power domains are grouped by VD_GPU */
- pd_gpu@RK3399_PD_GPU {
+ power-domain@RK3399_PD_GPU {
reg = <RK3399_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
+ #power-domain-cells = <0>;
};
/* These power domains are grouped by VD_LOGIC */
- pd_edp@RK3399_PD_EDP {
+ power-domain@RK3399_PD_EDP {
reg = <RK3399_PD_EDP>;
clocks = <&cru PCLK_EDP_CTRL>;
+ #power-domain-cells = <0>;
};
- pd_emmc@RK3399_PD_EMMC {
+ power-domain@RK3399_PD_EMMC {
reg = <RK3399_PD_EMMC>;
clocks = <&cru ACLK_EMMC>;
pm_qos = <&qos_emmc>;
+ #power-domain-cells = <0>;
};
- pd_gmac@RK3399_PD_GMAC {
+ power-domain@RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
pm_qos = <&qos_gmac>;
+ #power-domain-cells = <0>;
};
- pd_sd@RK3399_PD_SD {
+ power-domain@RK3399_PD_SD {
reg = <RK3399_PD_SD>;
clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>;
pm_qos = <&qos_sd>;
+ #power-domain-cells = <0>;
};
- pd_sdioaudio@RK3399_PD_SDIOAUDIO {
+ power-domain@RK3399_PD_SDIOAUDIO {
reg = <RK3399_PD_SDIOAUDIO>;
clocks = <&cru HCLK_SDIO>;
pm_qos = <&qos_sdioaudio>;
+ #power-domain-cells = <0>;
};
- pd_tcpc0@RK3399_PD_TCPD0 {
+ power-domain@RK3399_PD_TCPD0 {
reg = <RK3399_PD_TCPD0>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
+ #power-domain-cells = <0>;
};
- pd_tcpc1@RK3399_PD_TCPD1 {
+ power-domain@RK3399_PD_TCPD1 {
reg = <RK3399_PD_TCPD1>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
+ #power-domain-cells = <0>;
};
- pd_usb3@RK3399_PD_USB3 {
+ power-domain@RK3399_PD_USB3 {
reg = <RK3399_PD_USB3>;
clocks = <&cru ACLK_USB3>;
pm_qos = <&qos_usb_otg0>,
<&qos_usb_otg1>;
+ #power-domain-cells = <0>;
};
- pd_vio@RK3399_PD_VIO {
+ power-domain@RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
+ #power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
- pd_hdcp@RK3399_PD_HDCP {
+ power-domain@RK3399_PD_HDCP {
reg = <RK3399_PD_HDCP>;
clocks = <&cru ACLK_HDCP>,
<&cru HCLK_HDCP>,
<&cru PCLK_HDCP>;
pm_qos = <&qos_hdcp>;
+ #power-domain-cells = <0>;
};
- pd_isp0@RK3399_PD_ISP0 {
+ power-domain@RK3399_PD_ISP0 {
reg = <RK3399_PD_ISP0>;
clocks = <&cru ACLK_ISP0>,
<&cru HCLK_ISP0>;
pm_qos = <&qos_isp0_m0>,
<&qos_isp0_m1>;
+ #power-domain-cells = <0>;
};
- pd_isp1@RK3399_PD_ISP1 {
+ power-domain@RK3399_PD_ISP1 {
reg = <RK3399_PD_ISP1>;
clocks = <&cru ACLK_ISP1>,
<&cru HCLK_ISP1>;
pm_qos = <&qos_isp1_m0>,
<&qos_isp1_m1>;
+ #power-domain-cells = <0>;
};
- pd_vo@RK3399_PD_VO {
+ power-domain@RK3399_PD_VO {
reg = <RK3399_PD_VO>;
+ #power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
- pd_vopb@RK3399_PD_VOPB {
+ power-domain@RK3399_PD_VOPB {
reg = <RK3399_PD_VOPB>;
clocks = <&cru ACLK_VOP0>,
<&cru HCLK_VOP0>;
pm_qos = <&qos_vop_big_r>,
<&qos_vop_big_w>;
+ #power-domain-cells = <0>;
};
- pd_vopl@RK3399_PD_VOPL {
+ power-domain@RK3399_PD_VOPL {
reg = <RK3399_PD_VOPL>;
clocks = <&cru ACLK_VOP1>,
<&cru HCLK_VOP1>;
pm_qos = <&qos_vop_little>;
+ #power-domain-cells = <0>;
};
};
};
@@ -1398,7 +1418,7 @@
status = "disabled";
};
- u2phy0: usb2-phy@e450 {
+ u2phy0: usb2phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
clocks = <&cru SCLK_USB2PHY0_REF>;
@@ -1425,7 +1445,7 @@
};
};
- u2phy1: usb2-phy@e460 {
+ u2phy1: usb2phy@e460 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe460 0x10>;
clocks = <&cru SCLK_USB2PHY1_REF>;
@@ -2354,7 +2374,7 @@
};
};
- sleep {
+ suspend {
ap_pwroff: ap-pwroff {
rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
};
diff --git a/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi b/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi
index c0074b3..01d1a75 100644
--- a/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi
+++ b/src/arm64/rockchip/rk3399pro-vmarc-som.dtsi
@@ -329,7 +329,6 @@
&pcie0 {
ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
- max-link-speed = <2>;
num-lanes = <4>;
pinctrl-0 = <&pcie_clkreqnb_cpm>;
pinctrl-names = "default";
diff --git a/src/arm64/rockchip/rk3568-evb1-v10.dts b/src/arm64/rockchip/rk3568-evb1-v10.dts
new file mode 100644
index 0000000..6978655
--- /dev/null
+++ b/src/arm64/rockchip/rk3568-evb1-v10.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
+ compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd0_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd1_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/src/arm64/rockchip/rk3568-pinctrl.dtsi b/src/arm64/rockchip/rk3568-pinctrl.dtsi
new file mode 100644
index 0000000..a588ca9
--- /dev/null
+++ b/src/arm64/rockchip/rk3568-pinctrl.dtsi
@@ -0,0 +1,3111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ acodec {
+ /omit-if-no-ref/
+ acodec_pins: acodec-pins {
+ rockchip,pins =
+ /* acodec_adc_sync */
+ <1 RK_PB1 5 &pcfg_pull_none>,
+ /* acodec_adcclk */
+ <1 RK_PA1 5 &pcfg_pull_none>,
+ /* acodec_adcdata */
+ <1 RK_PA0 5 &pcfg_pull_none>,
+ /* acodec_dac_datal */
+ <1 RK_PA7 5 &pcfg_pull_none>,
+ /* acodec_dac_datar */
+ <1 RK_PB0 5 &pcfg_pull_none>,
+ /* acodec_dacclk */
+ <1 RK_PA3 5 &pcfg_pull_none>,
+ /* acodec_dacsync */
+ <1 RK_PA5 5 &pcfg_pull_none>;
+ };
+ };
+
+ audiopwm {
+ /omit-if-no-ref/
+ audiopwm_lout: audiopwm-lout {
+ rockchip,pins =
+ /* audiopwm_lout */
+ <1 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_loutn: audiopwm-loutn {
+ rockchip,pins =
+ /* audiopwm_loutn */
+ <1 RK_PA1 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_loutp: audiopwm-loutp {
+ rockchip,pins =
+ /* audiopwm_loutp */
+ <1 RK_PA0 6 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_rout: audiopwm-rout {
+ rockchip,pins =
+ /* audiopwm_rout */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_routn: audiopwm-routn {
+ rockchip,pins =
+ /* audiopwm_routn */
+ <1 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ audiopwm_routp: audiopwm-routp {
+ rockchip,pins =
+ /* audiopwm_routp */
+ <1 RK_PA6 4 &pcfg_pull_none>;
+ };
+ };
+
+ bt656 {
+ /omit-if-no-ref/
+ bt656m0_pins: bt656m0-pins {
+ rockchip,pins =
+ /* bt656_clkm0 */
+ <3 RK_PA0 2 &pcfg_pull_none>,
+ /* bt656_d0m0 */
+ <2 RK_PD0 2 &pcfg_pull_none>,
+ /* bt656_d1m0 */
+ <2 RK_PD1 2 &pcfg_pull_none>,
+ /* bt656_d2m0 */
+ <2 RK_PD2 2 &pcfg_pull_none>,
+ /* bt656_d3m0 */
+ <2 RK_PD3 2 &pcfg_pull_none>,
+ /* bt656_d4m0 */
+ <2 RK_PD4 2 &pcfg_pull_none>,
+ /* bt656_d5m0 */
+ <2 RK_PD5 2 &pcfg_pull_none>,
+ /* bt656_d6m0 */
+ <2 RK_PD6 2 &pcfg_pull_none>,
+ /* bt656_d7m0 */
+ <2 RK_PD7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ bt656m1_pins: bt656m1-pins {
+ rockchip,pins =
+ /* bt656_clkm1 */
+ <4 RK_PB4 5 &pcfg_pull_none>,
+ /* bt656_d0m1 */
+ <3 RK_PC6 5 &pcfg_pull_none>,
+ /* bt656_d1m1 */
+ <3 RK_PC7 5 &pcfg_pull_none>,
+ /* bt656_d2m1 */
+ <3 RK_PD0 5 &pcfg_pull_none>,
+ /* bt656_d3m1 */
+ <3 RK_PD1 5 &pcfg_pull_none>,
+ /* bt656_d4m1 */
+ <3 RK_PD2 5 &pcfg_pull_none>,
+ /* bt656_d5m1 */
+ <3 RK_PD3 5 &pcfg_pull_none>,
+ /* bt656_d6m1 */
+ <3 RK_PD4 5 &pcfg_pull_none>,
+ /* bt656_d7m1 */
+ <3 RK_PD5 5 &pcfg_pull_none>;
+ };
+ };
+
+ bt1120 {
+ /omit-if-no-ref/
+ bt1120_pins: bt1120-pins {
+ rockchip,pins =
+ /* bt1120_clk */
+ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* bt1120_d0 */
+ <3 RK_PA1 2 &pcfg_pull_none>,
+ /* bt1120_d1 */
+ <3 RK_PA2 2 &pcfg_pull_none>,
+ /* bt1120_d2 */
+ <3 RK_PA3 2 &pcfg_pull_none>,
+ /* bt1120_d3 */
+ <3 RK_PA4 2 &pcfg_pull_none>,
+ /* bt1120_d4 */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* bt1120_d5 */
+ <3 RK_PA7 2 &pcfg_pull_none>,
+ /* bt1120_d6 */
+ <3 RK_PB0 2 &pcfg_pull_none>,
+ /* bt1120_d7 */
+ <3 RK_PB1 2 &pcfg_pull_none>,
+ /* bt1120_d8 */
+ <3 RK_PB2 2 &pcfg_pull_none>,
+ /* bt1120_d9 */
+ <3 RK_PB3 2 &pcfg_pull_none>,
+ /* bt1120_d10 */
+ <3 RK_PB4 2 &pcfg_pull_none>,
+ /* bt1120_d11 */
+ <3 RK_PB5 2 &pcfg_pull_none>,
+ /* bt1120_d12 */
+ <3 RK_PB6 2 &pcfg_pull_none>,
+ /* bt1120_d13 */
+ <3 RK_PC1 2 &pcfg_pull_none>,
+ /* bt1120_d14 */
+ <3 RK_PC2 2 &pcfg_pull_none>,
+ /* bt1120_d15 */
+ <3 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ cam {
+ /omit-if-no-ref/
+ cam_clkout0: cam-clkout0 {
+ rockchip,pins =
+ /* cam_clkout0 */
+ <4 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cam_clkout1: cam-clkout1 {
+ rockchip,pins =
+ /* cam_clkout1 */
+ <4 RK_PB0 1 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ /omit-if-no-ref/
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rxm0 */
+ <0 RK_PB4 2 &pcfg_pull_none>,
+ /* can0_txm0 */
+ <0 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rxm1 */
+ <2 RK_PA2 4 &pcfg_pull_none>,
+ /* can0_txm1 */
+ <2 RK_PA1 4 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ /omit-if-no-ref/
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rxm0 */
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ /* can1_txm0 */
+ <1 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rxm1 */
+ <4 RK_PC2 3 &pcfg_pull_none>,
+ /* can1_txm1 */
+ <4 RK_PC3 3 &pcfg_pull_none>;
+ };
+ };
+
+ can2 {
+ /omit-if-no-ref/
+ can2m0_pins: can2m0-pins {
+ rockchip,pins =
+ /* can2_rxm0 */
+ <4 RK_PB4 3 &pcfg_pull_none>,
+ /* can2_txm0 */
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ can2m1_pins: can2m1-pins {
+ rockchip,pins =
+ /* can2_rxm1 */
+ <2 RK_PB1 4 &pcfg_pull_none>,
+ /* can2_txm1 */
+ <2 RK_PB2 4 &pcfg_pull_none>;
+ };
+ };
+
+ cif {
+ /omit-if-no-ref/
+ cif_clk: cif-clk {
+ rockchip,pins =
+ /* cif_clkout */
+ <4 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_clk: cif-dvp-clk {
+ rockchip,pins =
+ /* cif_clkin */
+ <4 RK_PC1 1 &pcfg_pull_none>,
+ /* cif_href */
+ <4 RK_PB6 1 &pcfg_pull_none>,
+ /* cif_vsync */
+ <4 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus16: cif-dvp-bus16 {
+ rockchip,pins =
+ /* cif_d8 */
+ <3 RK_PD6 1 &pcfg_pull_none>,
+ /* cif_d9 */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* cif_d10 */
+ <4 RK_PA0 1 &pcfg_pull_none>,
+ /* cif_d11 */
+ <4 RK_PA1 1 &pcfg_pull_none>,
+ /* cif_d12 */
+ <4 RK_PA2 1 &pcfg_pull_none>,
+ /* cif_d13 */
+ <4 RK_PA3 1 &pcfg_pull_none>,
+ /* cif_d14 */
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ /* cif_d15 */
+ <4 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ cif_dvp_bus8: cif-dvp-bus8 {
+ rockchip,pins =
+ /* cif_d0 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* cif_d1 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* cif_d2 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* cif_d3 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* cif_d4 */
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ /* cif_d5 */
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ /* cif_d6 */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* cif_d7 */
+ <3 RK_PD5 1 &pcfg_pull_none>;
+ };
+ };
+
+ clk32k {
+ /omit-if-no-ref/
+ clk32k_in: clk32k-in {
+ rockchip,pins =
+ /* clk32k_in */
+ <0 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clk32k_out0: clk32k-out0 {
+ rockchip,pins =
+ /* clk32k_out0 */
+ <0 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ clk32k_out1: clk32k-out1 {
+ rockchip,pins =
+ /* clk32k_out1 */
+ <2 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ cpu {
+ /omit-if-no-ref/
+ cpu_pins: cpu-pins {
+ rockchip,pins =
+ /* cpu_avs */
+ <0 RK_PB7 2 &pcfg_pull_none>;
+ };
+ };
+
+ ebc {
+ /omit-if-no-ref/
+ ebc_extern: ebc-extern {
+ rockchip,pins =
+ /* ebc_sdce1 */
+ <4 RK_PA7 2 &pcfg_pull_none>,
+ /* ebc_sdce2 */
+ <4 RK_PB0 2 &pcfg_pull_none>,
+ /* ebc_sdce3 */
+ <4 RK_PB1 2 &pcfg_pull_none>,
+ /* ebc_sdshr */
+ <4 RK_PB5 2 &pcfg_pull_none>,
+ /* ebc_vcom */
+ <4 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ ebc_pins: ebc-pins {
+ rockchip,pins =
+ /* ebc_gdclk */
+ <4 RK_PC0 2 &pcfg_pull_none>,
+ /* ebc_gdoe */
+ <4 RK_PB3 2 &pcfg_pull_none>,
+ /* ebc_gdsp */
+ <4 RK_PB4 2 &pcfg_pull_none>,
+ /* ebc_sdce0 */
+ <4 RK_PA6 2 &pcfg_pull_none>,
+ /* ebc_sdclk */
+ <4 RK_PC1 2 &pcfg_pull_none>,
+ /* ebc_sddo0 */
+ <3 RK_PC6 2 &pcfg_pull_none>,
+ /* ebc_sddo1 */
+ <3 RK_PC7 2 &pcfg_pull_none>,
+ /* ebc_sddo2 */
+ <3 RK_PD0 2 &pcfg_pull_none>,
+ /* ebc_sddo3 */
+ <3 RK_PD1 2 &pcfg_pull_none>,
+ /* ebc_sddo4 */
+ <3 RK_PD2 2 &pcfg_pull_none>,
+ /* ebc_sddo5 */
+ <3 RK_PD3 2 &pcfg_pull_none>,
+ /* ebc_sddo6 */
+ <3 RK_PD4 2 &pcfg_pull_none>,
+ /* ebc_sddo7 */
+ <3 RK_PD5 2 &pcfg_pull_none>,
+ /* ebc_sddo8 */
+ <3 RK_PD6 2 &pcfg_pull_none>,
+ /* ebc_sddo9 */
+ <3 RK_PD7 2 &pcfg_pull_none>,
+ /* ebc_sddo10 */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* ebc_sddo11 */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* ebc_sddo12 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* ebc_sddo13 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* ebc_sddo14 */
+ <4 RK_PA4 2 &pcfg_pull_none>,
+ /* ebc_sddo15 */
+ <4 RK_PA5 2 &pcfg_pull_none>,
+ /* ebc_sdle */
+ <4 RK_PB6 2 &pcfg_pull_none>,
+ /* ebc_sdoe */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+ };
+
+ edpdp {
+ /omit-if-no-ref/
+ edpdpm0_pins: edpdpm0-pins {
+ rockchip,pins =
+ /* edpdp_hpdinm0 */
+ <4 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ edpdpm1_pins: edpdpm1-pins {
+ rockchip,pins =
+ /* edpdp_hpdinm1 */
+ <0 RK_PC2 2 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clkout */
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ emmc_datastrobe: emmc-datastrobe {
+ rockchip,pins =
+ /* emmc_datastrobe */
+ <1 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth0 {
+ /omit-if-no-ref/
+ eth0_pins: eth0-pins {
+ rockchip,pins =
+ /* eth0_refclko25m */
+ <2 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ eth1 {
+ /omit-if-no-ref/
+ eth1m0_pins: eth1m0-pins {
+ rockchip,pins =
+ /* eth1_refclko25mm0 */
+ <3 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ eth1m1_pins: eth1m1-pins {
+ rockchip,pins =
+ /* eth1_refclko25mm1 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ flash {
+ /omit-if-no-ref/
+ flash_pins: flash-pins {
+ rockchip,pins =
+ /* flash_ale */
+ <1 RK_PD0 2 &pcfg_pull_none>,
+ /* flash_cle */
+ <1 RK_PC6 3 &pcfg_pull_none>,
+ /* flash_cs0n */
+ <1 RK_PD3 2 &pcfg_pull_none>,
+ /* flash_cs1n */
+ <1 RK_PD4 2 &pcfg_pull_none>,
+ /* flash_d0 */
+ <1 RK_PB4 2 &pcfg_pull_none>,
+ /* flash_d1 */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* flash_d2 */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* flash_d3 */
+ <1 RK_PB7 2 &pcfg_pull_none>,
+ /* flash_d4 */
+ <1 RK_PC0 2 &pcfg_pull_none>,
+ /* flash_d5 */
+ <1 RK_PC1 2 &pcfg_pull_none>,
+ /* flash_d6 */
+ <1 RK_PC2 2 &pcfg_pull_none>,
+ /* flash_d7 */
+ <1 RK_PC3 2 &pcfg_pull_none>,
+ /* flash_dqs */
+ <1 RK_PC5 2 &pcfg_pull_none>,
+ /* flash_rdn */
+ <1 RK_PD2 2 &pcfg_pull_none>,
+ /* flash_rdy */
+ <1 RK_PD1 2 &pcfg_pull_none>,
+ /* flash_volsel */
+ <0 RK_PA7 1 &pcfg_pull_none>,
+ /* flash_wpn */
+ <1 RK_PC7 3 &pcfg_pull_none>,
+ /* flash_wrn */
+ <1 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ /omit-if-no-ref/
+ fspi_pins: fspi-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD0 1 &pcfg_pull_none>,
+ /* fspi_cs0n */
+ <1 RK_PD3 1 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PD1 1 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PD2 1 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PC7 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ fspi_cs1: fspi-cs1 {
+ rockchip,pins =
+ /* fspi_cs1n */
+ <1 RK_PC6 2 &pcfg_pull_up>;
+ };
+ };
+
+ gmac0 {
+ /omit-if-no-ref/
+ gmac0_miim: gmac0-miim {
+ rockchip,pins =
+ /* gmac0_mdc */
+ <2 RK_PC3 2 &pcfg_pull_none>,
+ /* gmac0_mdio */
+ <2 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_clkinout: gmac0-clkinout {
+ rockchip,pins =
+ /* gmac0_mclkinout */
+ <2 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rx_er: gmac0-rx-er {
+ rockchip,pins =
+ /* gmac0_rxer */
+ <2 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rx_bus2: gmac0-rx-bus2 {
+ rockchip,pins =
+ /* gmac0_rxd0 */
+ <2 RK_PB6 1 &pcfg_pull_none>,
+ /* gmac0_rxd1 */
+ <2 RK_PB7 2 &pcfg_pull_none>,
+ /* gmac0_rxdvcrs */
+ <2 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_tx_bus2: gmac0-tx-bus2 {
+ rockchip,pins =
+ /* gmac0_txd0 */
+ <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
+ /* gmac0_txd1 */
+ <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
+ /* gmac0_txen */
+ <2 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_clk: gmac0-rgmii-clk {
+ rockchip,pins =
+ /* gmac0_rxclk */
+ <2 RK_PA5 2 &pcfg_pull_none>,
+ /* gmac0_txclk */
+ <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_bus: gmac0-rgmii-bus {
+ rockchip,pins =
+ /* gmac0_rxd2 */
+ <2 RK_PA3 2 &pcfg_pull_none>,
+ /* gmac0_rxd3 */
+ <2 RK_PA4 2 &pcfg_pull_none>,
+ /* gmac0_txd2 */
+ <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
+ /* gmac0_txd3 */
+ <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ gmac1 {
+ /omit-if-no-ref/
+ gmac1m0_miim: gmac1m0-miim {
+ rockchip,pins =
+ /* gmac1_mdcm0 */
+ <3 RK_PC4 3 &pcfg_pull_none>,
+ /* gmac1_mdiom0 */
+ <3 RK_PC5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_clkinout: gmac1m0-clkinout {
+ rockchip,pins =
+ /* gmac1_mclkinoutm0 */
+ <3 RK_PC0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rx_er: gmac1m0-rx-er {
+ rockchip,pins =
+ /* gmac1_rxerm0 */
+ <3 RK_PB4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
+ rockchip,pins =
+ /* gmac1_rxd0m0 */
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ /* gmac1_rxd1m0 */
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ /* gmac1_rxdvcrsm0 */
+ <3 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
+ rockchip,pins =
+ /* gmac1_txd0m0 */
+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd1m0 */
+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txenm0 */
+ <3 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
+ rockchip,pins =
+ /* gmac1_rxclkm0 */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* gmac1_txclkm0 */
+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
+ rockchip,pins =
+ /* gmac1_rxd2m0 */
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m0 */
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ /* gmac1_txd2m0 */
+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd3m0 */
+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_miim: gmac1m1-miim {
+ rockchip,pins =
+ /* gmac1_mdcm1 */
+ <4 RK_PB6 3 &pcfg_pull_none>,
+ /* gmac1_mdiom1 */
+ <4 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_clkinout: gmac1m1-clkinout {
+ rockchip,pins =
+ /* gmac1_mclkinoutm1 */
+ <4 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rx_er: gmac1m1-rx-er {
+ rockchip,pins =
+ /* gmac1_rxerm1 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rx_bus2: gmac1m1-rx-bus2 {
+ rockchip,pins =
+ /* gmac1_rxd0m1 */
+ <4 RK_PA7 3 &pcfg_pull_none>,
+ /* gmac1_rxd1m1 */
+ <4 RK_PB0 3 &pcfg_pull_none>,
+ /* gmac1_rxdvcrsm1 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_tx_bus2: gmac1m1-tx-bus2 {
+ rockchip,pins =
+ /* gmac1_txd0m1 */
+ <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd1m1 */
+ <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txenm1 */
+ <4 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_clk: gmac1m1-rgmii-clk {
+ rockchip,pins =
+ /* gmac1_rxclkm1 */
+ <4 RK_PA3 3 &pcfg_pull_none>,
+ /* gmac1_txclkm1 */
+ <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_bus: gmac1m1-rgmii-bus {
+ rockchip,pins =
+ /* gmac1_rxd2m1 */
+ <4 RK_PA1 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m1 */
+ <4 RK_PA2 3 &pcfg_pull_none>,
+ /* gmac1_txd2m1 */
+ <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>,
+ /* gmac1_txd3m1 */
+ <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+
+ gpu {
+ /omit-if-no-ref/
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <0 RK_PC0 2 &pcfg_pull_none>,
+ /* gpu_pwren */
+ <0 RK_PA6 4 &pcfg_pull_none>;
+ };
+ };
+
+ hdmitx {
+ /omit-if-no-ref/
+ hdmitxm0_cec: hdmitxm0-cec {
+ rockchip,pins =
+ /* hdmitxm0_cec */
+ <4 RK_PD1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmitxm1_cec: hdmitxm1-cec {
+ rockchip,pins =
+ /* hdmitxm1_cec */
+ <0 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmitx_scl: hdmitx-scl {
+ rockchip,pins =
+ /* hdmitx_scl */
+ <4 RK_PC7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ hdmitx_sda: hdmitx-sda {
+ rockchip,pins =
+ /* hdmitx_sda */
+ <4 RK_PD0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB1 1 &pcfg_pull_none_smt>,
+ /* i2c0_sda */
+ <0 RK_PB2 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ /omit-if-no-ref/
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins =
+ /* i2c1_scl */
+ <0 RK_PB3 1 &pcfg_pull_none_smt>,
+ /* i2c1_sda */
+ <0 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ /omit-if-no-ref/
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_sclm0 */
+ <0 RK_PB5 1 &pcfg_pull_none_smt>,
+ /* i2c2_sdam0 */
+ <0 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_sclm1 */
+ <4 RK_PB5 1 &pcfg_pull_none_smt>,
+ /* i2c2_sdam1 */
+ <4 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ /omit-if-no-ref/
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_sclm0 */
+ <1 RK_PA1 1 &pcfg_pull_none_smt>,
+ /* i2c3_sdam0 */
+ <1 RK_PA0 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_sclm1 */
+ <3 RK_PB5 4 &pcfg_pull_none_smt>,
+ /* i2c3_sdam1 */
+ <3 RK_PB6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ /omit-if-no-ref/
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_sclm0 */
+ <4 RK_PB3 1 &pcfg_pull_none_smt>,
+ /* i2c4_sdam0 */
+ <4 RK_PB2 1 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_sclm1 */
+ <2 RK_PB2 2 &pcfg_pull_none_smt>,
+ /* i2c4_sdam1 */
+ <2 RK_PB1 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ /omit-if-no-ref/
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_sclm0 */
+ <3 RK_PB3 4 &pcfg_pull_none_smt>,
+ /* i2c5_sdam0 */
+ <3 RK_PB4 4 &pcfg_pull_none_smt>;
+ };
+
+ /omit-if-no-ref/
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_sclm1 */
+ <4 RK_PC7 2 &pcfg_pull_none_smt>,
+ /* i2c5_sdam1 */
+ <4 RK_PD0 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s1 {
+ /omit-if-no-ref/
+ i2s1m0_lrckrx: i2s1m0-lrckrx {
+ rockchip,pins =
+ /* i2s1m0_lrckrx */
+ <1 RK_PA6 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_lrcktx: i2s1m0-lrcktx {
+ rockchip,pins =
+ /* i2s1m0_lrcktx */
+ <1 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_mclk: i2s1m0-mclk {
+ rockchip,pins =
+ /* i2s1m0_mclk */
+ <1 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sclkrx: i2s1m0-sclkrx {
+ rockchip,pins =
+ /* i2s1m0_sclkrx */
+ <1 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sclktx: i2s1m0-sclktx {
+ rockchip,pins =
+ /* i2s1m0_sclktx */
+ <1 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi0: i2s1m0-sdi0 {
+ rockchip,pins =
+ /* i2s1m0_sdi0 */
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi1: i2s1m0-sdi1 {
+ rockchip,pins =
+ /* i2s1m0_sdi1 */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi2: i2s1m0-sdi2 {
+ rockchip,pins =
+ /* i2s1m0_sdi2 */
+ <1 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdi3: i2s1m0-sdi3 {
+ rockchip,pins =
+ /* i2s1m0_sdi3 */
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo0: i2s1m0-sdo0 {
+ rockchip,pins =
+ /* i2s1m0_sdo0 */
+ <1 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo1: i2s1m0-sdo1 {
+ rockchip,pins =
+ /* i2s1m0_sdo1 */
+ <1 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo2: i2s1m0-sdo2 {
+ rockchip,pins =
+ /* i2s1m0_sdo2 */
+ <1 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m0_sdo3: i2s1m0-sdo3 {
+ rockchip,pins =
+ /* i2s1m0_sdo3 */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_lrckrx: i2s1m1-lrckrx {
+ rockchip,pins =
+ /* i2s1m1_lrckrx */
+ <4 RK_PA7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_lrcktx: i2s1m1-lrcktx {
+ rockchip,pins =
+ /* i2s1m1_lrcktx */
+ <3 RK_PD0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_mclk: i2s1m1-mclk {
+ rockchip,pins =
+ /* i2s1m1_mclk */
+ <3 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sclkrx: i2s1m1-sclkrx {
+ rockchip,pins =
+ /* i2s1m1_sclkrx */
+ <4 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sclktx: i2s1m1-sclktx {
+ rockchip,pins =
+ /* i2s1m1_sclktx */
+ <3 RK_PC7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi0: i2s1m1-sdi0 {
+ rockchip,pins =
+ /* i2s1m1_sdi0 */
+ <3 RK_PD2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi1: i2s1m1-sdi1 {
+ rockchip,pins =
+ /* i2s1m1_sdi1 */
+ <3 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi2: i2s1m1-sdi2 {
+ rockchip,pins =
+ /* i2s1m1_sdi2 */
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdi3: i2s1m1-sdi3 {
+ rockchip,pins =
+ /* i2s1m1_sdi3 */
+ <3 RK_PD5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo0: i2s1m1-sdo0 {
+ rockchip,pins =
+ /* i2s1m1_sdo0 */
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo1: i2s1m1-sdo1 {
+ rockchip,pins =
+ /* i2s1m1_sdo1 */
+ <4 RK_PB0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo2: i2s1m1-sdo2 {
+ rockchip,pins =
+ /* i2s1m1_sdo2 */
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m1_sdo3: i2s1m1-sdo3 {
+ rockchip,pins =
+ /* i2s1m1_sdo3 */
+ <4 RK_PB5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_lrckrx: i2s1m2-lrckrx {
+ rockchip,pins =
+ /* i2s1m2_lrckrx */
+ <3 RK_PC5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_lrcktx: i2s1m2-lrcktx {
+ rockchip,pins =
+ /* i2s1m2_lrcktx */
+ <2 RK_PD2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_mclk: i2s1m2-mclk {
+ rockchip,pins =
+ /* i2s1m2_mclk */
+ <2 RK_PD0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sclkrx: i2s1m2-sclkrx {
+ rockchip,pins =
+ /* i2s1m2_sclkrx */
+ <3 RK_PC3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sclktx: i2s1m2-sclktx {
+ rockchip,pins =
+ /* i2s1m2_sclktx */
+ <2 RK_PD1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi0: i2s1m2-sdi0 {
+ rockchip,pins =
+ /* i2s1m2_sdi0 */
+ <2 RK_PD3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi1: i2s1m2-sdi1 {
+ rockchip,pins =
+ /* i2s1m2_sdi1 */
+ <2 RK_PD4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi2: i2s1m2-sdi2 {
+ rockchip,pins =
+ /* i2s1m2_sdi2 */
+ <2 RK_PD5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdi3: i2s1m2-sdi3 {
+ rockchip,pins =
+ /* i2s1m2_sdi3 */
+ <2 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo0: i2s1m2-sdo0 {
+ rockchip,pins =
+ /* i2s1m2_sdo0 */
+ <2 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo1: i2s1m2-sdo1 {
+ rockchip,pins =
+ /* i2s1m2_sdo1 */
+ <3 RK_PA0 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo2: i2s1m2-sdo2 {
+ rockchip,pins =
+ /* i2s1m2_sdo2 */
+ <3 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s1m2_sdo3: i2s1m2-sdo3 {
+ rockchip,pins =
+ /* i2s1m2_sdo3 */
+ <3 RK_PC2 5 &pcfg_pull_none>;
+ };
+ };
+
+ i2s2 {
+ /omit-if-no-ref/
+ i2s2m0_lrckrx: i2s2m0-lrckrx {
+ rockchip,pins =
+ /* i2s2m0_lrckrx */
+ <2 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_lrcktx: i2s2m0-lrcktx {
+ rockchip,pins =
+ /* i2s2m0_lrcktx */
+ <2 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ /* i2s2m0_mclk */
+ <2 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclkrx: i2s2m0-sclkrx {
+ rockchip,pins =
+ /* i2s2m0_sclkrx */
+ <2 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sclktx: i2s2m0-sclktx {
+ rockchip,pins =
+ /* i2s2m0_sclktx */
+ <2 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ /* i2s2m0_sdi */
+ <2 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ /* i2s2m0_sdo */
+ <2 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_lrckrx: i2s2m1-lrckrx {
+ rockchip,pins =
+ /* i2s2m1_lrckrx */
+ <4 RK_PA5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_lrcktx: i2s2m1-lrcktx {
+ rockchip,pins =
+ /* i2s2m1_lrcktx */
+ <4 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins =
+ /* i2s2m1_mclk */
+ <4 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sclkrx: i2s2m1-sclkrx {
+ rockchip,pins =
+ /* i2s2m1_sclkrx */
+ <4 RK_PC1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sclktx: i2s2m1-sclktx {
+ rockchip,pins =
+ /* i2s2m1_sclktx */
+ <4 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins =
+ /* i2s2m1_sdi */
+ <4 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins =
+ /* i2s2m1_sdo */
+ <4 RK_PB3 5 &pcfg_pull_none>;
+ };
+ };
+
+ i2s3 {
+ /omit-if-no-ref/
+ i2s3m0_lrck: i2s3m0-lrck {
+ rockchip,pins =
+ /* i2s3m0_lrck */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_mclk: i2s3m0-mclk {
+ rockchip,pins =
+ /* i2s3m0_mclk */
+ <3 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_sclk: i2s3m0-sclk {
+ rockchip,pins =
+ /* i2s3m0_sclk */
+ <3 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_sdi: i2s3m0-sdi {
+ rockchip,pins =
+ /* i2s3m0_sdi */
+ <3 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m0_sdo: i2s3m0-sdo {
+ rockchip,pins =
+ /* i2s3m0_sdo */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_lrck: i2s3m1-lrck {
+ rockchip,pins =
+ /* i2s3m1_lrck */
+ <4 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_mclk: i2s3m1-mclk {
+ rockchip,pins =
+ /* i2s3m1_mclk */
+ <4 RK_PC2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_sclk: i2s3m1-sclk {
+ rockchip,pins =
+ /* i2s3m1_sclk */
+ <4 RK_PC3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_sdi: i2s3m1-sdi {
+ rockchip,pins =
+ /* i2s3m1_sdi */
+ <4 RK_PC6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ i2s3m1_sdo: i2s3m1-sdo {
+ rockchip,pins =
+ /* i2s3m1_sdo */
+ <4 RK_PC5 5 &pcfg_pull_none>;
+ };
+ };
+
+ isp {
+ /omit-if-no-ref/
+ isp_pins: isp-pins {
+ rockchip,pins =
+ /* isp_flashtrigin */
+ <4 RK_PB4 4 &pcfg_pull_none>,
+ /* isp_flashtrigout */
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ /* isp_prelighttrig */
+ <4 RK_PB1 1 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ /omit-if-no-ref/
+ jtag_pins: jtag-pins {
+ rockchip,pins =
+ /* jtag_tck */
+ <1 RK_PD7 2 &pcfg_pull_none>,
+ /* jtag_tms */
+ <2 RK_PA0 2 &pcfg_pull_none>;
+ };
+ };
+
+ lcdc {
+ /omit-if-no-ref/
+ lcdc_ctl: lcdc-ctl {
+ rockchip,pins =
+ /* lcdc_clk */
+ <3 RK_PA0 1 &pcfg_pull_none>,
+ /* lcdc_d0 */
+ <2 RK_PD0 1 &pcfg_pull_none>,
+ /* lcdc_d1 */
+ <2 RK_PD1 1 &pcfg_pull_none>,
+ /* lcdc_d2 */
+ <2 RK_PD2 1 &pcfg_pull_none>,
+ /* lcdc_d3 */
+ <2 RK_PD3 1 &pcfg_pull_none>,
+ /* lcdc_d4 */
+ <2 RK_PD4 1 &pcfg_pull_none>,
+ /* lcdc_d5 */
+ <2 RK_PD5 1 &pcfg_pull_none>,
+ /* lcdc_d6 */
+ <2 RK_PD6 1 &pcfg_pull_none>,
+ /* lcdc_d7 */
+ <2 RK_PD7 1 &pcfg_pull_none>,
+ /* lcdc_d8 */
+ <3 RK_PA1 1 &pcfg_pull_none>,
+ /* lcdc_d9 */
+ <3 RK_PA2 1 &pcfg_pull_none>,
+ /* lcdc_d10 */
+ <3 RK_PA3 1 &pcfg_pull_none>,
+ /* lcdc_d11 */
+ <3 RK_PA4 1 &pcfg_pull_none>,
+ /* lcdc_d12 */
+ <3 RK_PA5 1 &pcfg_pull_none>,
+ /* lcdc_d13 */
+ <3 RK_PA6 1 &pcfg_pull_none>,
+ /* lcdc_d14 */
+ <3 RK_PA7 1 &pcfg_pull_none>,
+ /* lcdc_d15 */
+ <3 RK_PB0 1 &pcfg_pull_none>,
+ /* lcdc_d16 */
+ <3 RK_PB1 1 &pcfg_pull_none>,
+ /* lcdc_d17 */
+ <3 RK_PB2 1 &pcfg_pull_none>,
+ /* lcdc_d18 */
+ <3 RK_PB3 1 &pcfg_pull_none>,
+ /* lcdc_d19 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* lcdc_d20 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* lcdc_d21 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* lcdc_d22 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* lcdc_d23 */
+ <3 RK_PC0 1 &pcfg_pull_none>,
+ /* lcdc_den */
+ <3 RK_PC3 1 &pcfg_pull_none>,
+ /* lcdc_hsync */
+ <3 RK_PC1 1 &pcfg_pull_none>,
+ /* lcdc_vsync */
+ <3 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ mcu {
+ /omit-if-no-ref/
+ mcu_pins: mcu-pins {
+ rockchip,pins =
+ /* mcu_jtagtck */
+ <0 RK_PB4 4 &pcfg_pull_none>,
+ /* mcu_jtagtdi */
+ <0 RK_PC1 4 &pcfg_pull_none>,
+ /* mcu_jtagtdo */
+ <0 RK_PB3 4 &pcfg_pull_none>,
+ /* mcu_jtagtms */
+ <0 RK_PC2 4 &pcfg_pull_none>,
+ /* mcu_jtagtrstn */
+ <0 RK_PC3 4 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ /omit-if-no-ref/
+ npu_pins: npu-pins {
+ rockchip,pins =
+ /* npu_avs */
+ <0 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ pcie20 {
+ /omit-if-no-ref/
+ pcie20m0_pins: pcie20m0-pins {
+ rockchip,pins =
+ /* pcie20_clkreqnm0 */
+ <0 RK_PA5 3 &pcfg_pull_none>,
+ /* pcie20_perstnm0 */
+ <0 RK_PB6 3 &pcfg_pull_none>,
+ /* pcie20_wakenm0 */
+ <0 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20m1_pins: pcie20m1-pins {
+ rockchip,pins =
+ /* pcie20_clkreqnm1 */
+ <2 RK_PD0 4 &pcfg_pull_none>,
+ /* pcie20_perstnm1 */
+ <3 RK_PC1 4 &pcfg_pull_none>,
+ /* pcie20_wakenm1 */
+ <2 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20m2_pins: pcie20m2-pins {
+ rockchip,pins =
+ /* pcie20_clkreqnm2 */
+ <1 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie20_perstnm2 */
+ <1 RK_PB2 4 &pcfg_pull_none>,
+ /* pcie20_wakenm2 */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie20_buttonrstn: pcie20-buttonrstn {
+ rockchip,pins =
+ /* pcie20_buttonrstn */
+ <0 RK_PB4 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x1 {
+ /omit-if-no-ref/
+ pcie30x1m0_pins: pcie30x1m0-pins {
+ rockchip,pins =
+ /* pcie30x1_clkreqnm0 */
+ <0 RK_PA4 3 &pcfg_pull_none>,
+ /* pcie30x1_perstnm0 */
+ <0 RK_PC3 3 &pcfg_pull_none>,
+ /* pcie30x1_wakenm0 */
+ <0 RK_PC2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m1_pins: pcie30x1m1-pins {
+ rockchip,pins =
+ /* pcie30x1_clkreqnm1 */
+ <2 RK_PD2 4 &pcfg_pull_none>,
+ /* pcie30x1_perstnm1 */
+ <3 RK_PA1 4 &pcfg_pull_none>,
+ /* pcie30x1_wakenm1 */
+ <2 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1m2_pins: pcie30x1m2-pins {
+ rockchip,pins =
+ /* pcie30x1_clkreqnm2 */
+ <1 RK_PA5 4 &pcfg_pull_none>,
+ /* pcie30x1_perstnm2 */
+ <1 RK_PA2 4 &pcfg_pull_none>,
+ /* pcie30x1_wakenm2 */
+ <1 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x1_buttonrstn: pcie30x1-buttonrstn {
+ rockchip,pins =
+ /* pcie30x1_buttonrstn */
+ <0 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie30x2 {
+ /omit-if-no-ref/
+ pcie30x2m0_pins: pcie30x2m0-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqnm0 */
+ <0 RK_PA6 2 &pcfg_pull_none>,
+ /* pcie30x2_perstnm0 */
+ <0 RK_PC6 3 &pcfg_pull_none>,
+ /* pcie30x2_wakenm0 */
+ <0 RK_PC5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m1_pins: pcie30x2m1-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqnm1 */
+ <2 RK_PD4 4 &pcfg_pull_none>,
+ /* pcie30x2_perstnm1 */
+ <2 RK_PD6 4 &pcfg_pull_none>,
+ /* pcie30x2_wakenm1 */
+ <2 RK_PD5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2m2_pins: pcie30x2m2-pins {
+ rockchip,pins =
+ /* pcie30x2_clkreqnm2 */
+ <4 RK_PC2 4 &pcfg_pull_none>,
+ /* pcie30x2_perstnm2 */
+ <4 RK_PC4 4 &pcfg_pull_none>,
+ /* pcie30x2_wakenm2 */
+ <4 RK_PC3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pcie30x2_buttonrstn: pcie30x2-buttonrstn {
+ rockchip,pins =
+ /* pcie30x2_buttonrstn */
+ <0 RK_PB0 3 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ /omit-if-no-ref/
+ pdmm0_clk: pdmm0-clk {
+ rockchip,pins =
+ /* pdm_clk0m0 */
+ <1 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_clk1: pdmm0-clk1 {
+ rockchip,pins =
+ /* pdmm0_clk1 */
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins =
+ /* pdmm0_sdi0 */
+ <1 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins =
+ /* pdmm0_sdi1 */
+ <1 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins =
+ /* pdmm0_sdi2 */
+ <1 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins =
+ /* pdmm0_sdi3 */
+ <1 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk: pdmm1-clk {
+ rockchip,pins =
+ /* pdm_clk0m1 */
+ <3 RK_PD6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_clk1: pdmm1-clk1 {
+ rockchip,pins =
+ /* pdmm1_clk1 */
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi0: pdmm1-sdi0 {
+ rockchip,pins =
+ /* pdmm1_sdi0 */
+ <3 RK_PD7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi1: pdmm1-sdi1 {
+ rockchip,pins =
+ /* pdmm1_sdi1 */
+ <4 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi2: pdmm1-sdi2 {
+ rockchip,pins =
+ /* pdmm1_sdi2 */
+ <4 RK_PA2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm1_sdi3: pdmm1-sdi3 {
+ rockchip,pins =
+ /* pdmm1_sdi3 */
+ <4 RK_PA3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_clk1: pdmm2-clk1 {
+ rockchip,pins =
+ /* pdmm2_clk1 */
+ <3 RK_PC4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi0: pdmm2-sdi0 {
+ rockchip,pins =
+ /* pdmm2_sdi0 */
+ <3 RK_PB3 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi1: pdmm2-sdi1 {
+ rockchip,pins =
+ /* pdmm2_sdi1 */
+ <3 RK_PB4 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi2: pdmm2-sdi2 {
+ rockchip,pins =
+ /* pdmm2_sdi2 */
+ <3 RK_PB7 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pdmm2_sdi3: pdmm2-sdi3 {
+ rockchip,pins =
+ /* pdmm2_sdi3 */
+ <3 RK_PC0 5 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ /omit-if-no-ref/
+ pmic_pins: pmic-pins {
+ rockchip,pins =
+ /* pmic_sleep */
+ <0 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ /omit-if-no-ref/
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug0 */
+ <0 RK_PA5 4 &pcfg_pull_none>,
+ /* pmu_debug1 */
+ <0 RK_PA6 3 &pcfg_pull_none>,
+ /* pmu_debug2 */
+ <0 RK_PC4 4 &pcfg_pull_none>,
+ /* pmu_debug3 */
+ <0 RK_PC5 4 &pcfg_pull_none>,
+ /* pmu_debug4 */
+ <0 RK_PC6 4 &pcfg_pull_none>,
+ /* pmu_debug5 */
+ <0 RK_PC7 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ /omit-if-no-ref/
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <0 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <0 RK_PC7 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ /omit-if-no-ref/
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <0 RK_PB5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ /omit-if-no-ref/
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <0 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <0 RK_PB6 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ /omit-if-no-ref/
+ pwm3_pins: pwm3-pins {
+ rockchip,pins =
+ /* pwm3_ir */
+ <0 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ /omit-if-no-ref/
+ pwm4_pins: pwm4-pins {
+ rockchip,pins =
+ /* pwm4 */
+ <0 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ /omit-if-no-ref/
+ pwm5_pins: pwm5-pins {
+ rockchip,pins =
+ /* pwm5 */
+ <0 RK_PC4 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ /omit-if-no-ref/
+ pwm6_pins: pwm6-pins {
+ rockchip,pins =
+ /* pwm6 */
+ <0 RK_PC5 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ /omit-if-no-ref/
+ pwm7_pins: pwm7-pins {
+ rockchip,pins =
+ /* pwm7_ir */
+ <0 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm8 {
+ /omit-if-no-ref/
+ pwm8m0_pins: pwm8m0-pins {
+ rockchip,pins =
+ /* pwm8_m0 */
+ <3 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm8m1_pins: pwm8m1-pins {
+ rockchip,pins =
+ /* pwm8_m1 */
+ <1 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm9 {
+ /omit-if-no-ref/
+ pwm9m0_pins: pwm9m0-pins {
+ rockchip,pins =
+ /* pwm9_m0 */
+ <3 RK_PB2 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm9m1_pins: pwm9m1-pins {
+ rockchip,pins =
+ /* pwm9_m1 */
+ <1 RK_PD6 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm10 {
+ /omit-if-no-ref/
+ pwm10m0_pins: pwm10m0-pins {
+ rockchip,pins =
+ /* pwm10_m0 */
+ <3 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm10m1_pins: pwm10m1-pins {
+ rockchip,pins =
+ /* pwm10_m1 */
+ <2 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm11 {
+ /omit-if-no-ref/
+ pwm11m0_pins: pwm11m0-pins {
+ rockchip,pins =
+ /* pwm11_irm0 */
+ <3 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm11m1_pins: pwm11m1-pins {
+ rockchip,pins =
+ /* pwm11_irm1 */
+ <4 RK_PC0 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm12 {
+ /omit-if-no-ref/
+ pwm12m0_pins: pwm12m0-pins {
+ rockchip,pins =
+ /* pwm12_m0 */
+ <3 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm12m1_pins: pwm12m1-pins {
+ rockchip,pins =
+ /* pwm12_m1 */
+ <4 RK_PC5 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm13 {
+ /omit-if-no-ref/
+ pwm13m0_pins: pwm13m0-pins {
+ rockchip,pins =
+ /* pwm13_m0 */
+ <3 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm13m1_pins: pwm13m1-pins {
+ rockchip,pins =
+ /* pwm13_m1 */
+ <4 RK_PC6 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm14 {
+ /omit-if-no-ref/
+ pwm14m0_pins: pwm14m0-pins {
+ rockchip,pins =
+ /* pwm14_m0 */
+ <3 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm14m1_pins: pwm14m1-pins {
+ rockchip,pins =
+ /* pwm14_m1 */
+ <4 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm15 {
+ /omit-if-no-ref/
+ pwm15m0_pins: pwm15m0-pins {
+ rockchip,pins =
+ /* pwm15_irm0 */
+ <3 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ pwm15m1_pins: pwm15m1-pins {
+ rockchip,pins =
+ /* pwm15_irm1 */
+ <4 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ refclk {
+ /omit-if-no-ref/
+ refclk_pins: refclk-pins {
+ rockchip,pins =
+ /* refclk_ou */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ sata {
+ /omit-if-no-ref/
+ sata_pins: sata-pins {
+ rockchip,pins =
+ /* sata_cpdet */
+ <0 RK_PA4 2 &pcfg_pull_none>,
+ /* sata_cppod */
+ <0 RK_PA6 1 &pcfg_pull_none>,
+ /* sata_mpswitch */
+ <0 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ sata0 {
+ /omit-if-no-ref/
+ sata0_pins: sata0-pins {
+ rockchip,pins =
+ /* sata0_actled */
+ <4 RK_PC6 3 &pcfg_pull_none>;
+ };
+ };
+
+ sata1 {
+ /omit-if-no-ref/
+ sata1_pins: sata1-pins {
+ rockchip,pins =
+ /* sata1_actled */
+ <4 RK_PC5 3 &pcfg_pull_none>;
+ };
+ };
+
+ sata2 {
+ /omit-if-no-ref/
+ sata2_pins: sata2-pins {
+ rockchip,pins =
+ /* sata2_actled */
+ <4 RK_PC4 3 &pcfg_pull_none>;
+ };
+ };
+
+ scr {
+ /omit-if-no-ref/
+ scr_pins: scr-pins {
+ rockchip,pins =
+ /* scr_clk */
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ /* scr_det */
+ <1 RK_PA7 3 &pcfg_pull_up>,
+ /* scr_io */
+ <1 RK_PA3 3 &pcfg_pull_up>,
+ /* scr_rst */
+ <1 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ /* sdmmc0_det */
+ <0 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc0_pwren: sdmmc0-pwren {
+ rockchip,pins =
+ /* sdmmc0_pwren */
+ <0 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ /* sdmmc1_det */
+ <2 RK_PB2 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc1_pwren: sdmmc1-pwren {
+ rockchip,pins =
+ /* sdmmc1_pwren */
+ <2 RK_PB1 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc2 {
+ /omit-if-no-ref/
+ sdmmc2m0_bus4: sdmmc2m0-bus4 {
+ rockchip,pins =
+ /* sdmmc2_d0m0 */
+ <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d1m0 */
+ <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d2m0 */
+ <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d3m0 */
+ <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_clk: sdmmc2m0-clk {
+ rockchip,pins =
+ /* sdmmc2_clkm0 */
+ <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_cmd: sdmmc2m0-cmd {
+ rockchip,pins =
+ /* sdmmc2_cmdm0 */
+ <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_det: sdmmc2m0-det {
+ rockchip,pins =
+ /* sdmmc2_detm0 */
+ <3 RK_PD4 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m0_pwren: sdmmc2m0-pwren {
+ rockchip,pins =
+ /* sdmmc2m0_pwren */
+ <3 RK_PD5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_bus4: sdmmc2m1-bus4 {
+ rockchip,pins =
+ /* sdmmc2_d0m1 */
+ <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d1m1 */
+ <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d2m1 */
+ <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc2_d3m1 */
+ <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_clk: sdmmc2m1-clk {
+ rockchip,pins =
+ /* sdmmc2_clkm1 */
+ <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_cmd: sdmmc2m1-cmd {
+ rockchip,pins =
+ /* sdmmc2_cmdm1 */
+ <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_det: sdmmc2m1-det {
+ rockchip,pins =
+ /* sdmmc2_detm1 */
+ <3 RK_PA7 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ sdmmc2m1_pwren: sdmmc2m1-pwren {
+ rockchip,pins =
+ /* sdmmc2m1_pwren */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ /omit-if-no-ref/
+ spdifm0_tx: spdifm0-tx {
+ rockchip,pins =
+ /* spdifm0_tx */
+ <1 RK_PA4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm1_tx: spdifm1-tx {
+ rockchip,pins =
+ /* spdifm1_tx */
+ <3 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spdifm2_tx: spdifm2-tx {
+ rockchip,pins =
+ /* spdifm2_tx */
+ <4 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ /omit-if-no-ref/
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clkm0 */
+ <0 RK_PB5 2 &pcfg_pull_none>,
+ /* spi0_misom0 */
+ <0 RK_PC5 2 &pcfg_pull_none>,
+ /* spi0_mosim0 */
+ <0 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs0: spi0m0-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m0 */
+ <0 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs1: spi0m0-cs1 {
+ rockchip,pins =
+ /* spi0_cs1m0 */
+ <0 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clkm1 */
+ <2 RK_PD3 3 &pcfg_pull_none>,
+ /* spi0_misom1 */
+ <2 RK_PD0 3 &pcfg_pull_none>,
+ /* spi0_mosim1 */
+ <2 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs0: spi0m1-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m1 */
+ <2 RK_PD2 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi1 {
+ /omit-if-no-ref/
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clkm0 */
+ <2 RK_PB5 3 &pcfg_pull_none>,
+ /* spi1_misom0 */
+ <2 RK_PB6 3 &pcfg_pull_none>,
+ /* spi1_mosim0 */
+ <2 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs0: spi1m0-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m0 */
+ <2 RK_PC0 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs1: spi1m0-cs1 {
+ rockchip,pins =
+ /* spi1_cs1m0 */
+ <2 RK_PC6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clkm1 */
+ <3 RK_PC3 3 &pcfg_pull_none>,
+ /* spi1_misom1 */
+ <3 RK_PC2 3 &pcfg_pull_none>,
+ /* spi1_mosim1 */
+ <3 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs0: spi1m1-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m1 */
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi2 {
+ /omit-if-no-ref/
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clkm0 */
+ <2 RK_PC1 4 &pcfg_pull_none>,
+ /* spi2_misom0 */
+ <2 RK_PC2 4 &pcfg_pull_none>,
+ /* spi2_mosim0 */
+ <2 RK_PC3 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs0: spi2m0-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m0 */
+ <2 RK_PC4 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs1: spi2m0-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m0 */
+ <2 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clkm1 */
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ /* spi2_misom1 */
+ <2 RK_PD7 3 &pcfg_pull_none>,
+ /* spi2_mosim1 */
+ <2 RK_PD6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs0: spi2m1-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m1 */
+ <2 RK_PD5 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs1: spi2m1-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m1 */
+ <2 RK_PD4 3 &pcfg_pull_none>;
+ };
+ };
+
+ spi3 {
+ /omit-if-no-ref/
+ spi3m0_pins: spi3m0-pins {
+ rockchip,pins =
+ /* spi3_clkm0 */
+ <4 RK_PB3 4 &pcfg_pull_none>,
+ /* spi3_misom0 */
+ <4 RK_PB0 4 &pcfg_pull_none>,
+ /* spi3_mosim0 */
+ <4 RK_PB2 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs0: spi3m0-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m0 */
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs1: spi3m0-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m0 */
+ <4 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_pins: spi3m1-pins {
+ rockchip,pins =
+ /* spi3_clkm1 */
+ <4 RK_PC2 2 &pcfg_pull_none>,
+ /* spi3_misom1 */
+ <4 RK_PC5 2 &pcfg_pull_none>,
+ /* spi3_mosim1 */
+ <4 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs0: spi3m1-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m1 */
+ <4 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs1: spi3m1-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m1 */
+ <4 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc {
+ /omit-if-no-ref/
+ tsadcm0_shut: tsadcm0-shut {
+ rockchip,pins =
+ /* tsadcm0_shut */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadcm1_shut: tsadcm1-shut {
+ rockchip,pins =
+ /* tsadcm1_shut */
+ <0 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ tsadc_shutorg: tsadc-shutorg {
+ rockchip,pins =
+ /* tsadc_shutorg */
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <0 RK_PC0 3 &pcfg_pull_up>,
+ /* uart0_tx */
+ <0 RK_PC1 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ /* uart0_ctsn */
+ <0 RK_PC7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ /* uart0_rtsn */
+ <0 RK_PC4 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rxm0 */
+ <2 RK_PB3 2 &pcfg_pull_up>,
+ /* uart1_txm0 */
+ <2 RK_PB4 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <2 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <2 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rxm1 */
+ <3 RK_PD7 4 &pcfg_pull_up>,
+ /* uart1_txm1 */
+ <3 RK_PD6 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <4 RK_PC1 4 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <4 RK_PB6 4 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ /omit-if-no-ref/
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rxm0 */
+ <0 RK_PD0 1 &pcfg_pull_up>,
+ /* uart2_txm0 */
+ <0 RK_PD1 1 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rxm1 */
+ <1 RK_PD6 2 &pcfg_pull_up>,
+ /* uart2_txm1 */
+ <1 RK_PD5 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rxm0 */
+ <1 RK_PA0 2 &pcfg_pull_up>,
+ /* uart3_txm0 */
+ <1 RK_PA1 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_ctsn: uart3m0-ctsn {
+ rockchip,pins =
+ /* uart3m0_ctsn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m0_rtsn: uart3m0-rtsn {
+ rockchip,pins =
+ /* uart3m0_rtsn */
+ <1 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rxm1 */
+ <3 RK_PC0 4 &pcfg_pull_up>,
+ /* uart3_txm1 */
+ <3 RK_PB7 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rxm0 */
+ <1 RK_PA4 2 &pcfg_pull_up>,
+ /* uart4_txm0 */
+ <1 RK_PA6 2 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_ctsn: uart4m0-ctsn {
+ rockchip,pins =
+ /* uart4m0_ctsn */
+ <1 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m0_rtsn: uart4m0-rtsn {
+ rockchip,pins =
+ /* uart4m0_rtsn */
+ <1 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart4m1_xfer: uart4m1-xfer {
+ rockchip,pins =
+ /* uart4_rxm1 */
+ <3 RK_PB1 4 &pcfg_pull_up>,
+ /* uart4_txm1 */
+ <3 RK_PB2 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rxm0 */
+ <2 RK_PA1 3 &pcfg_pull_up>,
+ /* uart5_txm0 */
+ <2 RK_PA2 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <1 RK_PD7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rxm1 */
+ <3 RK_PC3 4 &pcfg_pull_up>,
+ /* uart5_txm1 */
+ <3 RK_PC2 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart6 {
+ /omit-if-no-ref/
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rxm0 */
+ <2 RK_PA3 3 &pcfg_pull_up>,
+ /* uart6_txm0 */
+ <2 RK_PA4 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_ctsn: uart6m0-ctsn {
+ rockchip,pins =
+ /* uart6m0_ctsn */
+ <2 RK_PC0 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m0_rtsn: uart6m0-rtsn {
+ rockchip,pins =
+ /* uart6m0_rtsn */
+ <2 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rxm1 */
+ <1 RK_PD6 3 &pcfg_pull_up>,
+ /* uart6_txm1 */
+ <1 RK_PD5 3 &pcfg_pull_up>;
+ };
+ };
+
+ uart7 {
+ /omit-if-no-ref/
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rxm0 */
+ <2 RK_PA5 3 &pcfg_pull_up>,
+ /* uart7_txm0 */
+ <2 RK_PA6 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <2 RK_PC2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <2 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rxm1 */
+ <3 RK_PC5 4 &pcfg_pull_up>,
+ /* uart7_txm1 */
+ <3 RK_PC4 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart7m2_xfer: uart7m2-xfer {
+ rockchip,pins =
+ /* uart7_rxm2 */
+ <4 RK_PA3 4 &pcfg_pull_up>,
+ /* uart7_txm2 */
+ <4 RK_PA2 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ /omit-if-no-ref/
+ uart8m0_xfer: uart8m0-xfer {
+ rockchip,pins =
+ /* uart8_rxm0 */
+ <2 RK_PC6 2 &pcfg_pull_up>,
+ /* uart8_txm0 */
+ <2 RK_PC5 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_ctsn: uart8m0-ctsn {
+ rockchip,pins =
+ /* uart8m0_ctsn */
+ <2 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m0_rtsn: uart8m0-rtsn {
+ rockchip,pins =
+ /* uart8m0_rtsn */
+ <2 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart8m1_xfer: uart8m1-xfer {
+ rockchip,pins =
+ /* uart8_rxm1 */
+ <3 RK_PA0 4 &pcfg_pull_up>,
+ /* uart8_txm1 */
+ <2 RK_PD7 4 &pcfg_pull_up>;
+ };
+ };
+
+ uart9 {
+ /omit-if-no-ref/
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rxm0 */
+ <2 RK_PA7 3 &pcfg_pull_up>,
+ /* uart9_txm0 */
+ <2 RK_PB0 3 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_ctsn: uart9m0-ctsn {
+ rockchip,pins =
+ /* uart9m0_ctsn */
+ <2 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m0_rtsn: uart9m0-rtsn {
+ rockchip,pins =
+ /* uart9m0_rtsn */
+ <2 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ uart9m1_xfer: uart9m1-xfer {
+ rockchip,pins =
+ /* uart9_rxm1 */
+ <4 RK_PC6 4 &pcfg_pull_up>,
+ /* uart9_txm1 */
+ <4 RK_PC5 4 &pcfg_pull_up>;
+ };
+
+ /omit-if-no-ref/
+ uart9m2_xfer: uart9m2-xfer {
+ rockchip,pins =
+ /* uart9_rxm2 */
+ <4 RK_PA5 4 &pcfg_pull_up>,
+ /* uart9_txm2 */
+ <4 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+
+ vop {
+ /omit-if-no-ref/
+ vopm0_pins: vopm0-pins {
+ rockchip,pins =
+ /* vop_pwmm0 */
+ <0 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ vopm1_pins: vopm1-pins {
+ rockchip,pins =
+ /* vop_pwmm1 */
+ <3 RK_PC4 2 &pcfg_pull_none>;
+ };
+ };
+};
+
+/*
+ * This part is edited handly.
+ */
+&pinctrl {
+ spi0-hs {
+ /omit-if-no-ref/
+ spi0m0_pins_hs: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clkm0 */
+ <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>,
+ /* spi0_misom0 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosim0 */
+ <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs0_hs: spi0m0-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m0 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m0_cs1_hs: spi0m0-cs1 {
+ rockchip,pins =
+ /* spi0_cs1m0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_pins_hs: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clkm1 */
+ <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>,
+ /* spi0_misom1 */
+ <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>,
+ /* spi0_mosim1 */
+ <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi0m1_cs0_hs: spi0m1-cs0 {
+ rockchip,pins =
+ /* spi0_cs0m1 */
+ <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi1-hs {
+ /omit-if-no-ref/
+ spi1m0_pins_hs: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clkm0 */
+ <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_misom0 */
+ <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosim0 */
+ <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs0_hs: spi1m0-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m0 */
+ <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m0_cs1_hs: spi1m0-cs1 {
+ rockchip,pins =
+ /* spi1_cs1m0 */
+ <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_pins_hs: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clkm1 */
+ <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_misom1 */
+ <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>,
+ /* spi1_mosim1 */
+ <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi1m1_cs0_hs: spi1m1-cs0 {
+ rockchip,pins =
+ /* spi1_cs0m1 */
+ <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi2-hs {
+ /omit-if-no-ref/
+ spi2m0_pins_hs: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clkm0 */
+ <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>,
+ /* spi2_misom0 */
+ <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosim0 */
+ <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs0_hs: spi2m0-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m0 */
+ <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m0_cs1_hs: spi2m0-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m0 */
+ <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_pins_hs: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clkm1 */
+ <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>,
+ /* spi2_misom1 */
+ <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>,
+ /* spi2_mosim1 */
+ <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs0_hs: spi2m1-cs0 {
+ rockchip,pins =
+ /* spi2_cs0m1 */
+ <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi2m1_cs1_hs: spi2m1-cs1 {
+ rockchip,pins =
+ /* spi2_cs1m1 */
+ <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ spi3-hs {
+ /omit-if-no-ref/
+ spi3m0_pins_hs: spi3m0-pins {
+ rockchip,pins =
+ /* spi3_clkm0 */
+ <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>,
+ /* spi3_misom0 */
+ <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosim0 */
+ <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs0_hs: spi3m0-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m0 */
+ <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m0_cs1_hs: spi3m0-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m0 */
+ <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_pins_hs: spi3m1-pins {
+ rockchip,pins =
+ /* spi3_clkm1 */
+ <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>,
+ /* spi3_misom1 */
+ <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>,
+ /* spi3_mosim1 */
+ <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs0_hs: spi3m1-cs0 {
+ rockchip,pins =
+ /* spi3_cs0m1 */
+ <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>;
+ };
+
+ /omit-if-no-ref/
+ spi3m1_cs1_hs: spi3m1-cs1 {
+ rockchip,pins =
+ /* spi3_cs1m1 */
+ <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>;
+ };
+ };
+
+ gmac-txd-level3 {
+ /omit-if-no-ref/
+ gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 {
+ rockchip,pins =
+ /* gmac0_txd0 */
+ <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
+ /* gmac0_txd1 */
+ <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
+ /* gmac0_txen */
+ <2 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 {
+ rockchip,pins =
+ /* gmac0_rxd2 */
+ <2 RK_PA3 2 &pcfg_pull_none>,
+ /* gmac0_rxd3 */
+ <2 RK_PA4 2 &pcfg_pull_none>,
+ /* gmac0_txd2 */
+ <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>,
+ /* gmac0_txd3 */
+ <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 {
+ rockchip,pins =
+ /* gmac1_txd0m0 */
+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd1m0 */
+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txenm0 */
+ <3 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 {
+ rockchip,pins =
+ /* gmac1_rxd2m0 */
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m0 */
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ /* gmac1_txd2m0 */
+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd3m0 */
+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 {
+ rockchip,pins =
+ /* gmac1_txd0m1 */
+ <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd1m1 */
+ <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txenm1 */
+ <4 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 {
+ rockchip,pins =
+ /* gmac1_rxd2m1 */
+ <4 RK_PA1 3 &pcfg_pull_none>,
+ /* gmac1_rxd3m1 */
+ <4 RK_PA2 3 &pcfg_pull_none>,
+ /* gmac1_txd2m1 */
+ <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>,
+ /* gmac1_txd3m1 */
+ <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>;
+ };
+ };
+
+ gmac-txc-level2 {
+ /omit-if-no-ref/
+ gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 {
+ rockchip,pins =
+ /* gmac0_rxclk */
+ <2 RK_PA5 2 &pcfg_pull_none>,
+ /* gmac0_txclk */
+ <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 {
+ rockchip,pins =
+ /* gmac1_rxclkm0 */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* gmac1_txclkm0 */
+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>;
+ };
+
+ /omit-if-no-ref/
+ gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 {
+ rockchip,pins =
+ /* gmac1_rxclkm1 */
+ <4 RK_PA3 3 &pcfg_pull_none>,
+ /* gmac1_txclkm1 */
+ <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>;
+ };
+ };
+};
diff --git a/src/arm64/rockchip/rk3568.dtsi b/src/arm64/rockchip/rk3568.dtsi
new file mode 100644
index 0000000..d225e6a
--- /dev/null
+++ b/src/arm64/rockchip/rk3568.dtsi
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rk3568-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "rockchip,rk3568";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ clocks = <&scmi_clk 0>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ clock-latency-ns = <40000>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ opp-suspend;
+ };
+
+ opp-1104000000 {
+ opp-hz = /bits/ 64 <1104000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <900000 900000 1150000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <975000 975000 1150000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1050000 1050000 1150000>;
+ };
+
+ opp-1992000000 {
+ opp-hz = /bits/ 64 <1992000000>;
+ opp-microvolt = <1150000 1150000 1150000>;
+ };
+ };
+
+ firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ arm,smc-id = <0x82000010>;
+ shmem = <&scmi_shmem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a55-pmu";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ arm,no-tick-in-suspend;
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ pinctrl-0 = <&clk32k_out0>;
+ pinctrl-names = "default";
+ #clock-cells = <0>;
+ };
+
+ sram@10f000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x0010f000 0x100>;
+
+ scmi_shmem: sram@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x100>;
+ };
+ };
+
+ gic: interrupt-controller@fd400000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
+ <0x0 0xfd460000 0 0x80000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ mbi-alias = <0x0 0xfd100000>;
+ mbi-ranges = <296 24>;
+ msi-controller;
+ };
+
+ pmugrf: syscon@fdc20000 {
+ compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
+ reg = <0x0 0xfdc20000 0x0 0x10000>;
+ };
+
+ grf: syscon@fdc60000 {
+ compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xfdc60000 0x0 0x10000>;
+ };
+
+ pmucru: clock-controller@fdd00000 {
+ compatible = "rockchip,rk3568-pmucru";
+ reg = <0x0 0xfdd00000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@fdd20000 {
+ compatible = "rockchip,rk3568-cru";
+ reg = <0x0 0xfdd20000 0x0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ i2c0: i2c@fdd40000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfdd40000 0x0 0x1000>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@fdd50000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfdd50000 0x0 0x100>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 0>, <&dmac0 1>;
+ pinctrl-0 = <&uart0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ sdmmc2: mmc@fe000000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe000000 0x0 0x4000>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
+ <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC2>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc0: mmc@fe2b0000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC0>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@fe2c0000 {
+ compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xfe2c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <150000000>;
+ resets = <&cru SRST_SDMMC1>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdhci: mmc@fe310000 {
+ compatible = "rockchip,rk3568-dwcmshc";
+ reg = <0x0 0xfe310000 0x0 0x10000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>;
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ status = "disabled";
+ };
+
+ dmac0: dmac@fe530000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfe530000 0x0 0x4000>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_BUS>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ dmac1: dmac@fe550000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xfe550000 0x0 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_BUS>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ };
+
+ i2c1: i2c@fe5a0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5a0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c1_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe5b0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5b0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe5c0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@fe5d0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5d0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@fe5e0000 {
+ compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xfe5e0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart1: serial@fe650000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe650000 0x0 0x100>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 2>, <&dmac0 3>;
+ pinctrl-0 = <&uart1m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@fe660000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe660000 0x0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 4>, <&dmac0 5>;
+ pinctrl-0 = <&uart2m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart3: serial@fe670000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe670000 0x0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 6>, <&dmac0 7>;
+ pinctrl-0 = <&uart3m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@fe680000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe680000 0x0 0x100>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 8>, <&dmac0 9>;
+ pinctrl-0 = <&uart4m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@fe690000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe690000 0x0 0x100>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 10>, <&dmac0 11>;
+ pinctrl-0 = <&uart5m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart6: serial@fe6a0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 12>, <&dmac0 13>;
+ pinctrl-0 = <&uart6m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart7: serial@fe6b0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6b0000 0x0 0x100>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 14>, <&dmac0 15>;
+ pinctrl-0 = <&uart7m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart8: serial@fe6c0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6c0000 0x0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 16>, <&dmac0 17>;
+ pinctrl-0 = <&uart8m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart9: serial@fe6d0000 {
+ compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xfe6d0000 0x0 0x100>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac0 18>, <&dmac0 19>;
+ pinctrl-0 = <&uart9m0_xfer>;
+ pinctrl-names = "default";
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3568-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@fdd60000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfdd60000 0x0 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@fe740000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe740000 0x0 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@fe750000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe750000 0x0 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@fe760000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe760000 0x0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@fe770000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xfe770000 0x0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rk3568-pinctrl.dtsi"
diff --git a/src/arm64/rockchip/rockchip-pinconf.dtsi b/src/arm64/rockchip/rockchip-pinconf.dtsi
new file mode 100644
index 0000000..5c64543
--- /dev/null
+++ b/src/arm64/rockchip/rockchip-pinconf.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+&pinctrl {
+ /omit-if-no-ref/
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+ bias-disable;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+ bias-disable;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+ bias-disable;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
+ bias-disable;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
+ bias-disable;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
+ bias-disable;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
+ bias-disable;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
+ bias-disable;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
+ bias-disable;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
+ bias-disable;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
+ bias-disable;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
+ bias-disable;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+ bias-pull-up;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+ bias-pull-up;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
+ bias-pull-up;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
+ bias-pull-up;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
+ bias-pull-up;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
+ bias-pull-up;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
+ bias-pull-up;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
+ bias-pull-up;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
+ bias-pull-up;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
+ bias-pull-up;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
+ bias-pull-up;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
+ bias-pull-down;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
+ bias-pull-down;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
+ bias-pull-down;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
+ bias-pull-down;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
+ bias-pull-down;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
+ bias-pull-down;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
+ bias-pull-down;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
+ bias-pull-down;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
+ bias-pull-down;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
+ bias-pull-down;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
+ bias-pull-down;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
+ bias-pull-down;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
+ bias-pull-down;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
+ bias-pull-down;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
+ bias-pull-down;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_smt: pcfg-pull-up-smt {
+ bias-pull-up;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down_smt: pcfg-pull-down-smt {
+ bias-pull-down;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_smt: pcfg-pull-none-smt {
+ bias-disable;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
+ bias-disable;
+ drive-strength = <0>;
+ input-schmitt-enable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ /omit-if-no-ref/
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+};
diff --git a/src/arm64/ti/k3-am64-main.dtsi b/src/arm64/ti/k3-am64-main.dtsi
index ca59d1f..02c3fdf 100644
--- a/src/arm64/ti/k3-am64-main.dtsi
+++ b/src/arm64/ti/k3-am64-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
oc_sram: sram@70000000 {
compatible = "mmio-sram";
@@ -13,8 +24,30 @@
#size-cells = <1>;
ranges = <0x0 0x00 0x70000000 0x200000>;
- atf-sram@0 {
- reg = <0x0 0x1a000>;
+ tfa-sram@1c0000 {
+ reg = <0x1c0000 0x20000>;
+ };
+
+ dmsc-sram@1e0000 {
+ reg = <0x1e0000 0x1c000>;
+ };
+
+ sproxy-sram@1fc000 {
+ reg = <0x1fc000 0x4000>;
+ };
+ };
+
+ main_conf: syscon@43000000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x0 0x43000000 0x0 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x43000000 0x20000>;
+
+ serdes_ln_ctrl: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */
};
};
@@ -189,8 +222,6 @@
main_uart0: serial@2800000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -202,8 +233,6 @@
main_uart1: serial@2810000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -215,8 +244,6 @@
main_uart2: serial@2820000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -228,8 +255,6 @@
main_uart3: serial@2830000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -241,8 +266,6 @@
main_uart4: serial@2840000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -254,8 +277,6 @@
main_uart5: serial@2850000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -267,8 +288,6 @@
main_uart6: serial@2860000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -489,7 +508,8 @@
ti,mac-only;
label = "port1";
phys = <&phy_gmii_sel 1>;
- mac-address = [00 00 de ad be ef];
+ mac-address = [00 00 00 00 00 00];
+ ti,syscon-efuse = <&main_conf 0x200>;
};
cpsw_port2: port@2 {
@@ -497,7 +517,7 @@
ti,mac-only;
label = "port2";
phys = <&phy_gmii_sel 2>;
- mac-address = [00 01 de ad be ef];
+ mac-address = [00 00 00 00 00 00];
};
};
@@ -673,4 +693,170 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
};
+
+ main_r5fss0: r5fss@78000000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x78000000 0x00 0x78000000 0x10000>,
+ <0x78100000 0x00 0x78100000 0x10000>,
+ <0x78200000 0x00 0x78200000 0x08000>,
+ <0x78300000 0x00 0x78300000 0x08000>;
+ power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss0_core0: r5f@78000000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78000000 0x00010000>,
+ <0x78100000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <121>;
+ ti,sci-proc-ids = <0x01 0xff>;
+ resets = <&k3_reset 121 1>;
+ firmware-name = "am64-main-r5f0_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss0_core1: r5f@78200000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78200000 0x00008000>,
+ <0x78300000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <122>;
+ ti,sci-proc-ids = <0x02 0xff>;
+ resets = <&k3_reset 122 1>;
+ firmware-name = "am64-main-r5f0_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ main_r5fss1: r5fss@78400000 {
+ compatible = "ti,am64-r5fss";
+ ti,cluster-mode = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x78400000 0x00 0x78400000 0x10000>,
+ <0x78500000 0x00 0x78500000 0x10000>,
+ <0x78600000 0x00 0x78600000 0x08000>,
+ <0x78700000 0x00 0x78700000 0x08000>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+
+ main_r5fss1_core0: r5f@78400000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78400000 0x00010000>,
+ <0x78500000 0x00010000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <123>;
+ ti,sci-proc-ids = <0x06 0xff>;
+ resets = <&k3_reset 123 1>;
+ firmware-name = "am64-main-r5f1_0-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+
+ main_r5fss1_core1: r5f@78600000 {
+ compatible = "ti,am64-r5f";
+ reg = <0x78600000 0x00008000>,
+ <0x78700000 0x00008000>;
+ reg-names = "atcm", "btcm";
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <124>;
+ ti,sci-proc-ids = <0x07 0xff>;
+ resets = <&k3_reset 124 1>;
+ firmware-name = "am64-main-r5f1_1-fw";
+ ti,atcm-enable = <1>;
+ ti,btcm-enable = <1>;
+ ti,loczrama = <1>;
+ };
+ };
+
+ serdes_wiz0: wiz@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+
+ assigned-clocks = <&k3_clks 162 1>;
+ assigned-clock-parents = <&k3_clks 162 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 162 1>,
+ <&k3_clks 162 1>,
+ <&k3_clks 162 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pcie0_rc: pcie@f102000 {
+ compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>;
+ clock-names = "fck", "pcie_refclk";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = <0x104c>;
+ device-id = <0xb010>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
+ <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
+ };
+
+ pcie0_ep: pcie-ep@f102000 {
+ compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x0f102000 0x00 0x1000>,
+ <0x00 0x0f100000 0x00 0x400>,
+ <0x00 0x0d000000 0x00 0x00800000>,
+ <0x00 0x68000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&main_conf 0x4070>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <1>;
+ };
};
diff --git a/src/arm64/ti/k3-am64-mcu.dtsi b/src/arm64/ti/k3-am64-mcu.dtsi
index deb19ae..59cc58f 100644
--- a/src/arm64/ti/k3-am64-mcu.dtsi
+++ b/src/arm64/ti/k3-am64-mcu.dtsi
@@ -9,8 +9,6 @@
mcu_uart0: serial@4a00000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -22,8 +20,6 @@
mcu_uart1: serial@4a10000 {
compatible = "ti,am64-uart", "ti,am654-uart";
reg = <0x00 0x04a10000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -87,7 +83,7 @@
};
mcu_gpio0: gpio@4201000 {
- compatible = "ti,am64-gpio", "keystone-gpio";
+ compatible = "ti,am64-gpio", "ti,keystone-gpio";
reg = <0x0 0x4201000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
diff --git a/src/arm64/ti/k3-am642-evm.dts b/src/arm64/ti/k3-am642-evm.dts
index dad0efa..0307122 100644
--- a/src/arm64/ti/k3-am642-evm.dts
+++ b/src/arm64/ti/k3-am642-evm.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/ti-serdes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
@@ -36,6 +38,60 @@
alignment = <0x1000>;
no-map;
};
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a5000000 {
+ reg = <0x00 0xa5000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
evm_12v0: fixedregulator-evm12v0 {
@@ -334,7 +390,7 @@
&main_spi0 {
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
eeprom@0 {
compatible = "microchip,93lc46b";
reg = <0>;
@@ -466,3 +522,55 @@
&mailbox0_cluster7 {
status = "disabled";
};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_PCIE0>;
+};
+
+&serdes0 {
+ serdes0_pcie_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_PCIE>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&pcie0_rc {
+ reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie0_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
diff --git a/src/arm64/ti/k3-am642-sk.dts b/src/arm64/ti/k3-am642-sk.dts
index 8424cd0..d3aa290 100644
--- a/src/arm64/ti/k3-am642-sk.dts
+++ b/src/arm64/ti/k3-am642-sk.dts
@@ -5,6 +5,8 @@
/dts-v1/;
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/net/ti-dp83867.h>
#include "k3-am642.dtsi"
@@ -35,6 +37,60 @@
alignment = <0x1000>;
no-map;
};
+
+ main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa0100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa1100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa2100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3000000 0x00 0x100000>;
+ no-map;
+ };
+
+ main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
+ compatible = "shared-dma-pool";
+ reg = <0x00 0xa3100000 0x00 0xf00000>;
+ no-map;
+ };
+
+ rtos_ipc_memory_region: ipc-memories@a5000000 {
+ reg = <0x00 0xa5000000 0x00 0x00800000>;
+ alignment = <0x1000>;
+ no-map;
+ };
};
vusb_main: fixed-regulator-vusb-main5v0 {
@@ -85,6 +141,12 @@
>;
};
+ main_usb0_pins_default: main-usb0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+ >;
+ };
+
main_i2c1_pins_default: main-i2c1-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
@@ -235,6 +297,33 @@
disable-wp;
};
+&serdes_ln_ctrl {
+ idle-states = <AM64_SERDES0_LANE0_USB>;
+};
+
+&serdes0 {
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usbss0 {
+ ti,vbus-divider;
+};
+
+&usb0 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb0_pins_default>;
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
+
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
@@ -332,3 +421,35 @@
&mailbox0_cluster7 {
status = "disabled";
};
+
+&main_r5fss0_core0 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>;
+ memory-region = <&main_r5fss0_core0_dma_memory_region>,
+ <&main_r5fss0_core0_memory_region>;
+};
+
+&main_r5fss0_core1 {
+ mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>;
+ memory-region = <&main_r5fss0_core1_dma_memory_region>,
+ <&main_r5fss0_core1_memory_region>;
+};
+
+&main_r5fss1_core0 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>;
+ memory-region = <&main_r5fss1_core0_dma_memory_region>,
+ <&main_r5fss1_core0_memory_region>;
+};
+
+&main_r5fss1_core1 {
+ mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>;
+ memory-region = <&main_r5fss1_core1_dma_memory_region>,
+ <&main_r5fss1_core1_memory_region>;
+};
+
+&pcie0_rc {
+ status = "disabled";
+};
+
+&pcie0_ep {
+ status = "disabled";
+};
diff --git a/src/arm64/ti/k3-am65-iot2050-common.dtsi b/src/arm64/ti/k3-am65-iot2050-common.dtsi
index de763ca..1008e91 100644
--- a/src/arm64/ti/k3-am65-iot2050-common.dtsi
+++ b/src/arm64/ti/k3-am65-iot2050-common.dtsi
@@ -555,6 +555,7 @@
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
disable-wp;
+ no-1-8-v;
};
&usb0 {
@@ -575,7 +576,7 @@
#address-cells = <1>;
#size-cells= <0>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
};
&tscadc0 {
@@ -653,3 +654,63 @@
&pcie1_ep {
status = "disabled";
};
+
+&mailbox0_cluster0 {
+ status = "disabled";
+};
+
+&mailbox0_cluster1 {
+ status = "disabled";
+};
+
+&mailbox0_cluster2 {
+ status = "disabled";
+};
+
+&mailbox0_cluster3 {
+ status = "disabled";
+};
+
+&mailbox0_cluster4 {
+ status = "disabled";
+};
+
+&mailbox0_cluster5 {
+ status = "disabled";
+};
+
+&mailbox0_cluster6 {
+ status = "disabled";
+};
+
+&mailbox0_cluster7 {
+ status = "disabled";
+};
+
+&mailbox0_cluster8 {
+ status = "disabled";
+};
+
+&mailbox0_cluster9 {
+ status = "disabled";
+};
+
+&mailbox0_cluster10 {
+ status = "disabled";
+};
+
+&mailbox0_cluster11 {
+ status = "disabled";
+};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
+
+&icssg2_mdio {
+ status = "disabled";
+};
diff --git a/src/arm64/ti/k3-am65-main.dtsi b/src/arm64/ti/k3-am65-main.dtsi
index 6cd3131..ba4e5d3 100644
--- a/src/arm64/ti/k3-am65-main.dtsi
+++ b/src/arm64/ti/k3-am65-main.dtsi
@@ -84,8 +84,6 @@
main_uart0: serial@2800000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -95,8 +93,6 @@
main_uart1: serial@2810000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
@@ -105,8 +101,6 @@
main_uart2: serial@2820000 {
compatible = "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
@@ -301,7 +295,6 @@
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
- no-1-8-v;
};
scm_conf: scm-conf@100000 {
@@ -1053,6 +1046,16 @@
reg-names = "iram", "control", "debug";
firmware-name = "am65x-txpru0_1-fw";
};
+
+ icssg0_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 62 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
icssg1: icssg@b100000 {
@@ -1184,6 +1187,16 @@
reg-names = "iram", "control", "debug";
firmware-name = "am65x-txpru1_1-fw";
};
+
+ icssg1_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 63 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
icssg2: icssg@b200000 {
@@ -1315,5 +1328,15 @@
reg-names = "iram", "control", "debug";
firmware-name = "am65x-txpru2_1-fw";
};
+
+ icssg2_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 64 3>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
};
diff --git a/src/arm64/ti/k3-am65-mcu.dtsi b/src/arm64/ti/k3-am65-mcu.dtsi
index f5b8ef2..c93ff15 100644
--- a/src/arm64/ti/k3-am65-mcu.dtsi
+++ b/src/arm64/ti/k3-am65-mcu.dtsi
@@ -23,8 +23,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
diff --git a/src/arm64/ti/k3-am65-wakeup.dtsi b/src/arm64/ti/k3-am65-wakeup.dtsi
index 7cb864b..9d21cdf 100644
--- a/src/arm64/ti/k3-am65-wakeup.dtsi
+++ b/src/arm64/ti/k3-am65-wakeup.dtsi
@@ -50,8 +50,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,am654-uart";
reg = <0x42300000 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
diff --git a/src/arm64/ti/k3-am6528-iot2050-basic.dts b/src/arm64/ti/k3-am6528-iot2050-basic.dts
index 4f7e3f2..94bb5dd 100644
--- a/src/arm64/ti/k3-am6528-iot2050-basic.dts
+++ b/src/arm64/ti/k3-am6528-iot2050-basic.dts
@@ -59,3 +59,8 @@
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
+
+&mcu_r5fss0 {
+ /* lock-step mode not supported on this board */
+ ti,cluster-mode = <0>;
+};
diff --git a/src/arm64/ti/k3-am654-base-board.dts b/src/arm64/ti/k3-am654-base-board.dts
index eddb2ff..cfbcebf 100644
--- a/src/arm64/ti/k3-am654-base-board.dts
+++ b/src/arm64/ti/k3-am654-base-board.dts
@@ -85,6 +85,38 @@
gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>;
};
};
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main supply */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vcc3v3_io: fixedregulator-vcc3v3io {
+ /* Output of TPS54334 */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_io";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&evm_12v0>;
+ };
+
+ vdd_mmc1_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vcc3v3_io>;
+ gpio = <&pca9554 4 GPIO_ACTIVE_HIGH>;
+ };
};
&wkup_pmx0 {
@@ -136,7 +168,7 @@
AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
- AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
+ AM65X_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* (N1) MCU_RGMII1_TXC */
AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
>;
};
@@ -299,7 +331,7 @@
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
#size-cells= <0>;
- ti,pindir-d0-out-d1-in = <1>;
+ ti,pindir-d0-out-d1-in;
flash@0{
compatible = "jedec,spi-nor";
@@ -327,6 +359,7 @@
* disable sdhci1
*/
&sdhci1 {
+ vmmc-supply = <&vdd_mmc1_sd>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
@@ -506,3 +539,15 @@
&dss {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
+
+&icssg2_mdio {
+ status = "disabled";
+};
diff --git a/src/arm64/ti/k3-j7200-common-proc-board.dts b/src/arm64/ti/k3-j7200-common-proc-board.dts
index bedd01b..d14f3c1 100644
--- a/src/arm64/ti/k3-j7200-common-proc-board.dts
+++ b/src/arm64/ti/k3-j7200-common-proc-board.dts
@@ -90,7 +90,7 @@
J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
diff --git a/src/arm64/ti/k3-j7200-main.dtsi b/src/arm64/ti/k3-j7200-main.dtsi
index 19fea8a..e8a41d0 100644
--- a/src/arm64/ti/k3-j7200-main.dtsi
+++ b/src/arm64/ti/k3-j7200-main.dtsi
@@ -301,8 +301,6 @@
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -314,8 +312,6 @@
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -327,8 +323,6 @@
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -340,8 +334,6 @@
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -353,8 +345,6 @@
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -366,8 +356,6 @@
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -379,8 +367,6 @@
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -392,8 +378,6 @@
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -405,8 +389,6 @@
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -418,8 +400,6 @@
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -683,6 +663,7 @@
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
+ cdns,phyrst-a-enable;
};
};
@@ -696,7 +677,6 @@
<149>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
@@ -714,7 +694,6 @@
<158>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
@@ -732,7 +711,6 @@
<167>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
@@ -750,7 +728,6 @@
<176>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <69>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
diff --git a/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
index 5663fe3..1044ec6 100644
--- a/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
@@ -73,8 +73,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -86,8 +84,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
@@ -117,7 +113,6 @@
interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <85>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
@@ -134,7 +129,6 @@
interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
interrupt-controller;
#interrupt-cells = <2>;
- #address-cells = <0>;
ti,ngpio = <85>;
ti,davinci-gpio-unbanked = <0>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
diff --git a/src/arm64/ti/k3-j721e-common-proc-board.dts b/src/arm64/ti/k3-j721e-common-proc-board.dts
index 6076436..8bd02d9 100644
--- a/src/arm64/ti/k3-j721e-common-proc-board.dts
+++ b/src/arm64/ti/k3-j721e-common-proc-board.dts
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
/ {
chosen {
@@ -237,7 +238,7 @@
J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
>;
};
@@ -358,7 +359,7 @@
};
&serdes3 {
- serdes3_usb_link: link@0 {
+ serdes3_usb_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -635,8 +636,45 @@
status = "disabled";
};
+&cmn_refclk1 {
+ clock-frequency = <100000000>;
+};
+
+&wiz0_pll1_refclk {
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_pll1_refclk {
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_refclk_dig {
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_pll1_refclk {
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&cmn_refclk1>;
+};
+
&serdes0 {
- serdes0_pcie_link: link@0 {
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>;
+
+ serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
#phy-cells = <0>;
@@ -646,7 +684,10 @@
};
&serdes1 {
- serdes1_pcie_link: link@0 {
+ assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz1_pll1_refclk>;
+
+ serdes1_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -656,7 +697,10 @@
};
&serdes2 {
- serdes2_pcie_link: link@0 {
+ assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <&wiz2_pll1_refclk>;
+
+ serdes2_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
#phy-cells = <0>;
@@ -718,3 +762,11 @@
&dss {
status = "disabled";
};
+
+&icssg0_mdio {
+ status = "disabled";
+};
+
+&icssg1_mdio {
+ status = "disabled";
+};
diff --git a/src/arm64/ti/k3-j721e-main.dtsi b/src/arm64/ti/k3-j721e-main.dtsi
index 3bcafe4..cf34823 100644
--- a/src/arm64/ti/k3-j721e-main.dtsi
+++ b/src/arm64/ti/k3-j721e-main.dtsi
@@ -8,6 +8,20 @@
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
+/ {
+ cmn_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ cmn_refclk1: clock-cmnrefclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -338,24 +352,12 @@
pinctrl-single,function-mask = <0xffffffff>;
};
- dummy_cmn_refclk: dummy-cmn-refclk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
- dummy_cmn_refclk1: dummy-cmn-refclk1 {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <100000000>;
- };
-
serdes_wiz0: wiz@5000000 {
compatible = "ti,j721e-wiz-16g";
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
@@ -364,21 +366,21 @@
ranges = <0x5000000 0x0 0x5000000 0x10000>;
wiz0_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 292 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll0_refclk>;
assigned-clock-parents = <&k3_clks 292 11>;
};
wiz0_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_pll1_refclk>;
assigned-clock-parents = <&k3_clks 292 0>;
};
wiz0_refclk_dig: refclk-dig {
- clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz0_refclk_dig>;
assigned-clock-parents = <&k3_clks 292 11>;
@@ -400,10 +402,13 @@
reg = <0x5000000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz0 0>;
reset-names = "sierra_reset";
- clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>,
+ <&wiz0_pll0_refclk>, <&wiz0_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -412,7 +417,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
@@ -421,21 +426,21 @@
ranges = <0x5010000 0x0 0x5010000 0x10000>;
wiz1_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 293 13>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll0_refclk>;
assigned-clock-parents = <&k3_clks 293 13>;
};
wiz1_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_pll1_refclk>;
assigned-clock-parents = <&k3_clks 293 0>;
};
wiz1_refclk_dig: refclk-dig {
- clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz1_refclk_dig>;
assigned-clock-parents = <&k3_clks 293 13>;
@@ -457,10 +462,13 @@
reg = <0x5010000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz1 0>;
reset-names = "sierra_reset";
- clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>,
+ <&wiz1_pll0_refclk>, <&wiz1_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -469,7 +477,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
@@ -478,21 +486,21 @@
ranges = <0x5020000 0x0 0x5020000 0x10000>;
wiz2_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 294 11>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll0_refclk>;
assigned-clock-parents = <&k3_clks 294 11>;
};
wiz2_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_pll1_refclk>;
assigned-clock-parents = <&k3_clks 294 0>;
};
wiz2_refclk_dig: refclk-dig {
- clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz2_refclk_dig>;
assigned-clock-parents = <&k3_clks 294 11>;
@@ -514,10 +522,13 @@
reg = <0x5020000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz2 0>;
reset-names = "sierra_reset";
- clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>,
+ <&wiz2_pll0_refclk>, <&wiz2_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -526,7 +537,7 @@
#address-cells = <1>;
#size-cells = <1>;
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
- clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&cmn_refclk>;
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
@@ -535,21 +546,21 @@
ranges = <0x5030000 0x0 0x5030000 0x10000>;
wiz3_pll0_refclk: pll0-refclk {
- clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clocks = <&k3_clks 295 9>, <&cmn_refclk>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll0_refclk>;
assigned-clock-parents = <&k3_clks 295 9>;
};
wiz3_pll1_refclk: pll1-refclk {
- clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_pll1_refclk>;
assigned-clock-parents = <&k3_clks 295 0>;
};
wiz3_refclk_dig: refclk-dig {
- clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
#clock-cells = <0>;
assigned-clocks = <&wiz3_refclk_dig>;
assigned-clock-parents = <&k3_clks 295 9>;
@@ -571,10 +582,13 @@
reg = <0x5030000 0x10000>;
#address-cells = <1>;
#size-cells = <0>;
+ #clock-cells = <1>;
resets = <&serdes_wiz3 0>;
reset-names = "sierra_reset";
- clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
- clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>,
+ <&wiz3_pll0_refclk>, <&wiz3_pll1_refclk>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div",
+ "pll0_refclk", "pll1_refclk";
};
};
@@ -775,8 +789,6 @@
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -788,8 +800,6 @@
main_uart1: serial@2810000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02810000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -801,8 +811,6 @@
main_uart2: serial@2820000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02820000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -814,8 +822,6 @@
main_uart3: serial@2830000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02830000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -827,8 +833,6 @@
main_uart4: serial@2840000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02840000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -840,8 +844,6 @@
main_uart5: serial@2850000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02850000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -853,8 +855,6 @@
main_uart6: serial@2860000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02860000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -866,8 +866,6 @@
main_uart7: serial@2870000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02870000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -879,8 +877,6 @@
main_uart8: serial@2880000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02880000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -892,8 +888,6 @@
main_uart9: serial@2890000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02890000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -1794,6 +1788,16 @@
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru0_1-fw";
};
+
+ icssg0_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 119 1>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
icssg1: icssg@b100000 {
@@ -1925,5 +1929,15 @@
reg-names = "iram", "control", "debug";
firmware-name = "j7-txpru1_1-fw";
};
+
+ icssg1_mdio: mdio@32400 {
+ compatible = "ti,davinci_mdio";
+ reg = <0x32400 0x100>;
+ clocks = <&k3_clks 120 4>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bus_freq = <1000000>;
+ };
};
};
diff --git a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
index 5e825e4..d2dceda 100644
--- a/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/src/arm64/ti/k3-j721e-mcu-wakeup.dtsi
@@ -73,8 +73,6 @@
wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
@@ -86,8 +84,6 @@
mcu_uart0: serial@40a00000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x40a00000 0x00 0x100>;
- reg-shift = <2>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
diff --git a/src/arm64/toshiba/tmpv7708-rm-mbrc.dts b/src/arm64/toshiba/tmpv7708-rm-mbrc.dts
index bf0620a..29a4d9f 100644
--- a/src/arm64/toshiba/tmpv7708-rm-mbrc.dts
+++ b/src/arm64/toshiba/tmpv7708-rm-mbrc.dts
@@ -68,3 +68,11 @@
&gpio {
status = "okay";
};
+
+&pwm_mux {
+ groups = "pwm0_gpio16_grp", "pwm1_gpio17_grp", "pwm2_gpio18_grp", "pwm3_gpio19_grp";
+};
+
+&pwm {
+ status = "okay";
+};
diff --git a/src/arm64/toshiba/tmpv7708.dtsi b/src/arm64/toshiba/tmpv7708.dtsi
index 17934fd..4b4231f 100644
--- a/src/arm64/toshiba/tmpv7708.dtsi
+++ b/src/arm64/toshiba/tmpv7708.dtsi
@@ -432,6 +432,15 @@
reg = <0 0x28330000 0 0x1000>;
status = "disabled";
};
+
+ pwm: pwm@241c0000 {
+ compatible = "toshiba,visconti-pwm";
+ reg = <0 0x241c0000 0 0x1000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_mux>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
};
};
diff --git a/src/arm64/toshiba/tmpv7708_pins.dtsi b/src/arm64/toshiba/tmpv7708_pins.dtsi
index 34de000..a480c6b 100644
--- a/src/arm64/toshiba/tmpv7708_pins.dtsi
+++ b/src/arm64/toshiba/tmpv7708_pins.dtsi
@@ -90,4 +90,9 @@
groups = "i2c8_grp";
bias-pull-up;
};
+
+ pwm_mux: pwm_mux {
+ function = "pwm";
+ };
+
};
diff --git a/src/mips/ingenic/ci20.dts b/src/mips/ingenic/ci20.dts
index 8877c62..a688809 100644
--- a/src/mips/ingenic/ci20.dts
+++ b/src/mips/ingenic/ci20.dts
@@ -118,6 +118,20 @@
assigned-clock-rates = <48000000>;
};
+&tcu {
+ /*
+ * 750 kHz for the system timers and clocksource,
+ * use channel #0 and #1 for the per cpu system timers,
+ * and use channel #2 for the clocksource.
+ *
+ * 3000 kHz for the OST timer to provide a higher
+ * precision clocksource.
+ */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+ assigned-clock-rates = <750000>, <750000>, <750000>, <3000000>;
+};
+
&mmc0 {
status = "okay";
@@ -522,13 +536,3 @@
bias-disable;
};
};
-
-&tcu {
- /*
- * 750 kHz for the system timer and 3 MHz for the clocksource,
- * use channel #0 for the system timer, #1 for the clocksource.
- */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
- <&tcu TCU_CLK_OST>;
- assigned-clock-rates = <750000>, <3000000>, <3000000>;
-};
diff --git a/src/mips/ingenic/gcw0.dts b/src/mips/ingenic/gcw0.dts
index f4c04f2..4abb031 100644
--- a/src/mips/ingenic/gcw0.dts
+++ b/src/mips/ingenic/gcw0.dts
@@ -74,7 +74,6 @@
simple-audio-card,widgets =
"Speaker", "Speaker",
"Headphone", "Headphones",
- "Line", "FM Radio",
"Microphone", "Built-in Mic";
simple-audio-card,routing =
"Headphones Amp INL", "LHPOUT",
@@ -85,8 +84,8 @@
"Speaker Amp INR", "ROUT",
"Speaker", "Speaker Amp OUTL",
"Speaker", "Speaker Amp OUTR",
- "LLINEIN", "FM Radio",
- "RLINEIN", "FM Radio",
+ "LLINEIN", "Cap-less",
+ "RLINEIN", "Cap-less",
"Built-in Mic", "MICBIAS",
"MIC1P", "Built-in Mic",
"MIC1N", "Built-in Mic";
diff --git a/src/mips/ingenic/jz4780.dtsi b/src/mips/ingenic/jz4780.dtsi
index 8d01fee..9e34f43 100644
--- a/src/mips/ingenic/jz4780.dtsi
+++ b/src/mips/ingenic/jz4780.dtsi
@@ -339,7 +339,7 @@
};
i2c0: i2c@10050000 {
- compatible = "ingenic,jz4780-i2c";
+ compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
#address-cells = <1>;
#size-cells = <0>;
@@ -357,7 +357,7 @@
};
i2c1: i2c@10051000 {
- compatible = "ingenic,jz4780-i2c";
+ compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10051000 0x1000>;
@@ -374,7 +374,7 @@
};
i2c2: i2c@10052000 {
- compatible = "ingenic,jz4780-i2c";
+ compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10052000 0x1000>;
@@ -391,7 +391,7 @@
};
i2c3: i2c@10053000 {
- compatible = "ingenic,jz4780-i2c";
+ compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10053000 0x1000>;
@@ -408,7 +408,7 @@
};
i2c4: i2c@10054000 {
- compatible = "ingenic,jz4780-i2c";
+ compatible = "ingenic,jz4780-i2c", "ingenic,jz4770-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10054000 0x1000>;
diff --git a/src/mips/ingenic/rs90.dts b/src/mips/ingenic/rs90.dts
index 4eb1edb..74fee7f 100644
--- a/src/mips/ingenic/rs90.dts
+++ b/src/mips/ingenic/rs90.dts
@@ -16,6 +16,18 @@
reg = <0x0 0x2000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ vmem: video-memory@1f00000 {
+ compatible = "shared-dma-pool";
+ reg = <0x1f00000 0x100000>;
+ reusable;
+ };
+ };
+
vcc: regulator {
compatible = "regulator-fixed";
@@ -300,6 +312,8 @@
};
&lcd {
+ memory-region = <&vmem>;
+
pinctrl-names = "default";
pinctrl-0 = <&pins_lcd>;
};
diff --git a/src/mips/ingenic/x1000.dtsi b/src/mips/ingenic/x1000.dtsi
index aac9ded..dec7909 100644
--- a/src/mips/ingenic/x1000.dtsi
+++ b/src/mips/ingenic/x1000.dtsi
@@ -80,6 +80,11 @@
status = "disabled";
};
+
+ mac_phy_ctrl: mac-phy-ctrl@e8 {
+ compatible = "syscon";
+ reg = <0xe8 0x4>;
+ };
};
ost: timer@12000000 {
@@ -347,6 +352,8 @@
clocks = <&cgu X1000_CLK_MAC>;
clock-names = "stmmaceth";
+ mode-reg = <&mac_phy_ctrl>;
+
status = "disabled";
mdio: mdio {
diff --git a/src/mips/ingenic/x1830.dtsi b/src/mips/ingenic/x1830.dtsi
index b21c930..215257f 100644
--- a/src/mips/ingenic/x1830.dtsi
+++ b/src/mips/ingenic/x1830.dtsi
@@ -73,6 +73,11 @@
status = "disabled";
};
+
+ mac_phy_ctrl: mac-phy-ctrl@e8 {
+ compatible = "syscon";
+ reg = <0xe8 0x4>;
+ };
};
ost: timer@12000000 {
@@ -97,9 +102,9 @@
#clock-cells = <1>;
- clocks = <&cgu X1830_CLK_RTCLK
- &cgu X1830_CLK_EXCLK
- &cgu X1830_CLK_PCLK>;
+ clocks = <&cgu X1830_CLK_RTCLK>,
+ <&cgu X1830_CLK_EXCLK>,
+ <&cgu X1830_CLK_PCLK>;
clock-names = "rtc", "ext", "pclk";
interrupt-controller;
@@ -274,8 +279,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1830-dma";
- reg = <0x13420000 0x400
- 0x13421000 0x40>;
+ reg = <0x13420000 0x400>, <0x13421000 0x40>;
#dma-cells = <2>;
interrupt-parent = <&intc>;
@@ -337,6 +341,8 @@
clocks = <&cgu X1830_CLK_MAC>;
clock-names = "stmmaceth";
+ mode-reg = <&mac_phy_ctrl>;
+
status = "disabled";
mdio: mdio {
diff --git a/src/mips/loongson/loongson64-2k1000.dtsi b/src/mips/loongson/loongson64-2k1000.dtsi
index 569e814..bfc3d32 100644
--- a/src/mips/loongson/loongson64-2k1000.dtsi
+++ b/src/mips/loongson/loongson64-2k1000.dtsi
@@ -23,7 +23,7 @@
};
};
- memory {
+ memory@200000 {
compatible = "memory";
device_type = "memory";
reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
@@ -114,6 +114,52 @@
ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>,
<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+ gmac@3,0 {
+ compatible = "pci0014,7a03.0",
+ "pci0014,7a03",
+ "pciclass0c0320",
+ "pciclass0c03",
+ "loongson, pci-gmac";
+
+ reg = <0x1800 0x0 0x0 0x0 0x0>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
+ <13 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "macirq", "eth_lpi";
+ interrupt-parent = <&liointc0>;
+ phy-mode = "rgmii";
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+ };
+
+ gmac@3,1 {
+ compatible = "pci0014,7a03.0",
+ "pci0014,7a03",
+ "pciclass0c0320",
+ "pciclass0c03",
+ "loongson, pci-gmac";
+
+ reg = <0x1900 0x0 0x0 0x0 0x0>;
+ interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
+ <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "macirq", "eth_lpi";
+ interrupt-parent = <&liointc0>;
+ phy-mode = "rgmii";
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy1: ethernet-phy@1 {
+ reg = <0>;
+ };
+ };
+ };
+
ehci@4,1 {
compatible = "pci0014,7a14.0",
"pci0014,7a14",
@@ -163,8 +209,8 @@
};
pci_bridge@a,0 {
- compatible = "pci0014,7a19.0",
- "pci0014,7a19",
+ compatible = "pci0014,7a09.0",
+ "pci0014,7a09",
"pciclass060400",
"pciclass0604";
@@ -178,8 +224,8 @@
};
pci_bridge@b,0 {
- compatible = "pci0014,7a19.0",
- "pci0014,7a19",
+ compatible = "pci0014,7a09.0",
+ "pci0014,7a09",
"pciclass060400",
"pciclass0604";
@@ -193,8 +239,8 @@
};
pci_bridge@c,0 {
- compatible = "pci0014,7a19.0",
- "pci0014,7a19",
+ compatible = "pci0014,7a09.0",
+ "pci0014,7a09",
"pciclass060400",
"pciclass0604";
@@ -223,8 +269,8 @@
};
pci_bridge@e,0 {
- compatible = "pci0014,7a19.0",
- "pci0014,7a19",
+ compatible = "pci0014,7a09.0",
+ "pci0014,7a09",
"pciclass060400",
"pciclass0604";
diff --git a/src/mips/loongson/loongson64g-package.dtsi b/src/mips/loongson/loongson64g-package.dtsi
index 38abc57..d4314f6 100644
--- a/src/mips/loongson/loongson64g-package.dtsi
+++ b/src/mips/loongson/loongson64g-package.dtsi
@@ -39,7 +39,7 @@
};
- cpu_uart0: serial@1fe001e0 {
+ cpu_uart0: serial@1fe00100 {
compatible = "ns16550a";
reg = <0 0x1fe00100 0x10>;
clock-frequency = <100000000>;
@@ -48,7 +48,7 @@
no-loopback-test;
};
- cpu_uart1: serial@1fe001e8 {
+ cpu_uart1: serial@1fe00110 {
status = "disabled";
compatible = "ns16550a";
reg = <0 0x1fe00110 0x10>;
diff --git a/src/mips/loongson/loongson64v_4core_virtio.dts b/src/mips/loongson/loongson64v_4core_virtio.dts
index 41f0b11..d0588d8 100644
--- a/src/mips/loongson/loongson64v_4core_virtio.dts
+++ b/src/mips/loongson/loongson64v_4core_virtio.dts
@@ -88,7 +88,7 @@
interrupt-map-mask = <0x1800 0x0 0x0 0x7>;
};
- isa {
+ isa@18000000 {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
diff --git a/src/mips/loongson/ls7a-pch.dtsi b/src/mips/loongson/ls7a-pch.dtsi
index f99a7a1..2f45fce 100644
--- a/src/mips/loongson/ls7a-pch.dtsi
+++ b/src/mips/loongson/ls7a-pch.dtsi
@@ -186,7 +186,8 @@
compatible = "pci0014,7a03.0",
"pci0014,7a03",
"pciclass020000",
- "pciclass0200";
+ "pciclass0200",
+ "loongson, pci-gmac";
reg = <0x1800 0x0 0x0 0x0 0x0>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
@@ -208,7 +209,8 @@
compatible = "pci0014,7a03.0",
"pci0014,7a03",
"pciclass020000",
- "pciclass0200";
+ "pciclass0200",
+ "loongson, pci-gmac";
reg = <0x1900 0x0 0x0 0x0 0x0>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
@@ -407,7 +409,7 @@
};
};
- isa {
+ isa@18000000 {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
diff --git a/src/mips/loongson/rs780e-pch.dtsi b/src/mips/loongson/rs780e-pch.dtsi
index 871c866..6f45951 100644
--- a/src/mips/loongson/rs780e-pch.dtsi
+++ b/src/mips/loongson/rs780e-pch.dtsi
@@ -21,7 +21,7 @@
<0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
};
- isa {
+ isa@18000000 {
compatible = "isa";
#address-cells = <2>;
#size-cells = <1>;
diff --git a/src/mips/mti/sead3.dts b/src/mips/mti/sead3.dts
index 1cf6728..046c97a 100644
--- a/src/mips/mti/sead3.dts
+++ b/src/mips/mti/sead3.dts
@@ -244,7 +244,7 @@
no-loopback-test;
};
- eth@1f010000 {
+ ethernet@1f010000 {
compatible = "smsc,lan9115";
reg = <0x1f010000 0x10000>;
reg-io-width = <4>;
diff --git a/src/mips/qca/ar9331.dtsi b/src/mips/qca/ar9331.dtsi
index 83b3c0c..c4102b2 100644
--- a/src/mips/qca/ar9331.dtsi
+++ b/src/mips/qca/ar9331.dtsi
@@ -148,6 +148,7 @@
fixed-link {
speed = <1000>;
full-duplex;
+ pause;
};
mdio {
@@ -183,6 +184,7 @@
fixed-link {
speed = <1000>;
full-duplex;
+ pause;
};
};
diff --git a/src/mips/qca/ar9331_openembed_som9331_board.dts b/src/mips/qca/ar9331_openembed_som9331_board.dts
new file mode 100644
index 0000000..e6622f8
--- /dev/null
+++ b/src/mips/qca/ar9331_openembed_som9331_board.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "ar9331.dtsi"
+
+/ {
+ model = "OpenEmbed SOM9331 Board";
+ compatible = "openembed,som9331";
+
+ aliases {
+ serial0 = &uart;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x4000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&gpio 27 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@0 {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&ref {
+ clock-frequency = <25000000>;
+};
+
+&uart {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
+
+&usb {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&spi {
+ num-chipselects = <1>;
+ status = "okay";
+
+ /* Winbond 25Q64FVSIG SPI flash */
+ spiflash: w25q64@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "winbond,w25q64", "jedec,spi-nor";
+ spi-max-frequency = <104000000>;
+ reg = <0>;
+ };
+};
+
+ð0 {
+ status = "okay";
+};
+
+ð1 {
+ status = "okay";
+};
+
+&switch_port1 {
+ label = "lan0";
+ status = "okay";
+};
+
+&switch_port3 {
+ label = "lan1";
+ status = "okay";
+};
+
+&phy_port0 {
+ status = "okay";
+};
+
+&phy_port2 {
+ status = "okay";
+};
+
+&phy_port4 {
+ status = "okay";
+};
diff --git a/src/powerpc/microwatt.dts b/src/powerpc/microwatt.dts
new file mode 100644
index 0000000..974abbd
--- /dev/null
+++ b/src/powerpc/microwatt.dts
@@ -0,0 +1,138 @@
+/dts-v1/;
+
+/ {
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ model-name = "microwatt";
+ compatible = "microwatt-soc";
+
+ aliases {
+ serial0 = &UART0;
+ };
+
+ reserved-memory {
+ #size-cells = <0x02>;
+ #address-cells = <0x02>;
+ ranges;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x10000000>;
+ };
+
+ cpus {
+ #size-cells = <0x00>;
+ #address-cells = <0x01>;
+
+ ibm,powerpc-cpu-features {
+ display-name = "Microwatt";
+ isa = <3000>;
+ device_type = "cpu-features";
+ compatible = "ibm,powerpc-cpu-features";
+
+ mmu-radix {
+ isa = <3000>;
+ usable-privilege = <2>;
+ };
+
+ little-endian {
+ isa = <2050>;
+ usable-privilege = <3>;
+ hwcap-bit-nr = <1>;
+ };
+
+ cache-inhibited-large-page {
+ isa = <2040>;
+ usable-privilege = <2>;
+ };
+
+ fixed-point-v3 {
+ isa = <3000>;
+ usable-privilege = <3>;
+ };
+
+ no-execute {
+ isa = <2010>;
+ usable-privilege = <2>;
+ };
+
+ floating-point {
+ hwcap-bit-nr = <27>;
+ isa = <0>;
+ usable-privilege = <3>;
+ };
+ };
+
+ PowerPC,Microwatt@0 {
+ i-cache-sets = <2>;
+ ibm,dec-bits = <64>;
+ reservation-granule-size = <64>;
+ clock-frequency = <100000000>;
+ timebase-frequency = <100000000>;
+ i-tlb-sets = <1>;
+ ibm,ppc-interrupt-server#s = <0>;
+ i-cache-block-size = <64>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <2>;
+ i-tlb-size = <64>;
+ cpu-version = <0x990000>;
+ status = "okay";
+ i-cache-size = <0x1000>;
+ ibm,processor-radix-AP-encodings = <0x0c 0xa0000010 0x20000015 0x4000001e>;
+ tlb-size = <0>;
+ tlb-sets = <0>;
+ device_type = "cpu";
+ d-tlb-size = <128>;
+ d-tlb-sets = <2>;
+ reg = <0>;
+ general-purpose;
+ 64-bit;
+ d-cache-size = <0x1000>;
+ ibm,chip-id = <0>;
+ };
+ };
+
+ soc@c0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&ICS>;
+
+ ranges = <0 0 0xc0000000 0x40000000>;
+
+ interrupt-controller@4000 {
+ compatible = "openpower,xics-presentation", "ibm,ppc-xicp";
+ ibm,interrupt-server-ranges = <0x0 0x1>;
+ reg = <0x4000 0x100>;
+ };
+
+ ICS: interrupt-controller@5000 {
+ compatible = "openpower,xics-sources";
+ interrupt-controller;
+ interrupt-ranges = <0x10 0x10>;
+ reg = <0x5000 0x100>;
+ #address-cells = <0>;
+ #size-cells = <0>;
+ #interrupt-cells = <2>;
+ };
+
+ UART0: serial@2000 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <0x2000 0x8>;
+ clock-frequency = <100000000>;
+ current-speed = <115200>;
+ reg-shift = <2>;
+ fifo-size = <16>;
+ interrupts = <0x10 0x1>;
+ };
+ };
+
+ chosen {
+ bootargs = "";
+ ibm,architecture-vec-5 = [19 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 40 00 40];
+ stdout-path = &UART0;
+ };
+};
