| From de17eb0a86edbf87cb7619eebf00f3130b521e9e Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Tue, 7 Mar 2017 19:03:24 +0100 |
| Subject: [PATCH 032/286] arm64: dts: r8a7796: Add CA53 L2 cache-controller |
| node |
| |
| Add a device node for the Cortex-A53 L2 cache-controller. |
| |
| The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as |
| 32 KiB x 16 ways). |
| |
| Extracted from a patch by Takeshi Kihara in the BSP. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit a681e6d63285b879bb9bab0bd79e2021e6dcbda1) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 +++++++ |
| 1 file changed, 7 insertions(+) |
| |
| --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| @@ -61,6 +61,13 @@ |
| cache-unified; |
| cache-level = <2>; |
| }; |
| + |
| + L2_CA53: cache-controller-1 { |
| + compatible = "cache"; |
| + power-domains = <&sysc R8A7796_PD_CA53_SCU>; |
| + cache-unified; |
| + cache-level = <2>; |
| + }; |
| }; |
| |
| extal_clk: extal { |
