| From f187d3ef9f6d25d6afac8d6c401f567f4be85d48 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Fri, 3 Mar 2017 14:18:17 +0100 |
| Subject: [PATCH 025/286] arm64: dts: r8a7796: Remove unit-address and reg from |
| integrated cache |
| |
| The Cortex-A57 cache controller is an integrated controller, and thus |
| the device node representing it should not have a unit-addresses or reg |
| property. |
| |
| Fixes: 1561f20760ec96db ("arm64: dts: r8a7796: Add Renesas R8A7796 SoC support") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 57a4fd420c6e8a04b6a87ff24d34250cd7c48f15) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +-- |
| 1 file changed, 1 insertion(+), 2 deletions(-) |
| |
| --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| @@ -47,9 +47,8 @@ |
| enable-method = "psci"; |
| }; |
| |
| - L2_CA57: cache-controller@0 { |
| + L2_CA57: cache-controller-0 { |
| compatible = "cache"; |
| - reg = <0>; |
| power-domains = <&sysc R8A7796_PD_CA57_SCU>; |
| cache-unified; |
| cache-level = <2>; |
