| From 38d94a2c2d3dffb0c18d28baf668d89b9c334dea Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Mon, 6 Mar 2017 17:40:39 +0100 |
| Subject: [PATCH 058/286] ARM: dts: r8a7790: Remove unit-addresses and regs |
| from integrated caches |
| |
| The Cortex-A15/A7 cache controllers are integrated controllers, and thus |
| the device nodes representing them should not have unit-addresses or reg |
| properties. |
| |
| Fixes: 2c3de36700d4f3a5 ("ARM: dts: r8a7790: Fix W=1 dtc warnings") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit d492909c84b895564d7ac413546ae988945c68db) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7790.dtsi | 6 ++---- |
| 1 file changed, 2 insertions(+), 4 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7790.dtsi |
| +++ b/arch/arm/boot/dts/r8a7790.dtsi |
| @@ -129,17 +129,15 @@ |
| next-level-cache = <&L2_CA7>; |
| }; |
| |
| - L2_CA15: cache-controller@0 { |
| + L2_CA15: cache-controller-0 { |
| compatible = "cache"; |
| - reg = <0>; |
| power-domains = <&sysc R8A7790_PD_CA15_SCU>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| - L2_CA7: cache-controller@100 { |
| + L2_CA7: cache-controller-1 { |
| compatible = "cache"; |
| - reg = <0x100>; |
| power-domains = <&sysc R8A7790_PD_CA7_SCU>; |
| cache-unified; |
| cache-level = <2>; |
