| From 0feb9f39069b2b6afd4258df090fe94755c4034f Mon Sep 17 00:00:00 2001 |
| From: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| Date: Mon, 29 Jan 2018 19:01:52 +0100 |
| Subject: [PATCH 1132/1795] clk: renesas: r8a7795: Add Z2 clock |
| |
| This patch adds Z2 clock for r8a7795 SoC. |
| |
| Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit 1eadca3557f77afbb64100e077f48ac338d731dc) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| --- |
| drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| index 995a4c4fb01e..775b0ceaa337 100644 |
| --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| @@ -75,6 +75,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { |
| |
| /* Core Clock Outputs */ |
| DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), |
| + DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), |
| DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), |
| DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), |
| DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), |
| -- |
| 2.19.0 |
| |
