| From c9ae039aa0af3eac0f187339fcffb1b0e71c0a96 Mon Sep 17 00:00:00 2001 |
| From: Soren Brinkmann <soren.brinkmann@xilinx.com> |
| Date: Fri, 19 Jul 2013 10:16:45 -0700 |
| Subject: clk/zynq/pll: Use #defines for fbdiv min/max values |
| |
| Use more descriptive #defines for the minimum and maximum PLL |
| feedback divider. |
| |
| Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> |
| Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
| (cherry picked from commit 353dc6c47d67c83f7cc20334f8deb251674e6864) |
| Signed-off-by: Daniel Sangorrin <daniel.sangorrin@toshiba.co.jp> |
| Signed-off-by: Yoshitake Kobayashi <yoshitake.kobayashi@toshiba.co.jp> |
| --- |
| drivers/clk/zynq/pll.c | 11 +++++++---- |
| 1 file changed, 7 insertions(+), 4 deletions(-) |
| |
| diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c |
| index 6daa7b6702ed..3226f54fa595 100644 |
| --- a/drivers/clk/zynq/pll.c |
| +++ b/drivers/clk/zynq/pll.c |
| @@ -50,6 +50,9 @@ struct zynq_pll { |
| #define PLLCTRL_RESET_MASK 1 |
| #define PLLCTRL_RESET_SHIFT 0 |
| |
| +#define PLL_FBDIV_MIN 13 |
| +#define PLL_FBDIV_MAX 66 |
| + |
| /** |
| * zynq_pll_round_rate() - Round a clock frequency |
| * @hw: Handle between common and hardware-specific interfaces |
| @@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
| u32 fbdiv; |
| |
| fbdiv = DIV_ROUND_CLOSEST(rate, *prate); |
| - if (fbdiv < 13) |
| - fbdiv = 13; |
| - else if (fbdiv > 66) |
| - fbdiv = 66; |
| + if (fbdiv < PLL_FBDIV_MIN) |
| + fbdiv = PLL_FBDIV_MIN; |
| + else if (fbdiv > PLL_FBDIV_MAX) |
| + fbdiv = PLL_FBDIV_MAX; |
| |
| return *prate * fbdiv; |
| } |
| -- |
| 1.8.5.rc3 |
| |