| From 17d84a3a4c31e154d5593a63ad6cb1ee5dfe2fd9 Mon Sep 17 00:00:00 2001 |
| From: Seungwon Jeon <tgih.jun@samsung.com> |
| Date: Fri, 14 Mar 2014 21:12:33 +0900 |
| Subject: mmc: sh_mmcif: clarify DDR timing mode between SD-UHS and eMMC |
| |
| Replaced UHS_DDR50 with MMC_DDR52. |
| |
| CC: Guennadi Liakhovetski <g.liakhovetski@gmx.de> |
| Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> |
| Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
| Signed-off-by: Chris Ball <chris@printf.net> |
| (cherry picked from commit 4039ff4741c6e8d27b5ca42dc92d87dc2d625b80) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/mmc/host/sh_mmcif.c | 9 +++++---- |
| 1 file changed, 5 insertions(+), 4 deletions(-) |
| |
| diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c |
| index 54730f4aac87..656fbba4c422 100644 |
| --- a/drivers/mmc/host/sh_mmcif.c |
| +++ b/drivers/mmc/host/sh_mmcif.c |
| @@ -803,12 +803,13 @@ static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, |
| break; |
| } |
| switch (host->timing) { |
| - case MMC_TIMING_UHS_DDR50: |
| + case MMC_TIMING_MMC_DDR52: |
| /* |
| * MMC core will only set this timing, if the host |
| - * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF |
| - * implementations with this capability, e.g. sh73a0, |
| - * will have to set it in their platform data. |
| + * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR |
| + * capability. MMCIF implementations with this |
| + * capability, e.g. sh73a0, will have to set it |
| + * in their platform data. |
| */ |
| tmp |= CMD_SET_DARS; |
| break; |
| -- |
| 2.1.2 |
| |
