| From f51077a76ad2f36b6a81a84ea809a5f806b49a8d Mon Sep 17 00:00:00 2001 |
| From: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
| Date: Tue, 10 Jun 2014 11:37:15 +0900 |
| Subject: pinctrl: sh-pfc: r8a7791: Add HSCIF pin support |
| |
| Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> |
| Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
| (cherry picked from commit 92b14d56d3edf68eff258bc69a62e295dbfb4780) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 250 +++++++++++++++++++++++++++++++++++ |
| 1 file changed, 250 insertions(+) |
| |
| diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c |
| index 2e688dc4a3c8..394b234488cc 100644 |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c |
| @@ -1867,6 +1867,192 @@ static const unsigned int eth_rmii_mux[] = { |
| ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, |
| ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, |
| }; |
| + |
| +/* - HSCIF0 ----------------------------------------------------------------- */ |
| +static const unsigned int hscif0_data_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4), |
| +}; |
| +static const unsigned int hscif0_data_mux[] = { |
| + HRX0_MARK, HTX0_MARK, |
| +}; |
| +static const unsigned int hscif0_clk_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(7, 2), |
| +}; |
| +static const unsigned int hscif0_clk_mux[] = { |
| + HSCK0_MARK, |
| +}; |
| +static const unsigned int hscif0_ctrl_pins[] = { |
| + /* RTS, CTS */ |
| + RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0), |
| +}; |
| +static const unsigned int hscif0_ctrl_mux[] = { |
| + HRTS0_N_MARK, HCTS0_N_MARK, |
| +}; |
| +static const unsigned int hscif0_data_b_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15), |
| +}; |
| +static const unsigned int hscif0_data_b_mux[] = { |
| + HRX0_B_MARK, HTX0_B_MARK, |
| +}; |
| +static const unsigned int hscif0_ctrl_b_pins[] = { |
| + /* RTS, CTS */ |
| + RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13), |
| +}; |
| +static const unsigned int hscif0_ctrl_b_mux[] = { |
| + HRTS0_N_B_MARK, HCTS0_N_B_MARK, |
| +}; |
| +static const unsigned int hscif0_data_c_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), |
| +}; |
| +static const unsigned int hscif0_data_c_mux[] = { |
| + HRX0_C_MARK, HTX0_C_MARK, |
| +}; |
| +static const unsigned int hscif0_clk_c_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(5, 31), |
| +}; |
| +static const unsigned int hscif0_clk_c_mux[] = { |
| + HSCK0_C_MARK, |
| +}; |
| +/* - HSCIF1 ----------------------------------------------------------------- */ |
| +static const unsigned int hscif1_data_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6), |
| +}; |
| +static const unsigned int hscif1_data_mux[] = { |
| + HRX1_MARK, HTX1_MARK, |
| +}; |
| +static const unsigned int hscif1_clk_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(7, 7), |
| +}; |
| +static const unsigned int hscif1_clk_mux[] = { |
| + HSCK1_MARK, |
| +}; |
| +static const unsigned int hscif1_ctrl_pins[] = { |
| + /* RTS, CTS */ |
| + RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8), |
| +}; |
| +static const unsigned int hscif1_ctrl_mux[] = { |
| + HRTS1_N_MARK, HCTS1_N_MARK, |
| +}; |
| +static const unsigned int hscif1_data_b_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), |
| +}; |
| +static const unsigned int hscif1_data_b_mux[] = { |
| + HRX1_B_MARK, HTX1_B_MARK, |
| +}; |
| +static const unsigned int hscif1_data_c_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), |
| +}; |
| +static const unsigned int hscif1_data_c_mux[] = { |
| + HRX1_C_MARK, HTX1_C_MARK, |
| +}; |
| +static const unsigned int hscif1_clk_c_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(7, 16), |
| +}; |
| +static const unsigned int hscif1_clk_c_mux[] = { |
| + HSCK1_C_MARK, |
| +}; |
| +static const unsigned int hscif1_ctrl_c_pins[] = { |
| + /* RTS, CTS */ |
| + RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17), |
| +}; |
| +static const unsigned int hscif1_ctrl_c_mux[] = { |
| + HRTS1_N_C_MARK, HCTS1_N_C_MARK, |
| +}; |
| +static const unsigned int hscif1_data_d_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18), |
| +}; |
| +static const unsigned int hscif1_data_d_mux[] = { |
| + HRX1_D_MARK, HTX1_D_MARK, |
| +}; |
| +static const unsigned int hscif1_data_e_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15), |
| +}; |
| +static const unsigned int hscif1_data_e_mux[] = { |
| + HRX1_C_MARK, HTX1_C_MARK, |
| +}; |
| +static const unsigned int hscif1_clk_e_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(2, 6), |
| +}; |
| +static const unsigned int hscif1_clk_e_mux[] = { |
| + HSCK1_E_MARK, |
| +}; |
| +static const unsigned int hscif1_ctrl_e_pins[] = { |
| + /* RTS, CTS */ |
| + RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7), |
| +}; |
| +static const unsigned int hscif1_ctrl_e_mux[] = { |
| + HRTS1_N_E_MARK, HCTS1_N_E_MARK, |
| +}; |
| +/* - HSCIF2 ----------------------------------------------------------------- */ |
| +static const unsigned int hscif2_data_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17), |
| +}; |
| +static const unsigned int hscif2_data_mux[] = { |
| + HRX2_MARK, HTX2_MARK, |
| +}; |
| +static const unsigned int hscif2_clk_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(4, 15), |
| +}; |
| +static const unsigned int hscif2_clk_mux[] = { |
| + HSCK2_MARK, |
| +}; |
| +static const unsigned int hscif2_ctrl_pins[] = { |
| + /* RTS, CTS */ |
| + RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), |
| +}; |
| +static const unsigned int hscif2_ctrl_mux[] = { |
| + HRTS2_N_MARK, HCTS2_N_MARK, |
| +}; |
| +static const unsigned int hscif2_data_b_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22), |
| +}; |
| +static const unsigned int hscif2_data_b_mux[] = { |
| + HRX2_B_MARK, HTX2_B_MARK, |
| +}; |
| +static const unsigned int hscif2_ctrl_b_pins[] = { |
| + /* RTS, CTS */ |
| + RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21), |
| +}; |
| +static const unsigned int hscif2_ctrl_b_mux[] = { |
| + HRTS2_N_B_MARK, HCTS2_N_B_MARK, |
| +}; |
| +static const unsigned int hscif2_data_c_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), |
| +}; |
| +static const unsigned int hscif2_data_c_mux[] = { |
| + HRX2_C_MARK, HTX2_C_MARK, |
| +}; |
| +static const unsigned int hscif2_clk_c_pins[] = { |
| + /* SCK */ |
| + RCAR_GP_PIN(5, 31), |
| +}; |
| +static const unsigned int hscif2_clk_c_mux[] = { |
| + HSCK2_C_MARK, |
| +}; |
| +static const unsigned int hscif2_data_d_pins[] = { |
| + /* RX, TX */ |
| + RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31), |
| +}; |
| +static const unsigned int hscif2_data_d_mux[] = { |
| + HRX2_B_MARK, HTX2_D_MARK, |
| +}; |
| /* - I2C0 ------------------------------------------------------------------- */ |
| static const unsigned int i2c0_pins[] = { |
| /* SCL, SDA */ |
| @@ -3885,6 +4071,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { |
| SH_PFC_PIN_GROUP(eth_magic), |
| SH_PFC_PIN_GROUP(eth_mdio), |
| SH_PFC_PIN_GROUP(eth_rmii), |
| + SH_PFC_PIN_GROUP(hscif0_data), |
| + SH_PFC_PIN_GROUP(hscif0_clk), |
| + SH_PFC_PIN_GROUP(hscif0_ctrl), |
| + SH_PFC_PIN_GROUP(hscif0_data_b), |
| + SH_PFC_PIN_GROUP(hscif0_ctrl_b), |
| + SH_PFC_PIN_GROUP(hscif0_data_c), |
| + SH_PFC_PIN_GROUP(hscif0_clk_c), |
| + SH_PFC_PIN_GROUP(hscif1_data), |
| + SH_PFC_PIN_GROUP(hscif1_clk), |
| + SH_PFC_PIN_GROUP(hscif1_ctrl), |
| + SH_PFC_PIN_GROUP(hscif1_data_b), |
| + SH_PFC_PIN_GROUP(hscif1_data_c), |
| + SH_PFC_PIN_GROUP(hscif1_clk_c), |
| + SH_PFC_PIN_GROUP(hscif1_ctrl_c), |
| + SH_PFC_PIN_GROUP(hscif1_data_d), |
| + SH_PFC_PIN_GROUP(hscif1_data_e), |
| + SH_PFC_PIN_GROUP(hscif1_clk_e), |
| + SH_PFC_PIN_GROUP(hscif1_ctrl_e), |
| + SH_PFC_PIN_GROUP(hscif2_data), |
| + SH_PFC_PIN_GROUP(hscif2_clk), |
| + SH_PFC_PIN_GROUP(hscif2_ctrl), |
| + SH_PFC_PIN_GROUP(hscif2_data_b), |
| + SH_PFC_PIN_GROUP(hscif2_ctrl_b), |
| + SH_PFC_PIN_GROUP(hscif2_data_c), |
| + SH_PFC_PIN_GROUP(hscif2_clk_c), |
| + SH_PFC_PIN_GROUP(hscif2_data_d), |
| SH_PFC_PIN_GROUP(i2c0), |
| SH_PFC_PIN_GROUP(i2c0_b), |
| SH_PFC_PIN_GROUP(i2c0_c), |
| @@ -4183,6 +4395,41 @@ static const char * const eth_groups[] = { |
| "eth_rmii", |
| }; |
| |
| +static const char * const hscif0_groups[] = { |
| + "hscif0_data", |
| + "hscif0_clk", |
| + "hscif0_ctrl", |
| + "hscif0_data_b", |
| + "hscif0_ctrl_b", |
| + "hscif0_data_c", |
| + "hscif0_clk_c", |
| +}; |
| + |
| +static const char * const hscif1_groups[] = { |
| + "hscif1_data", |
| + "hscif1_clk", |
| + "hscif1_ctrl", |
| + "hscif1_data_b", |
| + "hscif1_data_c", |
| + "hscif1_clk_c", |
| + "hscif1_ctrl_c", |
| + "hscif1_data_d", |
| + "hscif1_data_e", |
| + "hscif1_clk_e", |
| + "hscif1_ctrl_e", |
| +}; |
| + |
| +static const char * const hscif2_groups[] = { |
| + "hscif2_data", |
| + "hscif2_clk", |
| + "hscif2_ctrl", |
| + "hscif2_data_b", |
| + "hscif2_ctrl_b", |
| + "hscif2_data_c", |
| + "hscif2_clk_c", |
| + "hscif2_data_d", |
| +}; |
| + |
| static const char * const i2c0_groups[] = { |
| "i2c0", |
| "i2c0_b", |
| @@ -4547,6 +4794,9 @@ static const struct sh_pfc_function pinmux_functions[] = { |
| SH_PFC_FUNCTION(du0), |
| SH_PFC_FUNCTION(du1), |
| SH_PFC_FUNCTION(eth), |
| + SH_PFC_FUNCTION(hscif0), |
| + SH_PFC_FUNCTION(hscif1), |
| + SH_PFC_FUNCTION(hscif2), |
| SH_PFC_FUNCTION(i2c0), |
| SH_PFC_FUNCTION(i2c1), |
| SH_PFC_FUNCTION(i2c2), |
| -- |
| 2.1.2 |
| |