| From 271f89812cd7d4f735f2bbb931a7884a30ca4bd1 Mon Sep 17 00:00:00 2001 |
| From: Benoit Cousson <bcousson@baylibre.com> |
| Date: Tue, 3 Jun 2014 21:02:24 +0900 |
| Subject: ARM: shmobile: r8a7790/lager dts: Add DVFS parameters into cpu0 node |
| for r8a7790 |
| |
| Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. |
| |
| - voltage-tolerance = 1% |
| It reflects the tolerance for the CPU voltage defined inside the OPP |
| table. Due to the lack of proper OPP definition, use an arbitrary safe |
| value. |
| - clock-latency = 300 us |
| Approximate worst-case latency to do a full DVFS transition for every |
| OPPs. Due to the lack of HW information, use an arbitrary safe value. |
| Note: The term transition-latency will be more accurate to define this |
| value since the clock transition latency is not the only parameter that |
| will define the overall DVFS transition. |
| - operating-points = < kHz - uV > |
| List of 6 operating points. All of them are using the same voltage |
| since the valid Vmin voltage is not documented in the HW spec. |
| - clocks |
| phandle to the CPU clock source. This clock source is used for all the |
| 4 CortexA15 located inside the same cluster. |
| |
| Signed-off-by: Benoit Cousson <bcousson+renesas@baylibre.com> |
| [gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0] |
| Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> |
| Acked-by: Magnus Damm <damm@opensource.se> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| |
| (cherry picked from commit b989e1386385466761f703b8a91e00468bb5ca2a) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7790-lager.dts | 4 ++++ |
| arch/arm/boot/dts/r8a7790.dtsi | 11 +++++++++++ |
| 2 files changed, 15 insertions(+) |
| |
| diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts |
| index 8428204d9512..b9cbeda87530 100644 |
| --- a/arch/arm/boot/dts/r8a7790-lager.dts |
| +++ b/arch/arm/boot/dts/r8a7790-lager.dts |
| @@ -338,3 +338,7 @@ |
| regulator-always-on; |
| }; |
| }; |
| + |
| +&cpu0 { |
| + cpu0-supply = <&vdd_dvfs>; |
| +}; |
| diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi |
| index e2c7d6df5be4..e990d3c4fe62 100644 |
| --- a/arch/arm/boot/dts/r8a7790.dtsi |
| +++ b/arch/arm/boot/dts/r8a7790.dtsi |
| @@ -44,6 +44,17 @@ |
| compatible = "arm,cortex-a15"; |
| reg = <0>; |
| clock-frequency = <1300000000>; |
| + voltage-tolerance = <1>; /* 1% */ |
| + clocks = <&cpg_clocks R8A7790_CLK_Z>; |
| + clock-latency = <300000>; /* 300 us */ |
| + |
| + /* kHz - uV - OPPs unknown yet */ |
| + operating-points = <1400000 1000000>, |
| + <1225000 1000000>, |
| + <1050000 1000000>, |
| + < 875000 1000000>, |
| + < 700000 1000000>, |
| + < 350000 1000000>; |
| }; |
| |
| cpu1: cpu@1 { |
| -- |
| 2.1.2 |
| |
