| /* |
| * Copyright (C) 2013-2014 Imagination Technologies Ltd. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #ifndef _DT_BINDINGS_CLK_TZ1090_TOP_H |
| #define _DT_BINDINGS_CLK_TZ1090_TOP_H |
| |
| /* Ranges of top level clock numbers */ |
| #define CLK_TOP_CLKSWITCH_BASE 0 |
| #define CLK_TOP_CLKENAB_BASE (CLK_TOP_CLKSWITCH_BASE + 27) |
| #define CLK_TOP_CLKSWITCH2_BASE (CLK_TOP_CLKENAB_BASE + 9) |
| #define CLK_TOP_CLKENAB2_BASE (CLK_TOP_CLKSWITCH2_BASE + 10) |
| #define CLK_TOP_DEL_BASE (CLK_TOP_CLKENAB2_BASE + 7) |
| #define CLK_TOP_DIV_BASE (CLK_TOP_DEL_BASE + 4) |
| #define CLK_TOP_PLL_BASE (CLK_TOP_DIV_BASE + 18) |
| #define CLK_TOP_CLKEN_BASE (CLK_TOP_PLL_BASE + 2) |
| #define CLK_TOP_MAX (CLK_TOP_CLKEN_BASE + 1) |
| |
| |
| /* CR_TOP_CLKSWITCH clocks */ |
| #define CLK_TOP_SYS_SW (CLK_TOP_CLKSWITCH_BASE + 0) |
| #define CLK_TOP_SYS_X2_UNDELETED (CLK_TOP_CLKSWITCH_BASE + 1) |
| #define CLK_TOP_OUT0_SW0 (CLK_TOP_CLKSWITCH_BASE + 2) |
| #define CLK_TOP_OUT0_SW1 (CLK_TOP_CLKSWITCH_BASE + 3) |
| #define CLK_TOP_OUT0_SW2 (CLK_TOP_CLKSWITCH_BASE + 4) |
| #define CLK_TOP_OUT0_SW3 (CLK_TOP_CLKSWITCH_BASE + 5) |
| #define CLK_TOP_OUT1_SW0 (CLK_TOP_CLKSWITCH_BASE + 6) |
| #define CLK_TOP_OUT1_SW1 (CLK_TOP_CLKSWITCH_BASE + 7) |
| #define CLK_TOP_OUT1_SW2 (CLK_TOP_CLKSWITCH_BASE + 8) |
| #define CLK_TOP_OUT1_SW3 (CLK_TOP_CLKSWITCH_BASE + 9) |
| #define CLK_TOP_I2S_SW2 (CLK_TOP_CLKSWITCH_BASE + 10) |
| #define CLK_TOP_I2S_SW0 (CLK_TOP_CLKSWITCH_BASE + 11) |
| #define CLK_TOP_I2S_SW1 (CLK_TOP_CLKSWITCH_BASE + 12) |
| #define CLK_TOP_SCB_SW (CLK_TOP_CLKSWITCH_BASE + 13) |
| #define CLK_TOP_UART_SW (CLK_TOP_CLKSWITCH_BASE + 14) |
| #define CLK_TOP_EXT_STC0_SW (CLK_TOP_CLKSWITCH_BASE + 15) |
| #define CLK_TOP_EXT_STC1_SW (CLK_TOP_CLKSWITCH_BASE + 16) |
| #define CLK_TOP_USB_SW0 (CLK_TOP_CLKSWITCH_BASE + 17) |
| #define CLK_TOP_USB_SW1 (CLK_TOP_CLKSWITCH_BASE + 18) |
| #define CLK_TOP_AFE_SW0 (CLK_TOP_CLKSWITCH_BASE + 19) |
| #define CLK_TOP_AFE_SW1 (CLK_TOP_CLKSWITCH_BASE + 20) |
| #define CLK_TOP_ADCPLL_SW0 (CLK_TOP_CLKSWITCH_BASE + 21) |
| #define CLK_TOP_ADCPLL_SW1 (CLK_TOP_CLKSWITCH_BASE + 22) |
| #define CLK_TOP_ADCPLL_SW2 (CLK_TOP_CLKSWITCH_BASE + 23) |
| #define CLK_TOP_ADCPLL_SW3 (CLK_TOP_CLKSWITCH_BASE + 24) |
| #define CLK_TOP_USB_SW2 (CLK_TOP_CLKSWITCH_BASE + 25) |
| #define CLK_TOP_USB_SW3 (CLK_TOP_CLKSWITCH_BASE + 26) |
| |
| /* CR_TOP_CLKENAB clocks */ |
| #define CLK_TOP_OUT0_EN (CLK_TOP_CLKENAB_BASE + 0) |
| #define CLK_TOP_OUT1_EN (CLK_TOP_CLKENAB_BASE + 1) |
| #define CLK_TOP_I2S_EN (CLK_TOP_CLKENAB_BASE + 2) |
| #define CLK_TOP_SCB (CLK_TOP_CLKENAB_BASE + 3) |
| #define CLK_TOP_UART_EN (CLK_TOP_CLKENAB_BASE + 4) |
| #define CLK_TOP_EXT_STC0 (CLK_TOP_CLKENAB_BASE + 5) |
| #define CLK_TOP_EXT_STC1 (CLK_TOP_CLKENAB_BASE + 6) |
| #define CLK_TOP_USB_EN (CLK_TOP_CLKENAB_BASE + 7) |
| #define CLK_TOP_ADCPLL_EN (CLK_TOP_CLKENAB_BASE + 8) |
| |
| /* CR_TOP_CLKSWITCH2 clocks */ |
| #define CLK_TOP_PIXEL_SW0 (CLK_TOP_CLKSWITCH2_BASE + 0) |
| #define CLK_TOP_PIXEL_SW1 (CLK_TOP_CLKSWITCH2_BASE + 1) |
| #define CLK_TOP_PIXEL_SW2 (CLK_TOP_CLKSWITCH2_BASE + 2) |
| #define CLK_TOP_PIXEL_SW3 (CLK_TOP_CLKSWITCH2_BASE + 3) |
| #define CLK_TOP_PIXEL_SW4 (CLK_TOP_CLKSWITCH2_BASE + 4) |
| #define CLK_TOP_IF1_SW (CLK_TOP_CLKSWITCH2_BASE + 5) |
| #define CLK_TOP_IF0_SW (CLK_TOP_CLKSWITCH2_BASE + 6) |
| #define CLK_TOP_DAC0_SW (CLK_TOP_CLKSWITCH2_BASE + 7) |
| #define CLK_TOP_UCC1_SW (CLK_TOP_CLKSWITCH2_BASE + 8) |
| #define CLK_TOP_UCC0_SW (CLK_TOP_CLKSWITCH2_BASE + 9) |
| |
| /* CR_TOP_CLKENAB2 clocks */ |
| #define CLK_TOP_PIXEL_EN (CLK_TOP_CLKENAB2_BASE + 0) |
| #define CLK_TOP_IF1 (CLK_TOP_CLKENAB2_BASE + 1) |
| #define CLK_TOP_IF0 (CLK_TOP_CLKENAB2_BASE + 2) |
| #define CLK_TOP_EXT_ADC_EN (CLK_TOP_CLKENAB2_BASE + 3) |
| #define CLK_TOP_DAC0 (CLK_TOP_CLKENAB2_BASE + 4) |
| #define CLK_TOP_SYS_UCC1 (CLK_TOP_CLKENAB2_BASE + 5) |
| #define CLK_TOP_SYS_MTX (CLK_TOP_CLKENAB2_BASE + 6) |
| |
| /* Clock deleters */ |
| #define CLK_TOP_SYS (CLK_TOP_DEL_BASE + 0) |
| #define CLK_TOP_META (CLK_TOP_DEL_BASE + 1) |
| #define CLK_TOP_UCC0 (CLK_TOP_DEL_BASE + 2) |
| #define CLK_TOP_UCC1_DEL (CLK_TOP_DEL_BASE + 3) |
| |
| /* Clock dividers */ |
| #define CLK_TOP_SYS_DIV (CLK_TOP_DIV_BASE + 0) |
| #define CLK_TOP_SYS_UNDELETED (CLK_TOP_DIV_BASE + 1) |
| #define CLK_TOP_AFE (CLK_TOP_DIV_BASE + 2) |
| #define CLK_TOP_ADCPLL_DIV (CLK_TOP_DIV_BASE + 3) |
| #define CLK_TOP_UART (CLK_TOP_DIV_BASE + 4) |
| #define CLK_TOP_PDM (CLK_TOP_DIV_BASE + 5) |
| #define CLK_TOP_SPI0 (CLK_TOP_DIV_BASE + 6) |
| #define CLK_TOP_SPI1 (CLK_TOP_DIV_BASE + 7) |
| #define CLK_TOP_I2SM (CLK_TOP_DIV_BASE + 8) |
| #define CLK_TOP_USB_PHY (CLK_TOP_DIV_BASE + 9) |
| #define CLK_TOP_SDHOST (CLK_TOP_DIV_BASE + 10) |
| #define CLK_TOP_RING_OSC (CLK_TOP_DIV_BASE + 11) |
| #define CLK_TOP_I2S (CLK_TOP_DIV_BASE + 12) |
| #define CLK_TOP_META_TRACE (CLK_TOP_DIV_BASE + 13) |
| #define CLK_TOP_PIXEL (CLK_TOP_DIV_BASE + 14) |
| #define CLK_TOP_OUT0 (CLK_TOP_DIV_BASE + 15) |
| #define CLK_TOP_OUT1 (CLK_TOP_DIV_BASE + 16) |
| #define CLK_TOP_DDR (CLK_TOP_DIV_BASE + 17) |
| |
| /* PLL clocks */ |
| #define CLK_TOP_SYSPLL (CLK_TOP_PLL_BASE + 0) |
| #define CLK_TOP_ADCPLL (CLK_TOP_PLL_BASE + 1) |
| |
| /* CR_TOP_CLKEN clocks */ |
| #define CLK_TOP_PDC (CLK_TOP_CLKEN_BASE + 0) |
| |
| #endif |
