| /* |
| * Device Tree Source for the r8a7795 SoC |
| * |
| * Copyright (C) 2015 Renesas Electronics Corp. |
| * |
| * This file is licensed under the terms of the GNU General Public License |
| * version 2. This program is licensed "as is" without any warranty of any |
| * kind, whether express or implied. |
| */ |
| |
| #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "renesas,r8a7795"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| i2c6 = &i2c6; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| a57_0: cpu@0 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| reg = <0x0>; |
| device_type = "cpu"; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| }; |
| |
| a57_1: cpu@1 { |
| compatible = "arm,cortex-a57","arm,armv8"; |
| reg = <0x1>; |
| device_type = "cpu"; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| }; |
| a57_2: cpu@2 { |
| compatible = "arm,cortex-a57","arm,armv8"; |
| reg = <0x2>; |
| device_type = "cpu"; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| }; |
| a57_3: cpu@3 { |
| compatible = "arm,cortex-a57","arm,armv8"; |
| reg = <0x3>; |
| device_type = "cpu"; |
| next-level-cache = <&L2_CA57>; |
| enable-method = "psci"; |
| }; |
| }; |
| |
| L2_CA57: cache-controller@0 { |
| compatible = "cache"; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| L2_CA53: cache-controller@1 { |
| compatible = "cache"; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| extalr_clk: extalr { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| /* |
| * The external audio clocks are configured as 0 Hz fixed frequency |
| * clocks by default. |
| * Boards that provide audio clocks should override them. |
| */ |
| audio_clk_a: audio_clk_a { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| audio_clk_b: audio_clk_b { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| audio_clk_c: audio_clk_c { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External CAN clock - to be overridden by boards that provide it */ |
| can_clk: can { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External SCIF clock - to be overridden by boards that provide it */ |
| scif_clk: scif { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| /* External PCIe clock - can be overridden by the board */ |
| pcie_bus_clk: pcie_bus { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gic: interrupt-controller@0xf1010000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0xf1010000 0 0x1000>, |
| <0x0 0xf1020000 0 0x2000>, |
| <0x0 0xf1040000 0 0x20000>, |
| <0x0 0xf1060000 0 0x2000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| }; |
| |
| gpio0: gpio@e6050000 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6050000 0 0x50>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 16>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 912>; |
| power-domains = <&cpg>; |
| }; |
| |
| gpio1: gpio@e6051000 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6051000 0 0x50>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 28>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 911>; |
| power-domains = <&cpg>; |
| }; |
| |
| gpio2: gpio@e6052000 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6052000 0 0x50>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 15>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 910>; |
| power-domains = <&cpg>; |
| }; |
| |
| gpio3: gpio@e6053000 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6053000 0 0x50>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 16>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 909>; |
| power-domains = <&cpg>; |
| }; |
| |
| gpio4: gpio@e6054000 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6054000 0 0x50>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 18>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 908>; |
| power-domains = <&cpg>; |
| }; |
| |
| gpio5: gpio@e6055000 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055000 0 0x50>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 160 26>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 907>; |
| power-domains = <&cpg>; |
| }; |
| |
| gpio6: gpio@e6055400 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055400 0 0x50>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 192 32>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 906>; |
| power-domains = <&cpg>; |
| }; |
| |
| gpio7: gpio@e6055800 { |
| compatible = "renesas,gpio-r8a7795", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055800 0 0x50>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 224 4>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 905>; |
| power-domains = <&cpg>; |
| }; |
| |
| pmu_a57 { |
| compatible = "arm,cortex-a57-pmu"; |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&a57_0>, |
| <&a57_1>, |
| <&a57_2>, |
| <&a57_3>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| cpg: clock-controller@e6150000 { |
| compatible = "renesas,r8a7795-cpg-mssr"; |
| reg = <0 0xe6150000 0 0x1000>; |
| clocks = <&extal_clk>, <&extalr_clk>; |
| clock-names = "extal", "extalr"; |
| #clock-cells = <2>; |
| #power-domain-cells = <0>; |
| }; |
| |
| audma0: dma-controller@ec700000 { |
| compatible = "renesas,rcar-dmac"; |
| reg = <0 0xec700000 0 0x10000>; |
| interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 502>; |
| clock-names = "fck"; |
| power-domains = <&cpg>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| audma1: dma-controller@ec720000 { |
| compatible = "renesas,rcar-dmac"; |
| reg = <0 0xec720000 0 0x10000>; |
| interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 501>; |
| clock-names = "fck"; |
| power-domains = <&cpg>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| pfc: pfc@e6060000 { |
| compatible = "renesas,pfc-r8a7795"; |
| reg = <0 0xe6060000 0 0x50c>; |
| }; |
| |
| intc_ex: interrupt-controller@e61c0000 { |
| compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| reg = <0 0xe61c0000 0 0x200>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 407>; |
| power-domains = <&cpg>; |
| }; |
| |
| dmac0: dma-controller@e6700000 { |
| compatible = "renesas,dmac-r8a7795", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6700000 0 0x10000>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 219>; |
| clock-names = "fck"; |
| power-domains = <&cpg>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| dmac1: dma-controller@e7300000 { |
| compatible = "renesas,dmac-r8a7795", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7300000 0 0x10000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 218>; |
| clock-names = "fck"; |
| power-domains = <&cpg>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| dmac2: dma-controller@e7310000 { |
| compatible = "renesas,dmac-r8a7795", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7310000 0 0x10000>; |
| interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 217>; |
| clock-names = "fck"; |
| power-domains = <&cpg>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| avb: ethernet@e6800000 { |
| compatible = "renesas,etheravb-r8a7795", |
| "renesas,etheravb-rcar-gen3"; |
| reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "ch22", "ch23", |
| "ch24"; |
| clocks = <&cpg CPG_MOD 812>; |
| power-domains = <&cpg>; |
| phy-mode = "rgmii-id"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| can0: can@e6c30000 { |
| compatible = "renesas,can-r8a7795", |
| "renesas,rcar-gen3-can"; |
| reg = <0 0xe6c30000 0 0x1000>; |
| interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 916>, |
| <&cpg CPG_CORE R8A7795_CLK_CANFD>, |
| <&can_clk>; |
| clock-names = "clkp1", "clkp2", "can_clk"; |
| assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; |
| assigned-clock-rates = <40000000>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| can1: can@e6c38000 { |
| compatible = "renesas,can-r8a7795", |
| "renesas,rcar-gen3-can"; |
| reg = <0 0xe6c38000 0 0x1000>; |
| interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 915>, |
| <&cpg CPG_CORE R8A7795_CLK_CANFD>, |
| <&can_clk>; |
| clock-names = "clkp1", "clkp2", "can_clk"; |
| assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; |
| assigned-clock-rates = <40000000>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| hscif0: serial@e6540000 { |
| compatible = "renesas,hscif-r8a7795", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6540000 0 96>; |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 520>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x31>, <&dmac1 0x30>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| hscif1: serial@e6550000 { |
| compatible = "renesas,hscif-r8a7795", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6550000 0 96>; |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 519>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x33>, <&dmac1 0x32>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| hscif2: serial@e6560000 { |
| compatible = "renesas,hscif-r8a7795", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6560000 0 96>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 518>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x35>, <&dmac1 0x34>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| hscif3: serial@e66a0000 { |
| compatible = "renesas,hscif-r8a7795", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe66a0000 0 96>; |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 517>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x37>, <&dmac0 0x36>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| hscif4: serial@e66b0000 { |
| compatible = "renesas,hscif-r8a7795", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe66b0000 0 96>; |
| interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 516>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x39>, <&dmac0 0x38>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| scif0: serial@e6e60000 { |
| compatible = "renesas,scif-r8a7795", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e60000 0 64>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 207>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x51>, <&dmac1 0x50>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| scif1: serial@e6e68000 { |
| compatible = "renesas,scif-r8a7795", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e68000 0 64>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 206>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x53>, <&dmac1 0x52>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| scif2: serial@e6e88000 { |
| compatible = "renesas,scif-r8a7795", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6e88000 0 64>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 310>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x13>, <&dmac1 0x12>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| scif3: serial@e6c50000 { |
| compatible = "renesas,scif-r8a7795", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6c50000 0 64>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 204>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x57>, <&dmac0 0x56>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| scif4: serial@e6c40000 { |
| compatible = "renesas,scif-r8a7795", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6c40000 0 64>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 203>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x59>, <&dmac0 0x58>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| scif5: serial@e6f30000 { |
| compatible = "renesas,scif-r8a7795", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| reg = <0 0xe6f30000 0 64>; |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 202>, |
| <&cpg CPG_CORE R8A7795_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; |
| dma-names = "tx", "rx"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@e6500000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a7795"; |
| reg = <0 0xe6500000 0 0x40>; |
| interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 931>; |
| power-domains = <&cpg>; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@e6508000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a7795"; |
| reg = <0 0xe6508000 0 0x40>; |
| interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 930>; |
| power-domains = <&cpg>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@e6510000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a7795"; |
| reg = <0 0xe6510000 0 0x40>; |
| interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 929>; |
| power-domains = <&cpg>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@e66d0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a7795"; |
| reg = <0 0xe66d0000 0 0x40>; |
| interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 928>; |
| power-domains = <&cpg>; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@e66d8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a7795"; |
| reg = <0 0xe66d8000 0 0x40>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 927>; |
| power-domains = <&cpg>; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@e66e0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a7795"; |
| reg = <0 0xe66e0000 0 0x40>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 919>; |
| power-domains = <&cpg>; |
| i2c-scl-internal-delay-ns = <110>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@e66e8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "renesas,i2c-r8a7795"; |
| reg = <0 0xe66e8000 0 0x40>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 918>; |
| power-domains = <&cpg>; |
| i2c-scl-internal-delay-ns = <6>; |
| status = "disabled"; |
| }; |
| |
| rcar_sound: sound@ec500000 { |
| /* |
| * #sound-dai-cells is required |
| * |
| * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; |
| * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; |
| */ |
| /* |
| * #clock-cells is required for audio_clkout0/1/2/3 |
| * |
| * clkout : #clock-cells = <0>; <&rcar_sound>; |
| * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; |
| */ |
| compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; |
| reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| <0 0xec5a0000 0 0x100>, /* ADG */ |
| <0 0xec540000 0 0x1000>, /* SSIU */ |
| <0 0xec541000 0 0x280>, /* SSI */ |
| <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ |
| reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; |
| |
| clocks = <&cpg CPG_MOD 1005>, |
| <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, |
| <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, |
| <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, |
| <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, |
| <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, |
| <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
| <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, |
| <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, |
| <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, |
| <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, |
| <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
| <&audio_clk_a>, <&audio_clk_b>, |
| <&audio_clk_c>, |
| <&cpg CPG_CORE R8A7795_CLK_S0D4>; |
| clock-names = "ssi-all", |
| "ssi.9", "ssi.8", "ssi.7", "ssi.6", |
| "ssi.5", "ssi.4", "ssi.3", "ssi.2", |
| "ssi.1", "ssi.0", |
| "src.9", "src.8", "src.7", "src.6", |
| "src.5", "src.4", "src.3", "src.2", |
| "src.1", "src.0", |
| "dvc.0", "dvc.1", |
| "clk_a", "clk_b", "clk_c", "clk_i"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| |
| rcar_sound,dvc { |
| dvc0: dvc@0 { |
| dmas = <&audma0 0xbc>; |
| dma-names = "tx"; |
| }; |
| dvc1: dvc@1 { |
| dmas = <&audma0 0xbe>; |
| dma-names = "tx"; |
| }; |
| }; |
| |
| rcar_sound,src { |
| src0: src@0 { |
| interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x85>, <&audma1 0x9a>; |
| dma-names = "rx", "tx"; |
| }; |
| src1: src@1 { |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x87>, <&audma1 0x9c>; |
| dma-names = "rx", "tx"; |
| }; |
| src2: src@2 { |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x89>, <&audma1 0x9e>; |
| dma-names = "rx", "tx"; |
| }; |
| src3: src@3 { |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x8b>, <&audma1 0xa0>; |
| dma-names = "rx", "tx"; |
| }; |
| src4: src@4 { |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x8d>, <&audma1 0xb0>; |
| dma-names = "rx", "tx"; |
| }; |
| src5: src@5 { |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x8f>, <&audma1 0xb2>; |
| dma-names = "rx", "tx"; |
| }; |
| src6: src@6 { |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x91>, <&audma1 0xb4>; |
| dma-names = "rx", "tx"; |
| }; |
| src7: src@7 { |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x93>, <&audma1 0xb6>; |
| dma-names = "rx", "tx"; |
| }; |
| src8: src@8 { |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x95>, <&audma1 0xb8>; |
| dma-names = "rx", "tx"; |
| }; |
| src9: src@9 { |
| interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x97>, <&audma1 0xba>; |
| dma-names = "rx", "tx"; |
| }; |
| }; |
| |
| rcar_sound,ssi { |
| ssi0: ssi@0 { |
| interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi1: ssi@1 { |
| interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi2: ssi@2 { |
| interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi3: ssi@3 { |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi4: ssi@4 { |
| interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi5: ssi@5 { |
| interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi6: ssi@6 { |
| interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi7: ssi@7 { |
| interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi8: ssi@8 { |
| interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| ssi9: ssi@9 { |
| interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; |
| dma-names = "rx", "tx", "rxu", "txu"; |
| }; |
| }; |
| }; |
| |
| sata: sata@ee300000 { |
| compatible = "renesas,sata-r8a7795"; |
| reg = <0 0xee300000 0 0x1fff>; |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 815>; |
| status = "disabled"; |
| }; |
| |
| xhci0: usb@ee000000 { |
| compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; |
| reg = <0 0xee000000 0 0xc00>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 328>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| xhci1: usb@ee0400000 { |
| compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; |
| reg = <0 0xee040000 0 0xc00>; |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 327>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| usb_dmac0: dma-controller@e65a0000 { |
| compatible = "renesas,r8a7795-usb-dmac", |
| "renesas,usb-dmac"; |
| reg = <0 0xe65a0000 0 0x100>; |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1"; |
| clocks = <&cpg CPG_MOD 330>; |
| power-domains = <&cpg>; |
| #dma-cells = <1>; |
| dma-channels = <2>; |
| }; |
| |
| usb_dmac1: dma-controller@e65b0000 { |
| compatible = "renesas,r8a7795-usb-dmac", |
| "renesas,usb-dmac"; |
| reg = <0 0xe65b0000 0 0x100>; |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1"; |
| clocks = <&cpg CPG_MOD 331>; |
| power-domains = <&cpg>; |
| #dma-cells = <1>; |
| dma-channels = <2>; |
| }; |
| |
| sdhi0: sd@ee100000 { |
| compatible = "renesas,sdhi-r8a7795"; |
| reg = <0 0xee100000 0 0x2000>; |
| interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 314>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| sdhi1: sd@ee120000 { |
| compatible = "renesas,sdhi-r8a7795"; |
| reg = <0 0xee120000 0 0x2000>; |
| interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 313>; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| sdhi2: sd@ee140000 { |
| compatible = "renesas,sdhi-r8a7795"; |
| reg = <0 0xee140000 0 0x2000>; |
| interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 312>; |
| power-domains = <&cpg>; |
| cap-mmc-highspeed; |
| status = "disabled"; |
| }; |
| |
| sdhi3: sd@ee160000 { |
| compatible = "renesas,sdhi-r8a7795"; |
| reg = <0 0xee160000 0 0x2000>; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 311>; |
| power-domains = <&cpg>; |
| cap-mmc-highspeed; |
| status = "disabled"; |
| }; |
| |
| usb2_phy0: usb-phy@ee080200 { |
| compatible = "renesas,usb2-phy-r8a7795"; |
| reg = <0 0xee080200 0 0x700>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>; |
| power-domains = <&cpg>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| usb2_phy1: usb-phy@ee0a0200 { |
| compatible = "renesas,usb2-phy-r8a7795"; |
| reg = <0 0xee0a0200 0 0x700>; |
| clocks = <&cpg CPG_MOD 702>; |
| power-domains = <&cpg>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| usb2_phy2: usb-phy@ee0c0200 { |
| compatible = "renesas,usb2-phy-r8a7795"; |
| reg = <0 0xee0c0200 0 0x700>; |
| clocks = <&cpg CPG_MOD 701>; |
| power-domains = <&cpg>; |
| #phy-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| ehci0: usb@ee080100 { |
| compatible = "generic-ehci"; |
| reg = <0 0xee080100 0 0x100>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>; |
| phys = <&usb2_phy0>; |
| phy-names = "usb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| ehci1: usb@ee0a0100 { |
| compatible = "generic-ehci"; |
| reg = <0 0xee0a0100 0 0x100>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 702>; |
| phys = <&usb2_phy1>; |
| phy-names = "usb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| ehci2: usb@ee0c0100 { |
| compatible = "generic-ehci"; |
| reg = <0 0xee0c0100 0 0x100>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 701>; |
| phys = <&usb2_phy2>; |
| phy-names = "usb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| ohci0: usb@ee080000 { |
| compatible = "generic-ohci"; |
| reg = <0 0xee080000 0 0x100>; |
| interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 703>; |
| phys = <&usb2_phy0>; |
| phy-names = "usb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| ohci1: usb@ee0a0000 { |
| compatible = "generic-ohci"; |
| reg = <0 0xee0a0000 0 0x100>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 702>; |
| phys = <&usb2_phy1>; |
| phy-names = "usb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| ohci2: usb@ee0c0000 { |
| compatible = "generic-ohci"; |
| reg = <0 0xee0c0000 0 0x100>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 701>; |
| phys = <&usb2_phy2>; |
| phy-names = "usb"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| pciec0: pcie@fe000000 { |
| compatible = "renesas,pcie-r8a7795"; |
| reg = <0 0xfe000000 0 0x80000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x00 0xff>; |
| device_type = "pci"; |
| ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 |
| 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 |
| 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 |
| 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; |
| /* Map all possible DDR as inbound ranges */ |
| dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; |
| clock-names = "pcie", "pcie_bus"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| |
| pciec1: pcie@ee800000 { |
| compatible = "renesas,pcie-r8a7795"; |
| reg = <0 0xee800000 0 0x80000>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| bus-range = <0x00 0xff>; |
| device_type = "pci"; |
| ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 |
| 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 |
| 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 |
| 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; |
| /* Map all possible DDR as inbound ranges */ |
| dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; |
| interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; |
| clock-names = "pcie", "pcie_bus"; |
| power-domains = <&cpg>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
