arch/riscv/boot/dts/kendryte/k210.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
 */
#include <dt-bindings/clock/k210-clk.h>

/ {
	/*
	 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
	 * wide, and the upper half of all addresses is ignored.
	 */
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "kendryte,k210";

	aliases {
		serial0 = &uarths0;
	};

	/*
	 * The K210 has an sv39 MMU following the priviledge specification v1.9.
	 * Since this is a non-ratified draft specification, the kernel does not
	 * support it and the K210 support enabled only for the !MMU case.
	 * Be consistent with this by setting the CPUs MMU type to "none".
	 */
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <7800000>;
		cpu0: cpu@0 {
			device_type = "cpu";
			reg = <0>;
			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
			riscv,isa = "rv64imafdc";
			mmu-type = "none";
			i-cache-size = <0x8000>;
			i-cache-block-size = <64>;
			d-cache-size = <0x8000>;
			d-cache-block-size = <64>;
			clocks = <&sysctl K210_CLK_CPU>;
			clock-frequency = <390000000>;
			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
			};
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			reg = <1>;
			compatible = "kendryte,k210", "sifive,rocket0", "riscv";
			riscv,isa = "rv64imafdc";
			mmu-type = "none";
			i-cache-size = <0x8000>;
			i-cache-block-size = <64>;
			d-cache-size = <0x8000>;
			d-cache-block-size = <64>;
			clocks = <&sysctl K210_CLK_CPU>;
			clock-frequency = <390000000>;
			cpu1_intc: interrupt-controller {
				#interrupt-cells = <1>;
				interrupt-controller;
				compatible = "riscv,cpu-intc";
			};
		};
	};

	sram: memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x400000>,
		      <0x80400000 0x200000>,
		      <0x80600000 0x200000>;
		reg-names = "sram0", "sram1", "aisram";
	};

	clocks {
		in0: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "kendryte,k210-soc", "simple-bus";
		ranges;
		interrupt-parent = <&plic0>;

		sysctl: sysctl@50440000 {
			compatible = "kendryte,k210-sysctl", "simple-mfd";
			reg = <0x50440000 0x1000>;
			#clock-cells = <1>;
		};

		clint0: interrupt-controller@2000000 {
			compatible = "riscv,clint0";
			reg = <0x2000000 0xC000>;
			interrupts-extended = <&cpu0_intc 3>,  <&cpu1_intc 3>;
			clocks = <&sysctl K210_CLK_ACLK>;
		};

		plic0: interrupt-controller@c000000 {
			#interrupt-cells = <1>;
			interrupt-controller;
			compatible = "kendryte,k210-plic0", "riscv,plic0";
			reg = <0xC000000 0x4000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>,
					      <&cpu1_intc 11>, <&cpu1_intc 0xffffffff>;
			riscv,ndev = <65>;
			riscv,max-priority = <7>;
		};

		uarths0: serial@38000000 {
			compatible = "kendryte,k210-uarths", "sifive,uart0";
			reg = <0x38000000 0x1000>;
			interrupts = <33>;
			clocks = <&sysctl K210_CLK_CPU>;
		};
	};
};