arch/arm/mach-pxa/mp900.c

/*
 * arch/arm/mach-pxa/mp900.c
 *
 * Support for the NEC MobilePro900/C platform
 *
 * Based on mach-pxa/gumstix.c
 *
 * 2007, 2008 Kristoffer Ericson <kristoffer.ericson@gmail.com>
 * 2007, 2008 Michael Petchkovsky <mkpetch@internode.on.net>
 * 2010       Yulay Rakhmangulov <yulayr@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/types.h>
#include <linux/usb/isp116x.h>
#include <linux/spi/spi.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>

#include <mach/pxa25x.h>
#include <mach/irqs.h>
#include <mach/gpio.h>
#include <mach/ssp.h>
#include <mach/pxa2xx_spi.h>
#include <mach/mfp-pxa25x.h>
#include <mach/irda.h>

#include "generic.h"

#include <video/s1d13xxxfb.h>


/* Video controller */

#define S1D13MP900_FB_PHYS	0x0C200000
#define S1D13MP900_REG_PHYS	0x0C000000
#define S1D13MP900_FB_SIZE	0x00140000
#define S1D13MP900_REG_SIZE	0x00100000

static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = {
	{0x0001, 0x00}, /* Miscellaneous Register */
	{0x01FC, 0x01}, /* Display Mode Register */
	{0x0004, 0x37}, /* General IO Pins Configuration Register 0 */
	{0x0005, 0x00}, /* General IO Pins Configuration Register 1 */
	{0x0008, 0xFE}, /* General IO Pins Control Register 0 */
	{0x0009, 0x1F}, /* General IO Pins Control Register 1 */
	{0x0010, 0x01}, /* Memory Clock Configuration Register */
	{0x0014, 0x21}, /* LCD Pixel Clock Configuration Register */
	{0x0018, 0x11}, /* CRT/TV Pixel Clock Configuration Register */
	{0x001C, 0x21}, /* MediaPlug Clock Configuration Register */
	{0x001E, 0x01}, /* CPU To Memory Wait State Select Register */
	{0x0020, 0x80}, /* Memory Configuration Register */
	{0x0021, 0x03}, /* DRAM Refresh Rate Register */
	{0x002A, 0x00}, /* DRAM Timings Control Register 0 */
	{0x002B, 0x01}, /* DRAM Timings Control Register 1 */
	{0x0030, 0x1C}, /* Panel Type Register */
	{0x0031, 0x00}, /* MOD Rate Register */
	{0x0032, 0x4F}, /* LCD Horizontal Display Width Register */
	{0x0034, 0x03}, /* LCD Horizontal Non-Display Period Register */
	{0x0035, 0x01}, /* TFT FPLINE Start Position Register */
	{0x0036, 0x0B}, /* TFT FPLINE Pulse Width Register */
	{0x0038, 0xEF}, /* LCD Vertical Display Height Register 0 */
	{0x0039, 0x00}, /* LCD Vertical Display Height Register 1 */
	{0x003A, 0x1D}, /* LCD Vertical Non-Display Period Register */
	{0x003B, 0x0A}, /* TFT FPFRAME Start Position Register */
	{0x003C, 0x01}, /* TFT FPFRAME Pulse Width Register */
	{0x0040, 0x05}, /* LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) */
	{0x0041, 0x01}, /* LCD Miscellaneous Register */
	{0x0042, 0x00}, /* LCD Display Start Address Register 0 */
	{0x0043, 0x00}, /* LCD Display Start Address Register 1 */
	{0x0044, 0x00}, /* LCD Display Start Address Register 2 */
	{0x0046, 0x80}, /* LCD Memory Address Offset Register 0 */
	{0x0047, 0x02}, /* LCD Memory Address Offset Register 1 */
	{0x0048, 0x00}, /* LCD Pixel Panning Register */
	{0x004A, 0x00}, /* LCD Display FIFO High Threshold Control Register */
	{0x004B, 0x00}, /* LCD Display FIFO Low Threshold Control Register */
	{0x0050, 0x4F}, /* CRT/TV Horizontal Display Width Register */
	{0x0052, 0x0F}, /* CRT/TV Horizontal Non-Display Period Register */
	{0x0053, 0x01}, /* CRT/TV HRTC Start Position Register */
	{0x0054, 0x0B}, /* CRT/TV HRTC Pulse Width Register */
	{0x0056, 0xDF}, /* CRT/TV Vertical Display Height Register 0 */
	{0x0057, 0x01}, /* CRT/TV Vertical Display Height Register 1 */
	{0x0058, 0x20}, /* CRT/TV Vertical Non-Display Period Register */
	{0x0059, 0x09}, /* CRT/TV VRTC Start Position Register */
	{0x005A, 0x01}, /* CRT/TV VRTC Pulse Width Register */
	{0x005B, 0x18}, /* TV Output Control Register */
	{0x0060, 0x85}, /* CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) */
	{0x0062, 0x00}, /* CRT/TV Display Start Address Register 0 */
	{0x0063, 0x00}, /* CRT/TV Display Start Address Register 1 */
	{0x0064, 0x00}, /* CRT/TV Display Start Address Register 2 */
	{0x0066, 0x80}, /* CRT/TV Memory Address Offset Register 0 */
	{0x0067, 0x02}, /* CRT/TV Memory Address Offset Register 1 */
	{0x0068, 0x00}, /* CRT/TV Pixel Panning Register */
	{0x006A, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
	{0x006B, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
	{0x0070, 0x01}, /* LCD Ink/Cursor Control Register */
	{0x0071, 0x01}, /* Ink/Cursor Start Address Register */
	{0x0072, 0xff}, /* LCD Cursor X Position Register 0 */
	{0x0073, 0x00}, /* LCD Cursor X Position Register 1 */
	{0x0074, 0xff}, /* LCD Cursor Y Position Register 0 */
	{0x0075, 0x00}, /* LCD Cursor Y Position Register 1 */
	{0x0076, 0x00}, /* LCD Ink/Cursor Blue Color 0 Registerv */
	{0x0077, 0x00}, /* LCD Ink/Cursor Green Color 0 Register */
	{0x0078, 0x00}, /* LCD Ink/Cursor Red Color 0 Register */
	{0x007A, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
	{0x007B, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
	{0x007C, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
	{0x007E, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
	{0x0080, 0x01}, /* CRT/TV Ink/Cursor Control Register */
	{0x0081, 0x01}, /* CRT/TV Ink/Cursor Start Address Register */
	{0x0082, 0xB6}, /* CRT/TV Cursor X Position Register 0 */
	{0x0083, 0x00}, /* CRT/TV Cursor X Position Register 1 */
	{0x0084, 0x4D}, /* CRT/TV Cursor Y Position Register 0 */
	{0x0085, 0x00}, /* CRT/TV Cursor Y Position Register 1 */
	{0x0086, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
	{0x0087, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
	{0x0088, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
	{0x008A, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
	{0x008B, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
	{0x008C, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
	{0x008E, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
	{0x0100, 0x00}, /* BitBlt Control Register 0 */
	{0x0101, 0x01}, /* BitBlt Control Register 1 */
	{0x0102, 0x07}, /* BitBlt ROP Code/Color Expansion Register */
	{0x0103, 0x09}, /* BitBlt Operation Register */
	{0x0104, 0x00}, /* BitBlt Source Start Address Register 0 */
	{0x0105, 0x00}, /* BitBlt Source Start Address Register 1 */
	{0x0106, 0x00}, /* BitBlt Source Start Address Register 2 */
	{0x0108, 0xA6}, /* BitBlt Destination Start Address Register 0 */
	{0x0109, 0xE2}, /* BitBlt Destination Start Address Register 1 */
	{0x010A, 0x01}, /* BitBlt Destination Start Address Register 2 */
	{0x010C, 0x80}, /* BitBlt Memory Address Offset Register 0 */
	{0x010D, 0x02}, /* BitBlt Memory Address Offset Register 1 */
	{0x0110, 0x04}, /* BitBlt Width Register 0 */
	{0x0111, 0x00}, /* BitBlt Width Register 1 */
	{0x0112, 0x03}, /* BitBlt Height Register 0 */
	{0x0113, 0x00}, /* BitBlt Height Register 1 */
	{0x0114, 0x00}, /* BitBlt Background Color Register 0 */
	{0x0115, 0x00}, /* BitBlt Background Color Register 1 */
	{0x0118, 0x00}, /* BitBlt Foreground Color Register 0 */
	{0x0119, 0x00}, /* BitBlt Foreground Color Register 1 */
	{0x01E0, 0x00}, /* Look-Up Table Mode Register */
	{0x01E2, 0x00}, /* Look-Up Table Address Register */
	{0x01E4, 0x10}, /* Look-Up Table Data Register */
	{0x01F0, 0x10}, /* Power Save Configuration Register */
	{0x01F1, 0x00}, /* Power Save Status Register */
	{0x01F4, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
	{0x01FC, 0x01}, /* Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) */
};

static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
	.initregs		= s1d13xxxfb_initregs,
	.initregssize		= ARRAY_SIZE(s1d13xxxfb_initregs),
	.platform_init_video	= NULL
};

static struct resource s1d13xxxfb_resources[] = {
	[0] = {
		.start	= S1D13MP900_FB_PHYS,
		.end	= S1D13MP900_FB_PHYS + S1D13MP900_FB_SIZE,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= S1D13MP900_REG_PHYS,
		.end	= S1D13MP900_REG_PHYS + S1D13MP900_REG_SIZE,
		.flags	= IORESOURCE_MEM,
	}
};

static struct platform_device s1d13xxxfb_device = {
	.name		= S1D_DEVICENAME,
	.id		= 0,
	.dev		= {
		.platform_data	= &s1d13xxxfb_data,
	},
	.num_resources	= ARRAY_SIZE(s1d13xxxfb_resources),
	.resource	= s1d13xxxfb_resources,
};

/* -------------------- mp900 MFP parameters -------------------- */

static unsigned long mp900_pin_config[] __initdata = {
	MFP_CFG_OUT(GPIO0, AF0, DRIVE_HIGH),	//| WAKEUP_ON_EDGE_RISE,

	GPIO1_RST,	/* RESET pin */

	GPIO4_GPIO | MFP_LPM_EDGE_BOTH,				//? IRQ_GPIO(4)

	GPIO6_GPIO | MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_FALL,	//? IRQ_GPIO(6)

	MFP_CFG_OUT(GPIO12, AF0, DRIVE_HIGH),	//? output

	/* USB chip Phillips isp116x */
	MFP_CFG_OUT(GPIO65, AF0, DRIVE_HIGH),	/* nRESET */
	/* USB Device Controller */
	GPIO3_GPIO | MFP_LPM_CAN_WAKEUP,	/* MFP_LPM_EDGE_FALL nINT2 */
	MFP_CFG_OUT(GPIO60, AF0, DRIVE_LOW),	/* D_WAKEUP */
	GPIO62_GPIO,				/* D_SUSPEND */
	/* USB Host Controller */
	GPIO2_GPIO | MFP_LPM_CAN_WAKEUP,	/* MFP_LPM_EDGE_RISE nINT1 */
	GPIO61_GPIO,				/* H_SUSPEND */
	
	GPIO63_GPIO, // | MFP_LPM_EDGE_FALL,	//? IRQ_GPIO(63)

	MFP_CFG_OUT(GPIO72, AF0, DRIVE_LOW),	//? output
	MFP_CFG_OUT(GPIO73, AF0, DRIVE_HIGH),	//? output
	MFP_CFG_OUT(GPIO74, AF0, DRIVE_LOW),	//? output

	/* SDRAM and Static Memory I/O Signals */
	GPIO15_nCS_1,
	GPIO78_nCS_2,
	GPIO79_nCS_3,
	GPIO80_nCS_4,
	GPIO33_nCS_5,

	/* Miscellaneous I/O and DMA Signals */
	GPIO18_RDY,
	GPIO20_DREQ_0,
	GPIO19_DREQ_1,

	/* CF CARD and PC CARD */
	GPIO5_GPIO | MFP_LPM_EDGE_FALL,		/* PRDY CF */
	GPIO7_GPIO | MFP_LPM_EDGE_FALL,		/* PRDY PCCARD */
	GPIO11_GPIO | MFP_LPM_EDGE_BOTH,	/* nCD CF */
	GPIO13_GPIO | MFP_LPM_EDGE_BOTH,	/* nCD PCCARD */
	GPIO48_nPOE,
	GPIO49_nPWE,
	GPIO50_nPIOR,
	GPIO51_nPIOW,
	GPIO52_nPCE_1,
	GPIO53_nPCE_2,
	GPIO54_nPSKTSEL,
	GPIO55_nPREG,
	GPIO56_nPWAIT,
	GPIO57_nIOIS16,
	GPIO75_GPIO | MFP_LPM_EDGE_BOTH,	/* CFCARD IRQ_GPIO(75) */
	GPIO76_GPIO | MFP_LPM_EDGE_BOTH,	/* PCCARD IRQ_GPIO(76) */

	/* FFUART - RS232 connector */
	GPIO34_FFUART_RXD,
	GPIO35_FFUART_CTS,
	GPIO36_FFUART_DCD,
	GPIO37_FFUART_DSR,
	GPIO38_FFUART_RI,
	GPIO39_FFUART_TXD,
	GPIO40_FFUART_DTR,
	GPIO41_FFUART_RTS,

	/* BTUART - connected to PIC */
	GPIO42_BTUART_RXD,
	GPIO43_BTUART_TXD,

	/* STUART */
	GPIO46_STUART_RXD,
	GPIO47_STUART_TXD,

	/* PWM 0/1 */
	GPIO16_PWM0_OUT,
	GPIO17_PWM1_OUT,

	/* I2S audio interface to Wolfson WM8731 */
	GPIO28_I2S_BITCLK_OUT,	/* BCLK */
	GPIO29_I2S_SDATA_IN,	/* ADCDAT */
	GPIO30_I2S_SDATA_OUT,	/* DACDAT */
	GPIO31_I2S_SYNC,		/**/
	GPIO32_I2S_SYSCLK,	/* XTI/MCLK */

	/* SSP 1 control interface to Wolfson WM8731 */
	GPIO23_SSP1_SCLK,
	GPIO24_SSP1_SFRM,	/* ADCDAT */
	GPIO25_SSP1_TXD,
	GPIO26_SSP1_RXD,

};


/* isp116x USB controller */
static void isp116x_hw_reset(void)
{
	unsigned long flags;
	
	printk(KERN_INFO "isp116x: Hardware reset...");

	local_irq_save(flags);

	GPCR(65) = GPIO_bit(65);	/* clear GPIO65 - activate nRESET */
	udelay(300);			/* AN10044: nRESET time min 160 uS */
	GPSR(65) = GPIO_bit(65);	/* set GPIO65 - deactivate nRESET */

	local_irq_restore(flags);

	mdelay(1);
	printk(" done\n");
}

static void isp116x_pfm_delay(struct device *dev, int delay)
{
        /* 400Mhz PXA2 = 2.5ns / instruction */

         int cyc = delay / 5; //10;

         /* 4 Instructions = 4 x 2.5ns = 10ns */
         __asm__ volatile ("0:\n"
                 "subs %0, %1, #1\n"
                 "bge 0b\n"
                 :"=r" (cyc)
                 :"0"(cyc)
         );
}

static struct isp116x_platform_data isp116x_pfm_data = {
	.sel15Kres		= 1, /* Enable internal resistors on downstream ports */
	.oc_enable		= 0, /* On-chip overcurrent protection */
	.int_act_high		= 1, /* INT output polarity */
	.int_edge_triggered	= 1, /* INT edge or level triggered */
	.remote_wakeup_enable	= 0, /* Wakeup by devices on usb bus */
	.delay			= isp116x_pfm_delay,
};

static struct resource isp116x_pfm_resources[] = {
	[0] =	{
		.start	= 0x0d000000,	/* Host data port */
		.end	= 0x0d000001,
		.flags	= IORESOURCE_MEM,
		},
	[1] =	{
		.start  = 0x0d000002,	/* Host command port */
		.end	= 0x0d000003,
		.flags  = IORESOURCE_MEM,
		},
	[2] =	{
		.start	= IRQ_GPIO(2),
		.end	= IRQ_GPIO(2),
		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
		},
};

static struct platform_device mp900_usb_device = {
	.name		= "isp116x-hcd",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(isp116x_pfm_resources),
	.resource	= isp116x_pfm_resources,
	.dev		= {
		.platform_data = &isp116x_pfm_data,
	}
};

/* Communication with PIC controller throught BTUART */
static struct resource mp900_pic_resources[] = {
	[0] = {
		.start	= 0x40200000,
		.end	= 0x40200023,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= IRQ_BTUART,
		.end	= IRQ_BTUART,
		.flags	= IORESOURCE_IRQ,
	}
};

static struct platform_device mp900_pic_device = {
	.name		= "pic-pxa2xx",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(mp900_pic_resources),
	.resource	= mp900_pic_resources,
};

static struct platform_device mp900_kbd_device = {
	.name		= "mp900-kbd",
	.id		= -1,
	.dev		= {
		.parent = &mp900_pic_device.dev,
	}
};

static struct platform_device mp900_ts_device = {
	.name		= "mp900-ts",
	.id		= -1,
	.dev		= {
		.parent = &mp900_pic_device.dev,
	}
};

static struct platform_device mp900_bl_device = {
	.name		= "mp900-bl",
	.id			= -1,
	.dev		= {
		.parent = &mp900_pic_device.dev,
	}
};

static struct platform_device mp900_pm = {
	.name		= "mp900-pm",
	.id		= -1,
	.dev		= {
		.parent = &mp900_pic_device.dev,
	}
};

#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MASTER)
static struct pxa2xx_spi_master mp900_spi_info = {
		.num_chipselect = 1,
};

static struct spi_board_info spi_board_info[] __initdata = {
	[0] = {
			.modalias	= "wm8731",
			.max_speed_hz	= 1843200,
			.bus_num	= 1,
			.chip_select	= 0,
	},
};

static void __init mp900_init_sound(void)
{
	pxa2xx_set_spi_info(1, &mp900_spi_info);
	spi_register_board_info(ARRAY_AND_SIZE(spi_board_info));
}
#else
static inline void mp900_init_sound(void) {}
#endif


static struct resource flash_resources[] = {
	[0] = {
		.start  = PXA_CS0_PHYS,
		.end    = PXA_CS0_PHYS + SZ_64M - 1,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = PXA_CS1_PHYS,
		.end    = PXA_CS1_PHYS + SZ_64M - 1,
		.flags  = IORESOURCE_MEM,
	},
};

static struct mtd_partition mp900flash0_partitions[] = {
	{
		.name =         "Bootloader",
		.size =         0x00080000,
		.offset =       0,
		.mask_flags =   MTD_WRITEABLE  /* force read-only */
	},{
		.name =         "Kernel",
		.size =         0x00400000,
		.offset =       0x00080000,
	},{
		.name =         "Filesystem",
		.size =         MTDPART_SIZ_FULL,
		.offset =       0x00480000
	}
};

static struct flash_platform_data mst_flash_data[2] = {
	{
		.name		= "StrataFlash0",
		.map_name       = "cfi_probe",
		.width		= 4,
		.parts          = mp900flash0_partitions,
		.nr_parts       = ARRAY_SIZE(mp900flash0_partitions),
	}, {
		.name		= "StrataFlash1",
		.map_name       = "cfi_probe",
		.width		= 4,
		.parts          = NULL,
		.nr_parts       = 0,
	}
};
 
static struct platform_device mst_flash_device[2] = {
	{
		.name           = "pxa2xx-flash",
		.id             = 0,
		.dev = {
			.platform_data = &mst_flash_data[0],
		},
		.resource = &flash_resources[0],
		.num_resources = 1,
	}, {
		.name           = "pxa2xx-flash",
		.id             = 1,
		.dev = {
			.platform_data = &mst_flash_data[1],
		},
		.resource = &flash_resources[1],
		.num_resources = 1,
	},
};

static struct platform_device *devices[] __initdata = {
	&mst_flash_device[0],
	&mst_flash_device[1],
	&s1d13xxxfb_device,
	&mp900_usb_device,
	&mp900_pic_device,
	&mp900_kbd_device,
	&mp900_ts_device,
	&mp900_bl_device,
	&mp900_pm,
};

static void mp900_irda_transceiver_mode(struct device *dev, int mode)
{
	unsigned long flags;

	local_irq_save(flags);
	/*	TODO Find GPIO to select mode and power
	*/
	pxa2xx_transceiver_mode(dev, mode);
	local_irq_restore(flags);
}

static struct pxaficp_platform_data mp900_ficp_platform_data = {
        .gpio_pwdown            = -1,
        .transceiver_cap        = IR_SIRMODE | IR_FIRMODE,
        .transceiver_mode       = mp900_irda_transceiver_mode,
};

static void __init mp900c_init(void)
{
	printk(KERN_INFO "MobilePro 900/C machine init\n");

	pxa2xx_mfp_config(ARRAY_AND_SIZE(mp900_pin_config));

	isp116x_hw_reset();
	
	pxa_set_ffuart_info(NULL); /* RS232 connector */

	pxa_set_ficp_info(&mp900_ficp_platform_data);

	mp900_init_sound();

	platform_add_devices(devices, ARRAY_SIZE(devices));
}

/* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
MACHINE_START(NEC_MP900, "MobilePro900/C")
	.phys_io	= 0x40000000,
	.boot_params	= 0xa0220100,
	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
	.timer		= &pxa_timer,
	.map_io		= pxa_map_io,
	.init_irq	= pxa25x_init_irq,
	.init_machine	= mp900c_init,
MACHINE_END