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/* bnx2x_reg.h: Broadcom Everest network driver.
*
* Copyright (c) 2007-2013 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation.
*
* The registers description starts with the register Access type followed
* by size in bits. For example [RW 32]. The access types are:
* R - Read only
* RC - Clear on read
* RW - Read/Write
* ST - Statistics register (clear on read)
* W - Write only
* WB - Wide bus register - the size is over 32 bits and it should be
* read/write in consecutive 32 bits accesses
* WR - Write Clear (write 1 to clear the bit)
*
*/
#ifndef BNX2X_REG_H
#define BNX2X_REG_H
#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
/* [RW 1] Initiate the ATC array - reset all the valid bits */
#define ATC_REG_ATC_INIT_ARRAY 0x1100b8
/* [R 1] ATC initalization done */
#define ATC_REG_ATC_INIT_DONE 0x1100bc
/* [RC 6] Interrupt register #0 read clear */
#define ATC_REG_ATC_INT_STS_CLR 0x1101c0
/* [RW 5] Parity mask register #0 read/write */
#define ATC_REG_ATC_PRTY_MASK 0x1101d8
/* [R 5] Parity register #0 read */
#define ATC_REG_ATC_PRTY_STS 0x1101cc
/* [RC 5] Parity register #0 read clear */
#define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
/* [RW 19] Interrupt mask register #0 read/write */
#define BRB1_REG_BRB1_INT_MASK 0x60128
/* [R 19] Interrupt register #0 read */
#define BRB1_REG_BRB1_INT_STS 0x6011c
/* [RW 4] Parity mask register #0 read/write */
#define BRB1_REG_BRB1_PRTY_MASK 0x60138
/* [R 4] Parity register #0 read */
#define BRB1_REG_BRB1_PRTY_STS 0x6012c
/* [RC 4] Parity register #0 read clear */
#define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
* address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
* BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
* following reset the first rbc access to this reg must be write; there can
* be no more rbc writes after the first one; there can be any number of rbc
* read following the first write; rbc access not following these rules will
* result in hang condition. */
#define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
/* [RW 10] The number of free blocks below which the full signal to class 0
* is asserted */
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
/* [RW 11] The number of free blocks above which the full signal to class 0
* is de-asserted */
#define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
#define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
/* [RW 11] The number of free blocks below which the full signal to class 1
* is asserted */
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
/* [RW 11] The number of free blocks above which the full signal to class 1
* is de-asserted */
#define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
#define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
/* [RW 11] The number of free blocks below which the full signal to the LB
* port is asserted */
#define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
/* [RW 10] The number of free blocks above which the full signal to the LB
* port is de-asserted */
#define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
/* [RW 10] The number of free blocks above which the High_llfc signal to
interface #n is de-asserted. */
#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
/* [RW 10] The number of free blocks below which the High_llfc signal to
interface #n is asserted. */
#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
/* [RW 11] The number of blocks guarantied for the LB port */
#define BRB1_REG_LB_GUARANTIED 0x601ec
/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
* before signaling XON. */
#define BRB1_REG_LB_GUARANTIED_HYST 0x60264
/* [RW 24] LL RAM data. */
#define BRB1_REG_LL_RAM 0x61000
/* [RW 10] The number of free blocks above which the Low_llfc signal to
interface #n is de-asserted. */
#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
/* [RW 10] The number of free blocks below which the Low_llfc signal to
interface #n is asserted. */
#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
* register is applicable only when per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
* 1 before signaling XON. The register is applicable only when
* per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
* register is applicable only when per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
/* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
* before signaling XON. The register is applicable only when
* per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
/* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
* is applicable only when per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
* 1 before signaling XON. The register is applicable only when
* per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
/* [RW 11] The number of blocks guarantied for class 1 in MAC 1. The
* register is applicable only when per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
/* [RW 11] The hysteresis on the guarantied buffer space for class 1 in MAC
* 1 before signaling XON. The register is applicable only when
* per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
/* [RW 11] The number of blocks guarantied for the MAC port. The register is
* applicable only when per_class_guaranty_mode is reset. */
#define BRB1_REG_MAC_GUARANTIED_0 0x601e8
#define BRB1_REG_MAC_GUARANTIED_1 0x60240
/* [R 24] The number of full blocks. */
#define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
/* [ST 32] The number of cycles that the write_full signal towards MAC #0
was asserted. */
#define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
#define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
#define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
/* [ST 32] The number of cycles that the pause signal towards MAC #0 was
asserted. */
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
#define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
/* [RW 10] The number of free blocks below which the pause signal to class 0
* is asserted */
#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
#define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
/* [RW 11] The number of free blocks above which the pause signal to class 0
* is de-asserted */
#define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
#define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
/* [RW 11] The number of free blocks below which the pause signal to class 1
* is asserted */
#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
#define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
/* [RW 11] The number of free blocks above which the pause signal to class 1
* is de-asserted */
#define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
#define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
/* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
#define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
/* [RW 10] Write client 0: Assert pause threshold. */
#define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
/* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
* guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
* mode). 1=per-class guaranty mode (new mode). */
#define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268
/* [R 24] The number of full blocks occpied by port. */
#define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
/* [RW 1] Reset the design by software. */
#define BRB1_REG_SOFT_RESET 0x600dc
/* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
#define CCM_REG_CAM_OCCUP 0xd0188
/* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_CFC_IFEN 0xd003c
/* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
disregarded; valid is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_CQM_IFEN 0xd000c
/* [RW 1] If set the Q index; received from the QM is inserted to event ID.
Otherwise 0 is inserted. */
#define CCM_REG_CCM_CQM_USE_Q 0xd00c0
/* [RW 11] Interrupt mask register #0 read/write */
#define CCM_REG_CCM_INT_MASK 0xd01e4
/* [R 11] Interrupt register #0 read */
#define CCM_REG_CCM_INT_STS 0xd01d8
/* [RW 27] Parity mask register #0 read/write */
#define CCM_REG_CCM_PRTY_MASK 0xd01f4
/* [R 27] Parity register #0 read */
#define CCM_REG_CCM_PRTY_STS 0xd01e8
/* [RC 27] Parity register #0 read clear */
#define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
/* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
Is used to determine the number of the AG context REG-pairs written back;
when the input message Reg1WbFlg isn't set. */
#define CCM_REG_CCM_REG0_SZ 0xd00c4
/* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
disregarded; valid is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_STORM0_IFEN 0xd0004
/* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
disregarded; valid is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CCM_STORM1_IFEN 0xd0008
/* [RW 1] CDU AG read Interface enable. If 0 - the request input is
disregarded; valid output is deasserted; all other signals are treated as
usual; if 1 - normal activity. */
#define CCM_REG_CDU_AG_RD_IFEN 0xd0030
/* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
are disregarded; all other signals are treated as usual; if 1 - normal
activity. */
#define CCM_REG_CDU_AG_WR_IFEN 0xd002c
/* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
disregarded; valid output is deasserted; all other signals are treated as
usual; if 1 - normal activity. */
#define CCM_REG_CDU_SM_RD_IFEN 0xd0038
/* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
input is disregarded; all other signals are treated as usual; if 1 -
normal activity. */
#define CCM_REG_CDU_SM_WR_IFEN 0xd0034
/* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
the initial credit value; read returns the current value of the credit
counter. Must be initialized to 1 at start-up. */
#define CCM_REG_CFC_INIT_CRD 0xd0204
/* [RW 2] Auxiliary counter flag Q number 1. */
#define CCM_REG_CNT_AUX1_Q 0xd00c8
/* [RW 2] Auxiliary counter flag Q number 2. */
#define CCM_REG_CNT_AUX2_Q 0xd00cc
/* [RW 28] The CM header value for QM request (primary). */
#define CCM_REG_CQM_CCM_HDR_P 0xd008c
/* [RW 28] The CM header value for QM request (secondary). */
#define CCM_REG_CQM_CCM_HDR_S 0xd0090
/* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CQM_CCM_IFEN 0xd0014
/* [RW 6] QM output initial credit. Max credit available - 32. Write writes
the initial credit value; read returns the current value of the credit
counter. Must be initialized to 32 at start-up. */
#define CCM_REG_CQM_INIT_CRD 0xd020c
/* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_CQM_P_WEIGHT 0xd00b8
/* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
stands for weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_CQM_S_WEIGHT 0xd00bc
/* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_CSDM_IFEN 0xd0018
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the SDM interface is detected. */
#define CCM_REG_CSDM_LENGTH_MIS 0xd0170
/* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_CSDM_WEIGHT 0xd00b4
/* [RW 28] The CM header for QM formatting in case of an error in the QM
inputs. */
#define CCM_REG_ERR_CCM_HDR 0xd0094
/* [RW 8] The Event ID in case the input message ErrorFlg is set. */
#define CCM_REG_ERR_EVNT_ID 0xd0098
/* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 64 at start-up. */
#define CCM_REG_FIC0_INIT_CRD 0xd0210
/* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
writes the initial credit value; read returns the current value of the
credit counter. Must be initialized to 64 at start-up. */
#define CCM_REG_FIC1_INIT_CRD 0xd0214
/* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
- strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
~ccm_registers_gr_ld0_pr.gr_ld0_pr and
~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
#define CCM_REG_GR_ARB_TYPE 0xd015c
/* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
highest priority is 3. It is supposed; that the Store channel priority is
the compliment to 4 of the rest priorities - Aggregation channel; Load
(FIC0) channel and Load (FIC1). */
#define CCM_REG_GR_LD0_PR 0xd0164
/* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
highest priority is 3. It is supposed; that the Store channel priority is
the compliment to 4 of the rest priorities - Aggregation channel; Load
(FIC0) channel and Load (FIC1). */
#define CCM_REG_GR_LD1_PR 0xd0168
/* [RW 2] General flags index. */
#define CCM_REG_INV_DONE_Q 0xd0108
/* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
context and sent to STORM; for a specific connection type. The double
REG-pairs are used in order to align to STORM context row size of 128
bits. The offset of these data in the STORM context is always 0. Index
_(0..15) stands for the connection type (one of 16). */
#define CCM_REG_N_SM_CTX_LD_0 0xd004c
#define CCM_REG_N_SM_CTX_LD_1 0xd0050
#define CCM_REG_N_SM_CTX_LD_2 0xd0054
#define CCM_REG_N_SM_CTX_LD_3 0xd0058
#define CCM_REG_N_SM_CTX_LD_4 0xd005c
/* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
acknowledge output is deasserted; all other signals are treated as usual;
if 1 - normal activity. */
#define CCM_REG_PBF_IFEN 0xd0028
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the pbf interface is detected. */
#define CCM_REG_PBF_LENGTH_MIS 0xd0180
/* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_PBF_WEIGHT 0xd00ac
#define CCM_REG_PHYS_QNUM1_0 0xd0134
#define CCM_REG_PHYS_QNUM1_1 0xd0138
#define CCM_REG_PHYS_QNUM2_0 0xd013c
#define CCM_REG_PHYS_QNUM2_1 0xd0140
#define CCM_REG_PHYS_QNUM3_0 0xd0144
#define CCM_REG_PHYS_QNUM3_1 0xd0148
#define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
#define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
#define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
#define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
#define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
#define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
#define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
#define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
/* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_STORM_CCM_IFEN 0xd0010
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the STORM interface is detected. */
#define CCM_REG_STORM_LENGTH_MIS 0xd016c
/* [RW 3] The weight of the STORM input in the WRR (Weighted Round robin)
mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
weight 1(least prioritised); 2 stands for weight 2 (more prioritised);
tc. */
#define CCM_REG_STORM_WEIGHT 0xd009c
/* [RW 1] Input tsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_TSEM_IFEN 0xd001c
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the tsem interface is detected. */
#define CCM_REG_TSEM_LENGTH_MIS 0xd0174
/* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_TSEM_WEIGHT 0xd00a0
/* [RW 1] Input usem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_USEM_IFEN 0xd0024
/* [RC 1] Set when message length mismatch (relative to last indication) at
the usem interface is detected. */
#define CCM_REG_USEM_LENGTH_MIS 0xd017c
/* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_USEM_WEIGHT 0xd00a8
/* [RW 1] Input xsem Interface enable. If 0 - the valid input is
disregarded; acknowledge output is deasserted; all other signals are
treated as usual; if 1 - normal activity. */
#define CCM_REG_XSEM_IFEN 0xd0020
/* [RC 1] Set when the message length mismatch (relative to last indication)
at the xsem interface is detected. */
#define CCM_REG_XSEM_LENGTH_MIS 0xd0178
/* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
weight 8 (the most prioritised); 1 stands for weight 1(least
prioritised); 2 stands for weight 2; tc. */
#define CCM_REG_XSEM_WEIGHT 0xd00a4
/* [RW 19] Indirect access to the descriptor table of the XX protection
mechanism. The fields are: [5:0] - message length; [12:6] - message
pointer; 18:13] - next pointer. */
#define CCM_REG_XX_DESCR_TABLE 0xd0300
#define CCM_REG_XX_DESCR_TABLE_SIZE 24
/* [R 7] Used to read the value of XX protection Free counter. */
#define CCM_REG_XX_FREE 0xd0184
/* [RW 6] Initial value for the credit counter; responsible for fulfilling
of the Input Stage XX protection buffer by the XX protection pending
messages. Max credit available - 127. Write writes the initial credit
value; read returns the current value of the credit counter. Must be
initialized to maximum XX protected message size - 2 at start-up. */
#define CCM_REG_XX_INIT_CRD 0xd0220
/* [RW 7] The maximum number of pending messages; which may be stored in XX
protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
At write comprises the start value of the ~ccm_registers_xx_free.xx_free
counter. */
#define CCM_REG_XX_MSG_NUM 0xd0224
/* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
#define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
/* [RW 18] Indirect access to the XX table of the XX protection mechanism.
The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
header pointer. */
#define CCM_REG_XX_TABLE 0xd0280
#define CDU_REG_CDU_CHK_MASK0 0x101000
#define CDU_REG_CDU_CHK_MASK1 0x101004
#define CDU_REG_CDU_CONTROL0 0x101008
#define CDU_REG_CDU_DEBUG 0x101010
#define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
/* [RW 7] Interrupt mask register #0 read/write */
#define CDU_REG_CDU_INT_MASK 0x10103c
/* [R 7] Interrupt register #0 read */
#define CDU_REG_CDU_INT_STS 0x101030
/* [RW 5] Parity mask register #0 read/write */
#define CDU_REG_CDU_PRTY_MASK 0x10104c
/* [R 5] Parity register #0 read */
#define CDU_REG_CDU_PRTY_STS 0x101040
/* [RC 5] Parity register #0 read clear */
#define CDU_REG_CDU_PRTY_STS_CLR 0x101044
/* [RC 32] logging of error data in case of a CDU load error:
{expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
ype_error; ctual_active; ctual_compressed_context}; */
#define CDU_REG_ERROR_DATA 0x101014
/* [WB 216] L1TT ram access. each entry has the following format :
{mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
#define CDU_REG_L1TT 0x101800
/* [WB 24] MATT ram access. each entry has the following
format:{RegionLength[11:0]; egionOffset[11:0]} */
#define CDU_REG_MATT 0x101100
/* [RW 1] when this bit is set the CDU operates in e1hmf mode */
#define CDU_REG_MF_MODE 0x101050
/* [R 1] indication the initializing the activity counter by the hardware
was done. */
#define CFC_REG_AC_INIT_DONE 0x104078
/* [RW 13] activity counter ram access */
#define CFC_REG_ACTIVITY_COUNTER 0x104400
#define CFC_REG_ACTIVITY_COUNTER_SIZE 256
/* [R 1] indication the initializing the cams by the hardware was done. */
#define CFC_REG_CAM_INIT_DONE 0x10407c
/* [RW 2] Interrupt mask register #0 read/write */
#define CFC_REG_CFC_INT_MASK 0x104108
/* [R 2] Interrupt register #0 read */
#define CFC_REG_CFC_INT_STS 0x1040fc
/* [RC 2] Interrupt register #0 read clear */
#define CFC_REG_CFC_INT_STS_CLR 0x104100
/* [RW 4] Parity mask register #0 read/write */
#define CFC_REG_CFC_PRTY_MASK 0x104118
/* [R 4] Parity register #0 read */
#define CFC_REG_CFC_PRTY_STS 0x10410c
/* [RC 4] Parity register #0 read clear */
#define CFC_REG_CFC_PRTY_STS_CLR 0x104110
/* [RW 21] CID cam access (21:1 - Data; alid - 0) */
#define CFC_REG_CID_CAM 0x104800
#define CFC_REG_CONTROL0 0x104028
#define CFC_REG_DEBUG0 0x104050
/* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
vector) whether the cfc should be disabled upon it */
#define CFC_REG_DISABLE_ON_ERROR 0x104044
/* [RC 14] CFC error vector. when the CFC detects an internal error it will
set one of these bits. the bit description can be found in CFC
specifications */
#define CFC_REG_ERROR_VECTOR 0x10403c
/* [WB 93] LCID info ram access */
#define CFC_REG_INFO_RAM 0x105000
#define CFC_REG_INFO_RAM_SIZE 1024
#define CFC_REG_INIT_REG 0x10404c
#define CFC_REG_INTERFACES 0x104058
/* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
field allows changing the priorities of the weighted-round-robin arbiter
which selects which CFC load client should be served next */
#define CFC_REG_LCREQ_WEIGHTS 0x104084
/* [RW 16] Link List ram access; data = {prev_lcid; ext_lcid} */
#define CFC_REG_LINK_LIST 0x104c00
#define CFC_REG_LINK_LIST_SIZE 256
/* [R 1] indication the initializing the link list by the hardware was done. */
#define CFC_REG_LL_INIT_DONE 0x104074
/* [R 9] Number of allocated LCIDs which are at empty state */
#define CFC_REG_NUM_LCIDS_ALLOC 0x104020
/* [R 9] Number of Arriving LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
#define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
/* [R 9] Number of Leaving LCIDs in Link List Block */
#define CFC_REG_NUM_LCIDS_LEAVING 0x104018
#define CFC_REG_WEAK_ENABLE_PF 0x104124
/* [RW 8] The event id for aggregated interrupt 0 */
#define CSDM_REG_AGG_INT_EVENT_0 0xc2038
#define CSDM_REG_AGG_INT_EVENT_10 0xc2060
#define CSDM_REG_AGG_INT_EVENT_11 0xc2064
#define CSDM_REG_AGG_INT_EVENT_12 0xc2068
#define CSDM_REG_AGG_INT_EVENT_13 0xc206c
#define CSDM_REG_AGG_INT_EVENT_14 0xc2070
#define CSDM_REG_AGG_INT_EVENT_15 0xc2074
#define CSDM_REG_AGG_INT_EVENT_16 0xc2078
#define CSDM_REG_AGG_INT_EVENT_2 0xc2040
#define CSDM_REG_AGG_INT_EVENT_3 0xc2044
#define CSDM_REG_AGG_INT_EVENT_4 0xc2048
#define CSDM_REG_AGG_INT_EVENT_5 0xc204c
#define CSDM_REG_AGG_INT_EVENT_6 0xc2050
#define CSDM_REG_AGG_INT_EVENT_7 0xc2054
#define CSDM_REG_AGG_INT_EVENT_8 0xc2058
#define CSDM_REG_AGG_INT_EVENT_9 0xc205c
/* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
or auto-mask-mode (1) */
#define CSDM_REG_AGG_INT_MODE_10 0xc21e0
#define CSDM_REG_AGG_INT_MODE_11 0xc21e4
#define CSDM_REG_AGG_INT_MODE_12 0xc21e8
#define CSDM_REG_AGG_INT_MODE_13 0xc21ec
#define CSDM_REG_AGG_INT_MODE_14 0xc21f0
#define CSDM_REG_AGG_INT_MODE_15 0xc21f4
#define CSDM_REG_AGG_INT_MODE_16 0xc21f8
#define CSDM_REG_AGG_INT_MODE_6 0xc21d0
#define CSDM_REG_AGG_INT_MODE_7 0xc21d4
#define CSDM_REG_AGG_INT_MODE_8 0xc21d8
#define CSDM_REG_AGG_INT_MODE_9 0xc21dc
/* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
#define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
/* [RW 16] The maximum value of the completion counter #0 */
#define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
/* [RW 16] The maximum value of the completion counter #1 */
#define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
/* [RW 16] The maximum value of the completion counter #2 */
#define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
/* [RW 16] The maximum value of the completion counter #3 */
#define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
/* [RW 13] The start address in the internal RAM for the completion
counters. */
#define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
/* [RW 32] Interrupt mask register #0 read/write */
#define CSDM_REG_CSDM_INT_MASK_0 0xc229c
#define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
/* [R 32] Interrupt register #0 read */
#define CSDM_REG_CSDM_INT_STS_0 0xc2290
#define CSDM_REG_CSDM_INT_STS_1 0xc22a0
/* [RW 11] Parity mask register #0 read/write */
#define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
/* [R 11] Parity register #0 read */
#define CSDM_REG_CSDM_PRTY_STS 0xc22b0
/* [RC 11] Parity register #0 read clear */
#define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
#define CSDM_REG_ENABLE_IN1 0xc2238
#define CSDM_REG_ENABLE_IN2 0xc223c
#define CSDM_REG_ENABLE_OUT1 0xc2240
#define CSDM_REG_ENABLE_OUT2 0xc2244
/* [RW 4] The initial number of messages that can be sent to the pxp control
interface without receiving any ACK. */
#define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
/* [ST 32] The number of ACK after placement messages received */
#define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
/* [ST 32] The number of packet end messages received from the parser */
#define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
/* [ST 32] The number of requests received from the pxp async if */
#define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
/* [ST 32] The number of commands received in queue 0 */
#define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
/* [ST 32] The number of commands received in queue 10 */
#define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
/* [ST 32] The number of commands received in queue 11 */
#define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
/* [ST 32] The number of commands received in queue 1 */
#define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
/* [ST 32] The number of commands received in queue 3 */
#define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
/* [ST 32] The number of commands received in queue 4 */
#define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
/* [ST 32] The number of commands received in queue 5 */
#define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
/* [ST 32] The number of commands received in queue 6 */
#define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
/* [ST 32] The number of commands received in queue 7 */
#define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
/* [ST 32] The number of commands received in queue 8 */
#define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
/* [ST 32] The number of commands received in queue 9 */
#define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
/* [RW 13] The start address in the internal RAM for queue counters */
#define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
/* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
#define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
/* [R 1] parser fifo empty in sdm_sync block */
#define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
/* [R 1] parser serial fifo empty in sdm_sync block */
#define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
/* [RW 32] Tick for timer counter. Applicable only when
~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
#define CSDM_REG_TIMER_TICK 0xc2000
/* [RW 5] The number of time_slots in the arbitration cycle */
#define CSEM_REG_ARB_CYCLE_SIZE 0x200034
/* [RW 3] The source that is associated with arbitration element 0. Source
decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
sleeping thread with priority 1; 4- sleeping thread with priority 2 */
#define CSEM_REG_ARB_ELEMENT0 0x200020
/* [RW 3] The source that is associated with arbitration element 1. Source
decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
sleeping thread with priority 1; 4- sleeping thread with priority 2.
Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
#define CSEM_REG_ARB_ELEMENT1 0x200024
/* [RW 3] The source that is associated with arbitration element 2. Source
decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
sleeping thread with priority 1; 4- sleeping thread with priority 2.
Could not be equal to register ~csem_registers_arb_element0.arb_element0
and ~csem_registers_arb_element1.arb_element1 */
#define CSEM_REG_ARB_ELEMENT2 0x200028
/* [RW 3] The source that is associated with arbitration element 3. Source
decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
not be equal to register ~csem_registers_arb_element0.arb_element0 and
~csem_registers_arb_element1.arb_element1 and
~csem_registers_arb_element2.arb_element2 */
#define CSEM_REG_ARB_ELEMENT3 0x20002c
/* [RW 3] The source that is associated with arbitration element 4. Source
decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
sleeping thread with priority 1; 4- sleeping thread with priority 2.
Could not be equal to register ~csem_registers_arb_element0.arb_element0
and ~csem_registers_arb_element1.arb_element1 and
~csem_registers_arb_element2.arb_element2 and
~csem_registers_arb_element3.arb_element3 */
#define CSEM_REG_ARB_ELEMENT4 0x200030
/* [RW 32] Interrupt mask register #0 read/write */
#define CSEM_REG_CSEM_INT_MASK_0 0x200110
#define CSEM_REG_CSEM_INT_MASK_1 0x200120
/* [R 32] Interrupt register #0 read */
#define CSEM_REG_CSEM_INT_STS_0 0x200104
#define CSEM_REG_CSEM_INT_STS_1 0x200114
/* [RW 32] Parity mask register #0 read/write */
#define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
#define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
/* [R 32] Parity register #0 read */
#define CSEM_REG_CSEM_PRTY_STS_0 0x200124
#define CSEM_REG_CSEM_PRTY_STS_1 0x200134
/* [RC 32] Parity register #0 read clear */
#define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
#define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
#define CSEM_REG_ENABLE_IN 0x2000a4
#define CSEM_REG_ENABLE_OUT 0x2000a8
/* [RW 32] This address space contains all registers and memories that are
placed in SEM_FAST block. The SEM_FAST registers are described in
appendix B. In order to access the sem_fast registers the base address
~fast_memory.fast_memory should be added to eachsem_fast register offset. */
#define CSEM_REG_FAST_MEMORY 0x220000
/* [RW 1] Disables input messages from FIC0 May be updated during run_time
by the microcode */
#define CSEM_REG_FIC0_DISABLE 0x200224
/* [RW 1] Disables input messages from FIC1 May be updated during run_time
by the microcode */
#define CSEM_REG_FIC1_DISABLE 0x200234
/* [RW 15] Interrupt table Read and write access to it is not possible in
the middle of the work */
#define CSEM_REG_INT_TABLE 0x200400
/* [ST 24] Statistics register. The number of messages that entered through
FIC0 */
#define CSEM_REG_MSG_NUM_FIC0 0x200000
/* [ST 24] Statistics register. The number of messages that entered through
FIC1 */
#define CSEM_REG_MSG_NUM_FIC1 0x200004
/* [ST 24] Statistics register. The number of messages that were sent to
FOC0 */
#define CSEM_REG_MSG_NUM_FOC0 0x200008
/* [ST 24] Statistics register. The number of messages that were sent to
FOC1 */
#define CSEM_REG_MSG_NUM_FOC1 0x20000c
/* [ST 24] Statistics register. The number of messages that were sent to
FOC2 */
#define CSEM_REG_MSG_NUM_FOC2 0x200010
/* [ST 24] Statistics register. The number of messages that were sent to
FOC3 */
#define CSEM_REG_MSG_NUM_FOC3 0x200014
/* [RW 1] Disables input messages from the passive buffer May be updated
during run_time by the microcode */
#define CSEM_REG_PAS_DISABLE 0x20024c
/* [WB 128] Debug only. Passive buffer memory */
#define CSEM_REG_PASSIVE_BUFFER 0x202000
/* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
#define CSEM_REG_PRAM 0x240000
/* [R 16] Valid sleeping threads indication have bit per thread */
#define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
/* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
#define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
/* [RW 16] List of free threads . There is a bit per thread. */
#define CSEM_REG_THREADS_LIST 0x2002e4
/* [RW 3] The arbitration scheme of time_slot 0 */
#define CSEM_REG_TS_0_AS 0x200038
/* [RW 3] The arbitration scheme of time_slot 10 */
#define CSEM_REG_TS_10_AS 0x200060
/* [RW 3] The arbitration scheme of time_slot 11 */
#define CSEM_REG_TS_11_AS 0x200064
/* [RW 3] The arbitration scheme of time_slot 12 */
#define CSEM_REG_TS_12_AS 0x200068
/* [RW 3] The arbitration scheme of time_slot 13 */
#define CSEM_REG_TS_13_AS 0x20006c
/* [RW 3] The arbitration scheme of time_slot 14 */
#define CSEM_REG_TS_14_AS 0x200070
/* [RW 3] The arbitration scheme of time_slot 15 */
#define CSEM_REG_TS_15_AS 0x200074
/* [RW 3] The arbitration scheme of time_slot 16 */
#define CSEM_REG_TS_16_AS 0x200078
/* [RW 3] The arbitration scheme of time_slot 17 */
#define CSEM_REG_TS_17_AS 0x20007c
/* [RW 3] The arbitration scheme of time_slot 18 */
#define CSEM_REG_TS_18_AS 0x200080
/* [RW 3] The arbitration scheme of time_slot 1 */
#define CSEM_REG_TS_1_AS 0x20003c
/* [RW 3] The arbitration scheme of time_slot 2 */
#define CSEM_REG_TS_2_AS 0x200040
/* [RW 3] The arbitration scheme of time_slot 3 */
#define CSEM_REG_TS_3_AS 0x200044
/* [RW 3] The arbitration scheme of time_slot 4 */
#define CSEM_REG_TS_4_AS 0x200048
/* [RW 3] The arbitration scheme of time_slot 5 */
#define CSEM_REG_TS_5_AS 0x20004c
/* [RW 3] The arbitration scheme of time_slot 6 */
#define CSEM_REG_TS_6_AS 0x200050
/* [RW 3] The arbitration scheme of time_slot 7 */
#define CSEM_REG_TS_7_AS 0x200054
/* [RW 3] The arbitration scheme of time_slot 8 */
#define CSEM_REG_TS_8_AS 0x200058
/* [RW 3] The arbitration scheme of time_slot 9 */
#define CSEM_REG_TS_9_AS 0x20005c
/* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
* VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
#define CSEM_REG_VFPF_ERR_NUM 0x200380
/* [RW 1] Parity mask register #0 read/write */
#define DBG_REG_DBG_PRTY_MASK 0xc0a8
/* [R 1] Parity register #0 read */
#define DBG_REG_DBG_PRTY_STS 0xc09c
/* [RC 1] Parity register #0 read clear */
#define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
/* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The
* function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
* 4.Completion function=0; 5.Error handling=0 */
#define DMAE_REG_BACKWARD_COMP_EN 0x10207c
/* [RW 32] Commands memory. The address to command X; row Y is to calculated
as 14*X+Y. */
#define DMAE_REG_CMD_MEM 0x102400
#define DMAE_REG_CMD_MEM_SIZE 224
/* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
initial value is all ones. */
#define DMAE_REG_CRC16C_INIT 0x10201c
/* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
CRC-16 T10 initial value is all ones. */
#define DMAE_REG_CRC16T10_INIT 0x102020
/* [RW 2] Interrupt mask register #0 read/write */
#define DMAE_REG_DMAE_INT_MASK 0x102054
/* [RW 4] Parity mask register #0 read/write */
#define DMAE_REG_DMAE_PRTY_MASK 0x102064
/* [R 4] Parity register #0 read */
#define DMAE_REG_DMAE_PRTY_STS 0x102058
/* [RC 4] Parity register #0 read clear */
#define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
/* [RW 1] Command 0 go. */
#define DMAE_REG_GO_C0 0x102080
/* [RW 1] Command 1 go. */
#define DMAE_REG_GO_C1 0x102084
/* [RW 1] Command 10 go. */
#define DMAE_REG_GO_C10 0x102088
/* [RW 1] Command 11 go. */
#define DMAE_REG_GO_C11 0x10208c
/* [RW 1] Command 12 go. */
#define DMAE_REG_GO_C12 0x102090
/* [RW 1] Command 13 go. */
#define DMAE_REG_GO_C13 0x102094
/* [RW 1] Command 14 go. */
#define DMAE_REG_GO_C14 0x102098
/* [RW 1] Command 15 go. */
#define DMAE_REG_GO_C15 0x10209c
/* [RW 1] Command 2 go. */
#define DMAE_REG_GO_C2 0x1020a0
/* [RW 1] Command 3 go. */
#define DMAE_REG_GO_C3 0x1020a4
/* [RW 1] Command 4 go. */
#define DMAE_REG_GO_C4 0x1020a8
/* [RW 1] Command 5 go. */
#define DMAE_REG_GO_C5 0x1020ac
/* [RW 1] Command 6 go. */
#define DMAE_REG_GO_C6 0x1020b0
/* [RW 1] Command 7 go. */
#define DMAE_REG_GO_C7 0x1020b4
/* [RW 1] Command 8 go. */
#define DMAE_REG_GO_C8 0x1020b8
/* [RW 1] Command 9 go. */
#define DMAE_REG_GO_C9 0x1020bc
/* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
input is disregarded; valid is deasserted; all other signals are treated
as usual; if 1 - normal activity. */
#define DMAE_REG_GRC_IFEN 0x102008
/* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
acknowledge input is disregarded; valid is deasserted; full is asserted;
all other signals are treated as usual; if 1 - normal activity. */
#define DMAE_REG_PCI_IFEN 0x102004
/* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
initial value to the credit counter; related to the address. Read returns
the current value of the counter. */
#define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
/* [RW 8] Aggregation command. */
#define DORQ_REG_AGG_CMD0 0x170060
/* [RW 8] Aggregation command. */
#define DORQ_REG_AGG_CMD1 0x170064
/* [RW 8] Aggregation command. */
#define DORQ_REG_AGG_CMD2 0x170068
/* [RW 8] Aggregation command. */
#define DORQ_REG_AGG_CMD3 0x17006c
/* [RW 28] UCM Header. */
#define DORQ_REG_CMHEAD_RX 0x170050
/* [RW 32] Doorbell address for RBC doorbells (function 0). */
#define DORQ_REG_DB_ADDR0 0x17008c
/* [RW 5] Interrupt mask register #0 read/write */
#define DORQ_REG_DORQ_INT_MASK 0x170180
/* [R 5] Interrupt register #0 read */
#define DORQ_REG_DORQ_INT_STS 0x170174
/* [RC 5] Interrupt register #0 read clear */
#define DORQ_REG_DORQ_INT_STS_CLR 0x170178
/* [RW 2] Parity mask register #0 read/write */
#define DORQ_REG_DORQ_PRTY_MASK 0x170190
/* [R 2] Parity register #0 read */
#define DORQ_REG_DORQ_PRTY_STS 0x170184
/* [RC 2] Parity register #0 read clear */
#define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
/* [RW 8] The address to write the DPM CID to STORM. */
#define DORQ_REG_DPM_CID_ADDR 0x170044
/* [RW 5] The DPM mode CID extraction offset. */
#define DORQ_REG_DPM_CID_OFST 0x170030
/* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
#define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
/* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
#define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
/* [R 13] Current value of the DQ FIFO fill level according to following
pointer. The range is 0 - 256 FIFO rows; where each row stands for the
doorbell. */
#define DORQ_REG_DQ_FILL_LVLF 0x1700a4
/* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
equal to full threshold; reset on full clear. */
#define DORQ_REG_DQ_FULL_ST 0x1700c0
/* [RW 28] The value sent to CM header in the case of CFC load error. */
#define DORQ_REG_ERR_CMHEAD 0x170058
#define DORQ_REG_IF_EN 0x170004
#define DORQ_REG_MAX_RVFID_SIZE 0x1701ec
#define DORQ_REG_MODE_ACT 0x170008
/* [RW 5] The normal mode CID extraction offset. */
#define DORQ_REG_NORM_CID_OFST 0x17002c
/* [RW 28] TCM Header when only TCP context is loaded. */
#define DORQ_REG_NORM_CMHEAD_TX 0x17004c
/* [RW 3] The number of simultaneous outstanding requests to Context Fetch
Interface. */
#define DORQ_REG_OUTST_REQ 0x17003c
#define DORQ_REG_PF_USAGE_CNT 0x1701d0
#define DORQ_REG_REGN 0x170038
/* [R 4] Current value of response A counter credit. Initial credit is
configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
register. */
#define DORQ_REG_RSPA_CRD_CNT 0x1700ac
/* [R 4] Current value of response B counter credit. Initial credit is
configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
register. */
#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
/* [RW 4] The initial credit at the Doorbell Response Interface. The write
writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
read reads this written value. */
#define DORQ_REG_RSP_INIT_CRD 0x170048
#define DORQ_REG_RSPB_CRD_CNT 0x1700b0
#define DORQ_REG_VF_NORM_CID_BASE 0x1701a0
#define DORQ_REG_VF_NORM_CID_OFST 0x1701f4
#define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4
#define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4
#define DORQ_REG_VF_NORM_VF_BASE 0x1701a8
/* [RW 10] VF type validation mask value */
#define DORQ_REG_VF_TYPE_MASK_0 0x170218
/* [RW 17] VF type validation Min MCID value */
#define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8
/* [RW 17] VF type validation Max MCID value */
#define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298
/* [RW 10] VF type validation comp value */
#define DORQ_REG_VF_TYPE_VALUE_0 0x170258
#define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340
/* [RW 4] Initial activity counter value on the load request; when the
shortcut is done. */
#define DORQ_REG_SHRT_ACT_CNT 0x170070
/* [RW 28] TCM Header when both ULP and TCP context is loaded. */
#define DORQ_REG_SHRT_CMHEAD 0x170054
#define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
#define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
#define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
#define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
#define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
#define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
#define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
#define DORQ_REG_VF_USAGE_CNT 0x170320
#define HC_REG_AGG_INT_0 0x108050
#define HC_REG_AGG_INT_1 0x108054
#define HC_REG_ATTN_BIT 0x108120
#define HC_REG_ATTN_IDX 0x108100
#define HC_REG_ATTN_MSG0_ADDR_L 0x108018
#define HC_REG_ATTN_MSG1_ADDR_L 0x108020
#define HC_REG_ATTN_NUM_P0 0x108038
#define HC_REG_ATTN_NUM_P1 0x10803c
#define HC_REG_COMMAND_REG 0x108180
#define HC_REG_CONFIG_0 0x108000
#define HC_REG_CONFIG_1 0x108004
#define HC_REG_FUNC_NUM_P0 0x1080ac
#define HC_REG_FUNC_NUM_P1 0x1080b0
/* [RW 3] Parity mask register #0 read/write */
#define HC_REG_HC_PRTY_MASK 0x1080a0
/* [R 3] Parity register #0 read */
#define HC_REG_HC_PRTY_STS 0x108094
/* [RC 3] Parity register #0 read clear */
#define HC_REG_HC_PRTY_STS_CLR 0x108098
#define HC_REG_INT_MASK 0x108108
#define HC_REG_LEADING_EDGE_0 0x108040
#define HC_REG_LEADING_EDGE_1 0x108048
#define HC_REG_MAIN_MEMORY 0x108800
#define HC_REG_MAIN_MEMORY_SIZE 152
#define HC_REG_P0_PROD_CONS 0x108200
#define HC_REG_P1_PROD_CONS 0x108400
#define HC_REG_PBA_COMMAND 0x108140
#define HC_REG_PCI_CONFIG_0 0x108010
#define HC_REG_PCI_CONFIG_1 0x108014
#define HC_REG_STATISTIC_COUNTERS 0x109000
#define HC_REG_TRAILING_EDGE_0 0x108044
#define HC_REG_TRAILING_EDGE_1 0x10804c
#define HC_REG_UC_RAM_ADDR_0 0x108028
#define HC_REG_UC_RAM_ADDR_1 0x108030
#define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
#define HC_REG_VQID_0 0x108008
#define HC_REG_VQID_1 0x10800c
#define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
#define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
#define IGU_REG_ATTENTION_ACK_BITS 0x130108
/* [R 4] Debug: attn_fsm */
#define IGU_REG_ATTN_FSM 0x130054
#define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
#define IGU_REG_ATTN_MSG_ADDR_L 0x130120
/* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
* 1-pending). [2:0] = PFID. Pending means attention message was sent; but
* write done didn't receive. */
#define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
#define IGU_REG_BLOCK_CONFIGURATION 0x130000
#define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
#define IGU_REG_COMMAND_REG_CTRL 0x13012c
/* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
* is clear. The bits in this registers are set and clear via the producer
* command. Data valid only in addresses 0-4. all the rest are zero. */
#define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
/* [R 5] Debug: ctrl_fsm */
#define IGU_REG_CTRL_FSM 0x130064
/* [R 1] data available for error memory. If this bit is clear do not red
* from error_handling_memory. */
#define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
/* [RW 11] Parity mask register #0 read/write */
#define IGU_REG_IGU_PRTY_MASK 0x1300a8
/* [R 11] Parity register #0 read */
#define IGU_REG_IGU_PRTY_STS 0x13009c
/* [RC 11] Parity register #0 read clear */
#define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
/* [R 4] Debug: int_handle_fsm */
#define IGU_REG_INT_HANDLE_FSM 0x130050
#define IGU_REG_LEADING_EDGE_LATCH 0x130134
/* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
* [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
* number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
#define IGU_REG_MAPPING_MEMORY 0x131000
#define IGU_REG_MAPPING_MEMORY_SIZE 136
#define IGU_REG_PBA_STATUS_LSB 0x130138
#define IGU_REG_PBA_STATUS_MSB 0x13013c
#define IGU_REG_PCI_PF_MSI_EN 0x130140
#define IGU_REG_PCI_PF_MSIX_EN 0x130144
#define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
/* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
* pending; 1 = pending. Pendings means interrupt was asserted; and write
* done was not received. Data valid only in addresses 0-4. all the rest are
* zero. */
#define IGU_REG_PENDING_BITS_STATUS 0x130300
#define IGU_REG_PF_CONFIGURATION 0x130154
/* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
* memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
* prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
* 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
* - In backward compatible mode; for non default SB; each even line in the
* memory holds the U producer and each odd line hold the C producer. The
* first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
* last 20 producers are for the DSB for each PF. each PF has five segments
* (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
* 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
#define IGU_REG_PROD_CONS_MEMORY 0x132000
/* [R 3] Debug: pxp_arb_fsm */
#define IGU_REG_PXP_ARB_FSM 0x130068
/* [RW 6] Write one for each bit will reset the appropriate memory. When the
* memory reset finished the appropriate bit will be clear. Bit 0 - mapping
* memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
* - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
#define IGU_REG_RESET_MEMORIES 0x130158
/* [R 4] Debug: sb_ctrl_fsm */
#define IGU_REG_SB_CTRL_FSM 0x13004c
#define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
#define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
#define IGU_REG_SB_MASK_LSB 0x130164
#define IGU_REG_SB_MASK_MSB 0x130168
/* [RW 16] Number of command that were dropped without causing an interrupt
* due to: read access for WO BAR address; or write access for RO BAR
* address or any access for reserved address or PCI function error is set
* and address is not MSIX; PBA or cleanup */
#define IGU_REG_SILENT_DROP 0x13016c
/* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
* number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
* PF; 68-71 number of ATTN messages per PF */
#define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
/* [RW 32] Number of cycles the timer mask masking the IGU interrupt when a
* timer mask command arrives. Value must be bigger than 100. */
#define IGU_REG_TIMER_MASKING_VALUE 0x13003c
#define IGU_REG_TRAILING_EDGE_LATCH 0x130104
#define IGU_REG_VF_CONFIGURATION 0x130170
/* [WB_R 32] Each bit represent write done pending bits status for that SB
* (MSI/MSIX message was sent and write done was not received yet). 0 =
* clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
#define IGU_REG_WRITE_DONE_PENDING 0x130480
#define MCP_A_REG_MCPR_SCRATCH 0x3a0000
#define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
#define MCP_REG_MCPR_GP_INPUTS 0x800c0
#define MCP_REG_MCPR_GP_OENABLE 0x800c8
#define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
#define MCP_REG_MCPR_IMC_COMMAND 0x85900
#define MCP_REG_MCPR_IMC_DATAREG0 0x85920
#define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
#define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
#define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
#define MCP_REG_MCPR_NVM_ADDR 0x8640c
#define MCP_REG_MCPR_NVM_CFG4 0x8642c
#define MCP_REG_MCPR_NVM_COMMAND 0x86400
#define MCP_REG_MCPR_NVM_READ 0x86410
#define MCP_REG_MCPR_NVM_SW_ARB 0x86420
#define MCP_REG_MCPR_NVM_WRITE 0x86408
#define MCP_REG_MCPR_SCRATCH 0xa0000
#define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
#define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
/* [R 32] read first 32 bit after inversion of function 0. mapped as
follows: [0] NIG attention for function0; [1] NIG attention for
function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
[6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
[13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
Parity error; [31] PBF Hw interrupt; */
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
#define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
/* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
[7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
interrupt; */
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
/* [R 32] read second 32 bit after inversion of function 0. mapped as
follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
[17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
interrupt; */
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
#define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
/* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
[3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
[6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
[20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
[23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
[26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
[29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
#define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
/* [R 32] read third 32 bit after inversion of function 0. mapped as
follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
attn1; */
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
#define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
/* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
timers attn_4 func1; [30] General attn0; [31] General attn1; */
#define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
/* [R 32] read fourth 32 bit after inversion of function 0. mapped as
follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
[7] General attn9; [8] General attn10; [9] General attn11; [10] General
attn12; [11] General attn13; [12] General attn14; [13] General attn15;
[14] General attn16; [15] General attn17; [16] General attn18; [17]
General attn19; [18] General attn20; [19] General attn21; [20] Main power
interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
Latched timeout attention; [27] GRC Latched reserved access attention;
[28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
#define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
/* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
[4] General attn6; [5] General attn7; [6] General attn8; [7] General
attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
General attn13; [12] General attn14; [13] General attn15; [14] General
attn16; [15] General attn17; [16] General attn18; [17] General attn19;
[18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
attention; [27] GRC Latched reserved access attention; [28] MCP Latched
rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
ump_tx_parity; [31] MCP Latched scpad_parity; */
#define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
/* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
* follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
* attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
* CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
#define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
/* [W 14] write to this register results with the clear of the latched
signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
GRC Latched reserved access attention; one in d7 clears Latched
rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both
ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears
pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read
from this register return zero */
#define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
/* [RW 32] first 32b for enabling the output for function 0 output0. mapped
as follows: [0] NIG attention for function0; [1] NIG attention for
function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
[20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
#define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
/* [RW 32] first 32b for enabling the output for function 1 output0. mapped
as follows: [0] NIG attention for function0; [1] NIG attention for
function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
[20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
#define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
/* [RW 32] first 32b for enabling the output for close the gate nig. mapped
as follows: [0] NIG attention for function0; [1] NIG attention for
function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
[20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
#define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
#define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
/* [RW 32] first 32b for enabling the output for close the gate pxp. mapped
as follows: [0] NIG attention for function0; [1] NIG attention for
function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
[20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
#define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
#define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
/* [RW 32] second 32b for enabling the output for function 0 output0. mapped
as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
[17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
interrupt; */
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
#define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
/* [RW 32] second 32b for enabling the output for function 1 output0. mapped
as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
[17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
interrupt; */
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
#define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
/* [RW 32] second 32b for enabling the output for close the gate nig. mapped
as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
[17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
interrupt; */
#define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
#define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
/* [RW 32] second 32b for enabling the output for close the gate pxp. mapped
as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
[17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
interrupt; */
#define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
#define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
/* [RW 32] third 32b for enabling the output for function 0 output0. mapped
as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
[5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
attn1; */
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
#define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
/* [RW 32] third 32b for enabling the output for function 1 output0. mapped
as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
[5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
attn1; */
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
#define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
/* [RW 32] third 32b for enabling the output for close the gate nig. mapped
as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
[5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
attn1; */
#define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
#define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
/* [RW 32] third 32b for enabling the output for close the gate pxp. mapped
as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
[5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
attn1; */
#define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
#define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
/* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
[7] General attn9; [8] General attn10; [9] General attn11; [10] General
attn12; [11] General attn13; [12] General attn14; [13] General attn15;
[14] General attn16; [15] General attn17; [16] General attn18; [17]
General attn19; [18] General attn20; [19] General attn21; [20] Main power
interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
Latched timeout attention; [27] GRC Latched reserved access attention;
[28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
#define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
/* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
[7] General attn9; [8] General attn10; [9] General attn11; [10] General
attn12; [11] General attn13; [12] General attn14; [13] General attn15;
[14] General attn16; [15] General attn17; [16] General attn18; [17]
General attn19; [18] General attn20; [19] General attn21; [20] Main power
interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
Latched timeout attention; [27] GRC Latched reserved access attention;
[28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
#define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
/* [RW 32] fourth 32b for enabling the output for close the gate nig.mapped
as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
[7] General attn9; [8] General attn10; [9] General attn11; [10] General
attn12; [11] General attn13; [12] General attn14; [13] General attn15;
[14] General attn16; [15] General attn17; [16] General attn18; [17]
General attn19; [18] General attn20; [19] General attn21; [20] Main power
interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
Latched timeout attention; [27] GRC Latched reserved access attention;
[28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
#define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
#define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
/* [RW 32] fourth 32b for enabling the output for close the gate pxp.mapped
as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
[7] General attn9; [8] General attn10; [9] General attn11; [10] General
attn12; [11] General attn13; [12] General attn14; [13] General attn15;
[14] General attn16; [15] General attn17; [16] General attn18; [17]
General attn19; [18] General attn20; [19] General attn21; [20] Main power
interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
Latched timeout attention; [27] GRC Latched reserved access attention;
[28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
#define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
#define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
/* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
* as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
* attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
* mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
* parity; [31-10] Reserved; */
#define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
/* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped
* as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
* attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6]
* mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1
* parity; [31-10] Reserved; */
#define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
/* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
128 bit vector */
#define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
#define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
#define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
#define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
#define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
#define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
#define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
#define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
#define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
#define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
#define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
#define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
#define MISC_REG_AEU_GENERAL_MASK 0xa61c
/* [RW 32] first 32b for inverting the input for function 0; for each bit:
0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
[4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
[8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
#define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
#define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
/* [RW 32] second 32b for inverting the input for function 0; for each bit:
0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
[20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
[23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
[26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
[29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
#define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
#define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
/* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
[9:8] = raserved. Zero = mask; one = unmask */
#define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
#define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
/* [RW 1] If set a system kill occurred */
#define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
/* [RW 32] Represent the status of the input vector to the AEU when a system
kill occurred. The register is reset in por reset. Mapped as follows: [0]
NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
[7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
interrupt; */
#define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
#define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
/* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
Port. */
#define MISC_REG_BOND_ID 0xa400
/* [R 16] These bits indicate the part number for the chip. */
#define MISC_REG_CHIP_NUM 0xa408
/* [R 4] These bits indicate the base revision of the chip. This value
starts at 0x0 for the A0 tape-out and increments by one for each
all-layer tape-out. */
#define MISC_REG_CHIP_REV 0xa40c
/* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
* otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
* 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
#define MISC_REG_CHIP_TYPE 0xac60
#define MISC_REG_CHIP_TYPE_57811_MASK (1<<1)
#define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
/* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled
* by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
* 25MHz. Reset on hard reset. */
#define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
/* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI
* counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. */
#define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
/* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
* the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
* end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
* the FW command that all Queues are empty is disabled. When 0 indicates
* that the FW command that all Queues are empty is enabled. [2] - FW Early
* Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early
* Exit command is disabled. When 0 indicates that the FW Early Exit command
* is enabled. This bit applicable only in the EXIT Events Mask registers.
* [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
* is disabled. When 0 indicates that the PBF Request indication is enabled.
* [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
* Request indication is disabled. When 0 indicates that the Tx Other Than
* PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
* indicates that the RX EEE LPI Status indication is disabled. When 0
* indicates that the RX EEE LPI Status indication is enabled. In the EXIT
* Events Masks registers; this bit masks the falling edge detect of the LPI
* Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
* the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
* indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
* BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
* indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
* IDLE indication is disabled. When 0 indicates that the QM IDLE indication
* is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
* 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
* indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
* Status Mask. When 1 indicates that the L1 Status indication from the PCIE
* CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
* from the PCIE CORE is enabled. In the EXIT Events Masks registers; this
* bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
* - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
* LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
* REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
* indicates that the P0 EEE LPI REQ indication is disabled. When =0
* indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
* LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is
* disabled. When =0 indicates that the P0 EEE LPI REQ indication is
* enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
* LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
* indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
* REQ indication is disabled. When =0 indicates that the L1 indication is
* enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
* that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx
* EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
* Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
* bit is applicable only in the EXIT Events Masks registers. [17] - L1
* Status Edge Detect Mask. When =1 indicates that the L1 Status Falling
* Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
* When =0 indicates that the L1 Status Falling Edge Detect indication from
* the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
* the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. */
#define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
/* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
* that the Vmain SM end state is disabled. When 0 indicates that the Vmain
* SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
* that the FW command that all Queues are empty is disabled. When 0
* indicates that the FW command that all Queues are empty is enabled. [2] -
* FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW
* Early Exit command is disabled. When 0 indicates that the FW Early Exit
* command is enabled. This bit applicable only in the EXIT Events Mask
* registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
* indication is disabled. When 0 indicates that the PBF Request indication
* is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
* Than PBF Request indication is disabled. When 0 indicates that the Tx
* Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
* Mask. When 1 indicates that the RX EEE LPI Status indication is disabled.
* When 0 indicates that the RX LPI Status indication is enabled. In the
* EXIT Events Masks registers; this bit masks the falling edge detect of
* the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
* indicates that the Tx Pause indication is disabled. When 0 indicates that
* the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
* indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
* that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
* indicates that the QM IDLE indication is disabled. When 0 indicates that
* the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9]
* - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
* LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
* LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
* Status indication from the PCIE CORE is disabled. When 0 indicates that
* the RX EEE LPI Status indication from the PCIE CORE is enabled. In the
* EXIT Events Masks registers; this bit masks the falling edge detect of
* the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
* =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When
* =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
* E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication
* is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
* enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
* LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
* indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
* that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
* the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
* indicates that the L1 REQ indication is disabled. When =0 indicates that
* the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
* When =1 indicates that the RX EEE LPI Status Falling Edge Detect
* indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
* the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE
* LPI is on - off). This bit is applicable only in the EXIT Events Masks
* registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
* L1 Status Falling Edge Detect indication from the PCIE CORE is disabled
* (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
* Detect indication from the PCIE CORE is enabled (L1 is on - off). This
* bit is applicable only in the EXIT Events Masks registers.Clock 25MHz.
* Reset on hard reset. */
#define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
* of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
* register. Reset on hard reset. */
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
/* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number
* of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only
* register. Reset on hard reset. */
#define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
/* [RW 32] The following driver registers(1...16) represent 16 drivers and
32 clients. Each client can be controlled by one driver only. One in each
bit represent that this driver control the appropriate client (Ex: bit 5
is set means this driver control client number 5). addr1 = set; addr0 =
clear; read from both addresses will give the same result = status. write
to address 1 will set a request to control all the clients that their
appropriate bit (in the write command) is set. if the client is free (the
appropriate bit in all the other drivers is clear) one will be written to
that driver register; if the client isn't free the bit will remain zero.
if the appropriate bit is set (the driver request to gain control on a
client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
interrupt will be asserted). write to address 0 will set a request to
free all the clients that their appropriate bit (in the write command) is
set. if the appropriate bit is clear (the driver request to free a client
it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
be asserted). */
#define MISC_REG_DRIVER_CONTROL_1 0xa510
#define MISC_REG_DRIVER_CONTROL_7 0xa3c8
/* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
only. */
#define MISC_REG_E1HMF_MODE 0xa5f8
/* [R 1] Status of four port mode path swap input pin. */
#define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
/* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
the path_swap output is equal to 4 port mode path swap input pin; if it
is 1 - the path_swap output is equal to bit[1] of this register; [1] -
Overwrite value. If bit[0] of this register is 1 this is the value that
receives the path_swap output. Reset on Hard reset. */
#define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
/* [R 1] Status of 4 port mode port swap input pin. */
#define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
/* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
the port_swap output is equal to 4 port mode port swap input pin; if it
is 1 - the port_swap output is equal to bit[1] of this register; [1] -
Overwrite value. If bit[0] of this register is 1 this is the value that
receives the port_swap output. Reset on Hard reset. */
#define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
/* [RW 32] Debug only: spare RW register reset by core reset */
#define MISC_REG_GENERIC_CR_0 0xa460
#define MISC_REG_GENERIC_CR_1 0xa464
/* [RW 32] Debug only: spare RW register reset by por reset */
#define MISC_REG_GENERIC_POR_1 0xa474
/* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO
can not be configured as an output. Each output has its output enable in
the MCP register space; but this bit needs to be set to make use of that.
Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When
set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
the i/o to an output and will drive the TimeSync output. Bit[31:7]:
spare. Global register. Reset by hard reset. */
#define MISC_REG_GEN_PURP_HWG 0xa9a0
/* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
these bits is written as a '1'; the corresponding SPIO bit will turn off
it's drivers and become an input. This is the reset state of all GPIO
pins. The read value of these bits will be a '1' if that last command
(#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
[23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
as a '1'; the corresponding GPIO bit will drive low. The read value of
these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
SET When any of these bits is written as a '1'; the corresponding GPIO
bit will drive high (if it has that capability). The read value of these
bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
RO; These bits indicate the read value of each of the eight GPIO pins.
This is the result value of the pin; not the drive value. Writing these
bits will have not effect. */
#define MISC_REG_GPIO 0xa490
/* [RW 8] These bits enable the GPIO_INTs to signals event to the
IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2;
[7] p1_gpio_3; */
#define MISC_REG_GPIO_EVENT_EN 0xa2bc
/* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
'1' to these bit clears the corresponding bit in the #OLD_VALUE register.
This will acknowledge an interrupt on the falling edge of corresponding
GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE
register. This will acknowledge an interrupt on the rising edge of
corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input
value. When the ~INT_STATE bit is set; this bit indicates the OLD value
of the pin such that if ~INT_STATE is set and this bit is '0'; then the
interrupt is due to a low to high edge. If ~INT_STATE is set and this bit
is '1'; then the interrupt is due to a high to low edge (reset value 0).
[7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
current GPIO interrupt state for each GPIO pin. This bit is cleared when
the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is
set when the GPIO input does not match the current value in #OLD_VALUE
(reset value 0). */
#define MISC_REG_GPIO_INT 0xa494
/* [R 28] this field hold the last information that caused reserved
attention. bits [19:0] - address; [22:20] function; [23] reserved;
[27:24] the master that caused the attention - according to the following
encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
dbu; 8 = dmae */
#define MISC_REG_GRC_RSV_ATTN 0xa3c0
/* [R 28] this field hold the last information that caused timeout
attention. bits [19:0] - address; [22:20] function; [23] reserved;
[27:24] the master that caused the attention - according to the following
encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 =
dbu; 8 = dmae */
#define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
/* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
access that does not finish within
~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
cleared; this timeout is disabled. If this timeout occurs; the GRC shall
assert it attention output. */
#define MISC_REG_GRC_TIMEOUT_EN 0xa280
/* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
(reset value 001) Charge pump current control; 111 for 720u; 011 for
600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
Global bias control; When bit 7 is high bias current will be 10 0gh; When
bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
Pll_observe (reset value 010) Bits to control observability. bit 10 is
for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
(reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
internally). [14] reserved (reset value 0) Reset for VCO sequencer is
connected to RESET input directly. [15] capRetry_en (reset value 0)
enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
value 0) bit to continuously monitor vco freq (inverted). [17]
freqDetRestart_en (reset value 0) bit to enable restart when not freq
locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
(reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
restart. [27] capSelectM_en (reset value 0) bit to enable cap select
register bits. */
#define MISC_REG_LCPLL_CTRL_1 0xa2a4
#define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
/* [RW 1] LCPLL power down. Global register. Active High. Reset on POR
* reset. */
#define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
/* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */
#define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
/* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
* reset. */
#define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
/* [RW 4] Interrupt mask register #0 read/write */
#define MISC_REG_MISC_INT_MASK 0xa388
/* [RW 1] Parity mask register #0 read/write */
#define MISC_REG_MISC_PRTY_MASK 0xa398
/* [R 1] Parity register #0 read */
#define MISC_REG_MISC_PRTY_STS 0xa38c
/* [RC 1] Parity register #0 read clear */
#define MISC_REG_MISC_PRTY_STS_CLR 0xa390
#define MISC_REG_NIG_WOL_P0 0xa270
#define MISC_REG_NIG_WOL_P1 0xa274
/* [R 1] If set indicate that the pcie_rst_b was asserted without perst
assertion */
#define MISC_REG_PCIE_HOT_RESET 0xa618
/* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
(reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
[23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
testa_en (reset value 0); */
#define MISC_REG_PLL_STORM_CTRL_1 0xa294
#define MISC_REG_PLL_STORM_CTRL_2 0xa298
#define MISC_REG_PLL_STORM_CTRL_3 0xa29c
#define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
/* [R 1] Status of 4 port mode enable input pin. */
#define MISC_REG_PORT4MODE_EN 0xa750
/* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
* the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
* the port4mode_en output is equal to bit[1] of this register; [1] -
* Overwrite value. If bit[0] of this register is 1 this is the value that
* receives the port4mode_en output . */
#define MISC_REG_PORT4MODE_EN_OVWR 0xa720
/* [RW 32] reset reg#2; rite/read one = the specific block is out of reset;
write/read zero = the specific block is in reset; addr 0-wr- the write
value will be written to the register; addr 1-set - one will be written
to all the bits that have the value of one in the data written (bits that
have the value of zero will not be change) ; addr 2-clear - zero will be
written to all the bits that have the value of one in the data written
(bits that have the value of zero will not be change); addr 3-ignore;
read ignore from all addr except addr 00; inside order of the bits is:
[0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
[5] rst_mcp_n_reset_reg_hard_core; [6] rst_ mcp_n_hard_core_rst_b; [7]
rst_ mcp_n_reset_cmn_cpu; [8] rst_ mcp_n_reset_cmn_core; [9] rst_rbcn;
[10] rst_dbg; [11] rst_misc_core; [12] rst_dbue (UART); [13]
Pci_resetmdio_n; [14] rst_emac0_hard_core; [15] rst_emac1_hard_core; 16]
rst_pxp_rq_rd_wr; 31:17] reserved */
#define MISC_REG_RESET_REG_1 0xa580
#define MISC_REG_RESET_REG_2 0xa590
/* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
shared with the driver resides */
#define MISC_REG_SHARED_MEM_ADDR 0xa2b4
/* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
the corresponding SPIO bit will turn off it's drivers and become an
input. This is the reset state of all SPIO pins. The read value of these
bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
is written as a '1'; the corresponding SPIO bit will drive low. The read
value of these bits will be a '1' if that last command (#SET; #CLR; or
#FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
these bits is written as a '1'; the corresponding SPIO bit will drive
high (if it has that capability). The read value of these bits will be a
'1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
(reset value 0). [7-0] VALUE RO; These bits indicate the read value of
each of the eight SPIO pins. This is the result value of the pin; not the
drive value. Writing these bits will have not effect. Each 8 bits field
is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
from VAUX. (This is an output pin only; the FLOAT field is not applicable
for this pin); [1] VAUX Disable; when pulsed low; disables supply form
VAUX. (This is an output pin only; FLOAT field is not applicable for this
pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
select VAUX supply. (This is an output pin only; it is not controlled by
the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
field is not applicable for this pin; only the VALUE fields is relevant -
it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6]
Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
device ID select; read by UMP firmware. */
#define MISC_REG_SPIO 0xa4fc
/* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
[7:0] reserved */
#define MISC_REG_SPIO_EVENT_EN 0xa2b8
/* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
corresponding bit in the #OLD_VALUE register. This will acknowledge an
interrupt on the falling edge of corresponding SPIO input (reset value
0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
in the #OLD_VALUE register. This will acknowledge an interrupt on the
rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
RO; These bits indicate the old value of the SPIO input value. When the
~INT_STATE bit is set; this bit indicates the OLD value of the pin such
that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
RO; These bits indicate the current SPIO interrupt state for each SPIO
pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
command bit is written. This bit is set when the SPIO input does not
match the current value in #OLD_VALUE (reset value 0). */
#define MISC_REG_SPIO_INT 0xa500
/* [RW 32] reload value for counter 4 if reload; the value will be reload if
the counter reached zero and the reload bit
(~misc_registers_sw_timer_cfg_4.sw_timer_cfg_4[1] ) is set */
#define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
/* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
timer 8 */
#define MISC_REG_SW_TIMER_VAL 0xa5c0
/* [R 1] Status of two port mode path swap input pin. */
#define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
/* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
path_swap output is equal to 2 port mode path swap input pin; if it is 1
- the path_swap output is equal to bit[1] of this register; [1] -
Overwrite value. If bit[0] of this register is 1 this is the value that
receives the path_swap output. Reset on Hard reset. */
#define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
/* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
loaded; 0-prepare; -unprepare */
#define MISC_REG_UNPREPARED 0xa424
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
/* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or
* not it is the recipient of the message on the MDIO interface. The value
* is compared to the value on ctrl_md_devad. Drives output
* misc_xgxs0_phy_addr. Global register. */
#define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
#define MISC_REG_WC0_RESET 0xac30
/* [RW 2] XMAC Core port mode. Indicates the number of ports on the system
side. This should be less than or equal to phy_port_mode; if some of the
ports are not used. This enables reduction of frequency on the core side.
This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
input for the XMAC_MP core; and should be changed only while reset is
held low. Reset on Hard reset. */
#define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
/* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp
Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
XMAC_MP core; and should be changed only while reset is held low. Reset
on Hard reset. */
#define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
/* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
* Reads from this register will clear bits 31:0. */
#define MSTAT_REG_RX_STAT_GR64_LO 0x200
/* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits
* 31:0. Reads from this register will clear bits 31:0. */
#define MSTAT_REG_TX_STAT_GTXPOK_LO 0
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
#define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
#define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
#define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
#define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
/* [RW 1] Input enable for RX_BMAC0 IF */
#define NIG_REG_BMAC0_IN_EN 0x100ac
/* [RW 1] output enable for TX_BMAC0 IF */
#define NIG_REG_BMAC0_OUT_EN 0x100e0
/* [RW 1] output enable for TX BMAC pause port 0 IF */
#define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
/* [RW 1] output enable for RX_BMAC0_REGS IF */
#define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
/* [RW 1] output enable for RX BRB1 port0 IF */
#define NIG_REG_BRB0_OUT_EN 0x100f8
/* [RW 1] Input enable for TX BRB1 pause port 0 IF */
#define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
/* [RW 1] output enable for RX BRB1 port1 IF */
#define NIG_REG_BRB1_OUT_EN 0x100fc
/* [RW 1] Input enable for TX BRB1 pause port 1 IF */
#define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
/* [RW 1] output enable for RX BRB1 LP IF */
#define NIG_REG_BRB_LB_OUT_EN 0x10100
/* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush;
72:73]-vnic_num; 81:74]-sideband_info */
#define NIG_REG_DEBUG_PACKET_LB 0x10800
/* [RW 1] Input enable for TX Debug packet */
#define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
/* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
packets from PBFare not forwarded to the MAC and just deleted from FIFO.
First packet may be deleted from the middle. And last packet will be
always deleted till the end. */
#define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
/* [RW 1] Output enable to EMAC0 */
#define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
/* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
to emac for port0; other way to bmac for port0 */
#define NIG_REG_EGRESS_EMAC0_PORT 0x10058
/* [RW 1] Input enable for TX PBF user packet port0 IF */
#define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
/* [RW 1] Input enable for TX PBF user packet port1 IF */
#define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
/* [RW 1] Input enable for TX UMP management packet port0 IF */
#define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
/* [RW 1] Input enable for RX_EMAC0 IF */
#define NIG_REG_EMAC0_IN_EN 0x100a4
/* [RW 1] output enable for TX EMAC pause port 0 IF */
#define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
/* [R 1] status from emac0. This bit is set when MDINT from either the
EXT_MDINT pin or from the Copper PHY is driven low. This condition must
be cleared in the attached PHY device that is driving the MINT pin. */
#define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
/* [WB 48] This address space contains BMAC0 registers. The BMAC registers
are described in appendix A. In order to access the BMAC0 registers; the
base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
added to each BMAC register offset */
#define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
/* [WB 48] This address space contains BMAC1 registers. The BMAC registers
are described in appendix A. In order to access the BMAC0 registers; the
base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
added to each BMAC register offset */
#define NIG_REG_INGRESS_BMAC1_MEM 0x11000
/* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
#define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
/* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
#define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
/* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
logic for interrupts must be used. Enable per bit of interrupt of
~latch_status.latch_status */
#define NIG_REG_LATCH_BC_0 0x16210
/* [RW 27] Latch for each interrupt from Unicore.b[0]
status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete;
b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status;
b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn;
b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete;
b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status;
b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete;
b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet;
b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g;
b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact;
b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx;
b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx;
b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs */
#define NIG_REG_LATCH_STATUS_0 0x18000
/* [RW 1] led 10g for port 0 */
#define NIG_REG_LED_10G_P0 0x10320
/* [RW 1] led 10g for port 1 */
#define NIG_REG_LED_10G_P1 0x10324
/* [RW 1] Port0: This bit is set to enable the use of the
~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
defined below. If this bit is cleared; then the blink rate will be about
8Hz. */
#define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
/* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
is reset to 0x080; giving a default blink period of approximately 8Hz. */
#define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
/* [RW 1] Port0: If set along with the
~nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
bit; the Traffic LED will blink with the blink rate specified in
~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
fields. */
#define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
/* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
Traffic LED will then be controlled via bit ~nig_registers_
led_control_traffic_p0.led_control_traffic_p0 and bit
~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
#define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
/* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
set; the LED will blink with blink rate specified in
~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
fields. */
#define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
/* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
9-11PHY7; 12 MAC4; 13-15 PHY10; */
#define NIG_REG_LED_MODE_P0 0x102f0
/* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
tsdm enable; b2- usdm enable */
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
#define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
/* [RW 1] SAFC enable for port0. This register may get 1 only when
~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
port */
#define NIG_REG_LLFC_ENABLE_0 0x16208
#define NIG_REG_LLFC_ENABLE_1 0x1620c
/* [RW 16] classes are high-priority for port0 */
#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
#define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
/* [RW 16] classes are low-priority for port0 */
#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
#define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
/* [RW 1] Output enable of message to LLFC BMAC IF for port0 */
#define NIG_REG_LLFC_OUT_EN_0 0x160c8
#define NIG_REG_LLFC_OUT_EN_1 0x160cc
#define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
#define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
#define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
#define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
/* [RW 1] send to BRB1 if no match on any of RMP rules. */
#define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
/* [RW 2] Determine the classification participants. 0: no classification.1:
classification upon VLAN id. 2: classification upon MAC address. 3:
classification upon both VLAN id & MAC addr. */
#define NIG_REG_LLH0_CLS_TYPE 0x16080
/* [RW 32] cm header for llh0 */
#define NIG_REG_LLH0_CM_HEADER 0x1007c
#define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
#define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
/* [RW 16] destination TCP address 1. The LLH will look for this address in
all incoming packets. */
#define NIG_REG_LLH0_DEST_TCP_0 0x10220
/* [RW 16] destination UDP address 1 The LLH will look for this address in
all incoming packets. */
#define NIG_REG_LLH0_DEST_UDP_0 0x10214
#define NIG_REG_LLH0_ERROR_MASK 0x1008c
/* [RW 8] event id for llh0 */
#define NIG_REG_LLH0_EVENT_ID 0x10084
#define NIG_REG_LLH0_FUNC_EN 0x160fc
#define NIG_REG_LLH0_FUNC_MEM 0x16180
#define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
#define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
/* [RW 1] Determine the IP version to look for in
~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
#define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
/* [RW 1] t bit for llh0 */
#define NIG_REG_LLH0_T_BIT 0x10074
/* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */
#define NIG_REG_LLH0_VLAN_ID_0 0x1022c
/* [RW 8] init credit counter for port0 in LLH */
#define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
#define NIG_REG_LLH0_XCM_MASK 0x10130
#define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
/* [RW 1] send to BRB1 if no match on any of RMP rules. */
#define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
/* [RW 2] Determine the classification participants. 0: no classification.1:
classification upon VLAN id. 2: classification upon MAC address. 3:
classification upon both VLAN id & MAC addr. */
#define NIG_REG_LLH1_CLS_TYPE 0x16084
/* [RW 32] cm header for llh1 */
#define NIG_REG_LLH1_CM_HEADER 0x10080
#define NIG_REG_LLH1_ERROR_MASK 0x10090
/* [RW 8] event id for llh1 */
#define NIG_REG_LLH1_EVENT_ID 0x10088
#define NIG_REG_LLH1_FUNC_EN 0x16104
#define NIG_REG_LLH1_FUNC_MEM 0x161c0
#define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
#define NIG_REG_LLH1_FUNC_MEM_SIZE 16
/* [RW 1] When this bit is set; the LLH will classify the packet before
* sending it to the BRB or calculating WoL on it. This bit controls port 1
* only. The legacy llh_multi_function_mode bit controls port 0. */
#define NIG_REG_LLH1_MF_MODE 0x18614
/* [RW 8] init credit counter for port1 in LLH */
#define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
#define NIG_REG_LLH1_XCM_MASK 0x10134
/* [RW 1] When this bit is set; the LLH will expect all packets to be with
e1hov */
#define NIG_REG_LLH_E1HOV_MODE 0x160d8
/* [RW 1] When this bit is set; the LLH will classify the packet before
sending it to the BRB or calculating WoL on it. */
#define NIG_REG_LLH_MF_MODE 0x16024
#define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
#define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
/* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
#define NIG_REG_NIG_EMAC0_EN 0x1003c
/* [RW 1] Output signal from NIG to EMAC1. When set enables the EMAC1 block. */
#define NIG_REG_NIG_EMAC1_EN 0x10040
/* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
EMAC0 to strip the CRC from the ingress packets. */
#define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
/* [R 32] Interrupt register #0 read */
#define NIG_REG_NIG_INT_STS_0 0x103b0
#define NIG_REG_NIG_INT_STS_1 0x103c0
/* [RC 32] Interrupt register #0 read clear */
#define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
/* [R 32] Legacy E1 and E1H location for parity error mask register. */
#define NIG_REG_NIG_PRTY_MASK 0x103dc
/* [RW 32] Parity mask register #0 read/write */
#define NIG_REG_NIG_PRTY_MASK_0 0x183c8
#define NIG_REG_NIG_PRTY_MASK_1 0x183d8
/* [R 32] Legacy E1 and E1H location for parity error status register. */
#define NIG_REG_NIG_PRTY_STS 0x103d0
/* [R 32] Parity register #0 read */
#define NIG_REG_NIG_PRTY_STS_0 0x183bc
#define NIG_REG_NIG_PRTY_STS_1 0x183cc
/* [R 32] Legacy E1 and E1H location for parity error status clear register. */
#define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
/* [RC 32] Parity register #0 read clear */
#define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
#define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
#define MCPR_IMC_COMMAND_ENABLE (1L<<31)
#define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16
#define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28
#define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8
/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
* Ethernet header. */
#define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
/* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in
* the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be
* disabled when this bit is set. */
#define NIG_REG_P0_HWPFC_ENABLE 0x18078
#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
/* [RW 1] Input enable for RX MAC interface. */
#define NIG_REG_P0_MAC_IN_EN 0x185ac
/* [RW 1] Output enable for TX MAC interface */
#define NIG_REG_P0_MAC_OUT_EN 0x185b0
/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
#define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
* future expansion) each priorty is to be mapped to. Bits 3:0 specify the
* COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
* priority field is extracted from the outer-most VLAN in receive packet.
* Only COS 0 and COS 1 are supported in E2. */
#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
* priority is mapped to COS 0 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
* priority is mapped to COS 1 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
* priority is mapped to COS 2 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
* priority is mapped to COS 3 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
* priority is mapped to COS 4 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
* priority is mapped to COS 5 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
/* [R 1] RX FIFO for receiving data from MAC is empty. */
/* [RW 15] Specify which of the credit registers the client is to be mapped
* to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
* clients that are not subject to WFQ credit blocking - their
* specifications here are not used. */
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
/* [RW 32] Specify which of the credit registers the client is to be mapped
* to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
* for client 0; bits [35:32] are for client 8. For clients that are not
* subject to WFQ credit blocking - their specifications here are not used.
* This is a new register (with 2_) added in E3 B0 to accommodate the 9
* input clients to ETS arbiter. The reset default is set for management and
* debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
* use credit registers 0-5 respectively (0x543210876). Note that credit
* registers can not be shared between clients. */
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
/* [RW 4] Specify which of the credit registers the client is to be mapped
* to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
* for client 0; bits [35:32] are for client 8. For clients that are not
* subject to WFQ credit blocking - their specifications here are not used.
* This is a new register (with 2_) added in E3 B0 to accommodate the 9
* input clients to ETS arbiter. The reset default is set for management and
* debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
* use credit registers 0-5 respectively (0x543210876). Note that credit
* registers can not be shared between clients. */
#define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
/* [RW 5] Specify whether the client competes directly in the strict
* priority arbiter. The bits are mapped according to client ID (client IDs
* are defined in tx_arb_priority_client). Default value is set to enable
* strict priorities for clients 0-2 -- management and debug traffic. */
#define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
/* [RW 5] Specify whether the client is subject to WFQ credit blocking. The
* bits are mapped according to client ID (client IDs are defined in
* tx_arb_priority_client). Default value is 0 for not using WFQ credit
* blocking. */
#define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
/* [RW 32] Specify the upper bound that credit register 0 is allowed to
* reach. */
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
#define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
* when it is time to increment. */
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
#define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
/* [RW 12] Specify the number of strict priority arbitration slots between
* two round-robin arbitration slots to avoid starvation. A value of 0 means
* no strict priority cycles - the strict priority with anti-starvation
* arbiter becomes a round-robin arbiter. */
#define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
/* [RW 15] Specify the client number to be assigned to each priority of the
* strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
* are for priority 0 client; bits [14:12] are for priority 4 client. The
* clients are assigned the following IDs: 0-management; 1-debug traffic
* from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
* traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
* for management at priority 0; debug traffic at priorities 1 and 2; COS0
* traffic at priority 3; and COS1 traffic at priority 4. */
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
* Ethernet header. */
#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
/* [RW 32] Specify the client number to be assigned to each priority of the
* strict priority arbiter. This register specifies bits 31:0 of the 36-bit
* value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
* client; bits [35-32] are for priority 8 client. The clients are assigned
* the following IDs: 0-management; 1-debug traffic from this port; 2-debug
* traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
* 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
* set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
* accommodate the 9 input clients to ETS arbiter. */
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
/* [RW 4] Specify the client number to be assigned to each priority of the
* strict priority arbiter. This register specifies bits 35:32 of the 36-bit
* value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
* client; bits [35-32] are for priority 8 client. The clients are assigned
* the following IDs: 0-management; 1-debug traffic from this port; 2-debug
* traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
* 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
* set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
* accommodate the 9 input clients to ETS arbiter. */
#define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
* packets to BRB LB interface to forward the packet to the host. All
* packets from MCP are forwarded to the network when this bit is cleared -
* regardless of the configured destination in tx_mng_destination register.
* When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
* for BRB LB interface is bypassed and PBF LB traffic is always selected to
* send to BRB LB.
*/
#define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4
#define NIG_REG_P1_HWPFC_ENABLE 0x181d0
#define NIG_REG_P1_MAC_IN_EN 0x185c0
/* [RW 1] Output enable for TX MAC interface */
#define NIG_REG_P1_MAC_OUT_EN 0x185c4
/* [RW 1] Output enable for TX PAUSE signal to the MAC. */
#define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
/* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
* future expansion) each priorty is to be mapped to. Bits 3:0 specify the
* COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
* priority field is extracted from the outer-most VLAN in receive packet.
* Only COS 0 and COS 1 are supported in E2. */
#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
* priority is mapped to COS 0 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
* priority is mapped to COS 1 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
* priority is mapped to COS 2 when the corresponding mask bit is 1. More
* than one bit may be set; allowing multiple priorities to be mapped to one
* COS. */
#define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
/* [R 1] RX FIFO for receiving data from MAC is empty. */
#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
/* [R 1] TLLH FIFO is empty. */
#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
/* [RW 32] Specify which of the credit registers the client is to be mapped
* to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
* for client 0; bits [35:32] are for client 8. For clients that are not
* subject to WFQ credit blocking - their specifications here are not used.
* This is a new register (with 2_) added in E3 B0 to accommodate the 9
* input clients to ETS arbiter. The reset default is set for management and
* debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
* use credit registers 0-5 respectively (0x543210876). Note that credit
* registers can not be shared between clients. Note also that there are
* only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
* credit registers 0-5 are valid. This register should be configured
* appropriately before enabling WFQ. */
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
/* [RW 4] Specify which of the credit registers the client is to be mapped
* to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
* for client 0; bits [35:32] are for client 8. For clients that are not
* subject to WFQ credit blocking - their specifications here are not used.
* This is a new register (with 2_) added in E3 B0 to accommodate the 9
* input clients to ETS arbiter. The reset default is set for management and
* debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
* use credit registers 0-5 respectively (0x543210876). Note that credit
* registers can not be shared between clients. Note also that there are
* only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
* credit registers 0-5 are valid. This register should be configured
* appropriately before enabling WFQ. */
#define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
/* [RW 9] Specify whether the client competes directly in the strict
* priority arbiter. The bits are mapped according to client ID (client IDs
* are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
* from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
* traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
* Default value is set to enable strict priorities for all clients. */
#define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
/* [RW 9] Specify whether the client is subject to WFQ credit blocking. The
* bits are mapped according to client ID (client IDs are defined in
* tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
* 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
* traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
* 0 for not using WFQ credit blocking. */
#define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
#define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
/* [RW 32] Specify the weight (in bytes) to be added to credit register 0
* when it is time to increment. */
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
#define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
/* [RW 12] Specify the number of strict priority arbitration slots between
two round-robin arbitration slots to avoid starvation. A value of 0 means
no strict priority cycles - the strict priority with anti-starvation
arbiter becomes a round-robin arbiter. */
#define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
/* [RW 32] Specify the client number to be assigned to each priority of the
strict priority arbiter. This register specifies bits 31:0 of the 36-bit
value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
client; bits [35-32] are for priority 8 client. The clients are assigned
the following IDs: 0-management; 1-debug traffic from this port; 2-debug
traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
accommodate the 9 input clients to ETS arbiter. Note that this register
is the same as the one for port 0, except that port 1 only has COS 0-2
traffic. There is no traffic for COS 3-5 of port 1. */
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
/* [RW 4] Specify the client number to be assigned to each priority of the
strict priority arbiter. This register specifies bits 35:32 of the 36-bit
value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
client; bits [35-32] are for priority 8 client. The clients are assigned
the following IDs: 0-management; 1-debug traffic from this port; 2-debug
traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
accommodate the 9 input clients to ETS arbiter. Note that this register
is the same as the one for port 0, except that port 1 only has COS 0-2
traffic. There is no traffic for COS 3-5 of port 1. */
#define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
/* [R 1] TX FIFO for transmitting data to MAC is empty. */
#define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
/* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
* packets to BRB LB interface to forward the packet to the host. All
* packets from MCP are forwarded to the network when this bit is cleared -
* regardless of the configured destination in tx_mng_destination register.
*/
#define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8
/* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets
forwarded to the host. */
#define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
/* [RW 32] Specify the upper bound that credit register 0 is allowed to
* reach. */
/* [RW 1] Pause enable for port0. This register may get 1 only when
~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
port */
#define NIG_REG_PAUSE_ENABLE_0 0x160c0
#define NIG_REG_PAUSE_ENABLE_1 0x160c4
/* [RW 1] Input enable for RX PBF LP IF */
#define NIG_REG_PBF_LB_IN_EN 0x100b4
/* [RW 1] Value of this register will be transmitted to port swap when
~nig_registers_strap_override.strap_override =1 */
#define NIG_REG_PORT_SWAP 0x10394
/* [RW 1] PPP enable for port0. This register may get 1 only when
* ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
* same port */
#define NIG_REG_PPP_ENABLE_0 0x160b0
#define NIG_REG_PPP_ENABLE_1 0x160b4
/* [RW 1] output enable for RX parser descriptor IF */
#define NIG_REG_PRS_EOP_OUT_EN 0x10104
/* [RW 1] Input enable for RX parser request IF */
#define NIG_REG_PRS_REQ_IN_EN 0x100b8
/* [RW 5] control to serdes - CL45 DEVAD */
#define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
/* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
#define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
/* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
#define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
/* [R 1] status from serdes0 that inputs to interrupt logic of link status */
#define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
for port0 */
#define NIG_REG_STAT0_BRB_DISCARD 0x105f0
/* [R 32] Rx statistics : In user packets truncated due to BRB backpressure
for port0 */
#define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
between 1024 and 1522 bytes for port0 */
#define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
/* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that
between 1523 bytes and above for port0 */
#define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
/* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
for port1 */
#define NIG_REG_STAT1_BRB_DISCARD 0x10628
/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
between 1024 and 1522 bytes for port1 */
#define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
/* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that
between 1523 bytes and above for port1 */
#define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
/* [WB_R 64] Rx statistics : User octets received for LP */
#define NIG_REG_STAT2_BRB_OCTET 0x107e0
#define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
#define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
/* [RW 1] port swap mux selection. If this register equal to 0 then port
swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
ort swap is equal to ~nig_registers_port_swap.port_swap */
#define NIG_REG_STRAP_OVERRIDE 0x10398
/* [RW 1] output enable for RX_XCM0 IF */
#define NIG_REG_XCM0_OUT_EN 0x100f0
/* [RW 1] output enable for RX_XCM1 IF */
#define NIG_REG_XCM1_OUT_EN 0x100f4
/* [RW 1] control to xgxs - remote PHY in-band MDIO */
#define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
/* [RW 5] control to xgxs - CL45 DEVAD */
#define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
/* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
#define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
/* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
#define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
/* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
#define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
/* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
#define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
/* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
#define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
/* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
#define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
#define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter. */
#define PBF_REG_COS0_UPPER_BOUND 0x15c05c
/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
* of port 0. */
#define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
/* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter
* of port 1. */
#define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
/* [RW 31] The weight of COS0 in the ETS command arbiter. */
#define PBF_REG_COS0_WEIGHT 0x15c054
/* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
#define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
/* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */
#define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
/* [RW 31] The upper bound of the weight of COS1 in the ETS command arbiter. */
#define PBF_REG_COS1_UPPER_BOUND 0x15c060
/* [RW 31] The weight of COS1 in the ETS command arbiter. */
#define PBF_REG_COS1_WEIGHT 0x15c058
/* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
#define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
/* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */
#define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
/* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
#define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
/* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */
#define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
/* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
#define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
/* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
#define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
/* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
#define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
/* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte
* lines. */
#define PBF_REG_CREDIT_LB_Q 0x140338
/* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
* lines. */
#define PBF_REG_CREDIT_Q0 0x14033c
/* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte
* lines. */
#define PBF_REG_CREDIT_Q1 0x140340
/* [RW 1] Disable processing further tasks from port 0 (after ending the
current task in process). */
#define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
/* [RW 1] Disable processing further tasks from port 1 (after ending the
current task in process). */
#define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
/* [RW 1] Disable processing further tasks from port 4 (after ending the
current task in process). */
#define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
#define PBF_REG_DISABLE_PF 0x1402e8
#define PBF_REG_DISABLE_VF 0x1402ec
/* [RW 18] For port 0: For each client that is subject to WFQ (the
* corresponding bit is 1); indicates to which of the credit registers this
* client is mapped. For clients which are not credit blocked; their mapping
* is dont care. */
#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
/* [RW 9] For port 1: For each client that is subject to WFQ (the
* corresponding bit is 1); indicates to which of the credit registers this
* client is mapped. For clients which are not credit blocked; their mapping
* is dont care. */
#define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
/* [RW 6] For port 0: Bit per client to indicate if the client competes in
* the strict priority arbiter directly (corresponding bit = 1); or first
* goes to the RR arbiter (corresponding bit = 0); and then competes in the
* lowest priority in the strict-priority arbiter. */
#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
/* [RW 3] For port 1: Bit per client to indicate if the client competes in
* the strict priority arbiter directly (corresponding bit = 1); or first
* goes to the RR arbiter (corresponding bit = 0); and then competes in the
* lowest priority in the strict-priority arbiter. */
#define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
/* [RW 6] For port 0: Bit per client to indicate if the client is subject to
* WFQ credit blocking (corresponding bit = 1). */
#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
/* [RW 3] For port 0: Bit per client to indicate if the client is subject to
* WFQ credit blocking (corresponding bit = 1). */
#define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
/* [RW 16] For port 0: The number of strict priority arbitration slots
* between 2 RR arbitration slots. A value of 0 means no strict priority
* cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
* arbiter. */
#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
/* [RW 16] For port 1: The number of strict priority arbitration slots
* between 2 RR arbitration slots. A value of 0 means no strict priority
* cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
* arbiter. */
#define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
/* [RW 18] For port 0: Indicates which client is connected to each priority
* in the strict-priority arbiter. Priority 0 is the highest priority, and
* priority 5 is the lowest; to which the RR output is connected to (this is
* not configurable). */
#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
/* [RW 9] For port 1: Indicates which client is connected to each priority
* in the strict-priority arbiter. Priority 0 is the highest priority, and
* priority 5 is the lowest; to which the RR output is connected to (this is
* not configurable). */
#define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
/* [RW 1] Indicates that ETS is performed between the COSes in the command
* arbiter. If reset strict priority w/ anti-starvation will be performed
* w/o WFQ. */
#define PBF_REG_ETS_ENABLED 0x15c050
/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
* Ethernet header. */
#define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
#define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
/* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
* priority in the command arbiter. */
#define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
#define PBF_REG_IF_ENABLE_REG 0x140044
/* [RW 1] Init bit. When set the initial credits are copied to the credit
registers (except the port credits). Should be set and then reset after
the configuration of the block has ended. */
#define PBF_REG_INIT 0x140000
/* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte
* lines. */
#define PBF_REG_INIT_CRD_LB_Q 0x15c248
/* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
* lines. */
#define PBF_REG_INIT_CRD_Q0 0x15c230
/* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte
* lines. */
#define PBF_REG_INIT_CRD_Q1 0x15c234
/* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
copied to the credit register. Should be set and then reset after the
configuration of the port has ended. */
#define PBF_REG_INIT_P0 0x140004
/* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
copied to the credit register. Should be set and then reset after the
configuration of the port has ended. */
#define PBF_REG_INIT_P1 0x140008
/* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
copied to the credit register. Should be set and then reset after the
configuration of the port has ended. */
#define PBF_REG_INIT_P4 0x14000c
/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
* the LB queue. Reset upon init. */
#define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
* queue 0. Reset upon init. */
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
* queue 1. Reset upon init. */
#define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
/* [RW 1] Enable for mac interface 0. */
#define PBF_REG_MAC_IF0_ENABLE 0x140030
/* [RW 1] Enable for mac interface 1. */
#define PBF_REG_MAC_IF1_ENABLE 0x140034
/* [RW 1] Enable for the loopback interface. */
#define PBF_REG_MAC_LB_ENABLE 0x140040
/* [RW 6] Bit-map indicating which headers must appear in the packet */
#define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
/* [RW 16] The number of strict priority arbitration slots between 2 RR
* arbitration slots. A value of 0 means no strict priority cycles; i.e. the
* strict-priority w/ anti-starvation arbiter is a RR arbiter. */
#define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
/* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
not suppoterd. */
#define PBF_REG_P0_ARB_THRSH 0x1400e4
/* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
#define PBF_REG_P0_CREDIT 0x140200
/* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
lines. */
#define PBF_REG_P0_INIT_CRD 0x1400d0
/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
* port 0. Reset upon init. */
#define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
/* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
#define PBF_REG_P0_PAUSE_ENABLE 0x140014
/* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
#define PBF_REG_P0_TASK_CNT 0x140204
/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
* freed from the task queue of port 0. Reset upon init. */
#define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
/* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
#define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
/* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
* buffers in 16 byte lines. */
#define PBF_REG_P1_CREDIT 0x140208
/* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
* buffers in 16 byte lines. */
#define PBF_REG_P1_INIT_CRD 0x1400d4
/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
* port 1. Reset upon init. */
#define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
/* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
#define PBF_REG_P1_TASK_CNT 0x14020c
/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
* freed from the task queue of port 1. Reset upon init. */
#define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
/* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */
#define PBF_REG_P1_TQ_OCCUPANCY 0x140300
/* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
#define PBF_REG_P4_CREDIT 0x140210
/* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
lines. */
#define PBF_REG_P4_INIT_CRD 0x1400e0
/* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for
* port 4. Reset upon init. */
#define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
/* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
#define PBF_REG_P4_TASK_CNT 0x140214
/* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
* freed from the task queue of port 4. Reset upon init. */
#define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
/* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */
#define PBF_REG_P4_TQ_OCCUPANCY 0x140304
/* [RW 5] Interrupt mask register #0 read/write */
#define PBF_REG_PBF_INT_MASK 0x1401d4
/* [R 5] Interrupt register #0 read */
#define PBF_REG_PBF_INT_STS 0x1401c8
/* [RW 20] Parity mask register #0 read/write */
#define PBF_REG_PBF_PRTY_MASK 0x1401e4
/* [R 28] Parity register #0 read */
#define PBF_REG_PBF_PRTY_STS 0x1401d8
/* [RC 20] Parity register #0 read clear */
#define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
/* [RW 16] The Ethernet type value for L2 tag 0 */
#define PBF_REG_TAG_ETHERTYPE_0 0x15c090
/* [RW 4] The length of the info field for L2 tag 0. The length is between
* 2B and 14B; in 2B granularity */
#define PBF_REG_TAG_LEN_0 0x15c09c
/* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task
* queue. Reset upon init. */
#define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
/* [R 32] Cyclic counter for number of 8 byte lines freed from the task
* queue 0. Reset upon init. */
#define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
/* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1.
* Reset upon init. */
#define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
/* [R 13] Number of 8 bytes lines occupied in the task queue of the LB
* queue. */
#define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
#define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
/* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */
#define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
#define PB_REG_CONTROL 0
/* [RW 2] Interrupt mask register #0 read/write */
#define PB_REG_PB_INT_MASK 0x28
/* [R 2] Interrupt register #0 read */
#define PB_REG_PB_INT_STS 0x1c
/* [RW 4] Parity mask register #0 read/write */
#define PB_REG_PB_PRTY_MASK 0x38
/* [R 4] Parity register #0 read */
#define PB_REG_PB_PRTY_STS 0x2c
/* [RC 4] Parity register #0 read clear */
#define PB_REG_PB_PRTY_STS_CLR 0x30
#define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
#define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
#define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
#define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
#define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
#define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
/* [R 8] Config space A attention dirty bits. Each bit indicates that the
* corresponding PF generates config space A attention. Set by PXP. Reset by
* MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits
* from both paths. */
#define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
/* [R 8] Config space B attention dirty bits. Each bit indicates that the
* corresponding PF generates config space B attention. Set by PXP. Reset by
* MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits
* from both paths. */
#define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
/* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
* - enable. */
#define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
/* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
* its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
#define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
/* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
* - enable. */
#define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
/* [RW 16] Start offset of CSDM zone A (queue zone) in the internal RAM */
#define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
/* [RW 16] Start offset of CSDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
/* [RW 5] VF Shift of CSDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
#define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
/* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
* that the FLR register of the corresponding PF was set. Set by PXP. Reset
* by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits
* from both paths. */
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
/* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
* to a bit in this register in order to clear the corresponding bit in
* flr_request_pf_7_0 register. Note: register contains bits from both
* paths. */
#define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
/* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit
* indicates that the FLR register of the corresponding VF was set. Set by
* PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. */
#define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
/* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
* indicates that the FLR register of the corresponding VF was set. Set by
* PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. */
#define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
/* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit
* indicates that the FLR register of the corresponding VF was set. Set by
* PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. */
#define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
/* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit
* indicates that the FLR register of the corresponding VF was set. Set by
* PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. */
#define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
/* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit
* 0 - Target memory read arrived with a correctable error. Bit 1 - Target
* memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
* arrived with a correctable error. Bit 3 - Configuration RW arrived with
* an uncorrectable error. Bit 4 - Completion with Configuration Request
* Retry Status. Bit 5 - Expansion ROM access received with a write request.
* Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
* pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
* and pcie_rx_last not asserted. */
#define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
#define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
#define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
/* [W 7] Writing 1 to each bit in this register clears a corresponding error
* details register and enables logging new error details. Bit 0 - clears
* INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
* TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS
* TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32
* TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
* clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
* VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
* - clears TCPL_IN_TWO_RCBS_DETAILS. */
#define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c
/* [R 9] Interrupt register #0 read */
#define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
/* [RC 9] Interrupt register #0 read clear */
#define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
/* [RW 2] Parity mask register #0 read/write */
#define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
/* [R 2] Parity register #0 read */
#define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
/* [RC 2] Parity register #0 read clear */
#define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
/* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
* VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
* Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
* completer abort. 3 - Illegal value for this field. [12] valid - indicates
* if there was a completion error since the last time this register was
* cleared. */
#define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
/* [R 18] Details of first ATS Translation Completion request received with
* error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
* 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
* unsupported request. 2 - completer abort. 3 - Illegal value for this
* field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
* completion error since the last time this register was cleared. */
#define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
/* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
* a bit in this register in order to clear the corresponding bit in
* shadow_bme_pf_7_0 register. MCP should never use this unless a
* work-around is needed. Note: register contains bits from both paths. */
#define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
/* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the
* VF enable register of the corresponding PF is written to 0 and was
* previously 1. Set by PXP. Reset by MCP writing 1 to
* sr_iov_disabled_request_clr. Note: register contains bits from both
* paths. */
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
/* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
* completion did not return yet. 1 - tag is unused. Same functionality as
* pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
#define PGLUE_B_REG_TAGS_63_32 0x9244
/* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
* - enable. */
#define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
/* [RW 16] Start offset of TSDM zone A (queue zone) in the internal RAM */
#define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
/* [RW 16] Start offset of TSDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
/* [RW 5] VF Shift of TSDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
#define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
/* [R 32] Address [31:0] of first read request not submitted due to error */
#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
/* [R 32] Address [63:32] of first read request not submitted due to error */
#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
/* [R 31] Details of first read request not submitted due to error. [4:0]
* VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
* [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
* VFID. */
#define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
/* [R 26] Details of first read request not submitted due to error. [15:0]
* Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
* [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
* [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
* PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
* indicates if there was a request not submitted due to error since the
* last time this register was cleared. */
#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
/* [R 32] Address [31:0] of first write request not submitted due to error */
#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
/* [R 32] Address [63:32] of first write request not submitted due to error */
#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
/* [R 31] Details of first write request not submitted due to error. [4:0]
* VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
* - VFID. */
#define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
/* [R 26] Details of first write request not submitted due to error. [15:0]
* Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
* [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
* [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
* PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
* indicates if there was a request not submitted due to error since the
* last time this register was cleared. */
#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
/* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
* its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
* value (Byte resolution address). */
#define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
#define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
#define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
#define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
#define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
#define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
#define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
/* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
* - enable. */
#define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
/* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
* - enable. */
#define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
/* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
* - enable. */
#define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
/* [RW 16] Start offset of USDM zone A (queue zone) in the internal RAM */
#define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
/* [RW 16] Start offset of USDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
/* [RW 5] VF Shift of USDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
#define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
/* [R 26] Details of first target VF request accessing VF GRC space that
* failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
* [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
* request accessing VF GRC space that failed permission check since the
* last time this register was cleared. Permission checks are: function
* permission; R/W permission; address range permission. */
#define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
/* [R 31] Details of first target VF request with length violation (too many
* DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
* [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
* valid - indicates if there was a request with length violation since the
* last time this register was cleared. Length violations: length of more
* than 2DWs; length of 2DWs and address not QW aligned; window is GRC and
* length is more than 1 DW. */
#define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
/* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
* that there was a completion with uncorrectable error for the
* corresponding PF. Set by PXP. Reset by MCP writing 1 to
* was_error_pf_7_0_clr. */
#define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
/* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
* to a bit in this register in order to clear the corresponding bit in
* flr_request_pf_7_0 register. */
#define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
/* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit
* indicates that there was a completion with uncorrectable error for the
* corresponding VF. Set by PXP. Reset by MCP writing 1 to
* was_error_vf_127_96_clr. */
#define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
/* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP
* writes 1 to a bit in this register in order to clear the corresponding
* bit in was_error_vf_127_96 register. */
#define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
/* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
* indicates that there was a completion with uncorrectable error for the
* corresponding VF. Set by PXP. Reset by MCP writing 1 to
* was_error_vf_31_0_clr. */
#define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
/* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
* 1 to a bit in this register in order to clear the corresponding bit in
* was_error_vf_31_0 register. */
#define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
/* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit
* indicates that there was a completion with uncorrectable error for the
* corresponding VF. Set by PXP. Reset by MCP writing 1 to
* was_error_vf_63_32_clr. */
#define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
/* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes
* 1 to a bit in this register in order to clear the corresponding bit in
* was_error_vf_63_32 register. */
#define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
/* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit
* indicates that there was a completion with uncorrectable error for the
* corresponding VF. Set by PXP. Reset by MCP writing 1 to
* was_error_vf_95_64_clr. */
#define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
/* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes
* 1 to a bit in this register in order to clear the corresponding bit in
* was_error_vf_95_64 register. */
#define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
/* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
* - enable. */
#define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
/* [RW 16] Start offset of XSDM zone A (queue zone) in the internal RAM */
#define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
/* [RW 16] Start offset of XSDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
/* [RW 5] VF Shift of XSDM zone B (legacy zone) in the internal RAM */
#define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
/* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
#define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
#define PRS_REG_A_PRSU_20 0x40134
/* [R 8] debug only: CFC load request current credit. Transaction based. */
#define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
/* [R 8] debug only: CFC search request current credit. Transaction based. */
#define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
/* [RW 6] The initial credit for the search message to the CFC interface.
Credit is transaction based. */
#define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
/* [RW 24] CID for port 0 if no match */
#define PRS_REG_CID_PORT_0 0x400fc
/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
load response is reset and packet type is 0. Used in packet start message
to TCM. */
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
#define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
/* [RW 32] The CM header for flush message where 'load existed' bit in CFC
load response is set and packet type is 0. Used in packet start message
to TCM. */
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
#define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
/* [RW 32] The CM header for a match and packet type 1 for loopback port.
Used in packet start message to TCM. */
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
#define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
/* [RW 32] The CM header for a match and packet type 0. Used in packet start
message to TCM. */
#define PRS_REG_CM_HDR_TYPE_0 0x40078
#define PRS_REG_CM_HDR_TYPE_1 0x4007c
#define PRS_REG_CM_HDR_TYPE_2 0x40080
#define PRS_REG_CM_HDR_TYPE_3 0x40084
#define PRS_REG_CM_HDR_TYPE_4 0x40088
/* [RW 32] The CM header in case there was not a match on the connection */
#define PRS_REG_CM_NO_MATCH_HDR 0x400b8
/* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
#define PRS_REG_E1HOV_MODE 0x401c8
/* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
start message to TCM. */
#define PRS_REG_EVENT_ID_1 0x40054
#define PRS_REG_EVENT_ID_2 0x40058
#define PRS_REG_EVENT_ID_3 0x4005c
/* [RW 16] The Ethernet type value for FCoE */
#define PRS_REG_FCOE_TYPE 0x401d0
/* [RW 8] Context region for flush packet with packet type 0. Used in CFC
load request message. */
#define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
#define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
#define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
#define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
#define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
#define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
#define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
#define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
* Ethernet header. */
#define PRS_REG_HDRS_AFTER_BASIC 0x40238
/* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
* Ethernet header for port 0 packets. */
#define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
#define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
/* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
#define PRS_REG_HDRS_AFTER_TAG_0 0x40248
/* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
* port 0 packets */
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
#define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
/* [RW 4] The increment value to send in the CFC load request message */
#define PRS_REG_INC_VALUE 0x40048
/* [RW 6] Bit-map indicating which headers must appear in the packet */
#define PRS_REG_MUST_HAVE_HDRS 0x40254
/* [RW 6] Bit-map indicating which headers must appear in the packet for
* port 0 packets */
#define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
#define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
#define PRS_REG_NIC_MODE 0x40138
/* [RW 8] The 8-bit event ID for cases where there is no match on the
connection. Used in packet start message to TCM. */
#define PRS_REG_NO_MATCH_EVENT_ID 0x40070
/* [ST 24] The number of input CFC flush packets */
#define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
/* [ST 32] The number of cycles the Parser halted its operation since it
could not allocate the next serial number */
#define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
/* [ST 24] The number of input packets */
#define PRS_REG_NUM_OF_PACKETS 0x40124
/* [ST 24] The number of input transparent flush packets */
#define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
/* [RW 8] Context region for received Ethernet packet with a match and
packet type 0. Used in CFC load request message */
#define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
#define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
#define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
#define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
#define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
#define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
#define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
#define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
/* [R 2] debug only: Number of pending requests for CAC on port 0. */
#define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
/* [R 2] debug only: Number of pending requests for header parsing. */
#define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
/* [R 1] Interrupt register #0 read */
#define PRS_REG_PRS_INT_STS 0x40188
/* [RW 8] Parity mask register #0 read/write */
#define PRS_REG_PRS_PRTY_MASK 0x401a4
/* [R 8] Parity register #0 read */
#define PRS_REG_PRS_PRTY_STS 0x40198
/* [RC 8] Parity register #0 read clear */
#define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
/* [RW 8] Context region for pure acknowledge packets. Used in CFC load
request message */
#define PRS_REG_PURE_REGIONS 0x40024
/* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
serail number was released by SDM but cannot be used because a previous
serial number was not released. */
#define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
/* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
serail number was released by SDM but cannot be used because a previous
serial number was not released. */
#define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
/* [R 4] debug only: SRC current credit. Transaction based. */
#define PRS_REG_SRC_CURRENT_CREDIT 0x4016c