| From 2a6c71b94360555b91405356b306a6c9e4af437e Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= |
| <niklas.soderlund+renesas@ragnatech.se> |
| Date: Tue, 1 Nov 2016 21:12:24 +0100 |
| Subject: [PATCH 193/299] clk: renesas: r8a7796: Add CSI2 clocks |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| Signed-off-by: Niklas Sรถderlund <niklas.soderlund+renesas@ragnatech.se> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit 5fccac6d945b84e056b8b3b7083a151faaf2492c) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/clk/renesas/r8a7796-cpg-mssr.c | 4 ++++ |
| 1 file changed, 4 insertions(+) |
| |
| --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| @@ -103,6 +103,8 @@ static const struct cpg_core_clk r8a7796 |
| DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
| DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), |
| |
| + DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |
| + |
| DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), |
| DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), |
| |
| @@ -156,6 +158,8 @@ static const struct mssr_mod_clk r8a7796 |
| DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2), |
| DEF_MOD("vspb", 626, R8A7796_CLK_S0D1), |
| DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1), |
| + DEF_MOD("csi20", 714, R8A7796_CLK_CSI0), |
| + DEF_MOD("csi40", 716, R8A7796_CLK_CSI0), |
| DEF_MOD("du2", 722, R8A7796_CLK_S2D1), |
| DEF_MOD("du1", 723, R8A7796_CLK_S2D1), |
| DEF_MOD("du0", 724, R8A7796_CLK_S2D1), |
