| From 7fb4b5bdc8a9f93316864b0d16a3bffca70c6709 Mon Sep 17 00:00:00 2001 |
| From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Date: Mon, 5 Sep 2016 23:55:01 +0300 |
| Subject: [PATCH 218/299] ARM: dts: r8a7792: add MSIOF clocks |
| |
| Describe the MSIOF0/1 clocks and their parent, MP clock in the R8A7792 |
| device tree. |
| |
| Based on the original (and large) patch by Vladimir Barinov |
| <vladimir.barinov@cogentembedded.com>. |
| |
| Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 5cef452bf895cc38af3a4e20f85c20c1a4d41001) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7792.dtsi | 21 +++++++++++++++++++-- |
| 1 file changed, 19 insertions(+), 2 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7792.dtsi |
| +++ b/arch/arm/boot/dts/r8a7792.dtsi |
| @@ -768,6 +768,13 @@ |
| clock-div = <48>; |
| clock-mult = <1>; |
| }; |
| + mp_clk: mp { |
| + compatible = "fixed-factor-clock"; |
| + clocks = <&pll1_div2_clk>; |
| + #clock-cells = <0>; |
| + clock-div = <15>; |
| + clock-mult = <1>; |
| + }; |
| m2_clk: m2 { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| @@ -798,6 +805,15 @@ |
| }; |
| |
| /* Gate clocks */ |
| + mstp0_clks: mstp0_clks@e6150130 { |
| + compatible = "renesas,r8a7792-mstp-clocks", |
| + "renesas,cpg-mstp-clocks"; |
| + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| + clocks = <&mp_clk>; |
| + #clock-cells = <1>; |
| + clock-indices = <R8A7792_CLK_MSIOF0>; |
| + clock-output-names = "msiof0"; |
| + }; |
| mstp1_clks: mstp1_clks@e6150134 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| @@ -816,12 +832,13 @@ |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| - clocks = <&zs_clk>, <&zs_clk>; |
| + clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| + R8A7792_CLK_MSIOF1 |
| R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 |
| >; |
| - clock-output-names = "sys-dmac1", "sys-dmac0"; |
| + clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; |
| }; |
| mstp3_clks: mstp3_clks@e615013c { |
| compatible = "renesas,r8a7792-mstp-clocks", |