| From 17eacb01b5f6bb8ba6dcf18117c50e52ef830c5a Mon Sep 17 00:00:00 2001 |
| From: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> |
| Date: Tue, 15 Mar 2016 16:07:29 +0900 |
| Subject: [PATCH 012/255] clk: renesas: r8a7796: Add MSIOF controller clocks |
| |
| This patch adds MSIOF{0,1,2,3} clocks for R8A7796 SoC. |
| |
| Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com> |
| Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit e6bdf28eff475a026b922abe78ae710e7179bdf7) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++++ |
| 1 file changed, 5 insertions(+) |
| |
| --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| @@ -105,6 +105,7 @@ static const struct cpg_core_clk r8a7796 |
| |
| DEF_DIV6P1("canfd", R8A7796_CLK_CANFD, CLK_PLL1_DIV4, 0x244), |
| DEF_DIV6P1("csi0", R8A7796_CLK_CSI0, CLK_PLL1_DIV4, 0x00c), |
| + DEF_DIV6P1("mso", R8A7796_CLK_MSO, CLK_PLL1_DIV4, 0x014), |
| |
| DEF_DIV6_RO("osc", R8A7796_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8), |
| DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), |
| @@ -118,6 +119,10 @@ static const struct mssr_mod_clk r8a7796 |
| DEF_MOD("scif3", 204, R8A7796_CLK_S3D4), |
| DEF_MOD("scif1", 206, R8A7796_CLK_S3D4), |
| DEF_MOD("scif0", 207, R8A7796_CLK_S3D4), |
| + DEF_MOD("msiof3", 208, R8A7796_CLK_MSO), |
| + DEF_MOD("msiof2", 209, R8A7796_CLK_MSO), |
| + DEF_MOD("msiof1", 210, R8A7796_CLK_MSO), |
| + DEF_MOD("msiof0", 211, R8A7796_CLK_MSO), |
| DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3), |
| DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3), |
| DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3), |
