| From 8949f820fadbd95083aa0f900272814c1579f4da Mon Sep 17 00:00:00 2001 |
| From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Date: Wed, 7 Dec 2016 17:44:26 +0100 |
| Subject: [PATCH 016/286] arm64: dts: r8a7796: Add all SCIF nodes |
| |
| Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks |
| and power domain. |
| |
| Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 19d76f3ec8fc6ff38f1c5ca534d75a957c8661ea) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm64/boot/dts/renesas/r8a7796.dtsi | 65 +++++++++++++++++++++++++++++++ |
| 1 file changed, 65 insertions(+) |
| |
| --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| @@ -559,6 +559,32 @@ |
| status = "disabled"; |
| }; |
| |
| + scif0: serial@e6e60000 { |
| + compatible = "renesas,scif-r8a7796", |
| + "renesas,rcar-gen3-scif", "renesas,scif"; |
| + reg = <0 0xe6e60000 0 64>; |
| + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 207>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif1: serial@e6e68000 { |
| + compatible = "renesas,scif-r8a7796", |
| + "renesas,rcar-gen3-scif", "renesas,scif"; |
| + reg = <0 0xe6e68000 0 64>; |
| + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 206>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| scif2: serial@e6e88000 { |
| compatible = "renesas,scif-r8a7796", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
| @@ -568,6 +594,45 @@ |
| <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif3: serial@e6c50000 { |
| + compatible = "renesas,scif-r8a7796", |
| + "renesas,rcar-gen3-scif", "renesas,scif"; |
| + reg = <0 0xe6c50000 0 64>; |
| + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 204>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif4: serial@e6c40000 { |
| + compatible = "renesas,scif-r8a7796", |
| + "renesas,rcar-gen3-scif", "renesas,scif"; |
| + reg = <0 0xe6c40000 0 64>; |
| + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 203>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + scif5: serial@e6f30000 { |
| + compatible = "renesas,scif-r8a7796", |
| + "renesas,rcar-gen3-scif", "renesas,scif"; |
| + reg = <0 0xe6f30000 0 64>; |
| + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 202>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |