| From 469531bf6d590e2ca38bd51e8547a4017da1bb3a Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Thu, 29 Sep 2016 13:06:15 +0200 |
| Subject: [PATCH 045/286] clk: renesas: Add r8a7795 ES2.0 CPG Core Clock |
| Definitions |
| |
| Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as |
| listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3 |
| Hardware User's Manual rev. 0.53E. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit 89f1b1c614253d7ea57543f769d93fced99d4d05) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| include/dt-bindings/clock/r8a7795-cpg-mssr.h | 7 +++++++ |
| 1 file changed, 7 insertions(+) |
| |
| --- a/include/dt-bindings/clock/r8a7795-cpg-mssr.h |
| +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h |
| @@ -60,4 +60,11 @@ |
| #define R8A7795_CLK_R 45 |
| #define R8A7795_CLK_OSC 46 |
| |
| +/* r8a7795 ES2.0 CPG Core Clocks */ |
| +#define R8A7795_CLK_S0D2 47 |
| +#define R8A7795_CLK_S0D3 48 |
| +#define R8A7795_CLK_S0D6 49 |
| +#define R8A7795_CLK_S0D8 50 |
| +#define R8A7795_CLK_S0D12 51 |
| + |
| #endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ |
