| From 42bf632b7d7b30934a952d11213b87d96bcc6023 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Mon, 6 Mar 2017 17:40:38 +0100 |
| Subject: [PATCH 057/286] ARM: dts: r8a7745: Remove unit-address and reg from |
| integrated cache |
| |
| The Cortex-A7 cache controller is an integrated controller, and thus the |
| device node representing it should not have a unit-addresses or reg |
| property. |
| |
| Fixes: c95360247bdd67d3 ("ARM: dts: r8a7745: initial SoC device tree") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 51c00a9f730dd27da23e9dec593c22c0f9f5a1b1) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7745.dtsi | 3 +-- |
| 1 file changed, 1 insertion(+), 2 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7745.dtsi |
| +++ b/arch/arm/boot/dts/r8a7745.dtsi |
| @@ -32,9 +32,8 @@ |
| next-level-cache = <&L2_CA7>; |
| }; |
| |
| - L2_CA7: cache-controller@0 { |
| + L2_CA7: cache-controller-0 { |
| compatible = "cache"; |
| - reg = <0>; |
| cache-unified; |
| cache-level = <2>; |
| power-domains = <&sysc R8A7745_PD_CA7_SCU>; |
