| From b8b1b09ceff9eecfbc0a209c40d46467af8eaa16 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Thu, 10 Nov 2016 13:18:25 +0100 |
| Subject: [PATCH 156/286] clk: renesas: r8a7796: Reformat core clock table |
| |
| For easier comparison with other clock drivers. |
| No functional changes. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit c013fc7d23ca5b29f0cdc37d58b2466ead4fd5f6) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/clk/renesas/r8a7796-cpg-mssr.c | 12 ++++++------ |
| 1 file changed, 6 insertions(+), 6 deletions(-) |
| |
| --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| @@ -54,8 +54,8 @@ enum clk_ids { |
| |
| static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { |
| /* External Clock Inputs */ |
| - DEF_INPUT("extal", CLK_EXTAL), |
| - DEF_INPUT("extalr", CLK_EXTALR), |
| + DEF_INPUT("extal", CLK_EXTAL), |
| + DEF_INPUT("extalr", CLK_EXTALR), |
| |
| /* Internal Core Clocks */ |
| DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL), |
| @@ -95,10 +95,10 @@ static const struct cpg_core_clk r8a7796 |
| DEF_FIXED("s3d2", R8A7796_CLK_S3D2, CLK_S3, 2, 1), |
| DEF_FIXED("s3d4", R8A7796_CLK_S3D4, CLK_S3, 4, 1), |
| |
| - DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x0074), |
| - DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x0078), |
| - DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x0268), |
| - DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x026c), |
| + DEF_GEN3_SD("sd0", R8A7796_CLK_SD0, CLK_SDSRC, 0x074), |
| + DEF_GEN3_SD("sd1", R8A7796_CLK_SD1, CLK_SDSRC, 0x078), |
| + DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268), |
| + DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c), |
| |
| DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1), |
| DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1), |
